Driving circuit, driving method, and display device

Abstract

The application provides a driving circuit, a driving method and a display device. The driving circuit comprises a driving signal generation circuit, M output driving ends and M control circuits; the mth control circuit comprises an mth gating circuit, an mth output control circuit and an mth output circuit; M is a positive integer; m is a positive integer less than or equal to M; the driving signal generation circuit outputs an Nth driving signal; the mth gating circuit controls writing of an mth gating input signal into an mth first node under control of an mth gating control signal; the mth output control circuit performs an AND NOT operation on the Nth driving signal and a potential of a second end of the mth output control circuit to obtain an mth first output signal; the mth output circuit inverts the mth first output signal to obtain an mth output driving signal; and N is a positive integer. The application can realize updating of a local picture of a display screen.

Description

[0001] This application is a divisional application of the invention application filed on June 16, 2023, with application number 202310720909.3. Technical Field

[0002] This invention relates to the field of display technology, and more particularly to a driving circuit, driving method, and display device. Background Technology

[0003] In related technologies, when updating the screen of an OLED (Organic Light Emitting Diode) display, the pixel voltage of all row pixel circuits needs to be initialized and written within one frame. However, in certain special screen conditions (such as Always-On Display (AOD) screens, where only a portion of the screen is illuminated without lighting up the entire phone screen), static screens, or screens with infrequent updates), most pixel circuits on the entire screen do not need to update their pixel voltages. That is, most pixel circuits can maintain their original display brightness through low-leakage LTPO (Low Temperature Polycrystalline Oxide) TFTs (Thin Film Transistors). Repeatedly writing and updating these pixel circuits results in wasted power consumption. Summary of the Invention

[0004] The main objective of this invention is to provide a driving circuit, driving method, and display device to solve the problem in related technologies that it is impossible to update the partial image of the display screen.

[0005] In one aspect, the present invention provides a driving circuit, including a driving signal generation circuit, M output driving terminals and M control circuits; the m-th control circuit includes an m-th gating circuit, an m-th output control circuit and an m-th output circuit; M is a positive integer; m is a positive integer less than or equal to M;

[0006] The drive signal generation circuit is electrically connected to the control clock signal terminal, the N-1th stage drive signal output terminal, and the Nth stage drive signal output terminal, respectively. It is used to shift the N-1th stage drive signal provided by the N-1th stage drive signal output terminal under the control of the control clock signal provided by the control clock signal terminal, so as to obtain and output the Nth stage drive signal through the Nth stage drive signal output terminal.

[0007] The m-th gating circuit is electrically connected to the m-th first node, the m-th gating input terminal and the m-th gating control terminal respectively, and is used to control the writing of the m-th gating input signal provided by the m-th gating input terminal into the m-th first node under the control of the m-th gating control signal provided by the m-th gating control terminal.

[0008] The first terminal of the m-th output control circuit is electrically connected to the output terminal of the N-th drive signal, and the second terminal of the m-th output control circuit is electrically connected to the m-th first node. It is used to perform a AND-NOT operation on the potential of the N-th drive signal and the second terminal of the m-th output control circuit to obtain the m-th first output signal.

[0009] The m-th output circuit is used to invert the m-th first output signal to obtain and provide the m-th output drive signal through the m-th output drive terminal;

[0010] N is a positive integer.

[0011] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a first inverting circuit;

[0012] The first inverting circuit is electrically connected to the control clock signal terminal and the inverting clock signal terminal respectively, and is used to invert the control clock signal to obtain an inverting clock signal, and output the inverting clock signal through the inverting clock signal terminal.

[0013] The drive signal generation circuit is also electrically connected to the inverted clock signal terminal, and is also used to perform a shift operation on the N-1 level drive signal provided by the N-1 level drive signal output terminal under the control of the inverted clock signal, so as to obtain and output the N-1 level drive signal through the N-1 level drive signal output terminal.

[0014] Optionally, the m-th gating circuit is used to control the writing of the m-th gating input signal provided by the m-th gating input terminal into the m-th first node when the potential of the N-1-th driving signal is a first voltage and the potential of the N-th driving signal is a second voltage.

[0015] Optionally, the m-th gating control terminal includes the m-th first control terminal, the m-th second control terminal, the m-th third control terminal, and the m-th fourth control terminal, and the m-th gating circuit includes the m-th first gating transistor, the m-th second gating transistor, the m-th third gating transistor, and the m-th fourth gating transistor;

[0016] The gate of the m-th first gating transistor is electrically connected to the m-th first control terminal, and the first terminal of the m-th first gating transistor is electrically connected to the m-th gating input terminal.

[0017] The gate of the m-th second selection transistor is electrically connected to the m-th second control terminal, and the first terminal of the m-th second selection transistor is electrically connected to the m-th selection input terminal;

[0018] The gate of the m-th third gate transistor is electrically connected to the m-th third control terminal, the first terminal of the m-th third gate transistor is electrically connected to the second terminal of the m-th first gate transistor, and the second terminal of the m-th third gate transistor is electrically connected to the m-th first node.

[0019] The gate of the m-th fourth selection transistor is electrically connected to the m-th fourth control terminal, the first terminal of the m-th fourth selection transistor is electrically connected to the second terminal of the m-th second selection transistor, and the second terminal of the m-th fourth selection transistor is electrically connected to the m-th first node.

[0020] The m-th first gating transistor is a p-type transistor, the m-th second gating transistor is an n-type transistor, the m-th third gating transistor is a p-type transistor, and the m-th fourth gating transistor is an n-type transistor;

[0021] The m-th first control terminal is connected to the inverted signal of the (N-1)-th level drive signal, the m-th second control terminal is the output terminal of the (N-1)-th level drive signal, the m-th third control terminal is the output terminal of the N-th level drive signal, and the m-th fourth control terminal is connected to the inverted signal of the N-th level drive signal; or, the m-th first control terminal is connected to the inverted signal of the N-th level drive signal, the m-th second control terminal is the output terminal of the N-th level drive signal, the m-th third control terminal is the output terminal of the (N-1)-th level drive signal, and the m-th fourth control terminal is connected to the inverted signal of the (N-1)-th level drive signal.

[0022] Optionally, the second terminal of the m-th first gating transistor is electrically connected to the second terminal of the m-th second gating transistor.

[0023] Optionally, the m-th gating circuit includes the m-th first gating transistor;

[0024] The gate of the m-th first selection transistor is electrically connected to the m-th selection control terminal, the first terminal of the m-th first selection transistor is electrically connected to the m-th first node, and the second terminal of the m-th first selection transistor is electrically connected to the m-th selection input terminal.

[0025] Optionally, the m-th gating control terminal includes the m-th first control terminal and the m-th second control terminal; the m-th gating circuit includes the m-th first gating transistor and the m-th second gating transistor;

[0026] The gate of the m-th first gating transistor is electrically connected to the m-th first control terminal, the first terminal of the m-th first gating transistor is electrically connected to the m-th first node, and the second terminal of the m-th first gating transistor is electrically connected to the first terminal of the m-th second gating transistor.

[0027] The gate of the m-th second gating transistor is electrically connected to the m-th second control terminal, and the second terminal of the m-th second gating transistor is electrically connected to the m-th gating input terminal;

[0028] The m-th first control terminal is the output terminal of the (N-1)-th stage drive signal, the m-th second control terminal is the output terminal of the N-th stage drive signal, the m-th first gating transistor is an n-type transistor, and the m-th second gating transistor is a p-type transistor; or...

[0029] The m-th first control terminal is the N-th stage drive signal output terminal, the m-th second control terminal is the (N-1)-th stage drive signal output terminal, the m-th first gating transistor is a p-type transistor, and the m-th second gating transistor is an n-type transistor; or...

[0030] The m-th first control terminal is connected to the inverted signal of the (N-1)-th stage drive signal, the m-th second control terminal is the output terminal of the N-th stage drive signal, and both the m-th first gating transistor and the m-th second gating transistor are p-type transistors; or...

[0031] The m-th first control terminal is the output terminal of the N-th stage drive signal, and the m-th second control terminal is connected to the inverted signal of the (N-1)-th stage drive signal; both the m-th first gating transistor and the m-th second gating transistor are p-type transistors; or...

[0032] The m-th first control terminal is the (N-1)-th stage drive signal terminal, the m-th second control terminal is connected to the inverted signal of the N-th stage drive signal, and both the m-th first gating transistor and the m-th second gating transistor are n-type transistors; or,

[0033] The m-th first control terminal is connected to the inverted signal of the N-th level drive signal, the m-th second control terminal is the N-1 level drive signal terminal, and the m-th first gating transistor and the m-th second gating transistor are both n-type transistors.

[0034] Optionally, the m-th control circuit further includes the m-th first initialization circuit;

[0035] The m-th first initialization circuit is electrically connected to the initial control terminal, the first voltage terminal, and the m-th first node, respectively, and is used to control the connection between the m-th first node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0036] Optionally, the m-th control circuit further includes an m-th reset circuit;

[0037] The m-th reset circuit is electrically connected to the first voltage terminal, the (N-1)-th level drive signal output terminal, the N-th level drive signal output terminal, and the m-th first node, respectively, and is used to control the connection between the m-th first node and the first voltage terminal under the control of the N-th level drive signal and the (N-1)-th level drive signal provided by the (N-1)-th level drive signal output terminal.

[0038] Optionally, the m-th control circuit further includes the m-th first voltage sustaining circuit;

[0039] The first terminal of the m-th first voltage maintenance circuit is electrically connected to the m-th first node, and the second terminal of the m-th first voltage maintenance circuit is electrically connected to the DC voltage terminal. The m-th voltage maintenance circuit is used to maintain the potential of the m-th first node.

[0040] Optionally, the m-th control circuit further includes the m-th second voltage sustaining circuit; the m-th first node is electrically connected to the second terminal of the m-th output control circuit through the m-th second voltage sustaining circuit;

[0041] The m-th second voltage sustaining circuit includes the m-th first inverter, the m-th second inverter, and the m-th sustaining control circuit;

[0042] The input terminal of the m-th first inverter is electrically connected to the m-th first node, the output terminal of the m-th first inverter is electrically connected to the m-th second node, the input terminal of the m-th second inverter is electrically connected to the m-th second node, and the output terminal of the m-th second inverter is electrically connected to the m-th third node and the second terminal of the m-th output control circuit.

[0043] The m-th first inverter is used to invert the potential of the m-th first node and output the inverted potential of the m-th first node through the output terminal of the m-th first inverter. The m-th second inverter is used to invert the potential of its input terminal and output the inverted potential through the output terminal of the m-th second inverter.

[0044] The m-th maintenance control circuit is electrically connected to the m-th maintenance control terminal, the m-th third node, and the m-th first node, respectively, and is used to control the connection or disconnection between the m-th third node and the m-th first node under the control of the m-th maintenance control signal provided by the m-th maintenance control terminal.

[0045] Optionally, the m-th reset circuit includes the m-th first transistor and the m-th second transistor;

[0046] The gate of the m-th first transistor is electrically connected to the output terminal of the (N-1)-th stage drive signal, the first terminal of the m-th first transistor is electrically connected to the first voltage terminal, and the second terminal of the m-th first transistor is electrically connected to the first terminal of the m-th second transistor.

[0047] The gate of the m-th second transistor is electrically connected to the output terminal of the N-th drive signal, and the second electrode of the m-th second transistor is electrically connected to the m-th first node.

[0048] Optionally, the m-th maintenance control terminal includes the m-th first maintenance control terminal and the m-th second maintenance control terminal;

[0049] The m-th sustaining control circuit includes the m-th third transistor and the m-th fourth transistor;

[0050] The gate of the m-th third transistor is electrically connected to the m-th first sustaining control terminal, the first electrode of the m-th third transistor is electrically connected to the m-th first node, and the second electrode of the m-th third transistor is electrically connected to the m-th third node.

[0051] The gate of the m-th fourth transistor is electrically connected to the m-th second sustain control terminal, the first terminal of the m-th fourth transistor is electrically connected to the m-th third node, and the second terminal of the m-th fourth transistor is electrically connected to the m-th first node.

[0052] The m-th third transistor is a p-type transistor, and the m-th fourth transistor is an n-type transistor;

[0053] The m-th first sustain control terminal is the (N-1)-th stage drive signal terminal, and the m-th second sustain control terminal is the control clock signal terminal; or...

[0054] The m-th first sustain control terminal is an inverting clock signal terminal, and the m-th second sustain control terminal is a control clock signal terminal.

[0055] Optionally, the m-th first inverter includes the m-th fifth transistor and the m-th sixth transistor, and the m-th second inverter includes the m-th seventh transistor and the m-th eighth transistor;

[0056] The gate of the m-th fifth transistor is electrically connected to the m-th first node, the first electrode of the m-th fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the m-th fifth transistor is electrically connected to the m-th second node.

[0057] The gate of the m-th sixth transistor is electrically connected to the m-th first node, the first terminal of the m-th sixth transistor is electrically connected to the m-th second node, and the second terminal of the m-th sixth transistor is electrically connected to the second voltage terminal.

[0058] The m-th fifth transistor is a p-type transistor, and the m-th sixth transistor is an n-type transistor;

[0059] The gate of the m-th seventh transistor is electrically connected to the m-th second node, the first terminal of the m-th seventh transistor is electrically connected to the first voltage terminal, and the second terminal of the m-th seventh transistor is electrically connected to the m-th third node;

[0060] The gate of the m-th eighth transistor is electrically connected to the m-th second node, the first terminal of the m-th eighth transistor is electrically connected to the m-th third node, and the second terminal of the m-th eighth transistor is electrically connected to the second voltage terminal.

[0061] The m-th seventh transistor is a p-type transistor, and the m-th eighth transistor is an n-type transistor.

[0062] Optionally, the m-th first initialization circuit includes the m-th ninth transistor;

[0063] The gate of the m-th ninth transistor is electrically connected to the initial control terminal, the first terminal of the m-th ninth transistor is electrically connected to the first voltage terminal, and the second terminal of the m-th ninth transistor is electrically connected to the m-th first node.

[0064] Optionally, the m-th first voltage sustaining circuit includes the m-th capacitor;

[0065] The first terminal of the m-th capacitor is electrically connected to the m-th first node, and the second terminal of the m-th capacitor is electrically connected to the DC voltage terminal.

[0066] Optionally, the m-th output control circuit includes the m-th tenth transistor, the m-th eleventh transistor, the m-th twelfth transistor, and the m-th thirteenth transistor;

[0067] The gate of the m-th tenth transistor is electrically connected to the m-th first node, the first electrode of the m-th tenth transistor is electrically connected to the first voltage terminal, and the second electrode of the m-th tenth transistor is electrically connected to the m-th second node.

[0068] The gate of the m-th eleventh transistor is electrically connected to the output terminal of the N-th drive signal, the first electrode of the m-th eleventh transistor is electrically connected to the first voltage terminal, and the second electrode of the m-th eleventh transistor is electrically connected to the m-th second node.

[0069] The gate of the m-th twelfth transistor is electrically connected to the m-th first node, the first terminal of the m-th twelfth transistor is electrically connected to the m-th second node, and the second terminal of the m-th twelfth transistor is electrically connected to the first terminal of the m-th thirteenth transistor.

[0070] The gate of the m-th thirteenth transistor is electrically connected to the N-level drive signal output terminal, and the second terminal of the m-th thirteenth transistor is electrically connected to the second voltage terminal.

[0071] The m-th tenth transistor and the m-th eleventh transistor are p-type transistors, and the m-th twelfth transistor and the m-th thirteenth transistor are n-type transistors.

[0072] Optionally, the m-th output circuit includes the m-th fourteenth transistor and the m-th fifteenth transistor;

[0073] The gate of the m-th fourteenth transistor is electrically connected to the m-th second node, the first terminal of the m-th fourteenth transistor is electrically connected to the first voltage terminal, and the second terminal of the m-th fourteenth transistor is electrically connected to the m-th output drive terminal.

[0074] The gate of the m-th fifteenth transistor is electrically connected to the m-th second node, the first terminal of the m-th fifteenth transistor is electrically connected to the m-th output drive terminal, and the second terminal of the m-th fifteenth transistor is electrically connected to the second voltage terminal.

[0075] Optionally, the drive signal generation circuit includes a first drive control circuit, a second drive control circuit, a second inverting circuit, and a second initialization circuit.

[0076] The first drive control circuit is electrically connected to the control clock signal terminal, the inverted clock signal terminal, the N-1th stage drive signal output terminal and the fourth node, respectively. Under the control of the control clock signal provided by the control clock signal terminal and the inverted clock signal provided by the inverted clock signal terminal, the N-1th stage drive signal output terminal is shifted and inverted to obtain the inverted signal output through the fourth node.

[0077] The second drive control circuit is electrically connected to the control clock signal terminal, the inverted clock signal terminal, the Nth stage drive signal output terminal, and the fourth node, respectively. It is used to invert the Nth stage drive signal provided by the Nth stage drive signal output terminal under the control of the control clock signal and the inverted clock signal, so as to obtain the inverted signal and output it through the fourth node.

[0078] The second inverting circuit is electrically connected to the fourth node and the Nth stage drive signal output terminal, respectively, and is used to invert the potential of the fourth node and output the inverted signal through the Nth stage drive signal output terminal;

[0079] The second initialization circuit is electrically connected to the initial control terminal, the first voltage terminal, and the Nth stage drive signal output terminal, respectively, and is used to control the connection between the Nth stage drive signal output terminal and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0080] Optionally, the first drive control circuit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor;

[0081] The gate of the sixteenth transistor is electrically connected to the inverting clock signal terminal, the first terminal of the sixteenth transistor is electrically connected to the first voltage terminal, and the second terminal of the sixteenth transistor is electrically connected to the first terminal of the seventeenth transistor.

[0082] The gate of the seventeenth transistor is electrically connected to the output terminal of the (N-1)th stage drive signal, and the second terminal of the seventeenth transistor is electrically connected to the fourth node;

[0083] The gate of the eighteenth transistor is electrically connected to the output terminal of the (N-1)th stage drive signal, the first terminal of the eighteenth transistor is electrically connected to the fourth node, and the second terminal of the eighteenth transistor is electrically connected to the first terminal of the nineteenth transistor.

[0084] The gate of the nineteenth transistor is electrically connected to the control clock signal terminal, and the second terminal of the nineteenth transistor is electrically connected to the third voltage terminal.

[0085] The sixteenth and seventeenth transistors are p-type transistors, and the eighteenth and nineteenth transistors are n-type transistors.

[0086] Optionally, the second drive control circuit includes a twentieth transistor, a twenty-first transistor, a twenty-second transistor, and a twenty-third transistor;

[0087] The gate of the twentieth transistor is electrically connected to the output terminal of the Nth stage drive signal, the first terminal of the twentieth transistor is electrically connected to the first voltage terminal, and the second terminal of the twentieth transistor is electrically connected to the first terminal of the twentieth eleventh transistor.

[0088] The gate of the 21st transistor is electrically connected to the control clock signal terminal, and the second terminal of the 21st transistor is electrically connected to the fourth node;

[0089] The gate of the 22nd transistor is electrically connected to the inverting clock signal terminal, the first terminal of the 22nd transistor is electrically connected to the fourth node, and the second terminal of the 22nd transistor is electrically connected to the first terminal of the 23rd transistor.

[0090] The gate of the 23rd transistor is electrically connected to the output terminal of the Nth stage drive signal, and the second terminal of the 23rd transistor is electrically connected to the third voltage terminal;

[0091] The twentieth and twentieth transistors are p-type transistors, and the twentieth and twentieth transistors are n-type transistors.

[0092] Optionally, the second inverting circuit includes a twenty-fourth transistor and a twenty-fifth transistor; the second initialization circuit includes a twenty-sixth transistor;

[0093] The gate of the 24th transistor is electrically connected to the fourth node, the first terminal of the 24th transistor is electrically connected to the first voltage terminal, and the second terminal of the 24th transistor is electrically connected to the first terminal of the 25th transistor and the Nth stage drive signal output terminal.

[0094] The gate of the 25th transistor is electrically connected to the fourth node, and the second terminal of the 25th transistor is electrically connected to the third voltage terminal.

[0095] The twenty-fourth transistor is a p-type transistor, and the twenty-fifth transistor is an n-type transistor;

[0096] The gate of the 26th transistor is electrically connected to the initial control terminal, the first terminal of the 26th transistor is electrically connected to the first voltage terminal, and the second terminal of the 26th transistor is electrically connected to the Nth stage drive signal output terminal.

[0097] Optionally, the first inverting circuit includes a twenty-seventh transistor and a twenty-eighth transistor;

[0098] The gate of the 27th transistor is electrically connected to the control clock signal terminal, the first terminal of the 27th transistor is electrically connected to the first voltage terminal, and the second terminal of the 27th transistor is electrically connected to the first terminal of the 28th transistor and the inverting clock signal terminal.

[0099] The gate of the 28th transistor is electrically connected to the control clock signal terminal, and the second terminal of the 28th transistor is electrically connected to the third voltage terminal.

[0100] In a second aspect, embodiments of the present invention provide a driving method applied to the aforementioned driving circuit, the driving method comprising:

[0101] Under the control of the control clock signal, the drive signal generation circuit performs a shift operation on the (N-1)th stage drive signal to obtain and output the Nth stage drive signal through the Nth stage drive signal output terminal;

[0102] The m-th gating circuit, under the control of the m-th gating control signal, controls the writing of the m-th gating input signal into the m-th first node;

[0103] The m-th output control circuit performs a AND-NOT operation on the N-th stage drive signal and the potential of the second terminal of the m-th output control circuit to obtain the m-th first output signal;

[0104] The m-th output circuit is used to invert the m-th first output signal to obtain and provide the m-th output drive signal through the m-th output drive terminal.

[0105] M is a positive integer; m is a positive integer less than or equal to M; and N is a positive integer.

[0106] In a third aspect, embodiments of the present invention provide a display device including the driving circuit described above.

[0107] In this embodiment of the invention, the updating of a portion of the display screen can be achieved by controlling the gating input signal provided by the gating input terminal, thereby reducing power consumption. Attached Figure Description

[0108] Figure 1 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0109] Figure 2 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0110] Figure 3 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0111] Figure 4 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0112] Figure 5 It is the circuit diagram of the relevant pixel circuit;

[0113] Figure 6 yes Figure 5 The timing diagram of the relevant pixel circuit is shown below;

[0114] Figure 7 It is the circuit diagram of the relevant pixel circuit;

[0115] Figure 8 This is a circuit diagram of at least one embodiment of the gating circuit in the driving circuit described in the embodiments of the present invention;

[0116] Figure 9 This is a circuit diagram of at least one embodiment of the gating circuit in the driving circuit described in the embodiments of the present invention;

[0117] Figure 10 This is a circuit diagram of at least one embodiment of the gating circuit in the driving circuit described in the embodiments of the present invention;

[0118] Figure 11 This is a circuit diagram of at least one embodiment of the gating circuit in the driving circuit described in the embodiments of the present invention;

[0119] Figure 12 This is a circuit diagram of at least one embodiment of the gating circuit in the driving circuit described in the embodiments of the present invention;

[0120] Figure 13 This is a circuit diagram of at least one embodiment of the gating circuit in the driving circuit described in the embodiments of the present invention;

[0121] Figure 14 This is a circuit diagram of at least one embodiment of the gating circuit in the driving circuit described in the embodiments of the present invention;

[0122] Figure 15 This is a circuit diagram of at least one embodiment of the gating circuit in the driving circuit described in the embodiments of the present invention;

[0123] Figure 16 This is a circuit diagram of at least one embodiment of the gating circuit in the driving circuit described in the embodiments of the present invention;

[0124] Figure 17 This is a circuit diagram of at least one embodiment of the gating circuit in the driving circuit described in the embodiments of the present invention;

[0125] Figure 18 This is a circuit diagram of at least one embodiment of the first inverting module;

[0126] Figure 19 This is a circuit diagram of at least one embodiment of the second inverting module;

[0127] Figure 20 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0128] Figure 21 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0129] Figure 22 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0130] Figure 23 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0131] Figure 24 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0132] Figure 25 These are waveform diagrams of the control clock signal provided by the control clock signal terminal NCK and the first clock signal provided by the first clock signal terminal NCB.

[0133] Figure 26 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0134] Figure 27 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0135] Figure 28 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0136] Figure 29 This is a circuit diagram of the driving circuit according to at least one embodiment of the present invention;

[0137] Figure 30 This is a structural diagram of the driving circuit according to at least one embodiment of the present invention;

[0138] Figure 31 yes Figure 30 The timing diagram of at least one embodiment of the driving circuit shown;

[0139] Figure 32 It is a timing diagram of the signals output from each stage of the output driver terminal;

[0140] Figure 33 This is a circuit diagram of at least one embodiment of the second voltage sustaining circuit. Detailed Implementation

[0141] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0142] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In these embodiments, to distinguish between the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal, and the other as the second terminal.

[0143] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0144] The driving circuit described in this embodiment of the invention includes a driving signal generation circuit, M output driving terminals, and M control circuits; the m-th control circuit includes an m-th gating circuit, an m-th output control circuit, and an m-th output circuit; M is a positive integer; m is a positive integer less than or equal to M;

[0145] The drive signal generation circuit is electrically connected to the control clock signal terminal, the N-1th stage drive signal output terminal, and the Nth stage drive signal output terminal, respectively. It is used to shift the N-1th stage drive signal provided by the N-1th stage drive signal output terminal under the control of the control clock signal provided by the control clock signal terminal, so as to obtain and output the Nth stage drive signal through the Nth stage drive signal output terminal.

[0146] The m-th gating circuit is electrically connected to the m-th first node, the m-th gating input terminal and the m-th gating control terminal respectively, and is used to control the writing of the m-th gating input signal provided by the m-th gating input terminal into the m-th first node under the control of the m-th gating control signal provided by the m-th gating control terminal.

[0147] The first terminal of the m-th output control circuit is electrically connected to the output terminal of the N-th drive signal, and the second terminal of the m-th output control circuit is electrically connected to the m-th first node. It is used to perform a AND-NOT operation on the potential of the N-th drive signal and the second terminal of the m-th output control circuit to obtain the m-th first output signal.

[0148] The m-th output circuit is used to invert the m-th first output signal to obtain and provide the m-th output drive signal through the m-th output drive terminal;

[0149] N is a positive integer.

[0150] In the driving circuit described in the embodiments of the present invention, a driving signal generation circuit can correspond to at least one control circuit. Under the control of the control clock signal, the driving signal generation circuit performs a shift operation on the (N-1)th level driving signal to obtain the Nth level driving signal. The mth control circuit generates the mth output driving signal according to the Nth level driving signal.

[0151] In at least one embodiment of the present invention, m is given as an example of m equal to 1 or m equal to 2, but this is not a limitation. In actual operation, m can also be an integer greater than 2.

[0152] like Figure 1As shown, the driving circuit of at least one embodiment of the present invention includes a driving signal generation circuit 10, an output driving terminal NO (N), and a control circuit; the control circuit includes a gating circuit 11, an output control circuit 12, and an output circuit 13;

[0153] The drive signal generation circuit 10 is electrically connected to the control clock signal terminal NCK, the N-1th stage drive signal output terminal NS(N-1), and the Nth stage drive signal output terminal NS(N), respectively. Under the control of the control clock signal provided by the control clock signal terminal NCK, it performs a shift operation on the N-1th stage drive signal provided by the N-1th stage drive signal output terminal NS(N-1) to obtain and output the Nth stage drive signal through the Nth stage drive signal output terminal NS(N).

[0154] The gating circuit 11 is electrically connected to the first node N1, the gating input terminal VCT, and the gating control terminal CX, respectively, and is used to control the gating input signal provided by the gating input terminal VCT to be written into the first node N1 under the control of the gating control signal provided by the gating control terminal CX.

[0155] The first terminal of the output control circuit 12 is electrically connected to the Nth stage drive signal output terminal NS(N), and the second terminal of the output control circuit 12 is electrically connected to the first node N1. It is used to perform a AND-NOT operation on the potential of the Nth stage drive signal and the second terminal of the output control circuit 12 to obtain the first output signal.

[0156] The output circuit 13 is electrically connected to the output control circuit 12 and the output drive terminal NO (N) respectively, and is used to invert the first output signal to obtain an output drive signal provided through the output drive terminal NO (N);

[0157] N is a positive integer.

[0158] This invention Figure 1 The embodiment of the driving circuit shown can be the Nth stage driving circuit.

[0159] This invention Figure 1 The illustrated driving circuit embodiment, when in operation, within one frame time,

[0160] Before the Nth stage of driving signal provision, the gating circuit 11, under the control of the gating control signal, writes the gating input signal provided by the gating input terminal VCT into the first node N1;

[0161] When the strobe input signal is a high voltage signal, during the Nth level drive signal provision stage, the Nth level drive signal output terminal NS(N) outputs a high voltage signal. Then, the first output signal output by the output control circuit 12 is a low voltage signal. The output circuit 13 provides a high voltage signal through the output drive terminal NO(N), which can control the corresponding row pixel circuit to update the pixel voltage.

[0162] When the strobe input signal is a low voltage signal, during the Nth level drive signal provision stage, the Nth level drive signal output terminal NS(N) outputs a high voltage signal. Then, the first output signal output by the output control circuit 12 is a high voltage signal. The output circuit 13 provides a low voltage signal through the output drive terminal NO(N), which can control the corresponding row pixel circuit not to update the pixel voltage.

[0163] At least one embodiment of the present invention can update a portion of the display screen by controlling the gating input signal provided by the gating input terminal VCT, thereby reducing power consumption, or achieve ultra-low power consumption of OLED (organic light-emitting diode) display products such as wearable products, mobile terminals, and notebook computers by updating the display screen portion.

[0164] like Figure 2 As shown, the driving circuit of at least one embodiment of the present invention includes a driving signal generation circuit 10, a first output driving terminal NO1 (N), a second output driving terminal NO2 (N), a first control circuit, and a second control circuit; the first control circuit includes a first gating circuit 111, a first output control circuit 121, and a first output circuit 131; the second control circuit includes a second gating circuit 112, a second output control circuit 122, and a second output circuit 132.

[0165] The drive signal generation circuit 10 is electrically connected to the control clock signal terminal NCK, the N-1th stage drive signal output terminal NS(N-1), and the Nth stage drive signal output terminal NS(N), respectively. Under the control of the control clock signal provided by the control clock signal terminal NCK, it performs a shift operation on the N-1th stage drive signal provided by the N-1th stage drive signal output terminal NS(N-1) to obtain and output the Nth stage drive signal through the Nth stage drive signal output terminal NS(N).

[0166] The first gating circuit 111 is electrically connected to the first first node N11, the first gating input terminal VCT1 and the first gating control terminal CX1 respectively, and is used to control the first gating input signal provided by the first gating input terminal VCT1 to be written into the first first node N11 under the control of the first gating control signal provided by the first gating control terminal CX1.

[0167] The first terminal of the first output control circuit 121 is electrically connected to the Nth stage drive signal output terminal NS(N), and the second terminal of the first output control circuit 121 is electrically connected to the first first node N11. It is used to perform a AND-NOT operation on the potential of the Nth stage drive signal and the second terminal of the first output control circuit 121 to obtain the first first output signal.

[0168] The first output circuit 131 is electrically connected to the first output control circuit 121 and the first output drive terminal NO1 (N) respectively, and is used to invert the first first output signal to obtain a first output drive signal provided through the first output drive terminal NO1 (N);

[0169] The second gating circuit 112 is electrically connected to the second first node N21, the second gating input terminal VCT2, and the second gating control terminal CX2, respectively, and is used to control the writing of the second gating input signal provided by the second gating input terminal VCT2 into the second first node N21 under the control of the second gating control signal provided by the second gating control terminal CX2.

[0170] The first terminal of the second output control circuit 122 is electrically connected to the Nth stage drive signal output terminal NS(N), and the second terminal of the second output control circuit 122 is electrically connected to the second first node N21. It is used to perform a AND-NOT operation on the potential of the Nth stage drive signal and the second terminal of the second output control circuit 122 to obtain the second first output signal.

[0171] The second output circuit 132 is electrically connected to the second output control circuit 122 and the second output drive terminal NO2 (N) respectively, and is used to invert the second first output signal to obtain a second output drive signal provided through the second output drive terminal NO2 (N);

[0172] N is a positive integer.

[0173] This invention Figure 2 The embodiment of the driving circuit shown can be the Nth stage driving circuit.

[0174] This invention Figure 2 The illustrated driving circuit embodiment, when in operation, within one frame time,

[0175] Before the Nth stage of driving signal provision, the first gating circuit 111, under the control of the first gating control signal, writes the first gating input signal provided by the first gating input terminal VCT1 into the first first node N11; the second gating circuit 112, under the control of the second gating control signal, writes the second gating input signal provided by the second gating input terminal VCT2 into the second first node N21.

[0176] When the first strobe input signal is a high voltage signal, during the Nth level drive signal provision stage, the Nth level drive signal output terminal NS(N) outputs a high voltage signal, and the first first output signal output by the first output control circuit 121 is a low voltage signal. The first output circuit 131 provides a high voltage signal through the first output drive terminal NO1(N), which can control the corresponding row pixel circuit to update the pixel voltage.

[0177] When the first strobe input signal is a low voltage signal, during the Nth level drive signal provision stage, the Nth level drive signal output terminal NS(N) outputs a high voltage signal. Then, the first first output signal output by the first output control circuit 121 is a high voltage signal. The first output circuit 131 provides a low voltage signal through the first output drive terminal NO1(N), which can control the corresponding row pixel circuit not to update the pixel voltage.

[0178] When the second strobe input signal is a high voltage signal, during the Nth level drive signal provision stage, the Nth level drive signal output terminal NS(N) outputs a high voltage signal, then the second first output signal output by the second output control circuit 122 is a low voltage signal, and the second output circuit 132 provides a high voltage signal through the second output drive terminal NO2(N), which can control the corresponding row pixel circuit to update the pixel voltage.

[0179] When the second strobe input signal is a low voltage signal, during the Nth level drive signal provision stage, the Nth level drive signal output terminal NS(N) outputs a high voltage signal. Then, the second first output signal output by the second output control circuit 122 is a high voltage signal. The second output circuit 132 provides a low voltage signal through the second output drive terminal NO2(N), which can control the corresponding row pixel circuit not to update the pixel voltage.

[0180] At least one embodiment of the present invention can update a portion of the display screen by controlling the first gating input signal provided by the first gating input terminal VCT1 and the second gating input signal provided by the second gating input terminal VCT2, thereby reducing power consumption, or achieve ultra-low power consumption of OLED (organic light-emitting diode) display products such as wearable products, mobile terminals, and notebook computers by updating the display screen portion.

[0181] In at least one embodiment of the present invention, the driving circuit further includes a first inverting circuit;

[0182] The first inverting circuit is electrically connected to the control clock signal terminal and the inverting clock signal terminal respectively, and is used to invert the control clock signal to obtain an inverting clock signal, and output the inverting clock signal through the inverting clock signal terminal.

[0183] The drive signal generation circuit is also electrically connected to the inverted clock signal terminal, and is also used to perform a shift operation on the N-1 level drive signal provided by the N-1 level drive signal output terminal under the control of the inverted clock signal, so as to obtain and output the N-1 level drive signal through the N-1 level drive signal output terminal.

[0184] In a specific implementation, the driving circuit may further include a first inverting circuit, which inverts the control clock signal to obtain an inverted clock signal. Under the control of the control clock signal and the inverted clock signal, the driving signal generation circuit performs a shift operation on the (N-1)th level driving signal to obtain the Nth level driving signal.

[0185] like Figure 3 As shown, in Figure 1 Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a first inverter circuit 31;

[0186] The first inverter circuit 31 is electrically connected to the control clock signal terminal NCK and the inverter clock signal terminal NCKI respectively, and is used to invert the control clock signal to obtain an inverter clock signal, and output the inverter clock signal through the inverter clock signal terminal NCKI.

[0187] The drive signal generation circuit 10 is also electrically connected to the inverted clock signal terminal NCKI, and is also used to perform a shift operation on the N-1 level drive signal provided by the N-1 level drive signal output terminal NS(N-1) under the control of the inverted clock signal, so as to obtain and output the N-1 level drive signal through the N-1 level drive signal output terminal NS(N).

[0188] like Figure 4 As shown, in Figure 2 Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a first inverter circuit 31;

[0189] The first inverter circuit 31 is electrically connected to the control clock signal terminal NCK and the inverter clock signal terminal NCKI respectively, and is used to invert the control clock signal to obtain an inverter clock signal, and output the inverter clock signal through the inverter clock signal terminal NCKI.

[0190] The drive signal generation circuit 10 is also electrically connected to the inverted clock signal terminal NCKI, and is also used to perform a shift operation on the N-1 level drive signal provided by the N-1 level drive signal output terminal NS(N-1) under the control of the inverted clock signal, so as to obtain and output the N-1 level drive signal through the N-1 level drive signal output terminal NS(N).

[0191] like Figure 5As shown, the related pixel circuit may include a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, a storage capacitor Cst, and an organic light-emitting diode O1.

[0192] The gate of M1 is electrically connected to the first reset terminal NR (N), the source of M1 is electrically connected to the initial voltage terminal I1, and the drain of M1 is electrically connected to the gate of M3.

[0193] The gate of M2 is electrically connected to the first scan terminal NG (N), the source of M2 is electrically connected to the gate of M3, and the drain of M2 is electrically connected to the drain of M3.

[0194] The gate of M4 is electrically connected to the second scan terminal PG(N), the source of M4 is electrically connected to the data line D1, and the drain of M4 is electrically connected to the source of M3.

[0195] The gate of M5 is electrically connected to the light-emitting control terminal E(N), the source of M5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of M5 is electrically connected to the source of M3.

[0196] The gate of M6 is electrically connected to the light-emitting control terminal E(N), the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low-level terminal ELVSS.

[0197] The gate of M7 is electrically connected to the second scan terminal PG(N), the source of M7 is electrically connected to the initial voltage terminal I1, and the drain of M7 is electrically connected to the anode of O1.

[0198] In specific implementation, the first reset terminal NR(N) can be the first scan terminal NG(N) of the N-1th level, but is not limited thereto.

[0199] exist Figure 5 In the related pixel circuit shown, M1 and M2 are n-type transistors, M3, M4, M5, M6 and M7 are all p-type transistors, M1 and M2 are IGZO (indium gallium zinc oxide) TFTs (thin film transistors) with low leakage current, and M3, M4, M5, M6 and M7 are all LTPS (low temperature polycrystalline silicon) TFTs.

[0200] exist Figure 5 In the related pixel circuit shown, M1 and M2 are IGZO TFTs. When using low-frequency displays, IGZO TFTs can ensure that Cst can maintain the gate voltage of M3 for a longer period of time.

[0201] exist Figure 5In the related pixel circuit shown, the second scan terminal PG(N) is responsible for resetting the voltage of the anode of O1 and writing the data voltage on the data line to the source of the driving transistor. The first scan terminal NG(N) is responsible for resetting Cst, extracting Vth (Vth is the threshold voltage of the driving transistor), and writing the data voltage to the gate of the driving transistor.

[0202] In specific implementation, the first scan signal provided by the first scanning terminal NG(N) and the second scan signal provided by the second scanning terminal PG(N) can be inversely related, but are not limited thereto.

[0203] The driving circuit described in at least one embodiment of the present invention can provide a first scanning signal to the first scanning terminal NG(N) through the output driving terminal NO(N), but is not limited thereto.

[0204] like Figure 6 As shown, Figure 5 When the related pixel circuit shown is working, the display cycle may include a first display control stage t1, a second display control stage t2, and a third display control stage t3 set sequentially.

[0205] In the first display control phase t1, E(N) outputs a high voltage signal, NR(N) provides a high voltage signal, PG(N) provides a high voltage signal, NG(N) provides a low voltage signal, M5 and M6 are turned off, M1 is turned on, and the potential of the gate of M3 is pulled low to the initial voltage Vinit; the initial voltage terminal I1 is used to provide the initial voltage Vinit.

[0206] In the second display control phase t2, E(N) outputs a high voltage signal, NR(N) provides a low voltage signal, PG(N) provides a low voltage signal, and NG(N) provides a high voltage signal. M5 and M6 are turned off, M1 is turned off, M2 is turned on, and M4 is turned on. M2 and M3 form a diode structure, charging Cst through the data voltage Vdata provided by data line D1 until M3 is turned off. At this time, the gate voltage of M3 is Vdata + Vth, where Vth is the threshold voltage of M3. M7 is turned on to reset the anode voltage of O1.

[0207] In the third display control stage t3, E(N) outputs a low voltage signal, NR(N) provides a low voltage signal, PG(N) provides a high voltage signal, NG(N) provides a low voltage signal, M5 and M6 are turned on, and M3 drives O1 to emit light; O1 emits light according to the voltage setting of Vdata.

[0208] As can be seen from the above-mentioned pixel circuit operation process, NG(N) can control whether the data voltage Vdata (which can be the pixel voltage) is written into the gate of M3 during the second display control stage.

[0209] Figure 7 This is the circuit diagram of the relevant pixel circuit.

[0210] like Figure 7 As shown, the related pixel circuit may include a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, a storage capacitor Cst, and an organic light-emitting diode O1.

[0211] The gate of M1 is electrically connected to the third reset terminal RST1, the source of M1 is electrically connected to the initial voltage terminal I1, and the drain of M1 is electrically connected to the drain of M3.

[0212] The gate of M2 is electrically connected to the first scan terminal NG (N), the source of M2 is electrically connected to the gate of M3, and the drain of M2 is electrically connected to the drain of M3.

[0213] The gate of M4 is electrically connected to the second scan terminal PG(N), the source of M4 is electrically connected to the data line D1, and the drain of M4 is electrically connected to the source of M3.

[0214] The gate of M5 is electrically connected to the light-emitting control terminal E(N), the source of M5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of M5 is electrically connected to the source of M3.

[0215] The gate of M6 is electrically connected to the light-emitting control terminal E(N), the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1, and the cathode of O1 is electrically connected to the low-level terminal ELVSS.

[0216] The gate of M7 is electrically connected to the fourth reset terminal RST2, the source of M7 is electrically connected to the initial voltage terminal I1, and the drain of M7 is electrically connected to the anode of O1.

[0217] Figure 7 When the related pixel circuit shown is in operation, NG(N) can control whether the data voltage Vdata on the data line D1 is written to the gate of the driving transistor M3.

[0218] In practical implementation, the first scan signal provided by NG(N) can be used to control the opening or closing of the second transistor, thereby controlling whether the data voltage on the data line is written to the gate of the driving transistor, and thus controlling whether the brightness of the current row of pixel circuits is updated. When NG(N) outputs a high voltage signal, the second transistor is turned on, and the brightness of the current row of pixel circuits can be updated. When NG(N) outputs a low voltage signal, the second transistor is always turned off, and the change in data voltage on the data line is not written to the gate of the driving transistor, so the brightness of the organic light-emitting diode does not change, that is, the display brightness of the current row of pixel circuits remains unchanged in the current frame. In summary, the pixel brightness can be refreshed by controlling the opening or closing of the N-type transistor. Therefore, when it is desired that some pixels are not refreshed, the N-type transistor should be kept off.

[0219] Optionally, the m-th gating circuit is used to control the writing of the m-th gating input signal provided by the m-th gating input terminal into the m-th first node when the potential of the N-1-th driving signal is a first voltage and the potential of the N-th driving signal is a second voltage.

[0220] In a specific implementation, the m-th gating circuit can control the writing of the m-th gating input signal into the m-th first node when the potential of the (N-1)-th driving signal is the first voltage and the potential of the N-th driving signal is the second voltage.

[0221] Optionally, the first voltage can be a high voltage, and the second voltage can be a low voltage, but this is not a limitation. In at least one embodiment of the present invention, the first voltage can also be a low voltage, and the second voltage can be a high voltage.

[0222] Optionally, the m-th gating control terminal includes the m-th first control terminal, the m-th second control terminal, the m-th third control terminal, and the m-th fourth control terminal, and the m-th gating circuit includes the m-th first gating transistor, the m-th second gating transistor, the m-th third gating transistor, and the m-th fourth gating transistor;

[0223] The gate of the m-th first gating transistor is electrically connected to the m-th first control terminal, and the first terminal of the m-th first gating transistor is electrically connected to the m-th gating input terminal.

[0224] The gate of the m-th second selection transistor is electrically connected to the m-th second control terminal, and the first terminal of the m-th second selection transistor is electrically connected to the m-th selection input terminal;

[0225] The gate of the m-th third gate transistor is electrically connected to the m-th third control terminal, the first terminal of the m-th third gate transistor is electrically connected to the second terminal of the m-th first gate transistor, and the second terminal of the m-th third gate transistor is electrically connected to the m-th first node.

[0226] The gate of the m-th fourth selection transistor is electrically connected to the m-th fourth control terminal, the first terminal of the m-th fourth selection transistor is electrically connected to the second terminal of the m-th second selection transistor, and the second terminal of the m-th fourth selection transistor is electrically connected to the m-th first node.

[0227] The m-th first gating transistor is a p-type transistor, the m-th second gating transistor is an n-type transistor, the m-th third gating transistor is a p-type transistor, and the m-th fourth gating transistor is an n-type transistor;

[0228] The m-th first control terminal is connected to the inverted signal of the (N-1)-th level drive signal, the m-th second control terminal is the output terminal of the (N-1)-th level drive signal, the m-th third control terminal is the output terminal of the N-th level drive signal, and the m-th fourth control terminal is connected to the inverted signal of the N-th level drive signal; or, the m-th first control terminal is connected to the inverted signal of the N-th level drive signal, the m-th second control terminal is the output terminal of the N-th level drive signal, the m-th third control terminal is the output terminal of the (N-1)-th level drive signal, and the m-th fourth control terminal is connected to the inverted signal of the (N-1)-th level drive signal.

[0229] like Figure 8 As shown, the gating control terminal may include a first control terminal CT1, a second control terminal CT2, a third control terminal CT3 and a fourth control terminal CT4, and at least one embodiment of the gating circuit may include a first gating transistor TX1, a second gating transistor TX2, a third gating transistor TX3 and a fourth gating transistor TX4;

[0230] The gate of the first selection transistor TX1 is electrically connected to the first control terminal CT1, and the drain of the first selection transistor TX1 is electrically connected to the selection input terminal VCT.

[0231] The gate of the second selection transistor TX2 is electrically connected to the second control terminal CT2, and the drain of the second selection transistor TX2 is electrically connected to the selection input terminal VCT.

[0232] The gate of the third gate transistor TX3 is electrically connected to the third control terminal CT3, the drain of the third gate transistor TX3 is electrically connected to the source of the first gate transistor TX1, and the source of the third gate transistor TX3 is electrically connected to the first node N1.

[0233] The gate of the fourth gate transistor TX4 is electrically connected to the fourth control terminal CT4, the drain of the fourth gate transistor TX4 is electrically connected to the source of the second gate transistor TX2, and the source of the fourth gate transistor TX4 is electrically connected to the first node N1.

[0234] The first selection transistor TX1 is a p-type transistor, the second selection transistor TX2 is an n-type transistor, the third selection transistor TX3 is a p-type transistor, and the fourth selection transistor TX4 is an n-type transistor;

[0235] The first control terminal CT1 can be connected to the inverted signal of the (N-1)th stage drive signal, the second control terminal CT2 can be the output terminal of the (N-1)th stage drive signal, the third control terminal CT3 can be the output terminal of the Nth stage drive signal, and the fourth control terminal CT4 can be connected to the inverted signal of the Nth stage drive signal; or, the first control terminal CT1 can be connected to the inverted signal of the Nth stage drive signal, the second control terminal CT2 can be the output terminal of the Nth stage drive signal, the third control terminal CT3 can be the output terminal of the (N-1)th stage drive signal, and the fourth control terminal CT4 can be connected to the inverted signal of the (N-1)th stage drive signal.

[0236] In at least one embodiment of the present invention, the second terminal of the m-th first gating transistor is electrically connected to the second terminal of the m-th second gating transistor.

[0237] like Figure 9 As shown, in Figure 8 Based on at least one embodiment of the gating circuit shown, the source of the first gating transistor TX1 is electrically connected to the source of the second gating transistor TX2.

[0238] Optionally, the m-th gating circuit includes the m-th first gating transistor;

[0239] The gate of the m-th first selection transistor is electrically connected to the m-th selection control terminal, the first terminal of the m-th first selection transistor is electrically connected to the m-th first node, and the second terminal of the m-th first selection transistor is electrically connected to the m-th selection input terminal.

[0240] like Figure 10 As shown, at least one embodiment of the gating circuit may include a first gating transistor TX1;

[0241] The gate of the first selection transistor TX1 is electrically connected to the selection control terminal S0, the drain of the first selection transistor TX1 is electrically connected to the first node N1, and the source of the first selection transistor TX1 is electrically connected to the selection input terminal VCT.

[0242] TX1 is a p-type transistor.

[0243] like Figure 11 As shown, at least one embodiment of the gating circuit may include a first gating transistor TX1;

[0244] The gate of the first selection transistor TX1 is electrically connected to the selection control terminal S0, the source of the first selection transistor TX1 is electrically connected to the first node N1, and the drain of the first selection transistor TX1 is electrically connected to the selection input terminal VCT.

[0245] TX1 is an n-type transistor.

[0246] Optionally, the m-th gating control terminal includes the m-th first control terminal and the m-th second control terminal; the m-th gating circuit includes the m-th first gating transistor and the m-th second gating transistor;

[0247] The gate of the m-th first gating transistor is electrically connected to the m-th first control terminal, the first terminal of the m-th first gating transistor is electrically connected to the m-th first node, and the second terminal of the m-th first gating transistor is electrically connected to the first terminal of the m-th second gating transistor.

[0248] The gate of the m-th second gating transistor is electrically connected to the m-th second control terminal, and the second terminal of the m-th second gating transistor is electrically connected to the m-th gating input terminal;

[0249] The m-th first control terminal is the output terminal of the (N-1)-th stage drive signal, the m-th second control terminal is the output terminal of the N-th stage drive signal, the m-th first gating transistor is an n-type transistor, and the m-th second gating transistor is a p-type transistor; or...

[0250] The m-th first control terminal is the N-th stage drive signal output terminal, the m-th second control terminal is the (N-1)-th stage drive signal output terminal, the m-th first gating transistor is a p-type transistor, and the m-th second gating transistor is an n-type transistor; or...

[0251] The m-th first control terminal is connected to the inverted signal of the (N-1)-th stage drive signal, the m-th second control terminal is the output terminal of the N-th stage drive signal, and both the m-th first gating transistor and the m-th second gating transistor are p-type transistors; or...

[0252] The m-th first control terminal is the output terminal of the N-th stage drive signal, and the m-th second control terminal is connected to the inverted signal of the (N-1)-th stage drive signal; both the m-th first gating transistor and the m-th second gating transistor are p-type transistors; or...

[0253] The m-th first control terminal is the (N-1)-th stage drive signal terminal, the m-th second control terminal is connected to the inverted signal of the N-th stage drive signal, and both the m-th first gating transistor and the m-th second gating transistor are n-type transistors; or,

[0254] The m-th first control terminal is connected to the inverted signal of the N-th level drive signal, the m-th second control terminal is the N-1 level drive signal terminal, and the m-th first gating transistor and the m-th second gating transistor are both n-type transistors.

[0255] like Figure 12 As shown, at least one embodiment of the gating circuit may include a first gating transistor TX1 and a second gating transistor TX2;

[0256] The gate of the first selection transistor TX1 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the source of the first selection transistor TX1 is electrically connected to the first node N1, and the drain of the first selection transistor TX1 is electrically connected to the drain of the second selection transistor TX2.

[0257] The gate of the second gating transistor TX2 is electrically connected to the Nth stage drive signal output terminal NS(N), and the source of the second gating transistor TX2 is electrically connected to the gating input terminal VCT.

[0258] TX1 is an n-type transistor, and TX2 is a p-type transistor.

[0259] like Figure 13 As shown, at least one embodiment of the gating circuit may include a first gating transistor TX1 and a second gating transistor TX2;

[0260] The gate of the first gating transistor TX1 is electrically connected to the Nth stage drive signal output terminal NS(N), the drain of the first gating transistor TX1 is electrically connected to the first node N1, and the source of the first gating transistor TX1 is electrically connected to the source of the second gating transistor T2.

[0261] The gate of the second gating transistor TX2 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), and the drain of the second gating transistor TX2 is electrically connected to the gating input terminal VCT.

[0262] TX1 is a p-type transistor, and TX2 is an n-type transistor.

[0263] like Figure 14 As shown, at least one embodiment of the gating circuit may include a first gating transistor TX1 and a second gating transistor TX2;

[0264] The gate of the first gating transistor TX1 is electrically connected to the first inverting drive signal terminal NGI1, the drain of the first gating transistor TX1 is electrically connected to the first node N1, and the source of the first gating transistor TX1 is electrically connected to the drain of the second gating transistor TX2; the first inverting drive signal provided by the first inverting drive signal terminal NGI1 is inverted with the N-1th stage drive signal provided by the N-1th stage drive signal output terminal NS(N-1);

[0265] The gate of the second gating transistor TX2 is electrically connected to the Nth stage drive signal output terminal NS(N), and the source of the second gating transistor TX2 is electrically connected to the gating input terminal VCT.

[0266] TX1 is a p-type transistor, and TX2 is a p-type transistor.

[0267] like Figure 15 As shown, at least one embodiment of the gating circuit may include a first transistor TX1 and a second transistor TX2;

[0268] The gate of the first gate transistor TX1 is electrically connected to the Nth stage drive signal output terminal NS(N), the drain of the first gate transistor TX1 is electrically connected to the first node N1, and the source of the first gate transistor TX1 is electrically connected to the drain of the second gate transistor TX2.

[0269] The gate of the second gating transistor TX2 is electrically connected to the first inverting drive signal terminal NGI1, and the source of the second gating transistor TX2 is electrically connected to the gating input terminal VCT; the first inverting drive signal provided by the first inverting drive signal terminal NGI1 is inverted with the N-1 stage drive signal provided by the N-1 stage drive signal output terminal NS(N-1);

[0270] TX1 is a p-type transistor, and TX2 is a p-type transistor.

[0271] like Figure 16 As shown, at least one embodiment of the gating circuit may include a first gating transistor TX1 and a second gating transistor TX2;

[0272] The gate of the first selection transistor TX1 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the source of the first selection transistor TX1 is electrically connected to the first node N1, and the drain of the first selection transistor TX1 is electrically connected to the source of the second selection transistor TX2.

[0273] The gate of the second gating transistor TX2 is electrically connected to the second inverting drive signal terminal NGI2, and the drain of the second gating transistor TX2 is electrically connected to the gating input terminal VCT; the second inverting drive signal provided by the second inverting drive signal terminal NGI2 is inverted with the Nth stage drive signal provided by the Nth stage drive signal output terminal NS(N);

[0274] TX1 is an n-type transistor, and TX2 is an n-type transistor.

[0275] like Figure 17 As shown, at least one embodiment of the gating circuit may include a first gating transistor TX1 and a second gating transistor TX2;

[0276] The gate of the first gate transistor TX1 is electrically connected to the second inverting drive signal terminal NGI2, the source of the first gate transistor TX1 is electrically connected to the first node N1, and the drain of the first gate transistor TX1 is electrically connected to the source of the second gate transistor TX2; the second inverting drive signal provided by the second inverting drive signal terminal NGI2 is inverted with the Nth stage drive signal provided by the Nth stage drive signal output terminal NS(N);

[0277] The gate of the second gating transistor TX2 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), and the drain of the second gating transistor TX2 is electrically connected to the gating input terminal VCT.

[0278] TX1 is an n-type transistor, and TX2 is an n-type transistor.

[0279] like Figure 18 As shown, the N-1 stage drive signal provided by the N-1 stage drive signal output terminal NS(N-1) can be inverted by the first inverting module to obtain the first inverted drive signal provided by the first inverted drive signal terminal NGI1;

[0280] The first inverting module includes a first inverting control transistor T01 and a second inverting control transistor T02;

[0281] T01 is a p-type transistor, and T02 is an n-type transistor.

[0282] like Figure 19 As shown, the Nth stage drive signal provided by the Nth stage drive signal output terminal NS(N) can be inverted by the second inverting module to obtain the second inverted drive signal provided by the second inverted drive signal terminal NGI2;

[0283] The second inverting module includes a third inverting control transistor T03 and a fourth inverting control transistor T04;

[0284] T03 is a p-type transistor, and T04 is an n-type transistor.

[0285] In at least one embodiment of the present invention, the m-th control circuit further includes the m-th first initialization circuit;

[0286] The m-th first initialization circuit is electrically connected to the initial control terminal, the first voltage terminal, and the m-th first node, respectively, and is used to control the connection between the m-th first node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0287] In a specific implementation, the m-th control circuit may further include the m-th first initialization circuit, which, under the control of the initial control signal, controls the connection between the m-th first node and the first voltage terminal.

[0288] In at least one embodiment of the present invention, the first voltage terminal may be a high voltage terminal, but is not limited thereto.

[0289] like Figure 20 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown, the control circuit may further include a first initialization circuit 21;

[0290] The first initialization circuit 21 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the first node N1 respectively, and is used to control the connection between the first node N1 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0291] Figure 20 In at least one embodiment of the driving circuit shown, when in operation, at the start of a frame time, NCX provides an effective voltage signal, and the first initialization circuit 21 controls the connection between the first node N1 and the first voltage terminal V1.

[0292] like Figure 21 As shown, in Figure 4 Based on at least one embodiment of the driving circuit shown, the first control circuit may further include a first initialization circuit 211, and the second control circuit may further include a second first initialization circuit 212.

[0293] The first initialization circuit 211 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the first first node N11 respectively, and is used to control the connection between the first first node N11 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0294] The second first initialization circuit 212 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the second first node N21 respectively, and is used to control the connection between the second first node N21 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0295] In at least one embodiment of the present invention, the m-th control circuit further includes an m-th reset circuit;

[0296] The m-th reset circuit is electrically connected to the first voltage terminal, the (N-1)-th level drive signal output terminal, the N-th level drive signal output terminal, and the m-th first node, respectively, and is used to control the connection between the m-th first node and the first voltage terminal under the control of the N-th level drive signal and the (N-1)-th level drive signal provided by the (N-1)-th level drive signal output terminal.

[0297] In a specific implementation, the m-th control circuit may further include an m-th reset circuit. Under the control of the N-th drive signal and the (N-1)-th drive signal, the m-th reset circuit resets the potential of the m-th first node after the m-th output circuit provides the m-th output drive signal through the m-th output drive terminal.

[0298] In at least one embodiment of the present invention, the m-th control circuit further includes the m-th first voltage sustaining circuit;

[0299] The first terminal of the m-th first voltage maintenance circuit is electrically connected to the m-th first node, and the second terminal of the m-th first voltage maintenance circuit is electrically connected to the DC voltage terminal. The m-th voltage maintenance circuit is used to maintain the potential of the m-th first node.

[0300] In a specific implementation, the m-th control circuit may further include the m-th first voltage maintenance circuit, which can be used to maintain the potential of the m-th first node.

[0301] Optionally, the DC voltage terminal can be a first voltage terminal, a second voltage terminal, or a third voltage terminal, but is not limited thereto.

[0302] In at least one embodiment of the present invention, the first voltage terminal may be a high voltage terminal, the second voltage terminal may be a first low voltage terminal, and the third voltage terminal may be a second low voltage terminal, but is not limited thereto.

[0303] like Figure 22 As shown, in Figure 20 Based on at least one embodiment of the driving circuit shown, the control circuit may further include a first voltage sustaining circuit 22 and a reset circuit 23;

[0304] The reset circuit 23 is electrically connected to the first voltage terminal V1, the (N-1)th stage drive signal output terminal NS(N-1), the Nth stage drive signal output terminal NS(N), and the first node N1, respectively, and is used to control the connection between the first node N1 and the first voltage terminal V1 under the control of the Nth stage drive signal and the N-1th stage drive signal output terminal NS(N-1).

[0305] The first terminal of the first voltage sustaining circuit 22 is electrically connected to the first node N1, and the second terminal of the first voltage sustaining circuit 22 is electrically connected to the second voltage terminal V2. The first voltage sustaining circuit 22 is used to maintain the potential of the first node N1.

[0306] like Figure 23 As shown, in Figure 21 Based on at least one embodiment of the driving circuit shown, the first control circuit may further include a first first voltage sustaining circuit 221 and a first reset circuit 231; the second control circuit may further include a second first voltage sustaining circuit 222 and a second reset circuit 232.

[0307] The first reset circuit 231 is electrically connected to the first voltage terminal V1, the (N-1)th stage drive signal output terminal NS(N-1), the Nth stage drive signal output terminal NS(N), and the first first node N11, respectively, and is used to control the connection between the first first node N11 and the first voltage terminal V1 under the control of the Nth stage drive signal and the N-1th stage drive signal output terminal NS(N-1).

[0308] The first terminal of the first voltage sustaining circuit 221 is electrically connected to the first first node N11, and the second terminal of the first voltage sustaining circuit 221 is electrically connected to the second voltage terminal V2. The first voltage sustaining circuit 221 is used to maintain the potential of the first first node N11.

[0309] The second reset circuit 232 is electrically connected to the first voltage terminal V1, the (N-1)th stage drive signal output terminal NS(N-1), the Nth stage drive signal output terminal NS(N), and the second first node N21, respectively, and is used to control the connection between the second first node N21 and the first voltage terminal V1 under the control of the Nth stage drive signal and the N-1th stage drive signal output terminal NS(N-1).

[0310] The first terminal of the second first voltage sustaining circuit 222 is electrically connected to the second first node N21, and the second terminal of the second first voltage sustaining circuit 222 is electrically connected to the second voltage terminal V2. The second first voltage sustaining circuit 222 is used to maintain the potential of the second first node N21.

[0311] Optionally, the m-th control circuit further includes the m-th second voltage sustaining circuit; the m-th first node is electrically connected to the second terminal of the m-th output control circuit through the m-th second voltage sustaining circuit;

[0312] The m-th second voltage sustaining circuit includes the m-th first inverter, the m-th second inverter, and the m-th sustaining control circuit;

[0313] The input terminal of the m-th first inverter is electrically connected to the m-th first node, the output terminal of the m-th first inverter is electrically connected to the m-th second node, the input terminal of the m-th second inverter is electrically connected to the m-th second node, and the output terminal of the m-th second inverter is electrically connected to the m-th third node and the second terminal of the m-th output control circuit.

[0314] The m-th first inverter is used to invert the potential of the m-th first node and output the inverted potential of the m-th first node through the output terminal of the m-th first inverter. The m-th second inverter is used to invert the potential of its input terminal and output the inverted potential through the output terminal of the m-th second inverter.

[0315] The m-th maintenance control circuit is electrically connected to the m-th maintenance control terminal, the m-th third node, and the m-th first node, respectively, and is used to control the connection or disconnection between the m-th third node and the m-th first node under the control of the m-th maintenance control signal provided by the m-th maintenance control terminal.

[0316] In a specific implementation, the m-th control circuit may further include the m-th second voltage sustaining circuit. The m-th first node can be electrically connected to the second terminal of the m-th output control circuit through the m-th second voltage sustaining circuit. The m-th second voltage sustaining circuit may include the m-th first inverter, the m-th second inverter, and the m-th sustaining control circuit. The m-th first inverter inverts the potential of the m-th first node, and the m-th second inverter inverts the potential of its input terminal. Under the control of the sustaining control signal provided by the m-th sustaining control terminal, the m-th sustaining control circuit controls the connection or disconnection between the m-th third node and the m-th first node.

[0317] The m-th maintenance control circuit can disconnect the m-th third node from the m-th first node when the m-th gating circuit controls the writing of the m-th gating input signal into the m-th first node.

[0318] When the driving circuit described in at least one embodiment of the present invention is in operation, by adding a second voltage sustaining circuit, the second voltage sustaining circuit includes a first inverter and a second inverter. When the potential of the first node is high, the second inverter controls the connection between the third node and the high voltage terminal, so that the potential of the third node is higher than that of the first node. When the potential of the first node is low, the third inverter controls the connection between the third node and the low voltage terminal, so that the potential of the third node is lower than that of the first node. This allows the third node to better control the transistor whose gate is electrically connected to the third node in the output control circuit.

[0319] like Figure 24 As shown, in Figure 22 Based on at least one embodiment of the driving circuit shown, the control circuit may further include a second voltage sustaining circuit; the sustaining control terminal includes an N-1 stage driving signal output terminal NS(N-1) and a control clock signal terminal NCK; the first node N1 is electrically connected to the second terminal of the output control circuit 12 through the second voltage sustaining circuit;

[0320] The second voltage sustaining circuit includes a first inverter F1, a second inverter F2, and a sustaining control circuit W1;

[0321] The input terminal of the first inverter F1 is electrically connected to the first node N1, and the output terminal of the first inverter F1 is electrically connected to the second node N2.

[0322] The input terminal of the second inverter F2 is electrically connected to the second node N2, and the output terminal of the second inverter F2 is electrically connected to the third node N3 and the second terminal of the output control circuit 12.

[0323] The first inverter F1 is used to invert the potential of the first node N1, and outputs the inverted potential of the first node N1 through the output terminal of the first inverter F1.

[0324] The second inverter F2 is used to invert the potential at its input terminal and output the inverted potential through the output terminal of the second inverter F2;

[0325] The sustaining control circuit W1 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the control clock signal terminal NCK, the third node N3, and the first node N1, respectively. It is used to control the connection or disconnection between the third node N3 and the first node N1 under the control of the N-1th stage drive signal provided by the N-1th stage drive signal output terminal NS(N-1), and to control the connection or disconnection between the third node N3 and the first node N1 under the control of the control clock signal provided by the control clock signal terminal NCK.

[0326] exist Figure 24 In at least one embodiment shown, the N-1th stage drive signal output terminal can be replaced with an inverted clock signal terminal or a first clock signal terminal, but is not limited thereto.

[0327] Figure 25 The waveforms of the control clock signal provided by the control clock signal terminal NCK and the first clock signal provided by the first clock signal terminal NCB are shown.

[0328] In at least one embodiment of the present invention, the drive signal generation circuit includes a first drive control circuit, a second drive control circuit, a second inverting circuit, and a second initialization circuit.

[0329] The first drive control circuit is electrically connected to the control clock signal terminal, the inverted clock signal terminal, the N-1th stage drive signal output terminal and the fourth node, respectively. Under the control of the control clock signal provided by the control clock signal terminal and the inverted clock signal provided by the inverted clock signal terminal, the N-1th stage drive signal output terminal is shifted and inverted to obtain the inverted signal output through the fourth node.

[0330] The second drive control circuit is electrically connected to the control clock signal terminal, the inverted clock signal terminal, the Nth stage drive signal output terminal, and the fourth node, respectively. It is used to invert the Nth stage drive signal provided by the Nth stage drive signal output terminal under the control of the control clock signal and the inverted clock signal, so as to obtain the inverted signal and output it through the fourth node.

[0331] The second inverting circuit is electrically connected to the fourth node and the Nth stage drive signal output terminal, respectively, and is used to invert the potential of the fourth node and output the inverted signal through the Nth stage drive signal output terminal;

[0332] The second initialization circuit is electrically connected to the initial control terminal, the first voltage terminal, and the Nth stage drive signal output terminal, respectively, and is used to control the connection between the Nth stage drive signal output terminal and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0333] In at least one embodiment of the present invention, when M equals 1, the control circuit may include a first voltage sustaining circuit and / or a second voltage sustaining circuit to maintain the potential of the first node;

[0334] When M is greater than 1, the m-th control circuit may include the m-th first voltage sustaining circuit and / or the m-th second voltage sustaining circuit to maintain the potential of the m-th first node.

[0335] Optionally, the m-th reset circuit includes the m-th first transistor and the m-th second transistor;

[0336] The gate of the m-th first transistor is electrically connected to the output terminal of the (N-1)-th stage drive signal, the first terminal of the m-th first transistor is electrically connected to the first voltage terminal, and the second terminal of the m-th first transistor is electrically connected to the first terminal of the m-th second transistor.

[0337] The gate of the m-th second transistor is electrically connected to the output terminal of the N-th drive signal, and the second electrode of the m-th second transistor is electrically connected to the m-th first node.

[0338] Optionally, the m-th maintenance control terminal includes the m-th first maintenance control terminal and the m-th second maintenance control terminal;

[0339] The m-th sustaining control circuit includes the m-th third transistor and the m-th fourth transistor;

[0340] The gate of the m-th third transistor is electrically connected to the m-th first sustaining control terminal, the first electrode of the m-th third transistor is electrically connected to the m-th first node, and the second electrode of the m-th third transistor is electrically connected to the m-th third node.

[0341] The gate of the m-th fourth transistor is electrically connected to the m-th second sustain control terminal, the first terminal of the m-th fourth transistor is electrically connected to the m-th third node, and the second terminal of the m-th fourth transistor is electrically connected to the m-th first node.

[0342] The m-th third transistor is a p-type transistor, and the m-th fourth transistor is an n-type transistor;

[0343] The m-th first sustain control terminal is the (N-1)-th stage drive signal terminal, and the m-th second sustain control terminal is the control clock signal terminal; or...

[0344] The m-th first sustain control terminal is an inverting clock signal terminal, and the m-th second sustain control terminal is a control clock signal terminal.

[0345] Optionally, the m-th first inverter includes the m-th fifth transistor and the m-th sixth transistor, and the m-th second inverter includes the m-th seventh transistor and the m-th eighth transistor;

[0346] The gate of the m-th fifth transistor is electrically connected to the m-th first node, the first electrode of the m-th fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the m-th fifth transistor is electrically connected to the m-th second node.

[0347] The gate of the m-th sixth transistor is electrically connected to the m-th first node, the first terminal of the m-th sixth transistor is electrically connected to the m-th second node, and the second terminal of the m-th sixth transistor is electrically connected to the second voltage terminal.

[0348] The m-th fifth transistor is a p-type transistor, and the m-th sixth transistor is an n-type transistor;

[0349] The gate of the m-th seventh transistor is electrically connected to the m-th second node, the first terminal of the m-th seventh transistor is electrically connected to the first voltage terminal, and the second terminal of the m-th seventh transistor is electrically connected to the m-th third node;

[0350] The gate of the m-th eighth transistor is electrically connected to the m-th second node, the first terminal of the m-th eighth transistor is electrically connected to the m-th third node, and the second terminal of the m-th eighth transistor is electrically connected to the second voltage terminal.

[0351] The m-th seventh transistor is a p-type transistor, and the m-th eighth transistor is an n-type transistor.

[0352] Optionally, the m-th first initialization circuit includes the m-th ninth transistor;

[0353] The gate of the m-th ninth transistor is electrically connected to the initial control terminal, the first terminal of the m-th ninth transistor is electrically connected to the first voltage terminal, and the second terminal of the m-th ninth transistor is electrically connected to the m-th first node.

[0354] Optionally, the m-th first voltage sustaining circuit includes the m-th capacitor;

[0355] The first terminal of the m-th capacitor is electrically connected to the m-th first node, and the second terminal of the m-th capacitor is electrically connected to the DC voltage terminal.

[0356] Optionally, the m-th output control circuit includes the m-th tenth transistor, the m-th eleventh transistor, the m-th twelfth transistor, and the m-th thirteenth transistor;

[0357] The gate of the m-th tenth transistor is electrically connected to the m-th first node, the first electrode of the m-th tenth transistor is electrically connected to the first voltage terminal, and the second electrode of the m-th tenth transistor is electrically connected to the m-th second node.

[0358] The gate of the m-th eleventh transistor is electrically connected to the output terminal of the N-th drive signal, the first electrode of the m-th eleventh transistor is electrically connected to the first voltage terminal, and the second electrode of the m-th eleventh transistor is electrically connected to the m-th second node.

[0359] The gate of the m-th twelfth transistor is electrically connected to the m-th first node, the first terminal of the m-th twelfth transistor is electrically connected to the m-th second node, and the second terminal of the m-th twelfth transistor is electrically connected to the first terminal of the m-th thirteenth transistor.

[0360] The gate of the m-th thirteenth transistor is electrically connected to the N-level drive signal output terminal, and the second terminal of the m-th thirteenth transistor is electrically connected to the second voltage terminal.

[0361] The m-th tenth transistor and the m-th eleventh transistor are p-type transistors, and the m-th twelfth transistor and the m-th thirteenth transistor are n-type transistors.

[0362] Optionally, the m-th output circuit includes the m-th fourteenth transistor and the m-th fifteenth transistor;

[0363] The gate of the m-th fourteenth transistor is electrically connected to the m-th second node, the first terminal of the m-th fourteenth transistor is electrically connected to the first voltage terminal, and the second terminal of the m-th fourteenth transistor is electrically connected to the m-th output drive terminal.

[0364] The gate of the m-th fifteenth transistor is electrically connected to the m-th second node, the first terminal of the m-th fifteenth transistor is electrically connected to the m-th output drive terminal, and the second terminal of the m-th fifteenth transistor is electrically connected to the second voltage terminal.

[0365] In at least one embodiment of the present invention, the drive signal generation circuit includes a first drive control circuit, a second drive control circuit, a second inverting circuit, and a second initialization circuit.

[0366] The first drive control circuit is electrically connected to the control clock signal terminal, the inverted clock signal terminal, the N-1th stage drive signal output terminal and the fourth node, respectively. Under the control of the control clock signal provided by the control clock signal terminal and the inverted clock signal provided by the inverted clock signal terminal, the N-1th stage drive signal output terminal is shifted and inverted to obtain the inverted signal output through the fourth node.

[0367] The second drive control circuit is electrically connected to the control clock signal terminal, the inverted clock signal terminal, the Nth stage drive signal output terminal, and the fourth node, respectively. It is used to invert the Nth stage drive signal provided by the Nth stage drive signal output terminal under the control of the control clock signal and the inverted clock signal, so as to obtain the inverted signal and output it through the fourth node.

[0368] The second inverting circuit is electrically connected to the fourth node and the Nth stage drive signal output terminal, respectively, and is used to invert the potential of the fourth node and output the inverted signal through the Nth stage drive signal output terminal;

[0369] The second initialization circuit is electrically connected to the initial control terminal, the first voltage terminal, and the Nth stage drive signal output terminal, respectively, and is used to control the connection between the Nth stage drive signal output terminal and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0370] In a specific implementation, the drive signal generation circuit may include a first drive control circuit, a second drive control circuit, a second inverting circuit, and a second initialization circuit. Under the control of a control clock signal and an inverting clock signal, the first drive control circuit shifts and inverts the (N-1)th drive signal, and outputs the inverted signal through the fourth node. Under the control of the control clock signal and the inverting clock signal, the second drive control circuit inverts the Nth stage drive signal, and outputs the inverted signal through the fourth node. The second inverting circuit inverts the potential of the fourth node, and outputs the inverted signal through the Nth stage drive signal output terminal. Under the control of an initial control signal, the second initialization circuit controls the connection between the Nth stage drive signal output terminal and the first voltage terminal.

[0371] like Figure 26 As shown, in Figure 24 Based on at least one embodiment of the driving circuit shown, the driving signal generation circuit may include a first driving control circuit 41, a second driving control circuit 42, a second inverting circuit 44, and a second initialization circuit 40.

[0372] The first drive control circuit 41 is electrically connected to the control clock signal terminal NCK, the inverted clock signal terminal NCKI, the N-1th stage drive signal output terminal NS(N-1), and the fourth node N4, respectively. Under the control of the control clock signal provided by the control clock signal terminal NCK and the inverted clock signal provided by the inverted clock signal terminal NCKI, it shifts and inverts the N-1th stage drive signal provided by the N-1th stage drive signal output terminal NS(N-1) to obtain the inverted signal output through the fourth node N4.

[0373] The second drive control circuit 42 is electrically connected to the control clock signal terminal NCK, the inverted clock signal terminal NCKI, the Nth stage drive signal output terminal NS(N), and the fourth node N4, respectively. It is used to invert the Nth stage drive signal provided by the Nth stage drive signal output terminal NS(N) under the control of the control clock signal and the inverted clock signal, so as to obtain the inverted signal and output it through the fourth node N4.

[0374] The second inverter circuit 44 is electrically connected to the fourth node N4 and the Nth stage drive signal output terminal NS(N) respectively, and is used to invert the potential of the fourth node N4 and output the inverted signal through the Nth stage drive signal output terminal NS(N);

[0375] The second initialization circuit 40 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the Nth stage drive signal output terminal NS(N), respectively, and is used to control the connection between the Nth stage drive signal output terminal NS(N) and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0376] like Figure 27 As shown, in Figure 23 Based on at least one embodiment of the driving circuit shown, the driving signal generation circuit may include a first driving control circuit 41, a second driving control circuit 42, a second inverting circuit 44, and a second initialization circuit 40.

[0377] The first drive control circuit 41 is electrically connected to the control clock signal terminal NCK, the inverted clock signal terminal NCKI, the N-1th stage drive signal output terminal NS(N-1), and the fourth node N4, respectively. Under the control of the control clock signal provided by the control clock signal terminal NCK and the inverted clock signal provided by the inverted clock signal terminal NCKI, it shifts and inverts the N-1th stage drive signal provided by the N-1th stage drive signal output terminal NS(N-1) to obtain the inverted signal output through the fourth node N4.

[0378] The second drive control circuit 42 is electrically connected to the control clock signal terminal NCK, the inverted clock signal terminal NCKI, the Nth stage drive signal output terminal NS(N), and the fourth node N4, respectively. It is used to invert the Nth stage drive signal provided by the Nth stage drive signal output terminal NS(N) under the control of the control clock signal and the inverted clock signal, so as to obtain the inverted signal and output it through the fourth node N4.

[0379] The second inverter circuit 44 is electrically connected to the fourth node N4 and the Nth stage drive signal output terminal NS(N) respectively, and is used to invert the potential of the fourth node N4 and output the inverted signal through the Nth stage drive signal output terminal NS(N);

[0380] The second initialization circuit 40 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the Nth stage drive signal output terminal NS(N), respectively, and is used to control the connection between the Nth stage drive signal output terminal NS(N) and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0381] Figure 28 At least one embodiment of the driving circuit shown is Figure 26 The difference in at least one embodiment of the driving circuit shown is that it does not include a second voltage sustaining circuit.

[0382] Optionally, the first drive control circuit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor;

[0383] The gate of the sixteenth transistor is electrically connected to the inverting clock signal terminal, the first terminal of the sixteenth transistor is electrically connected to the first voltage terminal, and the second terminal of the sixteenth transistor is electrically connected to the first terminal of the seventeenth transistor.

[0384] The gate of the seventeenth transistor is electrically connected to the output terminal of the (N-1)th stage drive signal, and the second terminal of the seventeenth transistor is electrically connected to the fourth node;

[0385] The gate of the eighteenth transistor is electrically connected to the output terminal of the (N-1)th stage drive signal, the first terminal of the eighteenth transistor is electrically connected to the fourth node, and the second terminal of the eighteenth transistor is electrically connected to the first terminal of the nineteenth transistor.

[0386] The gate of the nineteenth transistor is electrically connected to the control clock signal terminal, and the second terminal of the nineteenth transistor is electrically connected to the third voltage terminal.

[0387] The sixteenth and seventeenth transistors are p-type transistors, and the eighteenth and nineteenth transistors are n-type transistors.

[0388] Optionally, the second drive control circuit includes a twentieth transistor, a twenty-first transistor, a twenty-second transistor, and a twenty-third transistor;

[0389] The gate of the twentieth transistor is electrically connected to the output terminal of the Nth stage drive signal, the first terminal of the twentieth transistor is electrically connected to the first voltage terminal, and the second terminal of the twentieth transistor is electrically connected to the first terminal of the twentieth eleventh transistor.

[0390] The gate of the 21st transistor is electrically connected to the control clock signal terminal, and the second terminal of the 21st transistor is electrically connected to the fourth node;

[0391] The gate of the 22nd transistor is electrically connected to the inverting clock signal terminal, the first terminal of the 22nd transistor is electrically connected to the fourth node, and the second terminal of the 22nd transistor is electrically connected to the first terminal of the 23rd transistor.

[0392] The gate of the 23rd transistor is electrically connected to the output terminal of the Nth stage drive signal, and the second terminal of the 23rd transistor is electrically connected to the third voltage terminal;

[0393] The twentieth and twentieth transistors are p-type transistors, and the twentieth and twentieth transistors are n-type transistors.

[0394] Optionally, the second inverting circuit includes a twenty-fourth transistor and a twenty-fifth transistor; the second initialization circuit includes a twenty-sixth transistor;

[0395] The gate of the 24th transistor is electrically connected to the fourth node, the first terminal of the 24th transistor is electrically connected to the first voltage terminal, and the second terminal of the 24th transistor is electrically connected to the first terminal of the 25th transistor and the Nth stage drive signal output terminal.

[0396] The gate of the 25th transistor is electrically connected to the fourth node, and the second terminal of the 25th transistor is electrically connected to the third voltage terminal.

[0397] The twenty-fourth transistor is a p-type transistor, and the twenty-fifth transistor is an n-type transistor;

[0398] The gate of the 26th transistor is electrically connected to the initial control terminal, the first terminal of the 26th transistor is electrically connected to the first voltage terminal, and the second terminal of the 26th transistor is electrically connected to the Nth stage drive signal output terminal.

[0399] Optionally, the first inverting circuit includes a twenty-seventh transistor and a twenty-eighth transistor;

[0400] The gate of the 27th transistor is electrically connected to the control clock signal terminal, the first terminal of the 27th transistor is electrically connected to the first voltage terminal, and the second terminal of the 27th transistor is electrically connected to the first terminal of the 28th transistor and the inverting clock signal terminal.

[0401] The gate of the 28th transistor is electrically connected to the control clock signal terminal, and the second terminal of the 28th transistor is electrically connected to the third voltage terminal.

[0402] like Figure 29 As shown, in Figure 28 Based on at least one embodiment of the driving circuit shown,

[0403] The gating control terminal includes a first control terminal, a second control terminal, a third control terminal and a fourth control terminal, and the gating circuit includes a first gating transistor TX1, a second gating transistor TX2, a third gating transistor TX3 and a fourth gating transistor TX4;

[0404] The gate of the first selection transistor TX1 is electrically connected to the first control terminal, and the drain of the first selection transistor TX1 is electrically connected to the selection input terminal VCT.

[0405] The gate of the second selection transistor TX2 is electrically connected to the second control terminal, and the drain of the second selection transistor TX2 is electrically connected to the selection input terminal VCT.

[0406] The gate of the third gate transistor TX3 is electrically connected to the third control terminal, the drain of the third gate transistor TX3 is electrically connected to the source of the first gate transistor TX1, and the source of the third gate transistor TX3 is electrically connected to the first node N1.

[0407] The gate of the fourth gate transistor TX4 is electrically connected to the fourth control terminal, the drain of the fourth gate transistor TX4 is electrically connected to the source of the second gate transistor TX2, and the source of the fourth gate transistor TX4 is electrically connected to the first node N1.

[0408] The first selection transistor TX1 is a p-type transistor, the second selection transistor TX2 is an n-type transistor, the third selection transistor TX3 is a p-type transistor, and the fourth selection transistor TX4 is an n-type transistor;

[0409] The first control terminal is connected to the inverted signal NSI(N-1) of the N-1 level drive signal, the second control terminal is the output terminal NS(N-1) of the N-1 level drive signal, the third control terminal is the output terminal NS(N) of the N level drive signal, and the fourth control terminal is connected to the inverted signal NSI(N) ​​of the N level drive signal.

[0410] The reset circuit includes a first transistor T1 and a second transistor T2;

[0411] The gate of the first transistor T1 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the drain of the first transistor T1 is electrically connected to the high voltage terminal VGHN, and the source of the first transistor T1 is electrically connected to the drain of the second transistor T2.

[0412] The gate of the second transistor T2 is electrically connected to the Nth stage drive signal output terminal NS(N), and the source of the second transistor T2 is electrically connected to the first node N1.

[0413] T1 and T2 are p-type transistors;

[0414] The first initialization circuit includes a ninth transistor T9;

[0415] The gate of the ninth transistor T9 is electrically connected to the initial control terminal NCX, the drain of the ninth transistor T9 is electrically connected to the high voltage terminal VGHN, and the source of the ninth transistor T9 is electrically connected to the first node N1.

[0416] T9 is a p-type transistor;

[0417] The first voltage sustaining circuit includes a capacitor C0;

[0418] The first terminal of capacitor C0 is electrically connected to the first node N1, and the second terminal of capacitor C0 is electrically connected to the first low voltage terminal VGL.

[0419] The output control circuit includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13;

[0420] The gate of the tenth transistor T10 is electrically connected to the first node N1, the drain of the tenth transistor T10 is electrically connected to the high voltage terminal VGHN, and the source of the tenth transistor T10 is electrically connected to the second node N2.

[0421] The gate of the eleventh transistor T11 is electrically connected to the Nth stage drive signal output terminal NS(N), the drain of the eleventh transistor T11 is electrically connected to the high voltage terminal VGHN, and the source of the eleventh transistor T11 is electrically connected to the second node N2.

[0422] The gate of the twelfth transistor T12 is electrically connected to the first node N1, the drain of the twelfth transistor T12 is electrically connected to the second node N2, and the source of the twelfth transistor T12 is electrically connected to the drain of the thirteenth transistor T13.

[0423] The gate of the thirteenth transistor T13 is electrically connected to the N-stage drive signal output terminal NS(N), and the source of the thirteenth transistor T13 is electrically connected to the first low voltage terminal VGL.

[0424] The tenth transistor T10 and the eleventh transistor T11 are p-type transistors, and the twelfth transistor T12 and the thirteenth transistor T13 are n-type transistors;

[0425] The output circuit includes a fourteenth transistor T14 and a fifteenth transistor T15;

[0426] The gate of the fourteenth transistor T14 is electrically connected to the second node N2, the drain of the fourteenth transistor T14 is electrically connected to the high voltage terminal VGHN, and the source of the fourteenth transistor T14 is electrically connected to the output drive terminal NO(N).

[0427] The gate of the fifteenth transistor T15 is electrically connected to the second node N2, the drain of the fifteenth transistor T15 is electrically connected to the output drive terminal NO (N), and the source of the fifteenth transistor T15 is electrically connected to the first low voltage terminal VGL.

[0428] T14 is a p-type transistor, and T15 is a p-type transistor;

[0429] The first drive control circuit includes a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, and a nineteenth transistor T19;

[0430] The gate of the sixteenth transistor T16 is electrically connected to the inverting clock signal terminal NCKI, the drain of the sixteenth transistor T16 is electrically connected to the high voltage terminal VGHN, and the source of the sixteenth transistor T16 is electrically connected to the drain of the seventeenth transistor T17.

[0431] The gate of the seventeenth transistor T17 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), and the source of the seventeenth transistor T17 is electrically connected to the fourth node N4.

[0432] The gate of the eighteenth transistor T18 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the drain of the eighteenth transistor T18 is electrically connected to the fourth node N4, and the source of the eighteenth transistor T18 is electrically connected to the drain of the nineteenth transistor T19.

[0433] The gate of the nineteenth transistor T19 is electrically connected to the control clock signal terminal NCK, and the source of the nineteenth transistor T19 is electrically connected to the second low voltage terminal VGLN.

[0434] The sixteenth transistor T16 and the seventeenth transistor T17 are p-type transistors, and the eighteenth transistor T18 and the nineteenth transistor T19 are n-type transistors;

[0435] The second drive control circuit includes the twentieth transistor T20, the twenty-first transistor T21, the twenty-second transistor T22, and the twenty-third transistor T23;

[0436] The gate of the twentieth transistor T20 is electrically connected to the Nth stage drive signal output terminal NS(N), the drain of the twentieth transistor T20 is electrically connected to the high voltage terminal VGHN, and the source of the twentieth transistor T20 is electrically connected to the drain of the twentieth eleventh transistor T21.

[0437] The gate of the 21st transistor T21 is electrically connected to the control clock signal terminal NCK, and the source of the 21st transistor T21 is electrically connected to the fourth node N4.

[0438] The gate of the 22nd transistor T22 is electrically connected to the inverting clock signal terminal NCKI, the drain of the 22nd transistor T22 is electrically connected to the fourth node N4, and the source of the 22nd transistor T22 is electrically connected to the drain of the 23rd transistor T23.

[0439] The gate of the 23rd transistor T23 is electrically connected to the Nth stage drive signal output terminal NS(N), and the source of the 23rd transistor T23 is electrically connected to the second low voltage terminal VGLN.

[0440] The twentieth transistor T20 and the twenty-first transistor T21 are p-type transistors, and the twenty-second transistor T22 and the twenty-third transistor T23 are n-type transistors;

[0441] The second inverting circuit includes a twenty-fourth transistor T24 and a twenty-fifth transistor T25; the second initialization circuit includes a twenty-sixth transistor T26.

[0442] The gate of the 24th transistor T24 is electrically connected to the fourth node N4, the drain of the 24th transistor T24 is electrically connected to the high voltage terminal VGHN, and the source of the 24th transistor T24 is electrically connected to the drain of the 25th transistor T25 and the Nth stage drive signal output terminal NS(N).

[0443] The gate of the 25th transistor T25 is electrically connected to the fourth node N4, and the source of the 25th transistor T25 is electrically connected to the second low voltage terminal VGLN.

[0444] The 24th transistor T24 is a p-type transistor, and the 25th transistor T25 is an n-type transistor;

[0445] The gate of the 26th transistor T26 is electrically connected to the initial control terminal NCX, the drain of the 26th transistor T26 is electrically connected to the high voltage terminal VGHN, and the source of the 26th transistor T26 is electrically connected to the Nth stage drive signal output terminal NS(N).

[0446] The 26th transistor, T26, is a p-type transistor;

[0447] The first inverting circuit includes a twenty-seventh transistor T27 and a twenty-eighth transistor T28;

[0448] The gate of the 27th transistor T27 is electrically connected to the control clock signal terminal NCK, the drain of the 27th transistor T27 is electrically connected to the high voltage terminal VGHN, and the source of the 27th transistor T27 is electrically connected to the drain of the 28th transistor T28 and the inverting clock signal terminal NCKI.

[0449] The gate of the 28th transistor T28 is electrically connected to the control clock signal terminal NCK, and the source of the 28th transistor T28 is electrically connected to the second low voltage terminal VGLN.

[0450] The 27th transistor T27 is a p-type transistor, and the 28th transistor T28 is an n-type transistor.

[0451] exist Figure 29 In at least one embodiment of the driving circuit shown, the voltage value of the second low voltage signal provided by VGLN can be less than the voltage value of the first low voltage signal provided by VGL, so that when the N-stage driving signal output terminal NS(N) outputs a low voltage signal and the potential of the first node N1 is low, T12 and T13 can be turned off well.

[0452] exist Figure 29In at least one embodiment of the driving circuit shown, the first voltage terminal is a high voltage terminal VGHN, the second voltage terminal is a first low voltage terminal VGL, and the third voltage terminal is a second low voltage terminal VGLN.

[0453] This invention Figure 29 At least one embodiment of the driving circuit, when in operation,

[0454] 1. When GCK provides a high voltage signal, T19 is turned on and T20 is turned off. When GCB provides a low voltage signal, T16 is turned on and T23 is turned off. At this time, the drive signal generation circuit is in the transmission state.

[0455] When NS(N) provides a low voltage signal, T17 is turned on and T18 is turned off. The potential of N6 is high. When T25 is turned on and T24 is turned off, NS(N) provides a low voltage signal and NS(N-1) provides a low voltage signal.

[0456] When NS(N) provides a high voltage signal, T17 is turned off and T18 is turned on, the potential of N6 is low voltage, T25 is turned off and T24 is turned on, and both NS(N) and NS(N-1) provide high voltage signals.

[0457] 2. When GCK provides a low voltage signal, T19 is turned off and T20 is turned on. When GCB provides a high voltage signal, T16 is turned off and T23 is turned on. At this time, the circuit is in a register state. T21, T22, T23 and T11 form a latch circuit. The potential of N6 and the signal provided by NS (N) remain unchanged from the previous state.

[0458] 3. When the signal provided by NS(N-1) switches from a low voltage signal to a high voltage signal, GCK provides a low voltage signal, turns off T19 and turns on T20, and GCB provides a high voltage signal, turns off T16 and turns on T23. At this time, the circuit is in the register state. T21, T22, T23 and T11 form a latch circuit. The potential of N6 remains unchanged from the previous low voltage state of the signal provided by NS(N), completing the shift. At the next moment, GCK provides a high voltage signal, turns on T19 and turns off T20, and GCB provides a low voltage signal, turns on T16 and turns off T23. At this time, the circuit is in the transmission state. NS(N-1) provides a high voltage signal, turns off T17 and turns on T18. The potential of N6 is low voltage, turns off T25 and turns on T24. Both NS(N) and NS(N-1) provide high voltage signals, realizing the shift register from NS(N-1) to NS(N).

[0459] 4. When NS(N-1) switches from providing a high voltage signal to providing a low voltage signal, GCK provides a low voltage signal, turns off T19 and turns on T20, and GCB provides a high voltage signal, turns off T16 and turns on T23. At this time, the circuit is in the register state. T21, T22, T23 and T11 form a latch circuit. The potential of N6 and the signal provided by NS(N) remain unchanged at the previous high voltage state, completing the shift. At the next moment, GCK provides a high voltage signal, turns on T19 and turns off T20, and GCB provides a low voltage signal, turns on T16 and turns off T23. At this time, the circuit is in the transmission state. NS(N-1) provides a low voltage signal, turns on T17 and turns off T18. The potential of N6 is high voltage, turns on T25 and turns off T24. Both NS(N) and NS(N-1) provide low voltage signals, realizing the shift register from NS(N-1) to NS(N).

[0460] This invention Figure 29 At least one embodiment of the driving circuit shown, when in operation,

[0461] When NS(N-1) provides a high voltage signal, TX1 and TX2 are turned on; when NS(N) provides a low voltage signal, TX3 and TX4 are turned on. By simultaneously selecting the two signals, the state of the gating input signal provided by VCT within a high-low frequency switching cycle H can be obtained and written to the first node N1. Then, TX1, TX2, TX3, and TX4 will not be turned on simultaneously at other times to prevent the potential of N1 from being affected by the potential change of the gating input signal provided by VCT. T10, T11, T12, and T13 form a NAND gate. The input signals of the NAND gate are the signal provided by NS(N) and the potential of N1, respectively. The output of the NAND gate is electrically connected to the second node N2. T24 and T25 form a second inverter circuit. The input of the second inverter circuit is electrically connected to the fourth node N4, and the output of the second inverter circuit is electrically connected to NS(N).

[0462] If VCT provides a high voltage signal when TX1, TX2, TX3 and TX4 are turned on, N1 will be written with a high voltage, and the gating state of the NAND gate can ensure that NS(N) is properly passed to NO(N).

[0463] If VCT provides a low voltage signal when TX1, TX2, TX3 and TX4 are turned on, N1 will be written with a low voltage, the NAND gate will be turned off, ensuring that NO(N) provides a low voltage signal, thereby maintaining the low level of NO(N).

[0464] Optionally, at the start of display (i.e., when the display device is powered on), during the power-on phase before the first stage, NCX outputs a low voltage signal, T9 turns on to control the potential of N1 to be high voltage, and T26 turns on to enable NS(N) to provide a high voltage signal; at this time, both T12 and T13 are turned on, the potential of N2 is low voltage, T14 is turned on, T15 is turned off, and NO(N) outputs a high voltage signal, which can turn on all pixel circuits in the effective display area, including the second display control transistor M2, clear the residual charge in the storage capacitor Cst, and improve the poor screen flicker at startup;

[0465] Subsequently, when NS(N-1) outputs a high voltage signal and NS(N) outputs a low voltage signal, TX1, TX2, TX3, and TX4 are turned on.

[0466] When VCT provides a low voltage signal, the potential of N1 is a low voltage signal, and C0 maintains the potential of N1; T11 is turned on, T10 is turned on, the potential of N2 is a high voltage, T15 is turned on, and NO(N) outputs a low voltage signal.

[0467] When VCT provides a high voltage signal, the potential of N1 is a high voltage signal, C0 maintains the potential of N1, T11 is turned off, T10 is turned on, the potential of N2 is high voltage, T15 is turned on, and NO(N) outputs a low voltage signal.

[0468] Subsequently, during the Nth stage of drive signal provision, NS(N) outputs a high-voltage signal.

[0469] When the potential of N1 is low, T10 is off and T11 is on; when the potential of N2 is high, T15 is on, and NO(N) outputs a low voltage signal.

[0470] When the potential of N1 is high, T10 is off, T11 is off, and T12 and T13 are on. When the potential of N2 is low, T14 is on, and NO(N) outputs a high voltage signal.

[0471] After the Nth stage drive signal is provided, NS(N) outputs a low voltage signal.

[0472] When the potential of N1 is a low voltage signal, T10 is turned on, T11 is turned on, the potential of N2 is a high voltage, and NO(N) outputs a low voltage signal.

[0473] When the potential of N1 is a high voltage signal, T10 is turned on and T11 is turned off, the potential of N2 is high voltage, and NO(N) outputs a low voltage signal.

[0474] This invention Figure 29In at least one embodiment of the driving circuit shown, when NS(N-1) outputs a high voltage signal and NS(N) outputs a low voltage signal, TX1, TX2, TX3 and TX4 are turned on. By simultaneously selecting the above two signals, the state of the selected input signal within a high-low frequency switching cycle can be obtained.

[0475] like Figure 30 As shown, in Figure 27 Based on at least one embodiment of the driving circuit shown,

[0476] The first gating circuit includes a first first gating transistor TX11, a first second gating transistor TX12, a first third gating transistor TX13, and a first fourth gating transistor TX14;

[0477] The second gating circuit includes a second first gating transistor TX21, a second second gating transistor TX22, a second third gating transistor TX23, and a second fourth gating transistor TX24;

[0478] The gate of the first first gating transistor TX11 is connected to the inverted signal NSI(N-1) of the N-1th stage drive signal, and the drain of the first first gating transistor TX11 is electrically connected to the first gating input terminal VCT1.

[0479] The gate of the first second gating transistor TX12 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), and the drain of the first second gating transistor TX12 is electrically connected to the first gating input terminal VCT1.

[0480] The gate of the first third-selection transistor TX13 is electrically connected to the Nth-stage drive signal output terminal NS(N), the drain of the first third-selection transistor TX13 is electrically connected to the source of the first first-selection transistor TX11, and the source of the first third-selection transistor TX13 is electrically connected to the first first node N11.

[0481] The gate of the first fourth gating transistor TX14 is connected to the inverted signal NSI(N) ​​of the Nth stage drive signal. The drain of the first fourth gating transistor TX14 is electrically connected to the source of the first second gating transistor TX12. The source of the first fourth gating transistor TX14 is electrically connected to the first first node N11.

[0482] The first first gating transistor TX11 is a p-type transistor, the first second gating transistor TX12 is an n-type transistor, the first third gating transistor TX13 is a p-type transistor, and the first fourth gating transistor TX14 is an n-type transistor;

[0483] The gate of the second first gating transistor TX21 is connected to the inverted signal NSI(N-1) of the N-1th stage driving signal, and the drain of the second first gating transistor TX21 is electrically connected to the second gating input terminal VCT2.

[0484] The gate of the second second gating transistor TX22 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), and the drain of the second second gating transistor TX22 is electrically connected to the second gating input terminal VCT2.

[0485] The gate of the second third gating transistor TX23 is electrically connected to the Nth stage drive signal output terminal NS(N), the drain of the second third gating transistor TX23 is electrically connected to the source of the second first gating transistor TX21, and the source of the second third gating transistor TX23 is electrically connected to the second first node N21.

[0486] The gate of the second fourth gating transistor TX24 is connected to the inverted signal NSI(N) ​​of the Nth stage drive signal. The drain of the second fourth gating transistor TX24 is electrically connected to the source of the second second gating transistor TX22. The source of the second fourth gating transistor TX24 is electrically connected to the second first node N21.

[0487] The second first gating transistor TX21 is a p-type transistor, the second second gating transistor TX22 is an n-type transistor, the second third gating transistor TX23 is a p-type transistor, and the second fourth gating transistor TX24 is an n-type transistor;

[0488] The first reset circuit includes a first transistor T011 and a first transistor T012;

[0489] The gate of the first transistor T011 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the drain of the first transistor T011 is electrically connected to the high voltage terminal VGHN, and the source of the first transistor T011 is electrically connected to the drain of the first transistor T012.

[0490] The gate of the first second transistor T012 is electrically connected to the Nth stage drive signal output terminal NS(N), and the source of the first second transistor T012 is electrically connected to the first first node N11.

[0491] T011 and T012 are p-type transistors;

[0492] The second reset circuit includes a second first transistor T021 and a second second transistor T022;

[0493] The gate of the second first transistor T021 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the drain of the second first transistor T021 is electrically connected to the high voltage terminal VGHN, and the source of the second first transistor T021 is electrically connected to the drain of the second second transistor T022.

[0494] The gate of the second transistor T022 is electrically connected to the Nth stage drive signal output terminal NS(N), and the source of the second transistor T022 is electrically connected to the second first node N21.

[0495] T021 and T022 are p-type transistors;

[0496] The first initialization circuit includes a first ninth transistor T019;

[0497] The gate of the first ninth transistor T019 is electrically connected to the initial control terminal NCX, the drain of the first ninth transistor T019 is electrically connected to the high voltage terminal VGHN, and the source of the first ninth transistor T019 is electrically connected to the first node N11.

[0498] T019 is a p-type transistor;

[0499] The first voltage sustaining circuit includes a first capacitor C1; the second voltage sustaining circuit includes a second capacitor C2.

[0500] The first terminal of the first capacitor C1 is electrically connected to the first node N11, and the second terminal of the first capacitor C1 is electrically connected to the first low voltage terminal VGL.

[0501] The first terminal of the second capacitor C2 is electrically connected to the second first node N21, and the second terminal of the second capacitor C2 is electrically connected to the first low voltage terminal VGL.

[0502] The first output control circuit includes a first tenth transistor T110, a first eleventh transistor T111, a first twelfth transistor T112, and a first thirteenth transistor T113;

[0503] The gate of the first tenth transistor T110 is electrically connected to the first first node N11, the drain of the first tenth transistor T110 is electrically connected to the high voltage terminal VGHN, and the source of the first tenth transistor T110 is electrically connected to the first second node N12.

[0504] The gate of the first eleventh transistor T111 is electrically connected to the Nth stage drive signal output terminal NS(N), the drain of the first eleventh transistor T111 is electrically connected to the high voltage terminal VGHN, and the source of the first eleventh transistor T111 is electrically connected to the first second node N12.

[0505] The gate of the first twelfth transistor T112 is electrically connected to the first first node N11, the drain of the first twelfth transistor T112 is electrically connected to the first second node N12, and the source of the first twelfth transistor T112 is electrically connected to the drain of the first thirteenth transistor T113.

[0506] The gate of the first thirteenth transistor T113 is electrically connected to the N-level drive signal output terminal NS(N), and the source of the first thirteenth transistor T113 is electrically connected to the first low voltage terminal VGL.

[0507] The first tenth transistor T110 and the first eleventh transistor T111 are p-type transistors, and the first twelfth transistor T112 and the first thirteenth transistor T113 are n-type transistors;

[0508] The first output circuit includes a first fourteenth transistor T114 and a first fifteenth transistor T115;

[0509] The gate of the first fourteenth transistor T114 is electrically connected to the first second node N12, the drain of the first fourteenth transistor T114 is electrically connected to the high voltage terminal VGHN, and the source of the first fourteenth transistor T114 is electrically connected to the first output drive terminal NO1(N).

[0510] The gate of the first fifteenth transistor T115 is electrically connected to the first second node N12, the drain of the first fifteenth transistor T115 is electrically connected to the first output drive terminal NO1(N), and the source of the first fifteenth transistor T115 is electrically connected to the first low voltage terminal VGL.

[0511] T114 is a p-type transistor, and T115 is a p-type transistor;

[0512] The first initialization circuit includes a first ninth transistor T019;

[0513] The gate of the first ninth transistor T019 is electrically connected to the initial control terminal NCX, the drain of the first ninth transistor T019 is electrically connected to the high voltage terminal VGHN, and the source of the first ninth transistor T019 is electrically connected to the first node N11.

[0514] T019 is a p-type transistor;

[0515] The second first initialization circuit includes a second ninth transistor T029;

[0516] The gate of the second ninth transistor T029 is electrically connected to the initial control terminal NCX, the drain of the second ninth transistor T029 is electrically connected to the high voltage terminal VGHN, and the source of the second ninth transistor T029 is electrically connected to the second first node N21.

[0517] T029 is a p-type transistor;

[0518] The first voltage sustaining circuit includes a first capacitor C1; the second voltage sustaining circuit includes a second capacitor C2.

[0519] The first terminal of the first capacitor C1 is electrically connected to the first node N11, and the second terminal of the first capacitor C1 is electrically connected to the first low voltage terminal VGL.

[0520] The first terminal of the second capacitor C2 is electrically connected to the second first node N21, and the second terminal of the second capacitor C2 is electrically connected to the first low voltage terminal VGL.

[0521] The first output control circuit includes a first tenth transistor T110, a first eleventh transistor T111, a first twelfth transistor T112, and a first thirteenth transistor T113;

[0522] The gate of the first tenth transistor T110 is electrically connected to the first first node N11, the drain of the first tenth transistor T110 is electrically connected to the high voltage terminal VGHN, and the source of the first tenth transistor T110 is electrically connected to the first second node N12.

[0523] The gate of the first eleventh transistor T111 is electrically connected to the Nth stage drive signal output terminal NS(N), the drain of the first eleventh transistor T111 is electrically connected to the high voltage terminal VGHN, and the source of the first eleventh transistor T111 is electrically connected to the first second node N12.

[0524] The gate of the first twelfth transistor T112 is electrically connected to the first first node N11, the drain of the first twelfth transistor T112 is electrically connected to the first second node N12, and the source of the first twelfth transistor T112 is electrically connected to the drain of the first thirteenth transistor T113.

[0525] The gate of the first thirteenth transistor T113 is electrically connected to the N-level drive signal output terminal NS(N), and the source of the first thirteenth transistor T113 is electrically connected to the first low voltage terminal VGL.

[0526] The first tenth transistor T110 and the first eleventh transistor T111 are p-type transistors, and the first twelfth transistor T112 and the first thirteenth transistor T113 are n-type transistors;

[0527] The first output circuit includes a first fourteenth transistor T114 and a first fifteenth transistor T115;

[0528] The gate of the first fourteenth transistor T114 is electrically connected to the first second node N12, the drain of the first fourteenth transistor T114 is electrically connected to the high voltage terminal VGHN, and the source of the first fourteenth transistor T114 is electrically connected to the first output drive terminal NO1(N).

[0529] The gate of the first fifteenth transistor T115 is electrically connected to the first second node N12, the drain of the first fifteenth transistor T115 is electrically connected to the first output drive terminal NO1(N), and the source of the first fifteenth transistor T115 is electrically connected to the first low voltage terminal VGL.

[0530] T114 is a p-type transistor, and T115 is a p-type transistor;

[0531] The second output control circuit includes a second tenth transistor T210, a second eleventh transistor T211, a second twelfth transistor T112, and a second thirteenth transistor T213;

[0532] The gate of the second tenth transistor T210 is electrically connected to the second first node N21, the drain of the second tenth transistor T210 is electrically connected to the high voltage terminal VGHN, and the source of the second tenth transistor T110 is electrically connected to the second second node N22.

[0533] The gate of the second eleventh transistor T211 is electrically connected to the Nth stage drive signal output terminal NS(N), the drain of the second eleventh transistor T211 is electrically connected to the high voltage terminal VGHN, and the source of the second eleventh transistor T211 is electrically connected to the second second node N22.

[0534] The gate of the second twelfth transistor T212 is electrically connected to the second first node N21, the drain of the second twelfth transistor T212 is electrically connected to the second second node N22, and the source of the second twelfth transistor T212 is electrically connected to the drain of the second thirteenth transistor T213.

[0535] The gate of the second thirteenth transistor T213 is electrically connected to the N-level drive signal output terminal NS(N), and the source of the second thirteenth transistor T213 is electrically connected to the first low voltage terminal VGL.

[0536] The second tenth transistor T210 and the second eleventh transistor T211 are p-type transistors, and the second twelfth transistor T212 and the second thirteenth transistor T213 are n-type transistors;

[0537] The second output circuit includes a second fourteenth transistor T214 and a second fifteenth transistor T215;

[0538] The gate of the second fourteenth transistor T214 is electrically connected to the second second node N22, the drain of the second fourteenth transistor T214 is electrically connected to the high voltage terminal VGHN, and the source of the second fourteenth transistor T214 is electrically connected to the second output drive terminal NO2(N).

[0539] The gate of the second fifteenth transistor T215 is electrically connected to the second second node N22, the drain of the second fifteenth transistor T215 is electrically connected to the second output drive terminal NO2(N), and the source of the second fifteenth transistor T215 is electrically connected to the first low voltage terminal VGL.

[0540] T114 is a p-type transistor, and T115 is a p-type transistor;

[0541] The first drive control circuit includes a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, and a nineteenth transistor T19;

[0542] The gate of the sixteenth transistor T16 is electrically connected to the inverting clock signal terminal NCKI, the drain of the sixteenth transistor T16 is electrically connected to the high voltage terminal VGHN, and the source of the sixteenth transistor T16 is electrically connected to the drain of the seventeenth transistor T17.

[0543] The gate of the seventeenth transistor T17 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), and the source of the seventeenth transistor T17 is electrically connected to the fourth node N4.

[0544] The gate of the eighteenth transistor T18 is electrically connected to the N-1th stage drive signal output terminal NS(N-1), the drain of the eighteenth transistor T18 is electrically connected to the fourth node N4, and the source of the eighteenth transistor T18 is electrically connected to the drain of the nineteenth transistor T19.

[0545] The gate of the nineteenth transistor T19 is electrically connected to the control clock signal terminal NCK, and the source of the nineteenth transistor T19 is electrically connected to the second low voltage terminal LVGL.

[0546] The sixteenth transistor T16 and the seventeenth transistor T17 are p-type transistors, and the eighteenth transistor T18 and the nineteenth transistor T19 are n-type transistors;

[0547] The second drive control circuit includes the twentieth transistor T20, the twenty-first transistor T21, the twenty-second transistor T22, and the twenty-third transistor T23;

[0548] The gate of the twentieth transistor T20 is electrically connected to the control clock signal terminal NCK, the drain of the twentieth transistor T20 is electrically connected to the high voltage terminal VGHN, and the source of the twentieth transistor T20 is electrically connected to the drain of the twentieth transistor T21.

[0549] The gate of the 21st transistor T21 is electrically connected to the Nth stage drive signal output terminal NS(N), and the source of the 21st transistor T21 is electrically connected to the fourth node N4.

[0550] The gate of the twelfth transistor T22 is electrically connected to the Nth stage drive signal output terminal NS(N), the drain of the twelfth transistor T22 is electrically connected to the fourth node N4, and the source of the twelfth transistor T22 is electrically connected to the drain of the twelfth transistor T23.

[0551] The gate of the 23rd transistor T23 is electrically connected to the inverting clock signal terminal NCKI, and the source of the 23rd transistor T23 is electrically connected to the second low voltage terminal VGLN.

[0552] The twentieth transistor T20 and the twenty-first transistor T21 are p-type transistors, and the twenty-second transistor T22 and the twenty-third transistor T23 are n-type transistors;

[0553] The second inverting circuit includes a twenty-fourth transistor T24 and a twenty-fifth transistor T25; the second initialization circuit includes a twenty-sixth transistor T26.

[0554] The gate of the 24th transistor T24 is electrically connected to the fourth node N4, the drain of the 24th transistor T24 is electrically connected to the high voltage terminal VGHN, and the source of the 24th transistor T24 is electrically connected to the drain of the 25th transistor T25 and the Nth stage drive signal output terminal NS(N).

[0555] The gate of the 25th transistor T25 is electrically connected to the fourth node N4, and the source of the 25th transistor T25 is electrically connected to the second low voltage terminal VGLN.

[0556] The 24th transistor T24 is a p-type transistor, and the 25th transistor T25 is an n-type transistor;

[0557] The gate of the 26th transistor T26 is electrically connected to the initial control terminal NCX, the drain of the 26th transistor T26 is electrically connected to the high voltage terminal VGHN, and the source of the 26th transistor T26 is electrically connected to the Nth stage drive signal output terminal NS(N).

[0558] The 26th transistor, T26, is a p-type transistor;

[0559] The first inverting circuit includes a twenty-seventh transistor T27 and a twenty-eighth transistor T28;

[0560] The gate of the 27th transistor T27 is electrically connected to the control clock signal terminal NCK, the drain of the 27th transistor T27 is electrically connected to the high voltage terminal VGHN, and the source of the 27th transistor T27 is electrically connected to the drain of the 28th transistor T28 and the inverting clock signal terminal NCKI.

[0561] The gate of the 28th transistor T28 is electrically connected to the control clock signal terminal NCK, and the source of the 28th transistor T28 is electrically connected to the second low voltage terminal VGLN.

[0562] The 27th transistor T27 is a p-type transistor, and the 28th transistor T28 is an n-type transistor.

[0563] exist Figure 30 In at least one embodiment of the driving circuit shown, the voltage value of the second low voltage signal provided by VGLN can be less than the voltage value of the first low voltage signal provided by VGL, so that when the N-stage driving signal output terminal NS(N) outputs a low voltage signal and the potential of the first node N1 is low, T12 and T13 can be turned off well.

[0564] Figure 31 yes Figure 30 The timing diagram shows the operation of at least one embodiment of the driving circuit.

[0565] exist Figure 30 In at least one embodiment of the driving circuit shown, VCT1 and VCT2 can be independently written with control signals to achieve separate output control of NO1 (N) and NO2 (N).

[0566] exist Figure 32 In the diagram, NO1(1) is the first output driver of the first stage, NO1(2) is the first output driver of the second stage, NO1(3) is the first output driver of the third stage, NO1(4) is the first output driver of the fourth stage, NO1(5) is the first output driver of the fifth stage, NO1(6) is the first output driver of the sixth stage, NO1(7) is the first output driver of the seventh stage, NO1(8) is the first output driver of the eighth stage, NO1(9) is the first output driver of the ninth stage, NO1(10) is the first output driver of the tenth stage, NO1(11) is the first output driver of the eleventh stage, and NO1(12) is the first output driver of the twelfth stage.

[0567] The terminal labeled NO2(1) is the second output driver of the first stage, the terminal labeled NO2(2) is the second output driver of the second stage, the terminal labeled NO2(3) is the second output driver of the third stage, the terminal labeled NO2(4) is the second output driver of the fourth stage, the terminal labeled NO2(5) is the second output driver of the fifth stage, the terminal labeled NO2(6) is the second output driver of the sixth stage, the terminal labeled NO2(7) is the second output driver of the seventh stage, the terminal labeled NO2(8) is the second output driver of the eighth stage, the terminal labeled NO2(9) is the second output driver of the ninth stage, the terminal labeled NO2(10) is the second output driver of the tenth stage, the terminal labeled NO2(11) is the second output driver of the eleventh stage, and the terminal labeled NO2(12) is the second output driver of the twelfth stage.

[0568] like Figure 33 As shown, at least one embodiment of the second voltage sustaining circuit may include a sustaining control circuit, a first inverter, and a second inverter;

[0569] The sustaining control circuit may include a third transistor T3 and a fourth transistor T4;

[0570] The gate of the third transistor T3 is electrically connected to the N-1th stage drive signal terminal NS(N-1), the drain of the third transistor T3 is electrically connected to the first node N1, and the source of the third transistor T3 is electrically connected to the third node N3.

[0571] The gate of the fourth transistor T4 is electrically connected to the control clock signal terminal, the drain of the fourth transistor T4 is electrically connected to the third node N3, and the source of the fourth transistor T4 is electrically connected to the first node N1.

[0572] The third transistor T3 is a p-type transistor, and the fourth transistor T4 is an n-type transistor;

[0573] The first inverter includes a fifth transistor T5 and a sixth transistor T6, and the second inverter includes a seventh transistor T7 and an eighth transistor T8;

[0574] The gate of the fifth transistor T5 is electrically connected to the first node N1, the drain of the fifth transistor T5 is electrically connected to the high voltage terminal VGHN, and the source of the fifth transistor T5 is electrically connected to the second node N2.

[0575] The gate of the sixth transistor T6 is electrically connected to the first node N1, the drain of the sixth transistor T6 is electrically connected to the second node N2, and the source of the sixth transistor T6 is electrically connected to the first low voltage terminal VGL.

[0576] The fifth transistor T5 is a p-type transistor, and the sixth transistor T6 is an n-type transistor;

[0577] The gate of the seventh transistor T7 is electrically connected to the second node N2, the drain of the seventh transistor T7 is electrically connected to the high voltage terminal VGHN, and the source of the seventh transistor T7 is electrically connected to the third node N3.

[0578] The gate of the eighth transistor T8 is electrically connected to the second node N2, the drain of the eighth transistor T8 is electrically connected to the third node N3, and the source of the eighth transistor T8 is electrically connected to the first low voltage terminal VGL.

[0579] The seventh transistor T7 is a p-type transistor, and the eighth transistor T8 is an n-type transistor.

[0580] exist Figure 33 In at least one embodiment of the second voltage sustaining circuit shown, the gate of the third transistor T3 may be replaced with an electrical connection to either the inverting clock signal terminal NCKI or the first clock signal terminal.

[0581] In at least one embodiment of the present invention, since the p-type transistor has a threshold voltage loss when transmitting low voltage and the n-type transistor has a threshold voltage loss when transmitting high voltage, the absolute value of the potential of N1 will be lower. The absolute value of the potential of N1 can be increased by controlling the first inverter and the second inverter, thereby better controlling the corresponding transistors in the output circuit to turn on or off. When the control circuit controls each selected transistor to be on, it controls the disconnection between N1 and N3 so as not to affect the writing of the potential of N1.

[0582] The driving method described in at least one embodiment of the present invention is applied to the above-mentioned driving circuit, and the driving method includes:

[0583] Under the control of the control clock signal, the drive signal generation circuit performs a shift operation on the (N-1)th stage drive signal to obtain and output the Nth stage drive signal through the Nth stage drive signal output terminal;

[0584] The m-th gating circuit, under the control of the m-th gating control signal, controls the writing of the m-th gating input signal into the m-th first node;

[0585] The m-th output control circuit performs a AND-NOT operation on the N-th stage drive signal and the potential of the second terminal of the m-th output control circuit to obtain the m-th first output signal;

[0586] The m-th output circuit is used to invert the m-th first output signal to obtain and provide the m-th output drive signal through the m-th output drive terminal.

[0587] M is a positive integer; m is a positive integer less than or equal to M; and N is a positive integer.

[0588] The display device described in this embodiment of the invention includes the driving circuit described above.

[0589] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A driving circuit, characterized in that, It includes a drive signal generation circuit, M output drive terminals, and M control circuits; the m-th control circuit includes the m-th gating circuit, the m-th output control circuit, and the m-th output circuit; M is a positive integer greater than or equal to 2; m is a positive integer less than or equal to M; The drive signal generation circuit is electrically connected to the control clock signal terminal, the N-1th stage drive signal output terminal, and the Nth stage drive signal output terminal, respectively. It is used to shift the N-1th stage drive signal provided by the N-1th stage drive signal output terminal under the control of the control clock signal provided by the control clock signal terminal, so as to obtain and output the Nth stage drive signal through the Nth stage drive signal output terminal. The m-th gating circuit is electrically connected to the m-th first node, the m-th gating input terminal and the m-th gating control terminal respectively, and is used to control the writing of the m-th gating input signal provided by the m-th gating input terminal into the m-th first node under the control of the m-th gating control signal provided by the m-th gating control terminal. The first terminal of the m-th output control circuit is electrically connected to the N-th drive signal output terminal, and the second terminal of the m-th output control circuit is electrically connected to the m-th first node, for outputting the m-th first output signal; The m-th output circuit is used to invert the m-th first output signal to obtain and provide the m-th output drive signal through the m-th output drive terminal; N is a positive integer.

2. The driving circuit as described in claim 1, characterized in that, The drive signal generation circuit includes a first drive control circuit, which includes a seventeenth transistor and an eighteenth transistor. The gate of the seventeenth transistor is electrically connected to the output terminal of the (N-1)th stage drive signal, and the second terminal of the seventeenth transistor is electrically connected to the fourth node; The gate of the eighteenth transistor is electrically connected to the output terminal of the (N-1)th stage drive signal, the first terminal of the eighteenth transistor is electrically connected to the fourth node, and the second terminal of the eighteenth transistor is electrically connected to the third voltage terminal.

3. The driving circuit as described in claim 2, characterized in that, The seventeenth transistor is a p-type transistor, and the eighteenth transistor is an n-type transistor.

4. The driving circuit as described in claim 1, characterized in that, The m-th gating circuit includes the m-th first gating transistor; The gate of the m-th first selection transistor is electrically connected to the m-th selection control terminal, the first terminal of the m-th first selection transistor is electrically connected to the m-th first node, and the second terminal of the m-th first selection transistor is electrically connected to the m-th selection input terminal.

5. The driving circuit as described in claim 1, characterized in that, The m-th control circuit also includes the m-th first initialization circuit; The m-th first initialization circuit is electrically connected to the initial control terminal, the first voltage terminal, and the m-th first node, respectively, and is used to control the connection between the m-th first node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

6. The driving circuit as described in claim 1, characterized in that, The m-th control circuit also includes the m-th first voltage maintenance circuit; The first terminal of the m-th first voltage maintenance circuit is electrically connected to the m-th first node, and the second terminal of the m-th first voltage maintenance circuit is electrically connected to the DC voltage terminal. The m-th first voltage maintenance circuit is used to maintain the potential of the m-th first node.

7. The driving circuit as described in claim 5, characterized in that, The m-th first initialization circuit includes the m-th ninth transistor; The gate of the m-th ninth transistor is electrically connected to the initial control terminal, the first terminal of the m-th ninth transistor is electrically connected to the first voltage terminal, and the second terminal of the m-th ninth transistor is electrically connected to the m-th first node.

8. The driving circuit as described in claim 7, characterized in that, The m-th ninth transistor is a p-type transistor.

9. The driving circuit according to any one of claims 1 to 8, characterized in that, The m-th output circuit includes the m-th fourteenth transistor and the m-th fifteenth transistor; The gate of the m-th fourteenth transistor is electrically connected to the m-th second node, the first terminal of the m-th fourteenth transistor is electrically connected to the first voltage terminal, and the second terminal of the m-th fourteenth transistor is electrically connected to the m-th output drive terminal. The gate of the m-th fifteenth transistor is electrically connected to the m-th second node, the first terminal of the m-th fifteenth transistor is electrically connected to the m-th output drive terminal, and the second terminal of the m-th fifteenth transistor is electrically connected to the second voltage terminal.

10. A driving method, applied to the driving circuit as described in any one of claims 1 to 9, characterized in that, The driving method includes: Under the control of the control clock signal, the drive signal generation circuit performs a shift operation on the (N-1)th stage drive signal to obtain and output the Nth stage drive signal through the Nth stage drive signal output terminal; The m-th gating circuit, under the control of the m-th gating control signal, controls the writing of the m-th gating input signal into the m-th first node; The m-th output control circuit is used to output the m-th first output signal according to the N-th level drive signal; The m-th output circuit is used to invert the m-th first output signal to obtain and provide the m-th output drive signal through the m-th output drive terminal. M is a positive integer greater than or equal to 2; m is a positive integer less than or equal to M; and N is a positive integer.

11. A display device, characterized in that, The pixel circuit includes the driving circuit as described in claim 1; the pixel circuit includes a first display control transistor, a second display control transistor, a driving transistor, a fourth display control transistor, a fifth display control transistor, a sixth display control transistor, a seventh display control transistor, a storage capacitor, and an organic light-emitting diode; The gate of the second display control transistor is electrically connected to the first scan terminal. The driving circuit provides a first scanning signal to the first scanning terminal through the output driving terminal.

12. The display device as claimed in claim 11, characterized in that, The gate of the first display control transistor is electrically connected to the first reset terminal, the first electrode of the first display control transistor is electrically connected to the initial voltage terminal, and the second electrode of the first display control transistor is electrically connected to the gate of the driving transistor. The driving circuit provides a first scan signal to the first reset terminal through the output driving terminal.

13. The display device as claimed in claim 11, characterized in that, The first scanning signal provided by the first scanning end controls whether the second display control transistor is turned on or off, thereby controlling whether the data voltage on the data line is written to the gate of the driving transistor, and thus controlling whether the brightness of the pixel circuit of this row is updated.

14. A display device, characterized in that, Includes the driving circuit as described in any one of claims 1 to 9.

Images