Memory circuit and method of controlling the same

Abstract

A memory circuit and a control method thereof, the memory circuit comprising: a memory array including a plurality of memory cells configured across a first number (N) of word lines; a word line driver including a second number (N / 2) of logic gates, wherein each of the logic gates is to receive a first input signal corresponding to a first one of the word lines and a second input signal corresponding to a second one of the word lines, and to provide a boost signal based on respective logic states of the first and second input signals; and a pulser circuit including N / 2 pairs of first and second buffers, wherein each of the first buffers is to receive a corresponding boost signal and to deactivate a corresponding first word line, and each of the second buffers is to receive a corresponding boost signal and to activate a corresponding second word line.

Description

Technical Field

[0001] This disclosure relates to a memory circuit and its control method. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, this increase in integration density stems from the iterative reduction in the minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0003] This disclosure includes a memory circuit comprising: a memory array including a plurality of memory cells configured across a first number (N) word lines; a word line driver including a second number (N / 2) logic gates, wherein each of the logic gates is configured to receive a first input signal corresponding to a first word line and a second input signal corresponding to a second word line, and to provide a boost signal based on the respective logic states of the first input signal and the second input signal; and a booster circuit including N / 2 pairs of first buffers and second buffers, wherein each of the first buffers is configured to receive a corresponding boost signal and disable a corresponding first word line, and each of the second buffers is configured to receive a corresponding boost signal and enable a corresponding second word line.

[0004] This disclosure includes a memory circuit comprising: a plurality of first memory cells arranged along a first word line extending in a lateral direction; a plurality of second memory cells arranged along a second word line extending in a lateral direction; a logic gate disposed in the lateral direction at a first end of the first word line and the second word line, wherein the logic gate is configured to receive a first input signal corresponding to the first word line and a second input signal corresponding to the second word line, and to provide a boost signal through a boost word line based on respective logic states of the first input signal and the second input signal; a first buffer disposed in the lateral direction at a second end of the first word line and the second word line, wherein the first buffer is configured to receive the boost signal and to disable the first word line based on a first logic state of receiving an enable signal; and a second buffer disposed in the lateral direction at a second end of the first word line and the second word line, wherein the second buffer is configured to receive the boost signal and to enable the second word line based on a second logic state of receiving an enable signal.

[0005] This disclosure includes a method for controlling a memory circuit, comprising the steps of: disabling a first word line based on receiving a first decoded address bit having a first logic state; enabling a second word line based on receiving a second decoded address bit having a second logic state; performing a NOR operation on the first and second decoded address bits to provide a boost signal; forwarding the boost signal to the disabled first word line based on receiving an enable signal having a first logic state; and inverting the boost signal to the enabled second word line based on receiving an enable signal having a second logic state. Attached Figure Description

[0006] When with attachment Figure 1 When reading this document, it is best to understand the specifications as described below. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for ease of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 A schematic diagram of a memory circuit according to some embodiments is shown, the memory circuit including a WL driver circuit and a WL pusher circuit respectively physically disposed at opposite ends of a memory array;

[0008] Figure 2 Illustrations based on some embodiments Figure 1 The circuit diagram of the memory array and memory cell of the memory circuit;

[0009] Figure 3 Illustrations based on some embodiments Figure 1 Exemplary circuit implementation of memory circuitry;

[0010] Figure 4 The illustration shows the operation according to some embodiments. Figure 3 The waveforms of various signals during memory circuit operation;

[0011] Figure 5 Illustrations based on some embodiments Figure 1 An exemplary circuit implementation of a buffer for a WL actuator circuit of a memory circuit;

[0012] Figure 6 A schematic diagram of another memory circuit according to some embodiments is shown, the memory circuit including WL driver circuitry and WL pusher circuitry respectively physically disposed at opposite ends of a memory array;

[0013] Figure 7 The illustration shows the operation according to some embodiments. Figure 6 The waveforms of various signals during memory circuit operation;

[0014] Figure 8Illustrations based on some embodiments Figure 1 or Figure 6 A schematic diagram of a portion of the memory circuitry;

[0015] Figure 9 A schematic diagram of yet another memory circuit according to some embodiments is shown, the memory circuit including a WL pusher circuit physically inserted between a first memory array and a second memory;

[0016] Figure 10 Illustrations based on some embodiments Figure 9 Exemplary circuit implementation of memory circuitry;

[0017] Figure 11 An exemplary flowchart illustrating a method for controlling memory circuitry according to some embodiments is shown.

[0018] [Symbol Explanation]

[0019] 100, 600, 900: Memory circuit

[0020] 105, 605, 905: Memory controller

[0021] 120, 620, 920, 960: Memory Array

[0022] 125: Memory Unit

[0023] 130:BL driver circuit

[0024] 140, 640, 940: WL driver circuit

[0025] 150, 650, 950: WL thruster circuit

[0026] 150 <0> 150 <n k-1> 、950<0>、950 <n 2-1>: Buffer circuit

[0027] 301 <0> 301 <1> Decoded address bits

[0028] 301 <2> 302 <3> :Signal

[0029] 310, 320, 1010, 1020: Logic gates

[0030] 312, 314, 322, 324, 330, 500, 1012, 1014, 1022, 1024: Buffers; 340, 342: Inverters

[0031] 510, 520, 530, 540: Transistors

[0032] 601 <0> :WL activation signal

[0033] 660: Flip-Flip Circuit

[0034] 1100: Method

[0035] 1110, 1120, 1130, 1140, 1150: Operation

[0036] ADDR: Encoded address signal

[0037] BL, BLB: Bitline

[0038] CLK: Clock signal

[0039] M0, M1, M2, M3, M4, M5: Layers

[0040] N1, N2, N3, N4: n-type transistors

[0041] P1, P2: p-type transistors

[0042] Q, QB: Port

[0043] SEL: Enable signal

[0044] SEL_FF: signal

[0045] VDD: Power supply voltage

[0046] VSS: Grounding voltage

[0047] WL, WL <0> WL <1> WL <2> WL <3> WL <n-1>、WL <n-2>, WL_far<0>, WL_far<1>, WL_far<2>, WL_far<3>, WL_near<0>, WL_near<1>, WL_near<2>, WL_near<3>: Nominal word lines

[0048] WL_boost<0>, WL_boost<1>, WL_boost <n 2-1>Boost signal

[0049] WLB, WLB <0> WLB <1> WLB <n k-1>、WLB <n 2-1>:Boost line Detailed Implementation

[0050] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these elements and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0051] Furthermore, for ease of description, spatial relative terms such as "below," "lower," "lower," "higher," "upper," "top," "bottom," and the like are used herein to describe the relationship between one component or feature as illustrated in the accompanying drawings and another component or feature(s). In addition to the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive symbols used herein will be interpreted accordingly.

[0052] Generally, to write data bits into a memory cell, a word line (WL) is asserted to activate the individual access (or channel gate) transistors of the memory cell. When the WL is asserted, an appropriate bias voltage is applied to the bit line (BL) to write the data bits into the memory cell. For example, a WL driver can apply a WL pulse to the WL (or column) to be asserted, thereby activating the individual access transistors of the memory cells located on (or coupled to) that column (WL). Simultaneously, the bit line (BL) and bit line bar (BLB) of a row can be biased with a first voltage and a second voltage corresponding to logic "0" and logic "1," respectively, thereby writing data bits into the memory cells located at the intersection of the asserted WL and the biased BL / BLB.

[0053] While such write schemes are sufficient in many contexts, in some cases, the propagation time of the WL pulse provided by the WL driver along the length of the WL can be excessively long due to the parasitic resistance and capacitance associated with the WL. This is particularly true in advanced complementary metal-oxide-semiconductor (CMOS) processes, where the WLs can have relatively narrow pitches (resulting in increased resistance relative to previous technology nodes) and where adjacent WLs can be closely spaced (resulting in increased capacitance relative to previous technology nodes). These larger RC values ​​result in a larger RC time constant and slower slew rate when the WL pulse is first applied. Therefore, existing memory circuitry implementing WLs to control access is not entirely satisfactory in certain configurations.

[0054] This disclosure provides various embodiments of a memory circuit (or device) including WL drivers and WL pusher circuitry physically disposed at opposite ends of a memory (cell) array. In some embodiments, the WL drivers and WL pusher circuitry can operatively perform the same function, for example, driving a WL activated according to a decoded address signal. Additionally, the total number (N) of WLs can be divided into multiple (N / K) groups, each group having a boost WL and a subgroup (K) of buffers. The boost WL can be operatively coupled between the WL drivers and the pusher circuitry and is used to transmit boosted signals from the WL drivers to their respective buffers. By distributing substantially two WL drivers at opposite ends of the WLs, memory cells disposed at the distal ends of the WLs are advantageously protected from the bucked WL voltage. Therefore, the conversion efficiency of the WL can be significantly improved. Furthermore, by having multiple WLs share a single boost WL, valuable space in one or more metallization layers can be freed up, allowing more area within the metallization layers to be allocated to metal tracks.

[0055] In a non-limiting example where K=2, the actuator circuitry physically disposed on one side of a memory array having a plurality of WLs may include N / 2 groups. Each of the actuator groups may include a first buffer and a second buffer. The first buffer may correspond to (coupled to) a first WL, and the second buffer may correspond to (coupled to) a second WL. The WL driver physically disposed on the other side of the memory array may include N / 2 logic gates. Each of the logic gates may receive a first input signal (e.g., the first bit of a decoded address signal) and a second input signal (e.g., the second bit of a decoded address signal), the first input signal and the second input signal corresponding to the activation / deactivation of the first WL and the second WL, respectively. Each logic gate may provide a boost signal to the first buffer and the second buffer by performing a NOR operation on the first input signal and the second input signal, respectively. Thus, an activated WL may be applied with the first or second input signal and the boost signal from its two ends, respectively.

[0056] Figure 1 A schematic diagram of a memory circuit (or device) 100 according to one embodiment is shown. In some embodiments, the memory circuit 100 includes a memory controller 105 and a memory array 120. The memory array 120 may include a plurality of storage circuits or memory cells 125 configured in a two-dimensional or three-dimensional array. Each memory cell 125 may be coupled to a corresponding word line WL and a corresponding pair of bit lines BL. The memory controller 105 may write data to or read data from the memory array 120 according to electrical signals through the word line WL and the bit line BL. In other embodiments, the memory circuit 100 includes a memory controller 105 and a memory array 120. Figure 1 The text describes the use of more, fewer, or different components.

[0057] Memory array 120 is a hardware element for storing data. In one embodiment, memory array 120 is embodied as a semiconductor memory device. Memory array 120 includes a plurality of storage circuits or memory cells 125. Memory array 120 includes a first number of nominal word lines WL, for example, WL <0> WL <1> ...WL <n-1>and the second number of boost word lines WLB, for example, WLB <0> WLB <1> ...WLB <n k-1>In some embodiments, K can be any integer greater than 2 and a multiple of N. As a non-limiting example discussed below, K equals 2. Each of the nominal word line WL and the boost word line WLB may extend in the first direction. Memory array 120 includes a third number of bit lines BL( Figure 1 (Not shown in the image). Each of the bit lines BL can extend in a second direction. The word line WL, the boost word line WLB, and the bit line BL can each be implemented as a conductive metal or a conductive rail.

[0058] In one configuration, each memory cell 125 is coupled to a corresponding word line WL and a corresponding pair of bit lines BL and BLB, and is operable according to the voltage or current passing through the corresponding word line WL and the corresponding bit lines BL / BLB. The bit lines BL and BLB may receive and / or provide differential signals. Each memory cell 125 may include volatile memory, non-volatile memory, or a combination thereof. In some embodiments, each memory cell 125 is embodied as a static random access memory (SRAM) cell or other types of memory cells. In some embodiments, the memory array 120 includes additional wiring (e.g., select wiring, reference wiring, reference control wiring, power rails, etc.).

[0059] The memory controller 105 is a hardware element capable of controlling the operation of the memory array 120. In some embodiments, the memory circuit 100 further includes a BL controller (or driver circuit) 130, a WL controller (or driver circuit) 140, and a WL booster circuit 150. The BL driver circuit 130, the WL driver circuit 140, and the WL booster circuit 150 may each be embodied as logic circuitry, analog circuitry, or a combination thereof. In some embodiments, the WL driver circuit 140 is a circuit that can provide voltage or current (e.g., WL pulses) through the active word line WL of the memory array 120, and the BL driver circuit 130 is a circuit that can provide or read voltage or current through one or more bit lines BL of the memory array 120. The WL booster circuit 150 is a circuit that includes a second number of buffer circuits, each corresponding to a second boost word line WLB, such as buffer circuit 150. <0> ……150 <n k-1>Each of the buffer circuits can receive a corresponding boost signal WL_boost from the WL driver circuit 140 and selectively invert the boost signal to the active word line WL. In some other embodiments, the memory circuit 100 may include a... Figure 1 The components shown may be more, fewer, or different. For example, memory circuit 100 may further include a timing controller that can provide control signals or clock signals to synchronize the operation of BL driver circuit 130 and WL driver circuit 140.

[0060] In brief, the memory controller 105 may provide a clock (CLK) signal and a (encoded) address (ADDR) signal to the WL driver circuitry 140. Upon receiving the ADDR signal, the WL driver circuitry 140 may decode the ADDR signal. The decoded ADDR signal may include a plurality of bits (e.g., N bits), one of which has a first logic state (e.g., logic 1) corresponding to one of the nominal word lines WL to be activated (or selected), and the remaining bits have a second logic state (e.g., logic 0) corresponding to the other nominal word lines to be deactivated (or deselected). The WL driver circuitry 140 may apply those decoded bits to the word lines WL respectively. <0> WL <1> ...WL <n-1>Meanwhile, the WL driver circuit 140 may include a complex number of logic gates (e.g., N / K-1 NOR gates), each of which can output to a corresponding gate in the buffer circuit (e.g., 150). <0> Provide boost signals (e.g., WL_boost) <0> Each buffer circuit has K buffers respectively coupled to K word lines WL. The NOR gate of the WL driver circuit 140 can generate a boost signal based on the decoded ADDR signal applied to the corresponding K word lines WL. Based on the enable (SEL) signal received from the memory controller 105, one of the K buffers can logically invert the boost signal to the active word line WL, and the remaining buffers forward the boost signal to one or more inactive word lines WL.

[0061] Figure 2 An exemplary circuit diagram of a memory cell 125 according to one embodiment is shown, which is implemented as an SRAM cell (hereinafter referred to as "SRAM cell 125"). Figure 2 In an illustrative example, SRAM cell 125 includes a number of transistors (sometimes referred to as a 6T SRAM cell): four n-type transistors N1, N2, N3, N4 and two p-type transistors P1, P2. However, it should be understood that SRAM memory cell 125 may include any suitable number of transistors (e.g., 7, 8, 10) while still within the scope of this disclosure. The n-type transistors N1, N2, N3, N4 may be n-type metal-oxide-semiconductor field-effect transistors (MOSFETs). The p-type transistors P1, P2 may be p-type MOSFETs. These elements can operate together to store bits. In other embodiments, SRAM cell 125 includes more than... Figure 2 The text describes the use of more, fewer, or different components.

[0062] n-type transistors N3 and N4 include gate electrodes coupled to word line WL. In one configuration, the drain electrode of n-type transistor N3 is coupled to bit line BL, and the source gate of n-type transistor N3 is coupled to port Q. In another configuration, the drain electrode of n-type transistor N4 is coupled to bit line BLB, and the source electrode of n-type transistor N4 is coupled to port QB. In one configuration, n-type transistors N3 and N4 act as electrical switches. n-type transistors N3 and N4 can, depending on the voltage applied to word line WL, allow bit line BL to be electrically coupled to or decoupled from port Q, and allow bit line BLB to be electrically coupled to or decoupled from port QB. For example, based on a supply voltage VDD (or 1V) applied to word line WL corresponding to a high state (or logic 1), n-type transistor N3 is enabled to electrically couple bit line BL to port Q, and n-type transistor N4 is enabled to electrically couple bit line BLB to port QB. In another instance, based on the ground voltage VSS (or 0V) applied to word line WL corresponding to a low state (or logic 0), n-type transistor N3 is deactivated to electrically decouple bit line BL from port Q, and n-type transistor N4 is deactivated to electrically decouple bit line BLB from port QB.

[0063] n-type transistor N1 includes a source electrode coupled to a first power supply voltage rail (VSS or 0V), a gate electrode coupled to port QB, and a drain electrode coupled to port Q. In one configuration, p-type transistor P1 includes a source electrode coupled to a second power supply voltage rail (VDD), a gate electrode coupled to port QB, and a drain electrode coupled to port Q. In one configuration, n-type transistor N2 includes a source electrode coupled to a first power supply voltage rail (VSS or 0V), a gate electrode coupled to port Q, and a drain electrode coupled to port QB. In one configuration, p-type transistor P2 includes a source electrode coupled to a second power supply voltage rail (VDD), a gate electrode coupled to port Q, and a drain electrode coupled to port QB. In this example, n-type transistor N1 and p-type transistor P1 act as inverters, and n-type transistor N2 and p-type transistor P2 act as inverters, forming a cross-coupled inverter. In one state, the cross-coupled inverter can read and amplify the voltage difference at ports Q and QB. When writing data, the cross-coupled inverter can read the voltages provided at ports Q and QB through n-type transistors N3 and N4, and amplify the voltage difference at bit lines BL and BLB. For example, the cross-coupled inverter reads a voltage of 0.5V at port Q and a voltage of 0.4V at port QB, and amplifies the voltage difference at ports Q and QB through positive feedback (or regenerative feedback), so that the voltage at port Q becomes the supply voltage VDD (e.g., 1V), and the voltage at port QB becomes the ground voltage VSS (e.g., 0V). The amplified voltages at ports Q and QB can be provided to bit lines BL and BLB through n-type transistors N3 and N4, respectively, for reading.

[0064] Figure 3 Illustrations based on some embodiments Figure 1 An exemplary circuit diagram of a portion of the memory circuitry 100. For example, the memory array 120, the WL driver circuitry 140, and the WL actuator circuitry 150 are each partially shown. Additionally, in Figure 3 The diagram illustrates an implementation of memory circuit 100 where K=2. Therefore, the WL driver circuit 140 may include N / 2 logic gates, each of which is used to generate a separate boost signal. Furthermore, each of the boost signals may be received by a separate buffer circuit including two (or a pair) buffers. It should be understood that... Figure 3 The circuit diagrams are provided for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0065] exist Figure 3 The image shows the four nominal word lines WL of the memory array 120, for example, WL <0> WL <1> WL <2> and WL <3> Each of the nominal word lines WL is coupled to a specific number of memory cells 125. Each of the nominal word lines WL extends in a lateral direction, wherein WL driver circuitry 140 and WL pusher circuitry 150 are physically disposed at opposite ends of the word lines WL. WL driver circuitry 140 includes logic gates 310 and 320, and WL pusher circuitry 150 includes buffers 312, 314, 322, and 324.

[0066] In some embodiments, logic gates 310 and 320 may each be implemented as NOR gates having a first input, a second input, and an output. The first input and the second input are coupled to corresponding first word lines WL1 and WL2, respectively, and the outputs are coupled to a corresponding pair of buffers via a common boost word line WLB. The first word line WL1 (or the first input of the NOR gate) and the second word line WL2 (or the second input of the NOR gate) are respectively applied with the first and second bits of the decoded ADDR signal, and the common boost word line WLB (or the output of the NOR gate) is applied with a boost signal (WL_boost), which is a NOR combination of the first and second decoded bits. This pair of buffers corresponding to the common boost word line WLB may be alternately activated based on, for example, an enable (SEL) signal provided by the memory controller 105. When the SEL signal is provided in the first logic state, one of the buffers can be activated to perform a logic inversion on the received WL_boost signal; and when the SEL signal is provided in the second logic state, the other buffer can be deactivated to forward the received WL_boost signal (i.e., without performing a logic inversion). Therefore, one of the nominal word lines WL can be activated at a time (e.g., during one clock cycle), and signals can be applied to the activated word line WL from both ends of the activated word line WL via the WL driver 140 and the WL pusher circuit 150, respectively.

[0067] For example, NOR gate 310 has connections to word lines WL. <0> and WL <1> The first and second input terminals. Word line WL <0> It can be applied to or correspond to the first bit of the decoded ADDR signal, 301 <0> ; and the character line WL <1> The second bit, 301, can be applied to or correspond to the decoded ADDR signal. <1> These decoded address bits (sometimes called WL activation signals) 301 <0> and 301 <1> Each of these can be applied to the word line WL through an even number of buffers (e.g., 330). <0> or WL <1> The corresponding one in the context. Upon receiving decoded address bits, NOR gate 310 can perform a NOR operation on those bits to provide a boost signal, such as WL_boost, at its output. <0> Therefore, the boost signal WL_boost <0> The logical state can be determined based on the decoded address bits 301. <0> and 301 <1> The individual logic state determinations are listed in the table below. Boost signal WL_boost <0> Through a common boost word line (e.g., WLB) <0> The SEL signal is provided to buffers 312 and 314 of the WL thruster circuit 150. Simultaneously or subsequently, the SEL signal is provided to a first enable input of buffer 312 via inverter 340 and a second enable input of buffer 312 via inverters 340 and 342; and the SEL signal is provided to a first enable input of buffer 314 via inverter 340 and a second enable input of buffer 314 via inverters 340 and 342, thereby allowing buffers 312 and 314 to be activated alternately.

[0068] 301<0> 301<1> WL_boost <0> 0 0 1 0 1 0 1 0 0 1 1 0

[0069] surface

[0070] In the word line WL <0> In the selected or effective non-restricted instance, the decoded address bit 301 <0> and 301 <1> Each has logic 1 and logic 0 respectively. Therefore, the word line WL <0> Logic 1 is applied, and word line WL <1> A logic 0 is applied, and the NOR gate 310 outputs a boost signal WL_boost with a logic 0. <0> Depending on the implementation, the SEL signal may have a logic 1 or a 0, but in some embodiments disclosed herein, the SEL signal may be applied to the word line WL with a logic 1. <0> Previously, it remained in this logical state. In the current instance, buffer 312 can be activated by the SEL signal to invert the boost signal WL_boost. <0> Buffer 314 can be deactivated by the SEL signal to forward the boost signal WL_boost. <0> Therefore, the buffer 312 (of the WL thruster circuit 150) is connected via the word line WL. <0> One of the ends provides logic 1 to the word line, while the WL driver circuit 140 provides logic 1 through the word line WL. <0> The other end provides a logic 1 to the word line.

[0071] NOR gate 320, word line WL <2> and WL <3> Boost word line WL <1> Buffers 322 and 324 and associated signal 301 <2> 302 <3> and WL_boost <1> The configuration is essentially similar to that of the NOR gate 310 and its corresponding components (e.g., word line WL). <0> and WL <1> Boost word line WL <0> (such as buffers 312 and 314, etc.), and therefore, their description will not be repeated.

[0072] Figure 4 The waveforms of various signals described above according to some embodiments are illustrated. For example, the clock (CLK) signal, enable (SEL) signal, and WL enable signal (e.g., decoded address bit 301) are shown. <0> ) and boost signals (e.g., WL_boost) <0> According to the above word line WL <0> Instances that are active / selected, in Figure 4 In the middle, the SEL signal is in the decoded address bit 301 <0> Before being pulled up and after decoding, address bits 301 <0> After being pulled down, it remains at logic 1 or 0. When the decoded address bit 301... <0> and 301 <1> When one of them is at logic 1, the boost signal WL_boost <0> It was pulled down. In other words, when the decoded address bit 301... <0> and 301 <1> When one of them is pulled up, the boost signal WL_boost <0> It was pulled down.

[0073] Figure 5 Exemplary circuit diagrams of buffers (e.g., 312, 314, 322, 324) of the WL thruster circuit 150 (hereinafter referred to as "buffer 500") according to some embodiments are shown. Although Figure 3 The circuit diagram implements buffer 500 as a transmission gate, but it should be understood that buffer 500 can be implemented as any of a variety of other suitable circuits, while still within the scope of this disclosure.

[0074] As shown, in Figure 5 In this configuration, buffer 500 may include transistors 510, 520, 530, and 540 connected in series between a power supply voltage (e.g., VDD) and a reference voltage (e.g., VSS). Transistors 510 and 530 are each implemented as n-type field-effect transistors, and transistors 520 and 540 are each implemented as p-type field-effect transistors. The gates of transistors 510 and 520 may be connected to each other as inputs to buffer 500, and their drains may be connected to each other as outputs to buffer 500. The source of transistor 510 may be connected to the drain of transistor 530, and the source of transistor 530 is connected to VSS; and the source of transistor 520 may be connected to the drain of transistor 540, and the source of transistor 540 is connected to VDD. Furthermore, the gate of transistor 530 may be configured as a first enable input to receive the SEL signal; and the gate of transistor 540 may be configured as a second enable input to receive the SEL signal.

[0075] Figure 6 A schematic diagram of a memory circuit (or device) 600 according to one embodiment is shown. The memory circuit 600 is substantially similar to the memory circuit 100, except that the memory circuit 600 further includes a flip-flop circuit embedded in its memory controller. For example, the memory circuit 600 also includes a memory controller 605 (which further includes a flip-flop circuit 660), a memory array 620, a WL driver circuit 640, and a WL pusher circuit 650. Therefore, the following discussion of the memory circuit 600 will focus on the differences. In some embodiments, the flip-flop circuit 660 may be embedded in the memory controller 605 for providing CLK and ADDR signals. Using the flip-flop circuit 660, the memory controller 605 can provide an extended version of the SEL signal. For example, the flip-flop circuit 660 can extend the falling edge of the SEL signal and output a SEL__FF signal to control the buffer circuit of the WL pusher circuit 650, such as... Figure 7 As shown in the waveform. The SEL_FF signal can extend the hold time of the SEL_FF signal, which advantageously ensures that even when the WL active signal (e.g., 601) is active, it is still valid. <0> After being pulled down, the logic state of the SEL_FF signal remains unchanged for the extended period of time.

[0076] Figure 8 A schematic diagram illustrating a portion of the memory circuit described above (e.g., memory circuit 100, 600) according to some embodiments is shown. As shown, one of the memory cells 125 implemented as 6T SRAM cells may be formed along the main surface of the substrate, sometimes referred to as a front-end-of-line (FEOL) process portion. During the FEOL process, a plurality of metallization layers may be formed, sometimes referred to as a back-end-of-line (BEOL) process. Each of the metallization layers may include a plurality of metal tracks embedded in a dielectric material. Those metallization layers are typically referred to as optional M0 layers, M1 layers, M2 layers, M3 layers, M4 layers, M5 layers, etc. (from bottom to top), and the metal tracks embedded therein are typically referred to as M0 tracks, M1 tracks, M2 tracks, M3 tracks, M4 tracks, M5 tracks, etc., respectively. In some embodiments, the nominal word line WL (e.g., Figure 3 WL <0> WL <1> WL <2> WL <3> ) can be formed in the M1 layer and / or M3 layer, and the boost word line WLB (e.g., Figure 3 WL <0> WL <1> These word lines (WL and WLB) can be formed in different metallization layers (e.g., the M5 layer). These word lines (WL and WLB) can extend in the same lateral direction, and the width of the boost word line (WLB) (extending in a direction perpendicular to the length direction of the word lines WL and WLB) can be wider than the nominal word line (WL).

[0077] Figure 9 A schematic diagram of a memory circuit (or device) 900 according to one embodiment is shown. The memory circuit 900 is substantially similar to the memory circuit 100, except that the memory circuit 900 includes an additional memory array 960. For example, the memory circuit 900 also includes a memory controller 905, a memory array 920, a WL driver circuit 940, and a WL actuator circuit 950. Therefore, the following discussion of the memory circuit 900 will focus on the differences.

[0078] In some embodiments, a WL actuator circuit 950 is physically inserted between memory array 920 and memory array 960, wherein a WL driver circuit 940 is positioned at one end of memory array 920, opposite the other end closer to the WL actuator circuit 950. Therefore, memory array 920 is sometimes referred to as the near array, and memory array 960 is sometimes referred to as the far array. The WL driver circuit 940 can apply a first WL activation signal, such as WL_near, to the corresponding nominal word line of memory array 920. <0> WL_near <1> ...WL_near <n-2>and WL_near <n-1>Furthermore, the WL actuator circuit 950 can apply a second WL activation signal, WL_far, to the corresponding nominal word line of the memory array 960. <0> WL_far <1> ……WL_far <n-2>and WL_far <n-1>.

[0079] Additionally, in instances where K=2 (e.g., where two nominal word lines WL correspond to one boost word line WLB), N / 2 boost word lines WLB (e.g., WLB) <0> ...WLB <n 2-1>It can be operatively coupled between the WL driver circuit 940 and the WL thruster circuit 950, as... Figure 6 or Figure 1 An example. Unlike other examples, when a boost signal is received via the boost word line WLB (e.g., WL_boost). <0> ...WL_boost <n 2-1>When a boost signal is applied, the WL booster circuit 950 can activate one of the nominal word lines at a time. For example, the WL booster circuit 950 may include N / 2 buffer circuits, such as 950... <0> ……950 <n 2-1>Each component in the buffer circuit can activate a pair of corresponding nominal word lines at once using the corresponding boost signal, for example, WL_far. <0> and WL_far <1> Yes...WL_far <n-2>and WL_far <n-1>right.

[0080] Figure 10 Illustrations based on some embodiments Figure 9 An exemplary circuit diagram of a portion of the memory circuitry 900. For example, memory arrays 920 and 960, WL driver circuitry 940, and WL actuator circuitry 950 are each partially shown. It should be understood that... Figure 10 The circuit diagrams are provided for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0081] exist Figure 10 The image shows the four nominal word lines WL of the memory array 920, such as WL_near. <0> WL_near <1> WL_near <2> and WL_near <3> ), and the four nominal word lines of memory array 960, such as WL_far <0> WL_far <1> WL_far <2> and WL_far <3> Each of the nominal word lines WL in memory arrays 920 and 960 extends laterally. A WL actuator circuit 950 is physically inserted laterally between memory arrays 920 and 960, and a WL driver circuit 940 is positioned on the nominal word line WL_near. <0> To WL_near <3> At one end, that is, opposite to the other end closer to the WL driver circuit 950. The WL driver circuit 940 includes logic gates (e.g., NOR gates) 1010 and 1020, and the WL driver circuit 950 includes buffers 1012, 1014, 1022, and 1024. Each of the buffers 1012 to 1024 may be implemented as a transmission gate.

[0082] Buffers 1012-1014 can be operatively formed into a buffer circuit (e.g., 950). <0> ……950 <n 2-1>One of them, and buffers 1022-1024 can be operatively formed into a buffer circuit (e.g., 950). <0> ……950 <n 2-1>The other one in the series. Buffers 1012 and 1014 can receive the boost signal WL_boost from NOR gate 1010. <0> The NOR gate 1010 receives signals applied to the nominal word line WL (WL_near). <0> and WL_near <1> The decoded address bits on the NOR gate; and buffers 1022 and 1024 can receive the boost signal WL_boost from the NOR gate 1020. <1> The NOR gate 1020 receives signals applied to the nominal word line WL (WL_near). <2> and WL_near <3> The decoded address bits on the buffer. Buffers 1012 and 1014 can receive the SEL signal using different enable inputs (so that buffers 1012-1014 can be activated alternately), and buffers 1022 and 1024 can receive the SEL signal using different enable inputs (so that buffers 1022-1024 can be activated alternately). Buffer 1012 can receive the boost signal WL_boost. <0> The logic state of the SEL signal is used to boost the signal WL_boost. <0> Perform logic inversion or forwarding, and convert the inverted / forwarded boost signal WL_boost <0> Provide to the nominal word line WL_far <0> Furthermore, buffer 1014 can receive the boost signal WL_boost. <0> The logic state of the SEL signal is used to boost the signal WL_boost. <0> Perform logic inversion or forwarding, and convert the inverted / forwarded boost signal WL_boost <0> Provide to the nominal word line WL_far <1> Similarly, buffer 1022 can receive the boost signal WL_boost. <1> The logic state of the SEL signal is used to boost the signal WL_boost. <1> Perform logic inversion or forwarding, and convert the inverted / forwarded boost signal WL_boost <1> Provide to the nominal word line WL_far <2> Furthermore, buffer 1024 can receive the boost signal WL_boost. <1> The logic state of the SEL signal is used to boost the signal WL_boost. <1> Perform logic inversion or forwarding, and convert the inverted / forwarded boost signal WL_boost <1> Provide to the nominal word line WL_far <3> .

[0083] Figure 11 A flowchart illustrating a method 1100 for controlling a memory circuit according to some embodiments is shown. The exemplary method 1100 may be implemented using the aforementioned memory circuit 100 (…). Figure 1 ), 600 Figure 6 ) or 900 Figure 9 Any of the following can be performed. Therefore, the following embodiments of method 1100 may be combined with, but are not limited to, them. Figure 1 , Figure 6 or Figure 9 The method 1100 is described by at least one of the following. The illustrated embodiments of method 1100 are provided as examples and are not intended to limit the scope of this disclosure. Therefore, it should be understood that any of the various operations of method 110 may be omitted, reordered, and / or added while remaining within the scope of this disclosure.

[0084] Method 1100 begins with operation 1110, which disables the first nominal word line based on receiving a first decoded address bit having a first logic state, and continues to operation 1120, which enables the second nominal word line based on receiving a second decoded address bit having a second logic state. Using memory circuit 100 as a representative example, when the nominal word line WL... <1> Failed and nominal word line WL <0> When active, the WL driver circuit 140 can respectively target the nominal word line WL <0> and WL <1> Apply the first bit of the decoded ADDR signal (e.g., 301). <0> ) and the second bit of the decoded ADDR signal (e.g., 301) <1> In a non-restricted sample, the first element (301) <0> ) and the second bit (301 <1> ) can be equal to logic 1 and logic 0 respectively.

[0085] Method 1100 continues to operation 1130, which involves performing a NOR operation on the first and second decoded address bits to provide a boost signal. Continuing the above example, the WL driver circuit 140, or its method for receiving the first bit (301)... <0> ) and the second bit (301 <1> The corresponding one in the NOR gate of ) can be used for the first element (301) <0> ) and the second bit (301 <1> Perform NOR to provide the boost signal WL_boost <0> The WL driver circuit 140 can be connected via the boost word line WLB (e.g., WLB...). <0> The boost signal WL_boost <0> The corresponding buffer circuit (e.g., 150) applied to the WL thruster circuit 150 <0> In some embodiments, each of the buffer circuits may include a plurality of buffers, the number of which corresponds to the number of nominal word lines coupled to the boost word lines (e.g., 2). Each of the buffers may correspond to (or be coupled to) a corresponding one of the nominal word lines WL.

[0086] Method 1100 continues to operation 1140, which forwards the boost signal to the disabled first word line based on receiving an enable signal with a first logic state, and operation 1150, which inverts the boost signal to the enabled second word line based on receiving an enable signal with a second logic state. The above-described example, in which each buffer circuit includes a first buffer (e.g., 312) and a second buffer (e.g., 314), is still used, coupled to the nominal word line WL. <0> The first buffer 312 can boost the signal WL_boost based on a first logic state that receives the SEL signal at its first enable input. <0> Perform a logic inversion and provide the inverted version to the nominal word line WL. <0> And coupled to the nominal word line WL <1> The second buffer 314 can boost the signal WL_boost based on a second logic state that receives the SEL signal at its first enable input. <0> Forwarded to WL (online name) <1> .

[0087] In one embodiment of this disclosure, a memory circuit is disclosed. The memory circuit includes: a memory array comprising a plurality of memory cells configured across a first number (N) word lines; a word line driver comprising a second number (N / 2) logic gates, wherein each of the logic gates is configured to receive a first input signal corresponding to a first word line and a second input signal corresponding to a second word line, and to provide a boost signal based on the respective logic states of the first input signal and the second input signal; and a booster circuit comprising N / 2 pairs of first buffers and second buffers, wherein each of the first buffers is configured to receive a corresponding boost signal and disable a corresponding first word line, and each of the second buffers is configured to receive a corresponding boost signal and enable a corresponding second word line.

[0088] In some embodiments, each logic gate includes a NOR gate. In some embodiments, each buffer includes a transmission gate. In some embodiments, the first buffer and the second buffer in each pair are respectively used to receive a first logic state and a second logic state of an enable signal. In some embodiments, each of the word lines extends substantially in a lateral direction. In some embodiments, a word line driver is substantially disposed in the lateral direction at a first end of the word line, and a pusher circuit is substantially disposed in the lateral direction at a second end of the word line opposite to the first end. In some embodiments, the memory circuitry further includes a flip-flop circuit. In some embodiments, the flip-flop circuitry is used to expand the pulse window of the enable signal. In some embodiments, memory cells in the memory array are configured across N / 2 boost word lines. In some embodiments, the word lines and boost word lines are respectively disposed in multiple different metallization layers. In some embodiments, the word lines are respectively formed as multiple first metal tracks with a first width, and the boost word lines are respectively formed as multiple second metal tracks with a second width, wherein the first width is smaller than the second width.

[0089] In another embodiment of this disclosure, a memory circuit is disclosed. The memory circuit includes: a plurality of first memory cells arranged along a first word line extending in a lateral direction; a plurality of second memory cells arranged along a second word line extending in a lateral direction; a logic gate disposed in the lateral direction at a first end of the first word line and the second word line, wherein the logic gate is configured to receive a first input signal corresponding to the first word line and a second input signal corresponding to the second word line, and to provide a boost signal through a boost word line based on the respective logic states of the first input signal and the second input signal; a first buffer disposed in the lateral direction at a second end of the first word line and the second word line, wherein the first buffer is configured to receive the boost signal and to disable the first word line based on a first logic state of receiving an enable signal; and a second buffer disposed in the lateral direction at a second end of the first word line and the second word line, wherein the second buffer is configured to receive the boost signal and to enable the second word line based on a second logic state of receiving an enable signal.

[0090] In some embodiments, the logic gate includes a NOR gate. In some embodiments, the first buffer and the second buffer each include a transmission gate. In some embodiments, the boost word line also extends in a lateral direction. In some embodiments, the first word line and the second word line are disposed in a first metallization layer, and the boost word line is disposed in different second metallization layers. In some embodiments, the first word line and the second word line are each formed as a first metal track with a first width, and the boost word line is formed as a second metal track with a second width, wherein the first width is smaller than the second width. In some embodiments, an enable signal is held in a first logic state or a second logic state before enabling the second word line.

[0091] In another embodiment of this disclosure, a method for controlling memory circuitry is disclosed. The method includes: disabling a first word line based on receiving a first decoded address bit having a first logic state; enabling a second word line based on receiving a second decoded address bit having a second logic state; performing a NOR operation on the first decoded address bit and the second decoded address bit signal to provide a boost signal; forwarding the boost signal to the disabled first word line based on receiving an enable signal having the first logic state; and inverting the boost signal to the enabled second word line based on receiving an enable signal having the second logic state.

[0092] In some embodiments, the enable signal remains in a first logic state or a second logic state before enabling the second word line.

[0093] As used herein, the terms "about" and "approximately" generally indicate the value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may indicate, for example, the value of a given quantity that varies within 10% to 30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0094] The foregoing summary outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A memory circuit, characterized in that, Include: A memory array comprising a plurality of memory cells configured across a first number of word lines; A word line driver includes a second number of logic gates, each of which is configured to receive a first input signal corresponding to a first of the word lines and a second input signal corresponding to a second of the word lines, and to provide a boost signal based on the respective logic states of the first input signal and the second input signal. and A thruster circuit includes the second number of pairs of first buffers and second buffers, wherein each of the first buffers is used to receive a corresponding boost signal and disable a corresponding first word line, and each of the second buffers is used to receive the corresponding boost signal and enable a corresponding second word line.

2. The memory circuit as described in claim 1, characterized in that, The first buffer and the second buffer in each pair are respectively used to receive a first logic state and a second logic state of an enable signal.

3. The memory circuit as described in claim 1, characterized in that, Each of these lines extends substantially in one direction.

4. The memory circuit as described in claim 3, characterized in that, The word line driver is physically disposed on a first end of the word lines in the lateral direction, and the actuator circuit is physically disposed on a second end of the word lines opposite to the first end in the lateral direction.

5. The memory circuit as described in claim 1, characterized in that, The memory cells in the memory array are configured across the second number of boost word lines.

6. The memory circuit as described in claim 5, characterized in that, The word lines are each formed as a plurality of first metal tracks having a first width, and the boost word lines are each formed as a plurality of second metal tracks having a second width, wherein the first width is smaller than the second width.

7. A memory circuit, characterized in that, Include: Multiple first memory cells are arranged along a first word line extending in a lateral direction; Multiple second memory cells are arranged along a second word line extending in the lateral direction; A logic gate is disposed on a first end of the first word line and the second word line in the lateral direction, wherein the logic gate is used to receive a first input signal corresponding to the first word line and a second input signal corresponding to the second word line, and to provide a boost signal through a boost word line based on the respective logic states of the first input signal and the second input signal. A first buffer is disposed in the lateral direction at a second end of the first word line and the second word line, wherein the first buffer is used to receive the boost signal and disable the first word line based on a first logic state that receives an enable signal; and A second buffer is disposed in the lateral direction on the second end of the first word line and the second word line, wherein the second buffer is used to receive the boost signal and enable the second word line based on a second logic state that receives the enable signal.

8. The memory circuit as described in claim 7, characterized in that, The first word line and the second word line are disposed in a first metallization layer, and the boost word line is disposed in a different second metallization layer.

9. The memory circuit as described in claim 7, characterized in that, The first character line and the second character line are each formed as a first metal track with a first width, and the boost character line is formed as a second metal track with a second width, wherein the first width is smaller than the second width.

10. A method for controlling memory circuits, characterized in that, Includes the following steps: A first word line is disabled based on receiving a first decoded address bit having a first logic state; A second word line is activated based on receiving a second decoded address bit having a second logic state; Perform an inverse OR operation on the first decoded address bit and the second decoded address bit to provide a boost signal; Based on receiving an enable signal having the first logic state, the boost signal is forwarded to the failed first word line; and The boost signal is inverted to the active second word line based on the received enable signal having the second logic state.

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