Multi-level parallel and serial voltage sensing readout method and circuit for tnR memristive memory array

Abstract

The application provides a multilevel parallel-serial voltage sensing readout method and circuit for a 1TnR resistive memory array, which comprises the following steps: S1, at least two word line voltage coding combinations are applied to a selected 1TnR unit, each coding combination is used to dynamically configure n resistors in the 1TnR unit into different parallel-serial topologies, so as to generate corresponding readout voltages at an output node; S2, the readout voltages generated when different coding combinations are applied are differentially sampled and amplified by a differential sampling coupling voltage sensing amplifier, so as to obtain amplified decision voltages; and S3, according to the decision voltages corresponding to the multiple coding combinations, the resistance states of the n resistors in the 1TnR unit are mapped out. Therefore, the application overcomes the limitation that the existing VSA scheme is only applicable to 1T2R and cannot analyze more resistance states, can restore the multilevel resistance states of each resistive switching device, and thus greatly improves the effective storage capacity of the 1TnR array.

Description

Technical Field

[0001] This invention relates to the field of memory technology in integrated circuits, and specifically to a multi-level parallel-series voltage sensing readout method and circuit for a 1TnR memristor memory array. Background Technology

[0002] With the rapid development of large language models (LLMs) in search augmentation generation, intelligent agent systems, autonomous driving, and multi-scenario reasoning tasks, resistive random access memory arrays (RRAM / PCM, etc.) that can directly store large-scale LLM parameters on-chip in a high-density manner and complete read and write operations in a low-power and high-parallel manner have become an important component of edge AI chips.

[0003] Driven by this demand, various technical paths for constructing high-density memristor memory have been proposed. Among them, arrays based on the 1TnR (one-transistor–multi-resistor) structure have attracted much attention due to their extremely high area efficiency.

[0004] However, because the 1TnR structure significantly reduces transistor isolation, multiple RRAM cells share the same gating path. When a resistive switching device is selected for a read operation, the remaining unselected devices will form a sneak path through the array lines, causing additional interference current and severely affecting readout accuracy. To suppress the influence of the sneak path, existing 1TnR readout circuits mostly adopt a readout method based on a current sensing amplifier (CSA). In recent years, to reduce readout power consumption and improve signal integrity in large-scale arrays, another type of 1TnR / 1T2R readout method based on a voltage sensing amplifier (VSA) has been proposed.

[0005] With the widespread application of 1TnR structures in high-density memristor memories, inherent problems such as creeping current interference, high read power consumption, poor array scalability, and difficulty in reliably distinguishing multi-level resistance states are becoming increasingly prominent. While existing CSA-based readout methods can recover all resistance state information, they suffer from high peripheral circuit area ratios, high read power consumption, and sensitivity to wiring resistance, making them unsuitable for large-scale arrays. Voltage sensing (VSA)-based solutions, although reducing power consumption, have limited resistance state resolution capabilities for 1TnR (n≥2) structures due to the lack of effective device isolation, failing to support multi-level storage and reducing the effective storage density of the array. Furthermore, existing 1TnR (n≥2) structures mostly employ unidirectional readout, i.e., fixed read direction and read current polarity. Unidirectional readout introduces significant read interference problems, the core of which is the cumulative stress generated inside the device by continuous read operations, leading to state-dependent drift in resistance values. In severe cases, read disturbance faults occur, causing the read window to gradually shrink, decision margin to decrease, and ultimately leading to misjudgments or even functional failures. Moreover, traditional unidirectional readout architectures are difficult to directly extend to bidirectional readout. Summary of the Invention

[0006] The present invention is made to solve the above-mentioned problems, and aims to provide a multi-level parallel-series voltage sensing readout method and circuit for a 1TnR memristor memory array.

[0007] This invention provides a multi-level parallel-series voltage sensing readout method for a 1TnR memristor memory array, characterized by the following steps: Step S1, applying at least two word line voltage encoding combinations to a selected 1TnR cell, each encoding combination being used to dynamically configure n memristors within the 1TnR cell into different parallel-series topologies to generate a corresponding readout voltage at the output node; Step S2, differentially sampling and amplifying the readout voltages generated when applying different encoding combinations using a differential sampling coupled voltage sensing amplifier to obtain an amplified decision voltage; Step S3, mapping the resistance states of the n memristors within the 1TnR cell based on the decision voltages corresponding to the multiple encoding combinations.

[0008] The multi-level parallel-series voltage sensing and readout method for a 1TnR memristor memory array provided by the present invention may also have the following features: step S1 includes the following sub-steps: step S11, applying a first word line voltage encoding combination to form a first parallel-series topology with n memristors to generate a first readout voltage; step S12, applying a second word line voltage encoding combination to form a second parallel-series topology with n memristors to generate a second readout voltage, wherein the second word line voltage encoding combination and the first word line voltage encoding combination constitute an asymmetric flip relationship.

[0009] The multi-level parallel-series voltage sensing readout method for a 1TnR memristor memory array provided by the present invention may also have the following features: wherein step S2 includes the following sub-steps: step S21, in the first sampling phase, sampling the first readout voltage; step S22, in the second sampling phase, sampling the second readout voltage; step S23, through a capacitive coupling circuit, generating a decision voltage based on the bias voltage, the first readout voltage and the second readout voltage.

[0010] The multi-level parallel-series voltage sensing and readout method for a 1TnR memristor memory array provided by this invention may also have the following feature: In step S23, the calculation formula for the decision voltage is as follows:

[0011]

[0012] in, For the decision voltage, This is the bias voltage. The first read voltage, This is the second readout voltage.

[0013] The multi-level parallel-series voltage sensing and readout method for a 1TnR memristor memory array provided by the present invention may also have the following features: step S3 includes the following sub-steps: step S31, comparing the decision voltages corresponding to multiple sets of code combinations with at least one reference voltage to obtain multiple sets of decision results; step S32, matching the multiple sets of decision results with a pre-stored code-resistance state mapping table to obtain the resistance states corresponding to n memristors.

[0014] The multi-level parallel-series voltage sensing readout method for a 1TnR memristor memory array provided by the present invention may also have the following feature: wherein, in step S1, each coding combination is used to dynamically configure the n memristors in the 1TnR cell into a topology structure formed by the first parallel group and the second parallel group connected in series.

[0015] The multi-level parallel-series voltage sensing and readout method for a 1TnR memristor memory array provided by the present invention may also have the following feature: wherein the first parallel group contains p memristors, the second parallel group contains q memristors, and p+q=n.

[0016] This invention provides a multi-stage parallel-series voltage sensing readout circuit for a 1TnR memristor memory array, used to implement the multi-stage parallel-series voltage sensing readout method for a 1TnR memristor memory array as described above. It features the following components: an encoding control sub-circuit for generating and applying at least two word line voltage encoding combinations to a selected 1TnR cell; and a differential sampling coupled voltage sensing amplifier connected to the output node of the 1TnR cell for differentially sampling and amplifying the readout voltage generated when different encoding combinations are applied, to obtain an amplified decision voltage.

[0017] The multi-level parallel-series voltage sensing readout circuit of the 1TnR memristor memory array provided by the present invention may also have the following feature: wherein the memory array adopts an organization structure of horizontal bit lines and vertical word lines.

[0018] The role and effect of invention

[0019] The multi-level parallel-series voltage sensing readout method and circuit for a 1TnR memristor memory array according to the present invention includes: step S1, applying at least two word line voltage encoding combinations to a selected 1TnR cell, each encoding combination being used to dynamically configure the n memristors in the 1TnR cell into different parallel-series topologies to generate a corresponding readout voltage at the output node; step S2, differentially sampling and amplifying the readout voltage generated when applying different encoding combinations through a differential sampling coupled voltage sensing amplifier to obtain an amplified decision voltage; step S3, mapping the resistance states of the n memristors in the 1TnR cell according to the decision voltages corresponding to the multiple encoding combinations. Therefore, the multi-level parallel-series voltage sensing readout method and circuit for a 1TnR memristor memory array of the present invention overcomes the limitation of the existing VSA scheme, which is only applicable to 1T2R and cannot resolve more resistance states, and can recover the multi-level resistance states of each resistive switching device, thereby significantly improving the effective storage capacity of the 1TnR array. Attached Figure Description

[0020] Figure 1 This is a schematic flowchart of a multi-level parallel-series voltage sensing readout method for a 1TnR memristor memory array in an embodiment of the present invention.

[0021] Figure 2 This is a schematic diagram of the structure of the encoding control sub-circuit in the 1T4R array in an embodiment of the present invention.

[0022] Figure 3 This is a diagram showing the output node voltage results for different RRAM resistance state combinations under different word line encodings in embodiments of the present invention.

[0023] Figure 4 This is an output node voltage distribution diagram when the resistive state combination is paired with word line encoding in an embodiment of the present invention.

[0024] Figure 5 This is a comparison table of output node voltage results in an embodiment of the present invention.

[0025] Figure 6 This is a schematic diagram of the differential sampling coupled voltage sensing amplifier in an embodiment of the present invention.

[0026] Figure 7 This is a schematic diagram of the working cycle of the differential sampling coupled voltage sensing amplifier in an embodiment of the present invention.

[0027] Figure 8 This is a readout truth table diagram of a differential sampling coupled voltage sensing amplifier combined with asymmetric encoding in an embodiment of the present invention. Detailed Implementation

[0028] To make the technical means, creative features, objectives and effects of the present invention easy to understand, the following embodiments, in conjunction with the accompanying drawings, specifically illustrate the multi-level parallel and series voltage sensing readout method and circuit of the 1TnR memristor memory array of the present invention.

[0029] Example

[0030] Figure 1 This is a schematic flowchart of a multi-level parallel-series voltage sensing readout method for a 1TnR memristor memory array in an embodiment of the present invention.

[0031] like Figure 1 As shown, this embodiment provides a multi-stage parallel-series voltage sensing readout method for a 1TnR memristor memory array, including:

[0032] Step S1: Apply at least two word line voltage encoding combinations to the selected 1TnR cell. Each encoding combination is used to dynamically configure the n memristors in the 1TnR cell into different parallel-series topologies to generate corresponding readout voltages at the output node.

[0033] Step S1 includes the following sub-steps:

[0034] Step S11: Apply the first word line voltage encoding combination to form a first parallel-connected topology with n memristors, generating the first readout voltage.

[0035] Step S12: Apply the second word line voltage encoding combination to form a second parallel-connected topology with n memristors, generating a second readout voltage, wherein the second word line voltage encoding combination and the first word line voltage encoding combination form an asymmetric flip relationship.

[0036] Each coding combination is used to dynamically configure the n memristors within a 1TnR cell into a topology consisting of a first parallel group and a second parallel group connected in series. The first parallel group contains p memristors, the second parallel group contains q memristors, and p + q = n. In this embodiment, p and q can be any integers, not limited to 1T2R, 1T4R, 1T8R, etc., and not limited to topologies such as 2+2, 1+3, 3+1 (when n=4).

[0037] In this embodiment, different voltage combinations are applied to the vertical word line (WL), and the voltage results are read from the horizontal bit line. By controlling the conduction direction of different units through the vertical word line, n memristors can be configured into different series and parallel combinations. The output node voltage can reflect the stored information and can be grouped. Multiple rounds of encoding combinations combined with the output node voltage grouping results can form a voltage result comparison chart, thereby uniquely determining the multi-stage resistance state of each group of memristors.

[0038] Figure 2 This is a schematic diagram of the structure of the encoding control sub-circuit in the 1T4R array in an embodiment of the present invention.

[0039] Figure 3 This is a diagram showing the output node voltage results for different RRAM resistance state combinations under different word line encodings in embodiments of the present invention.

[0040] Figure 4 This is an output node voltage distribution diagram when the resistive state combination is paired with word line encoding in an embodiment of the present invention.

[0041] like Figure 2 and Figure 3 and Figure 4As shown, in this embodiment, each encoding combination is used to dynamically configure the n memristors within the 1TnR cell into a topology consisting of a first parallel group and a second parallel group connected in series. The first parallel group contains p memristors, the second parallel group contains q memristors, and p+q=n, n=4, p=2, q=2. An encoding control sub-circuit (an expandable parallel-to-serial encoding readout structure) is introduced in the lateral bit line direction, employing a column-by-column gating method so that only one column of 1T4R cells needs to be activated for each readout. The word line levels are encoded using pull-up / pull-down MOS transistors: when encoding "1", it is pulled up to a high level through a PMOS transistor, and when encoding "0", it is pulled down to a low level through an NMOS transistor. Since the four word line levels are strongly driven and remain fixed during readout, the influence of creeping paths on the readout results can be significantly suppressed. This scheme utilizes four RRAMs to form an equivalent network connected in series under word line level control. The RRAMs corresponding to two high word lines are connected in parallel to form one branch, and the RRAMs corresponding to the other two low word lines are connected in parallel to form another branch. The two branches are then connected in series to form a voltage divider readout structure. Group I consists of A, B, and D; Group II consists of C and E; and Group III consists of −A, −B, and −D. The readout decision is made by a voltage sensing amplifier.

[0042] Information about the resistive state combination can be inferred by determining the region where the voltage is located. Furthermore, there is sufficient bandgap between regions I, II, and III for differentiation. For example, in word line encoding 1100, the output node voltage of the resistive state combination HLHH is A, and voltage A is located in region I of the normalized voltage distribution diagram.

[0043] Figure 5 This is a comparison table of output node voltage results in an embodiment of the present invention.

[0044] like Figure 5 As shown, the same resistance state combination yields a unique read result under three different word line codes (1100 1010 1001). By using three read results, the resistance state combination of the RRAM can be uniquely determined, enabling 15 levels of reading.

[0045] Step S2: Differential sampling coupled voltage sensing amplifier is used to differentially sample and amplify the readout voltage generated when different coding combinations are applied to obtain the amplified decision voltage.

[0046] Step S2 includes the following sub-steps:

[0047] Step S21: In the first sampling phase, sample the first readout voltage.

[0048] In step S22, the second readout voltage is sampled during the second sampling phase. During the second sampling phase, word line encoding needs to be switched.

[0049] Step S23: A decision voltage is generated based on the bias voltage, the first readout voltage, and the second readout voltage through a capacitive coupling circuit.

[0050] In step S23, the formula for calculating the decision voltage is as follows:

[0051]

[0052] in, For the decision voltage, This is the bias voltage. The first read voltage, This is the second readout voltage.

[0053] Step S3: Based on the decision voltages corresponding to multiple sets of code combinations, map the resistance states of the n memristors in the 1TnR unit.

[0054] Step S3 includes the following sub-steps:

[0055] Step S31: Compare the decision voltages corresponding to the multiple sets of coded combinations with at least one reference voltage to obtain multiple decision results.

[0056] Step S32: Match multiple sets of decision results with the pre-stored encoding-resistance state mapping table to obtain the resistance states corresponding to n memristors.

[0057] Figure 6 This is a schematic diagram of the differential sampling coupled voltage sensing amplifier in an embodiment of the present invention.

[0058] like Figure 6 As shown, the differential sampling coupled voltage sensing amplifier includes a MOM capacitor C1, a switch SW1, a complementary VSA, and a bias voltage. The differential sampling coupled voltage sensing amplifier, combined with asymmetric readout, yields a sum of values, allowing direct reading of the stored data.

[0059] Figure 7 This is a schematic diagram of the working cycle of the differential sampling coupled voltage sensing amplifier in an embodiment of the present invention.

[0060] like Figure 7 As shown, in state I, switch SW1 is closed, and the first readout voltage is sampled in the first sampling phase. In state II, switch SW1 is open, and word line encoding is switched. In state III, the second readout voltage is sampled in the second sampling phase. Simultaneously, a decision voltage is generated based on the bias voltage, the first readout voltage, and the second readout voltage through the capacitive coupling circuit. In state IV, the complementary VSA is activated, and the data stored in the RRAM is read out based on the decision voltage generated in the previous three states.

[0061] Figure 8This is a readout truth table diagram of a differential sampling coupled voltage sensing amplifier combined with asymmetric encoding in an embodiment of the present invention.

[0062] like Figure 8 As shown, when the resistive-state combination HLLL has word line encoding 1100, the output node voltage is -D; when it has word line encoding 0110, the output node voltage is D. The differential sampling coupled voltage sensing amplifier reads data as 1 during (1100→0110). Through three complete read cycles (1100→0110, 1010→0011, 1001→0101), 4-bit symmetrically quantized data can be read without an additional decoder.

[0063] The method of reading different RRAM resistance state combinations multiple times under a fixed word line encoding order can distinguish 15 resistance state combinations (excluding all high resistance combinations) by making a joint decision on the three read results, covering 15 / 16 (approximately 94%) of the theoretical resistance state combinations.

[0064] While implementing 15 kinds of resistive state combination decisions, it can achieve serial output of 4-bit symmetric quantized data without the need for an additional decoder and significantly reduce readout latency.

[0065] This embodiment employs a bidirectional readout and asymmetric flip strategy. Through multiple rounds of word line encoding (e.g., 1100→0110, 1010→0011, 1001→0101), read margin is superimposed. Each readout round does not use a symmetric flip like (1100→0011), but instead uses an asymmetric flip such as (1100→0110). By sampling different combinations (1100 and 0011 are essentially the same combination), the worst-case scenario is avoided from accumulating in a single read, further improving the read margin. Throughout the entire read cycle, all bit line combinations (e.g., 1100, 0110, 1010, 0011, 1001, 0101) are used. The bidirectional readout time for each memristor is equal, avoiding charge accumulation in the memristor and improving its durability.

[0066] In this embodiment, the multi-level parallel-series voltage sensing readout method of the 1TnR memristor memory array is also compatible with the following types of chip structures, such as planar 1T4R / 1T6R / 1T8R, three-dimensional stacked 1TnR (such as Via-RRAM structure), RRAM, FeRAM, PCM and all memristors based on resistance variation, memory-computing separation memory, in-memory computing accelerator (CIM), model storage NVM subsystem, etc.

[0067] This embodiment provides a multi-stage parallel-series voltage sensing and readout circuit for a 1TnR memristor memory array, used to implement the multi-stage parallel-series voltage sensing and readout method for a 1TnR memristor memory array as described above, including:

[0068] The encoding control subcircuit is used to generate and apply at least two word line voltage encoding combinations to the selected 1TnR cell.

[0069] The Differential Sampling-Coupled VSA (DSC-VSA) is connected to the output node of the 1TnR unit to differentially sample and amplify the readout voltage generated when different coding combinations are applied, so as to obtain the amplified decision voltage.

[0070] The storage array employs a horizontal bit line and vertical word line organization structure, effectively suppressing sneak paths through spatial isolation of read and write paths. Based on this, a voltage readout mechanism combining parallel and serial topologies is implemented, achieving a low-cost, scalable readout scheme suitable for large-scale arrays.

[0071] The role and effect of the embodiments

[0072] According to the multi-level parallel-series voltage sensing readout method and circuit of the 1TnR memristor memory array involved in this embodiment, it includes: step S1, applying at least two word line voltage encoding combinations to the selected 1TnR cell, each encoding combination being used to dynamically configure the n memristors in the 1TnR cell into different parallel-series topologies to generate corresponding readout voltages at the output node; step S2, differentially sampling and amplifying the readout voltages generated when applying different encoding combinations through a differential sampling coupled voltage sensing amplifier to obtain amplified decision voltages; step S3, mapping the resistance states of the n memristors in the 1TnR cell according to the decision voltages corresponding to the multiple sets of encoding combinations. Therefore, the multi-level parallel-series voltage sensing readout method and circuit of the 1TnR memristor memory array of the present invention overcomes the limitation of the existing VSA scheme being only applicable to 1T2R and unable to resolve more resistance states, and can recover the multi-level resistance states of each resistive switching device, thereby significantly improving the effective storage capacity of the 1TnR array.

[0073] This embodiment employs a voltage sensing method combined with lateral bit lines, eliminating the need for CSA and large-scale clamping circuitry. This significantly reduces the peripheral circuit area and readout power consumption, and also avoids the energy waste of uniformly charging all word lines / bit lines during read operations. Compared to traditional CSA readout, it can significantly reduce read power consumption by 40% to 70%.

[0074] This embodiment also achieves cross-phase differential amplification through a differential sampling coupled voltage sensing amplifier, significantly improving the separation of the output node voltage. It is particularly suitable for narrow resistance window devices with Roff / Ron ≈ 3~5, effectively suppressing the read window shrinkage problem caused by the sneak path and voltage drop. In addition, the bidirectional read strategy can counteract the directional charge accumulation of the memristor during long-term read operations, thereby improving array durability.

[0075] Those skilled in the art should understand that this invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to this invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A multi-stage parallel-series voltage sensing and readout method for a 1TnR memristor memory array, characterized in that, include: Step S1: Apply at least two word line voltage encoding combinations to the selected 1TnR cell. Each encoding combination is used to dynamically configure the n memristors in the 1TnR cell into different parallel-series topologies to generate a corresponding readout voltage at the output node. Step S2: Differential sampling coupled voltage sensing amplifier is used to differentially sample and amplify the readout voltage generated when different coding combinations are applied to obtain the amplified decision voltage; Step S3: Based on the decision voltage corresponding to the multiple sets of the encoded combinations, map the resistance states of the n memristors in the 1TnR unit.

2. The multi-stage parallel-series voltage sensing and readout method for a 1TnR memristor memory array according to claim 1, characterized in that: in, Step S1 includes the following sub-steps: Step S11: Apply the first word line voltage encoding combination to form a first parallel-series topology with the n memristors, thereby generating a first readout voltage; Step S12: Apply a second word line voltage encoding combination to form a second parallel-connected topology for the n memristors, generating a second readout voltage, wherein the second word line voltage encoding combination and the first word line voltage encoding combination form an asymmetric flip relationship.

3. The multi-stage parallel-series voltage sensing readout method for a 1TnR memristor memory array according to claim 1, Its features are: Step S2 includes the following sub-steps: Step S21: In the first sampling phase, sample the first readout voltage; Step S22, in the second sampling phase, sample the second readout voltage; Step S23: The decision voltage is generated based on the bias voltage, the first readout voltage, and the second readout voltage through a capacitive coupling circuit.

4. The multi-stage parallel-series voltage sensing and readout method for a 1TnR memristor memory array according to claim 3, characterized in that, In step S23, the formula for calculating the decision voltage is as follows: in, For the decision voltage, This is the bias voltage. The first read voltage, This is the second readout voltage.

5. The multi-stage parallel-series voltage sensing readout method for a 1TnR memristor memory array according to claim 1, Its features are: Step S3 includes the following sub-steps: Step S31: Compare the decision voltages corresponding to the multiple sets of code combinations with at least one reference voltage to obtain multiple sets of decision results; Step S32: Match the multiple sets of decision results with the pre-stored encoding-resistance state mapping table to obtain the resistance states corresponding to the n memristors.

6. The multi-stage parallel-series voltage sensing and readout method for a 1TnR memristor memory array according to claim 1, characterized in that: in, In step S1, each of the coding combinations is used to dynamically configure the n memristors in the 1TnR unit into a topology consisting of a first parallel group and a second parallel group connected in series.

7. The multi-stage parallel-series voltage sensing and readout method for a 1TnR memristor memory array according to claim 6, characterized in that: in, The first parallel group contains p memristors, the second parallel group contains q memristors, and p + q = n.

8. A multi-stage parallel-series voltage sensing and readout circuit for a 1TnR memristor memory array, used to implement the multi-stage parallel-series voltage sensing and readout method for a 1TnR memristor memory array as described in claims 1-7, characterized in that, include: An encoding control subcircuit is used to generate and apply the at least two word line voltage encoding combinations to the selected 1TnR cell; A differential sampling coupled voltage sensing amplifier is connected to the output node of the 1TnR unit to differentially sample and amplify the readout voltage generated when different coding combinations are applied, so as to obtain the amplified decision voltage.

9. The multi-stage parallel-series voltage sensing and readout circuit for a 1TnR memristor memory array according to claim 8, characterized in that: in, The storage array adopts a structure consisting of horizontal bit lines and vertical word lines.

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