A memory operation method, memory and system

Abstract

The application provides an operation method of a memory, a memory and a system, and relates to the technical field of semiconductor chips. The operation method comprises: in a first programming operation stage, performing programming operation on a first storage unit; in a second programming operation stage, performing programming operation on a second storage unit, and applying a programming inhibition voltage to a first bit line coupled with the first storage unit. The first storage unit and the second storage unit are coupled to the same word line, the target threshold voltage of the first storage unit is greater than the target threshold voltage of the second storage unit, and the first programming operation stage is prior to the second programming operation stage. The embodiments of the application change the programming sequence, so that the first storage unit that needs to be programmed to the first state is programmed first, and the second storage unit that needs to be programmed to the second state is programmed later. The problem that the programming interference expands the threshold voltage distribution interval corresponding to the second state is avoided, and the accuracy of in-memory calculation is improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor chip technology, and in particular relates to a method for operating a memory, a memory, and a system. Background Technology

[0002] Flash memory is a type of storage device characterized by non-volatility, fast read / write speeds, low power consumption, and long lifespan. Computing in memory (CIM) technology, based on this memory, writes (or programs) weight data into storage cells within the memory and utilizes Kirchhoff's laws and Ohm's law to perform multiplication and addition operations on the weight data and input data. It is widely used in artificial intelligence (AI) scenarios. The accuracy of writing the weight data into the storage cells directly affects the accuracy of CIM computation. Summary of the Invention

[0003] In a first aspect, this application provides a method for operating a memory. The method includes: performing a programming operation on a first memory cell in a first programming operation phase; performing a programming operation on a second memory cell in a second programming operation phase; and applying a programming disable voltage to a first bit line coupled to the first memory cell. The first and second memory cells are coupled to the same word line, a target threshold voltage for the first memory cell is greater than a target threshold voltage for the second memory cell, and the first programming operation phase precedes the second programming operation phase.

[0004] In some possible implementations, the method further includes: during the first programming operation phase, applying a programming disable voltage to a second bit line coupled to the second memory cell.

[0005] In some possible implementations, the method further includes: during the verification phase of the first programming operation phase, applying a first verification voltage to word lines coupled to the first and second memory cells to verify the threshold voltage of the first memory cell. During the verification phase of the second programming operation phase, applying a second verification voltage to word lines coupled to the first and second memory cells to verify the threshold voltage of the second memory cell. The first verification voltage is greater than the second verification voltage.

[0006] In some possible implementations, the second storage unit is further programmed during the first programming operation phase.

[0007] In some possible implementations, the method further includes: a verification phase during the first programming operation phase, wherein a first verification voltage is applied to word lines coupled to the first and second memory cells to verify a threshold voltage of the first memory cell; and a second verification voltage is applied to word lines coupled to the first and second memory cells to verify a threshold voltage of the second memory cell. During the verification phase of the second programming operation phase, a second verification voltage is applied to word lines coupled to the first and second memory cells to verify a threshold voltage of the second memory cell. The first verification voltage is greater than the second verification voltage, and the second verification voltage is greater than the third verification voltage.

[0008] In some possible implementations, the method further includes: applying a second verification voltage to word lines coupled to the first and second memory cells before the second programming operation phase to verify the threshold voltage of the second memory cell. In response to the threshold voltage of the second memory cell reaching a target threshold voltage, a programming disable voltage is applied to a second bit line coupled to the second memory cell during the second programming operation phase.

[0009] In some possible implementations, the method further includes: during the programming phase of the first programming operation, applying a first programming voltage to word lines coupled to the first and second memory cells; and during the programming phase of the second programming operation, applying a second programming voltage to word lines coupled to the first and second memory cells.

[0010] In some possible implementations, the first programming voltage includes a plurality of pulse voltages that increase in sequence, and the second programming voltage includes a plurality of pulse voltages that increase in sequence.

[0011] In some possible implementations, the initial voltage pulse of the first programming voltage is not less than the initial voltage pulse of the second programming voltage; or, the incremental voltage step of the first programming voltage is not less than the incremental voltage step of the second programming voltage.

[0012] In some possible implementations, the first programming voltage includes a plurality of pulse voltages that increase in sequence, and the second programming voltage includes a plurality of pulse voltages that are identical in value.

[0013] In some possible implementations, one or more pulse voltages in the first programming voltage are greater than the pulse voltages in the second programming voltage.

[0014] In some possible implementations, the first programming voltage includes multiple pulse voltages of the same voltage, and the second programming voltage includes multiple pulse voltages of the same voltage.

[0015] In some possible implementations, the pulse voltage in the first programming voltage is greater than the pulse voltage in the second programming voltage.

[0016] In some possible implementations, the first programming voltage comprises a plurality of pulse voltages with the same voltage, and the second programming voltage comprises a plurality of pulse voltages with voltages increasing sequentially in steps.

[0017] In some possible implementations, one or more pulse voltages in the second programming voltage are less than the pulse voltages in the first programming voltage.

[0018] Secondly, this application provides a memory. The memory includes a memory array, a plurality of word lines, a plurality of bit lines, and peripheral circuitry. The memory array includes a plurality of memory cells, each including a first memory cell and a second memory cell. The plurality of word lines are coupled to the plurality of memory cells, with the first and second memory cells coupled to the same word line. The plurality of bit lines are coupled to the plurality of memory cells and include a first bit line and a second bit line; the first memory cell is coupled to the first bit line, and the second memory cell is coupled to the second bit line. The peripheral circuitry is coupled to the plurality of word lines and the plurality of bit lines; the peripheral circuitry is configured to: perform a programming operation on the first memory cell during a first programming operation phase; perform a programming operation on the second memory cell during a second programming operation phase; and apply a programming disable voltage to the first bit line. The target threshold voltage of the first memory cell is greater than the target threshold voltage of the second memory cell; the first programming operation phase precedes the second programming operation phase.

[0019] In some possible implementations, the peripheral circuitry is also configured to apply a programming disable voltage to the second bit line during the first programming operation phase.

[0020] In some possible implementations, the peripheral circuitry is further configured to: verify the threshold voltage of the first memory cell by applying a first verification voltage to word lines coupled to the first and second memory cells during the verification phase of the first programming operation; and verify the threshold voltage of the second memory cell by applying a second verification voltage to word lines coupled to the first and second memory cells during the verification phase of the second programming operation. The first verification voltage is greater than the second verification voltage.

[0021] In some possible implementations, the peripheral circuitry is also configured to perform a programming operation on the second memory cell during the first programming operation phase.

[0022] In some possible implementations, the peripheral circuitry is further configured to: In a verification phase of the first programming operation, verify the threshold voltage of the first memory cell by applying a first verification voltage to word lines coupled to the first and second memory cells; in a second phase, verify the threshold voltage of the second memory cell by applying a third verification voltage to word lines coupled to the first and second memory cells; and in the verification phase of the second programming operation, verify the threshold voltage of the second memory cell by applying a second verification voltage to word lines coupled to the first and second memory cells. The first verification voltage is greater than the second verification voltage, and the second verification voltage is greater than the third verification voltage.

[0023] In some possible implementations, the peripheral circuitry is further configured to: verify the threshold voltage of the second memory cell by applying a second verification voltage to the word line coupled to the first and second memory cells before the second programming operation phase. In response to the threshold voltage of the second memory cell reaching a target threshold voltage, a programming disable voltage is applied to the second bit line during the second programming operation phase.

[0024] In some possible implementations, the peripheral circuitry is further configured to: apply a first programming voltage to word lines coupled to the first and second memory cells during the programming phase of the first programming operation; and apply a second programming voltage to word lines coupled to the first and second memory cells during the programming phase of the second programming operation.

[0025] In some possible implementations, the first programming voltage includes a plurality of pulse voltages that increase in sequence, and the second programming voltage includes a plurality of pulse voltages that increase in sequence.

[0026] In some possible implementations, the initial voltage pulse of the first programming voltage is not less than the initial voltage pulse of the second programming voltage; or, the incremental voltage step of the first programming voltage is not less than the incremental voltage step of the second programming voltage.

[0027] In some possible implementations, the first programming voltage includes a plurality of pulse voltages that increase in sequence, and the second programming voltage includes a plurality of pulse voltages that are identical in value.

[0028] In some possible implementations, one or more pulse voltages in the first programming voltage are greater than the pulse voltages in the second programming voltage.

[0029] In some possible implementations, the first programming voltage includes multiple pulse voltages of the same voltage, and the second programming voltage includes multiple pulse voltages of the same voltage.

[0030] In some possible implementations, the pulse voltage in the first programming voltage is greater than the pulse voltage in the second programming voltage.

[0031] In some possible implementations, the first programming voltage comprises a plurality of pulse voltages with the same voltage, and the second programming voltage comprises a plurality of pulse voltages with voltages increasing sequentially in steps.

[0032] In some possible implementations, one or more pulse voltages in the second programming voltage are less than the pulse voltages in the first programming voltage.

[0033] Thirdly, this application provides a system. The system includes a processor and a memory according to any of the second aspects described above, the processor being coupled to the memory and configured to control the memory. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this application.

[0035] Figure 1 This is a schematic diagram of the memory structure provided in an embodiment of this application;

[0036] Figure 2 This is a schematic diagram of the structure of a storage block provided in an embodiment of this application;

[0037] Figure 3 A partial cross-sectional schematic diagram of the storage string provided in an embodiment of this application;

[0038] Figure 4 This is a schematic diagram of the connection structure between the peripheral circuit and the memory array provided in the embodiments of this application;

[0039] Figure 5 A schematic diagram of the threshold voltage distribution of the storage unit provided in the embodiments of this application using a single-level cell storage mode;

[0040] Figure 6 A schematic diagram illustrating the computational principle of memory-based in-memory computing provided for embodiments of this application;

[0041] Figure 7 This is a schematic diagram illustrating the change in the threshold voltage distribution range during the ISPP programming method provided in this application embodiment;

[0042] Figure 8 A flowchart illustrating the operation method of the memory provided in an embodiment of this application;

[0043] Figure 9 A schematic diagram of a first type of voltage waveform applied to word lines and bit lines by a peripheral circuit according to an embodiment of this application;

[0044] Figure 10 The adoption of the embodiments provided in this application Figure 9 The diagram shows the change in the threshold voltage distribution range when the voltage waveform is programmed.

[0045] Figure 11 A schematic diagram of a second voltage waveform applied to word lines and bit lines by a peripheral circuit according to an embodiment of this application;

[0046] Figure 12 The adoption of the embodiments provided in this application Figure 11 The diagram shows the change in the threshold voltage distribution range when the voltage waveform is programmed.

[0047] Figure 13 A first voltage waveform diagram of the first programming voltage and the second programming voltage is provided for embodiments of this application;

[0048] Figure 14 A second voltage waveform diagram of the first programming voltage and the second programming voltage is provided for embodiments of this application;

[0049] Figure 15 A third voltage waveform diagram of the first programming voltage and the second programming voltage is provided for embodiments of this application;

[0050] Figure 16 A fourth voltage waveform diagram of the first programming voltage and the second programming voltage is provided for embodiments of this application;

[0051] Figure 17 A schematic diagram of the voltage waveforms applied by the peripheral circuit to the word line and bit line when verifying the threshold voltage of the second memory cell between the first programming operation stage and the second programming operation stage, provided for an embodiment of this application.

[0052] Figure 18 A schematic diagram of the structure of a system provided in this application embodiment;

[0053] Figure 19 This is a schematic diagram of another system provided in an embodiment of this application.

[0054] Reference numerals: 100, Memory; 110, Memory array; 120, Peripheral circuit; 121, Control logic circuit; 122, I / O interface; 123, Voltage generator; 124, Column decoder; 125, Row decoder; 126, Page buffer; 127, Data bus; 128, Register; 200, Memory block; 210, Memory string; 211, Top select transistor; 212, Memory cell; 213, Bottom select transistor; 310, Semiconductor layer; 320, Stacked structure; 321, Gate conductive layer; 322, Dielectric layer; 410, Bit line; 420, Source line; 430, Top select line; 440, Word line; 450, Bottom select line; 500, System; 600, Processor; 700, Memory controller. Detailed Implementation

[0055] The following will combine Figures 1-19 The technical solutions in some embodiments of this application are clearly and completely described. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application.

[0056] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, a particular feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0057] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0058] In describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, in describing some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical or electrical contact; in this case, "coupled" can also be described as "connected." Furthermore, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0059] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0060] Figure 1 A schematic diagram of the structure of a memory provided in an embodiment of this application is shown. For example... Figure 1 As shown, the memory 100 may include a memory array 110 and peripheral circuits 120, with the memory array 110 coupled to the peripheral circuits 120. In some embodiments, the peripheral circuits 120 and the memory array 110 may be independently formed on two separate wafers using different semiconductor manufacturing processes. In some examples, the memory array 110 may be formed using mature process technologies (e.g., any process technology of 22nm, 28nm, and above) to ensure the stability of stored data. The peripheral circuits 120 may be formed using advanced process technologies (e.g., any process technology of 14nm, 10nm, and below) to help improve the speed of data reading / writing in the memory 100. The wafer on which the memory array 110 is formed (which may be called an array wafer) and the wafer on which the peripheral circuits 120 are formed (which may be called a CMOS wafer) are then bonded together using a bonding process, thereby coupling the peripheral circuits 120 to the memory array 110.

[0061] Storage array 110 may include memory blocks 200. For example... Figure 2As shown, in some embodiments, the memory block 200 may include multiple memory strings 210, one end of which is coupled to a bitline (BL) 410, and the other end of which is coupled to a source line (SL) 420. Each memory string 210 may include a top select gate (TSG) 211, multiple memory cells 212, and a bottom select gate (BSG) 213 stacked in series. In some embodiments, the memory cell 212 may be a floating gate transistor or a charge trap field-effect transistor, or other devices capable of storing charge.

[0062] Figure 3 A partial cross-sectional schematic diagram of a possible memory string 210 is shown. The memory string 210 may extend vertically above the semiconductor layer 310. The semiconductor layer 310 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0063] The memory string 210 may include a channel structure extending through the stacked structure 320, which may include alternating gate conductive layers 321 and dielectric layers 322. The number of gate conductive layers 321 and dielectric layers 322 in the stacked structure 320 is related to the number of memory cells 212 in the memory string 210.

[0064] The gate conductive layer 321 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 321 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 321 includes a doped polysilicon layer. Each gate conductive layer 321 may include a control gate surrounding the memory cell 212, and the gate conductive layer 321 at the top of the stacked structure 320 may extend laterally and be coupled to the top select line (TSL) 430; the gate conductive layer 321 at the bottom of the stacked structure 320 may extend laterally and be coupled to the bottom select line (BSL) 450; or the gate conductive layer 321 between the top select line 430 and the bottom select line 450 may extend laterally and be coupled to the word line (WL) 440.

[0065] It should be understood that, despite Figure 3 Additional components, not shown, can form the memory string 210. These additional components include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0066] Please continue to refer to Figure 2 The memory strings 210 can be arranged in a row along a first direction, and multiple rows of memory strings 210 can be arranged in a second direction perpendicular to the first direction to form a memory block 200. In some embodiments, in the same row of memory strings 210, the gate of the top select transistor 211 of each memory string 210 can be coupled to the same top select line 430; in some embodiments, the gates of the top select transistors 211 of some rows of memory strings 210 can be coupled to the same top select line 430; memory strings 210 whose gates of the top select transistors 211 are coupled to the same top select line 430 can constitute a memory chip. The gate of the bottom select transistor 213 in each memory string 210 can be coupled to the same bottom select line 450. In some embodiments, the selected memory string 210 can be activated during read operations, programming operations, and erase operations via the top select line 430 and the bottom select line 450.

[0067] Each memory string 210 is coupled to the peripheral circuit 120 via a corresponding bit line 410. For example, the drain of the top selection transistor 211 in the memory string 210 is coupled to the bit line 410. In order to reduce the number of bit lines 410, the memory string 210 in any memory chip can be coupled to the same bit line 410 with the corresponding memory string 210 in other memory chips.

[0068] For multiple memory strings 210 in memory block 200, the control gate of memory cell 212 in any memory string 210 and the control gate of memory cell 212 at the corresponding position in other memory strings 210 can be coupled to the same word line 440. The source of the bottom select transistor 213 in memory string 210 can be coupled to the source line 420 (or, common source line (CSL)).

[0069] It should be noted that the accompanying drawings of this application only exemplarily illustrate the structure of the storage block 200 in some embodiments, but in practice, the structure of the storage block 200 may also be in other ways.

[0070] like Figure 4As shown, in some embodiments, the peripheral circuitry 120 includes control logic circuitry 121, I / O interface 122, voltage generator 123, column decoder 124, row decoder 125, page buffer 126, data bus 127, and register 128. It should be understood that in some examples, it may also include... Figure 4 Additional circuitry not shown.

[0071] The control logic circuit 121 can be coupled to the voltage generator 123, page buffer 126, column decoder 124, row decoder 125, and I / O interface 122, and is configured to control the operation of each peripheral circuit 120. The control logic circuit 121 can generate operation signals in response to commands (CMDs) or control signals received from the I / O interface 122 to control the operation of the row decoder 125, column decoder 124, page buffer 126, and voltage generator 123; wherein the command can be a programming command, a read command, etc.

[0072] I / O interface 122 can be coupled to control logic circuit 121 and act as a control buffer to buffer control commands received from the host and relay them to control logic circuit 121, as well as to buffer status information received from control logic circuit 121 and relay it to the host. I / O interface 122 can also be coupled to page buffer 126 via data bus 127 and act as a data interface and data buffer to buffer data and relay it to memory array 110 or to buffer data from memory array 110 and relay it to the host.

[0073] Voltage generator 123 can use external or internal power supply voltages to generate various voltages for performing operations such as erasing, programming, reading, and verifying on memory array 110; for example, programming voltage Vpgm, erase voltage Vera, and pass voltage Vpass applied to word line 440, as well as combinations thereof.

[0074] The column decoder 124 can be controlled by the control logic circuit 121 and select one or more memory strings 210 in the memory array 110 by applying a bit line voltage generated from the voltage generator 123.

[0075] The row decoder 125 can, in response to control of the control logic circuit 121, supply word line voltages generated from the voltage generator 123 to the selected word lines and unselected word lines of the memory array 110. As described in detail below, the row decoder 125 is configured to perform programming operations on one or more memory cells 212 in the memory array 110 coupled to the selected word lines.

[0076] Page buffer 126 is coupled to memory array 110 via bit line 410. In some examples, page buffer 126 can read data from memory array 110 and program (write) data to memory array 110 according to control signals from control logic circuitry 121. In other examples, page buffer 126 can store programming data to be programmed into memory array 110 (write data). In still other examples, page buffer 126 can also perform programming verification operations to ensure that data has been correctly programmed into memory cells 212 coupled to select word lines.

[0077] Register 128 can be coupled to control logic circuit 121 and includes a status register, a command register and an address register for storing status information, command opcode (OP code) and command address for controlling the operation of each peripheral circuit 120.

[0078] Those skilled in the art will understand that the operations performed by the line decoder 125, page buffer 126, control logic circuit 121, and voltage generator 123 described in this application can be performed by a processing circuit. This processing circuit may include, but is not limited to, hardware of logic circuits or a hardware / software combination of a processor executing software.

[0079] In some implementations, computing functions can be embedded in the memory 100 to enable in-memory computing, thereby reducing unnecessary data movement. In particular, for artificial intelligence (AI) applications that require matrix operations on large amounts of data (e.g., large models), in-memory computing can significantly reduce data transmission power consumption and latency. In some implementations, the storage unit 212 implementing in-memory computing can adopt a single-level cell (SLC) storage model. Figure 5As shown, the storage cell 212, employing a single-level cell model, can store one bit (i.e., 1 bit) and can have a first state and a second state. Each state of the storage cell 212 has a corresponding threshold voltage distribution interval; for example, the first state corresponds to the first interval, and the second state corresponds to the second interval. In some examples, the first interval is located to the right of the second interval, meaning that the threshold voltage in the first interval is greater than the threshold voltage in the second interval. Therefore, in the first state and the second state, the first state can be called the high state, and the second state can be called the low state.

[0080] like Figure 6 As shown, in some examples, in-memory calculations based on memory 100 are performed by using voltage values ​​V to indicate input data. in Applied to bit line 410 coupled to memory array 110 (e.g. Figure 6 As shown, V in<1> Apply to BL1, V in<2> Apply to BL2), and select word line (e.g.) Figure 6 Apply a first voltage V1 to the non-select word line (e.g., WL1) to the non-select word line. Figure 6 A second voltage V2 is applied to WL1 and WL2 in the memory. In some examples, the first voltage V1 is located between the first interval and the second interval. Thus, in the memory cell 212 coupled to the select word line, the first voltage V1 can turn on the memory cell 212 in the second state, but cannot turn on the memory cell 212 in the first state. In some examples, the second voltage V2 is greater than any voltage in the first interval. Thus, the second voltage V2 can turn on any memory cell 212 coupled to the non-select word line.

[0081] Based on the above discussion, in each memory string 210, if the memory cell 212 coupled to the select word line is in the second state, then there is current in the memory string 210; that is, the second state can indicate that the weight data stored in the memory cell 212 is "1". In some examples, the current in the memory string 210 can be expressed as... Where μ is the charge mobility, C ox V is the gate oxide capacitance of the memory cell, W is the channel width of the memory cell, L is the channel length of the memory cell, and V is the gate oxide capacitance of the memory cell. th This is the threshold voltage of the storage cell. In each storage string 210, if the storage cell 212 coupled to the select word line is in the first state, the current on that storage string 210 is relatively small; that is, the first state can indicate that the weighted data stored in storage cell 212 is "0". The currents on each storage string 210 ultimately converge on the source line 420 to achieve addition, thereby obtaining the output current used to represent the result of the multiplication and addition calculation of the input data and the weighted data (i.e., Figure 6 ΣI shown out <ij>< / ij> As can be seen, the threshold voltage of the storage cell 212 in the second state has a significant impact on the current on the storage string 210. When the threshold voltage distribution range corresponding to the second state (i.e., the second range) widens, the weight data stored in some storage cells 212 in the second state is not an exact "1", which affects the accuracy of in-memory calculation to some extent.

[0082] In some implementations, the peripheral circuit 120 may use increment steppulse programming (ISPP) to program the memory cell 212 so that its threshold voltage reaches a desired threshold voltage distribution range. In some examples, the programming operation may include multiple programming cycles, each including a programming phase and a verification phase. During the programming phase, the peripheral circuit 120 applies a programming voltage Vpgm to the select word line, causing charge to enter the floating gate layer (or charge trap) of the memory cell 212, increasing its threshold voltage. During the verification phase, the peripheral circuit 120 applies a verification voltage Vvfy to the select word line to verify whether the threshold voltage of the memory cell 212 reaches the desired threshold voltage distribution range. If the threshold voltage of the memory cell 212 reaches the desired threshold voltage distribution range (i.e., passes verification), the memory cell 212 will be inhibited from programming in the next programming cycle. During the programming phase of the next programming cycle, the peripheral circuit 120 applies an incremental voltage Vispp to the select word line, increasing the programming voltage Vpgm by a voltage increment, to program at least the unverified memory cell 212.

[0083] As can be seen, the ISPP programming method uses multiple programming cycles to gradually increase the threshold voltage of memory cell 212 until the threshold voltage of memory cell 212 reaches the desired threshold voltage distribution range. Furthermore, as... Figure 7 As shown, since the first interval is located to the right of the second interval, the threshold voltage of memory cell 212 reaches the second interval first. When the threshold voltage of memory cell 212 that needs to be programmed to the second state (i.e., the low state) reaches the second interval, the memory cell 212 completes programming and is disabled from programming in subsequent programming cycles. When the threshold voltage of memory cell 212 that needs to be programmed to the first state (i.e., the high state) reaches the second interval, the memory cell 212 does not complete programming and needs to continue to be programmed in subsequent programming cycles. In other words, memory cell 212 that needs to be programmed to the second state (i.e., the low state) will complete programming first, and memory cell 212 that needs to be programmed to the first state (i.e., the high state) will complete programming later. Therefore, when the peripheral circuit 120 continues to program the memory cell 212 that needs to be programmed to the first state, although the memory cell 212 that needs to be programmed to the second state (i.e., the low state) is prohibited from programming by the peripheral circuit 120 because it has already completed programming, the programming disturbance of continuing to program the memory cell 212 that needs to be programmed to the first state will also affect the memory cell that has already been programmed (i.e., the memory cell 212 programmed to the second state). As a result, after the memory cell 212 that needs to be programmed to the first state (i.e., the high state) is programmed, there is a problem of the threshold voltage distribution range (i.e., the second range) corresponding to the second state widening, which affects the accuracy of in-memory calculation.

[0084] This application provides an operation method for a memory 100, such as... Figure 8 As shown, the operation method includes S110-S120; wherein, S110 precedes S120.

[0085] S110. In the first programming operation stage, the peripheral circuit performs a programming operation on the first memory cell.

[0086] like Figure 9 As shown, in the programming phase of the first programming operation, the peripheral circuit 120 applies a first programming voltage Vpgm1 to the word line (i.e., the select word line) coupled to the first memory cell, and applies a programming selection voltage Vss to the first bit line coupled to the first memory cell, thereby programming the first memory cell. In the verification phase of the first programming operation, the peripheral circuit 120 applies a first verification voltage Vvfy1 to the select word line and applies a bit line voltage Vbl to the first bit line to verify whether the threshold voltage of the first memory cell reaches the target threshold voltage of the first memory cell.

[0087] Please continue to refer to Figure 9 In some embodiments, during the first programming operation phase, the peripheral circuit 120 further applies a programming inhibit voltage (Vinhibit) to the second bit line coupled to the second memory cell, thereby preventing programming of the second memory cell. The first and second memory cells are coupled to the same word line 440. The target threshold voltage of the first memory cell is any voltage within a first range, and the target threshold voltage of the second memory cell is any voltage within a second range. The target threshold voltage of the first memory cell is greater than the target threshold voltage of the second memory cell. That is, the first memory cell 212 is the memory cell 212 that needs to be programmed to a first state, and the second memory cell 212 is the memory cell 212 that needs to be programmed to a second state.

[0088] like Figure 10 As shown, in this embodiment, the first memory cell is programmed during the first programming operation stage. After the first programming operation stage, the peripheral circuit 120 can program the threshold voltage of the first memory cell into a first range, allowing the first memory cell that needs to be programmed to the first state (i.e., high state) to complete programming first. Simultaneously, during the first programming operation stage, a programming inhibit voltage (Vinhibit) is applied to the second bit line to prevent programming of the second memory cell. The second memory cell that needs to be programmed to the second state (i.e., low state) is not programmed. The programming interference in the first programming operation stage only slightly widens the threshold voltage distribution range of the second memory cell compared to the initial threshold voltage distribution range. In other words, this embodiment changes the programming order so that the first memory cell that needs to be programmed to the first state (i.e., high state) completes programming first, and the second memory cell that needs to be programmed to the second state (i.e., low state) completes programming later. Therefore, after the second memory cell that needs to be programmed to the second state (i.e., low state) completes programming, there is no problem of programming interference widening the threshold voltage distribution range (i.e., the second range) corresponding to the second state, thus achieving the purpose of narrowing the second range and helping to improve the accuracy of in-memory calculations.

[0089] like Figure 11 As shown, in some other embodiments, during the first programming operation phase, the peripheral circuit 120 also performs a programming operation on the second memory cell. This differs from... Figure 9 Specifically, during the programming phase of the first programming operation, the peripheral circuit 120 applies a programming selection voltage Vss to both the first bit line and the second bit line. During the verification phase of the first programming operation, the peripheral circuit 120 sequentially applies a third verification voltage Vvfy3 and a first verification voltage Vvfy1 to the word line 440 coupled to the first and second memory cells, and applies a bit line voltage Vbl to the first bit line and the second bit line. The third verification voltage Vvfy3 is less than the first verification voltage Vvfy1. The first verification voltage Vvfy1 is used to verify whether the threshold voltage of the first memory cell reaches the target threshold voltage of the first memory cell, and the third verification voltage Vvfy3 is used to verify whether the threshold voltage of the second memory cell is close to the target threshold voltage of the second memory cell.

[0090] In this embodiment of the application, both the first storage unit and the second storage unit are programmed during the first programming operation stage. For example... Figure 12 As shown, after the first programming operation phase, the peripheral circuit 120 programs the first memory cell to the first state (i.e., high state), and the first memory cell completes programming. Because the third verification voltage Vvfy3 is relatively small, the second memory cell can easily pass verification and be prevented from programming during the first programming operation phase. The first programming operation phase only performs coarse programming on the second memory cell, so that after the first programming operation phase, the threshold voltage of the second memory cell can approach the target threshold voltage of the second memory cell (the second memory cell is not yet fully programmed), thus helping to save the time required for subsequent fine programming of the second memory cell.

[0091] S120, in the second programming operation phase, the peripheral circuit performs a programming operation on the second memory cell and applies a programming disable voltage to the first bit line coupled to the first memory cell.

[0092] Please continue to refer to Figure 9 In the second programming operation phase, the peripheral circuit 120 prevents programming of the first memory cell by applying a programming inhibit voltage Vinhibit to the first bit line. Furthermore, in the programming phase of the second programming operation, the peripheral circuit 120 applies a second programming voltage Vpgm2 to the word line 440 (i.e., the select word line) coupled to the second memory cell, and applies a programming select voltage Vss to the second bit line, thereby programming the second memory cell. In the verification phase of the second programming operation, the peripheral circuit 120 applies a second verification voltage Vvfy2 to the select word line and applies a bit line voltage Vbl to the second bit line to verify whether the threshold voltage of the second memory cell reaches the target threshold voltage of the second memory cell. Wherein, as... Figure 11 As shown, the second verification voltage Vvfy2 is greater than the third verification voltage Vvfy3, and the second verification voltage Vvfy2 is less than the first verification voltage Vvfy1.

[0093] like Figure 13 As shown, in some embodiments, the first programming voltage Vpgm1 includes a plurality of pulse voltages that increase in sequential steps, and the second programming voltage Vpgm2 includes a plurality of pulse voltages that increase in sequential steps. The initial pulse voltage Vinit1 of the first programming voltage Vpgm1 and the initial pulse voltage Vinit2 of the second programming voltage Vpgm2 may be the same or different. The incremental voltage Vispp1 of the first programming voltage Vpgm1 and the incremental voltage Vispp2 of the second programming voltage Vpgm2 may be the same or different. In some embodiments, the initial pulse voltage Vinit1 of the first programming voltage Vpgm1 is not less than the initial pulse voltage Vinit2 of the second programming voltage Vpgm2. In some embodiments, the incremental voltage Vispp1 of the first programming voltage Vpgm1 is not less than the incremental voltage Vispp2 of the second programming voltage Vpgm2.

[0094] like Figure 14 As shown, in some embodiments, the first programming voltage Vpgm1 includes a plurality of pulse voltages that increase sequentially, and the second programming voltage Vpgm2 includes a plurality of pulse voltages with the same voltage. One or more pulse voltages in the first programming voltage Vpgm1 are greater than the pulse voltages in the second programming voltage Vpgm2.

[0095] like Figure 15 As shown, in some embodiments, the first programming voltage Vpgm1 includes multiple pulse voltages of the same voltage, and the second programming voltage Vpgm2 includes multiple pulse voltages of the same voltage. The pulse voltages in the first programming voltage Vpgm1 are greater than the pulse voltages in the second programming voltage Vpgm2.

[0096] like Figure 16 As shown, in some embodiments, the first programming voltage Vpgm1 includes multiple pulse voltages of the same voltage, and the second programming voltage Vpgm2 includes multiple pulse voltages with progressively increasing voltage steps. One or more pulse voltages in the second programming voltage Vpgm2 are less than the pulse voltages in the first programming voltage Vpgm1.

[0097] like Figure 17 As shown, in some embodiments, after the first programming operation phase and before the second programming operation phase, the peripheral circuit 120 further applies a second verification voltage Vvfy2 to the word line 440 (i.e., the select word line) coupled to the first and second memory cells, and applies a bit line voltage Vbl to the second bit line to verify the threshold voltage of the second memory cell. In response to the threshold voltage of the second memory cell reaching the target threshold voltage of the second memory cell (i.e., passing verification), during the second programming operation phase, the peripheral circuit 120 applies a programming inhibit voltage Vinhibit to the second bit line, thereby preventing programming of the verified second memory cell at the second programming operation node and avoiding overprogramming of the second memory cell.

[0098] This application provides a system in some embodiments, in which the system 500 can be applied to different types of electronic devices, such as mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, and servers, and any other electronic device capable of storing data.

[0099] like Figure 18 As shown, the system 500 may include a processor 600 and, as shown, ... Figure 1 The memory 100 is shown. A processor 600 is coupled to the memory 100 and can send commands to the memory 100 to control its operations (e.g., programming, reading, erasing, and arithmetic operations). Specifically, when the memory 100 performs a programming operation, it can perform operations such as... Figure 8 The operating method is shown. In some embodiments, the processor 600 may be a graphics processing unit (GPU), and the memory 100 may be directly connected to or integrated on the GPU.

[0100] like Figure 19 As shown, in some embodiments, the system 500 may further include a memory controller 700, which is coupled to one or more memories 100 to form a memory system. The memory controller 700 can be coupled to the processor 600 via at least one of various interface protocols, and the processor 600 controls the operation of the memory 100 (e.g., programming, reading, erasing, and arithmetic operations) through the memory controller 700. The interface protocol may include at least one of the following: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-E protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, and Integrated Drive Electronics (IDE) protocol.

[0101] It should be understood that the memory controller 700 can also be configured to manage various functions related to data stored or to be stored in the memory 100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. Of course, the memory controller 700 can also perform any other suitable functions (e.g., formatting the memory 100), which will not be elaborated here.

[0102] This application provides a memory operation method, memory, and system. The operation method includes: performing a programming operation on a first memory cell in a first programming operation phase; performing a programming operation on a second memory cell in a second programming operation phase; and applying a programming inhibit voltage to a bit line coupled to the first memory cell. The first and second memory cells are coupled to the same word line, the target threshold voltage of the first memory cell is greater than the target threshold voltage of the second memory cell, and the first programming operation phase precedes the second programming operation phase. This application's implementation changes the programming order so that the first memory cell, which needs to be programmed to a first state (i.e., a high state), completes programming first, and the second memory cell, which needs to be programmed to a second state (i.e., a low state), completes programming later. Therefore, after the second memory cell, which needs to be programmed to the second state (i.e., a low state), completes programming, there is no problem of programming interference widening the threshold voltage distribution range (i.e., the second interval) corresponding to the second state, thereby achieving the purpose of narrowing the second interval and helping to improve the accuracy of in-memory calculations.

[0103] This application provides a computer-readable storage medium storing computer-executable instructions; when executed, the computer-executable instructions can achieve the following: Figure 8 The method shown.

[0104] This application provides a computer device including a processor and a readable storage medium coupled to the processor. The readable storage medium stores executable instructions, which, when executed by the processor, can achieve the following: Figure 8 The method shown.

[0105] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the descriptions of each embodiment in the above embodiments have different focuses. For parts not described in detail in a certain embodiment, refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0106] In the embodiments provided in this application, it should be understood that the provided memory, memory operation method, and system can be implemented in other ways. For example, the division of a certain module is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0107] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0108] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for operating a memory, characterized in that, The operation method includes: In the first programming operation phase, a programming operation is performed on the first memory unit; In the second programming operation phase, a programming operation is performed on the second memory cell, and a programming disable voltage is applied to the first bit line coupled to the first memory cell; The first memory cell and the second memory cell are coupled to the same word line, the target threshold voltage of the first memory cell is greater than the target threshold voltage of the second memory cell, and the first programming operation phase occurs before the second programming operation phase.

2. The operating method according to claim 1, characterized in that, Also includes: During the first programming operation phase, a programming disable voltage is applied to the second bit line coupled to the second memory cell.

3. The operating method according to claim 2, characterized in that, Also includes: During the verification phase of the first programming operation phase, a first verification voltage is applied to the word line coupled to the first memory cell and the second memory cell to verify the threshold voltage of the first memory cell. During the verification phase of the second programming operation phase, a second verification voltage is applied to the word line coupled to the first memory cell and the second memory cell to verify the threshold voltage of the second memory cell; The first verification voltage is greater than the second verification voltage.

4. The operating method according to claim 1, characterized in that, Also includes: During the first programming operation phase, a programming operation is performed on the second storage unit.

5. The operating method according to claim 4, characterized in that, Also includes: In the verification phase of the first programming operation phase, a first verification voltage is applied to the word line coupled to the first memory cell and the second memory cell to verify the threshold voltage of the first memory cell. In the second stage, a third verification voltage is applied to the word line coupled to the first memory cell and the second memory cell to verify the threshold voltage of the second memory cell. During the verification phase of the second programming operation phase, a second verification voltage is applied to the word line coupled to the first memory cell and the second memory cell to verify the threshold voltage of the second memory cell; The first verification voltage is greater than the second verification voltage, and the second verification voltage is greater than the third verification voltage.

6. The operating method according to claim 1, characterized in that, Also includes: Prior to the second programming operation phase, a second verification voltage is applied to the word line coupled to the first memory cell and the second memory cell to verify the threshold voltage of the second memory cell; In response to the threshold voltage of the second memory cell reaching the target threshold voltage of the second memory cell, during the second programming operation phase, a programming disable voltage is applied to the second bit line coupled to the second memory cell.

7. The operating method according to any one of claims 1-6, characterized in that, Also includes: During the programming phase of the first programming operation phase, a first programming voltage is applied to the word line coupled to the first memory cell and the second memory cell; During the programming phase of the second programming operation, a second programming voltage is applied to the word lines coupled to the first memory cell and the second memory cell.

8. The operating method according to claim 7, characterized in that, The first programming voltage includes multiple pulse voltages that increase in a sequential step, and the second programming voltage includes multiple pulse voltages that increase in a sequential step.

9. The operating method according to claim 8, characterized in that, The initial voltage pulse of the first programming voltage is not less than the initial voltage pulse of the second programming voltage; or, the incremental voltage step of the first programming voltage is not less than the incremental voltage step of the second programming voltage.

10. The operating method according to claim 7, characterized in that, The first programming voltage includes multiple pulse voltages that increase sequentially in steps, and the second programming voltage includes multiple pulse voltages that are identical in value.

11. The operating method according to claim 10, characterized in that, One or more pulse voltages in the first programming voltage are greater than the pulse voltages in the second programming voltage.

12. The operating method according to claim 7, characterized in that, The first programming voltage includes multiple pulse voltages with the same voltage, and the second programming voltage includes multiple pulse voltages with the same voltage.

13. The operating method according to claim 12, characterized in that, The pulse voltage in the first programming voltage is greater than the pulse voltage in the second programming voltage.

14. The operating method according to claim 7, characterized in that, The first programming voltage includes multiple pulse voltages with the same voltage, and the second programming voltage includes multiple pulse voltages with voltages increasing sequentially.

15. The operating method according to claim 14, characterized in that, One or more pulse voltages in the second programming voltage are less than the pulse voltages in the first programming voltage.

16. A memory, characterized in that, include: A storage array, the storage array comprising a plurality of storage units, the plurality of storage units including a first storage unit and a second storage unit; Multiple word lines, wherein the multiple word lines are coupled to the multiple memory cells, and the first memory cell and the second memory cell are coupled to the same word line; A plurality of bit lines, coupled to a plurality of memory cells, including a first bit line and a second bit line, wherein the first memory cell is coupled to the first bit line and the second memory cell is coupled to the second bit line; and Peripheral circuitry, coupled to the plurality of word lines and the plurality of bit lines; the peripheral circuitry is configured to: In the first programming operation phase, a programming operation is performed on the first storage unit; In the second programming operation phase, a programming operation is performed on the second memory cell, and a programming disable voltage is applied to the first bit line; Wherein, the target threshold voltage of the first memory cell is greater than the target threshold voltage of the second memory cell; and the first programming operation phase precedes the second programming operation phase.

17. The memory according to claim 16, characterized in that, The peripheral circuit is also configured to apply a programming disable voltage to the second bit line during the first programming operation phase.

18. The memory according to claim 17, characterized in that, The peripheral circuit is also configured to: During the verification phase of the first programming operation phase, the threshold voltage of the first memory cell is verified by applying a first verification voltage to the word line coupled to the first memory cell and the second memory cell. In the verification phase of the second programming operation phase, the threshold voltage of the second memory cell is verified by applying a second verification voltage to the word line coupled to the first memory cell and the second memory cell. The first verification voltage is greater than the second verification voltage.

19. The memory according to claim 16, characterized in that, The peripheral circuit is also configured to perform a programming operation on the second storage unit during the first programming operation phase.

20. The memory according to claim 19, characterized in that, The peripheral circuit is also configured to: In the verification phase of the first programming operation phase, the first phase verifies the threshold voltage of the first memory cell by applying a first verification voltage to the word line coupled to the first memory cell and the second memory cell. The second stage verifies the threshold voltage of the second memory cell by applying a third verification voltage to the word line coupled to the first memory cell and the second memory cell. In the verification phase of the second programming operation phase, the threshold voltage of the second memory cell is verified by applying a second verification voltage to the word line coupled to the first memory cell and the second memory cell. The first verification voltage is greater than the second verification voltage, and the second verification voltage is greater than the third verification voltage.

21. The memory according to claim 16, characterized in that, The peripheral circuit is also configured to: Prior to the second programming operation phase, the threshold voltage of the second memory cell is verified by applying a second verification voltage to the word line coupled to the first memory cell and the second memory cell. In response to the threshold voltage of the second memory cell reaching the target threshold voltage of the second memory cell, a programming disable voltage is applied to the second bit line during the second programming operation phase.

22. The memory according to any one of claims 16-21, characterized in that, The peripheral circuit is also configured to: During the programming phase of the first programming operation phase, a first programming voltage is applied to the word line coupled to the first memory cell and the second memory cell; During the programming phase of the second programming operation, a second programming voltage is applied to the word lines coupled to the first memory cell and the second memory cell.

23. The memory according to claim 22, characterized in that, The first programming voltage includes multiple pulse voltages that increase in a sequential step, and the second programming voltage includes multiple pulse voltages that increase in a sequential step.

24. The memory according to claim 23, characterized in that, The initial voltage pulse of the first programming voltage is not less than the initial voltage pulse of the second programming voltage; or, the incremental voltage step of the first programming voltage is not less than the incremental voltage step of the second programming voltage.

25. The memory according to claim 22, characterized in that, The first programming voltage includes multiple pulse voltages that increase sequentially in steps, and the second programming voltage includes multiple pulse voltages that are identical in value.

26. The memory according to claim 25, characterized in that, One or more pulse voltages in the first programming voltage are greater than the pulse voltages in the second programming voltage.

27. The memory according to claim 22, characterized in that, The first programming voltage includes multiple pulse voltages with the same voltage, and the second programming voltage includes multiple pulse voltages with the same voltage.

28. The memory according to claim 27, characterized in that, The pulse voltage in the first programming voltage is greater than the pulse voltage in the second programming voltage.

29. The memory according to claim 22, characterized in that, The first programming voltage includes multiple pulse voltages with the same voltage, and the second programming voltage includes multiple pulse voltages with voltages increasing sequentially.

30. The memory according to claim 29, characterized in that, One or more pulse voltages in the second programming voltage are less than the pulse voltages in the first programming voltage.

31. A system, characterized in that, It includes a processor and a memory as described in any one of claims 16-30, wherein the processor is coupled to the memory and the processor is configured to control the memory.

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