Device without semiconductor channel and method of manufacturing the same

Abstract

The application provides a three-terminal electronic device without semiconductor channel, comprising: a gate control layer composed of a gate electrode and an insulating gate medium; a source electrode and a drain electrode, the source electrode and the drain electrode being nanometer-scale conductive material electrodes, a spacing distance between the source electrode and the drain electrode being in a range of atomic spacing to sub-10 nm, and a spacing space between the source electrode and the drain electrode being a channel region of the device; and a metal interconnection layer connected with the source electrode and the drain electrode. The three-terminal electronic device without semiconductor channel according to the application can realize an on-state current density of not less than 0.5 mA / μA and a sub-threshold swing of less than 60 mV / dec under a source-drain voltage of less than 0.3 V, solves the problems of low on-state current and slow switching speed of a traditional three-terminal electronic switch with vacuum / air channel medium, and exhibits the characteristics of high performance and low power consumption.

Description

Technical Field

[0001] This invention relates to a three-terminal electronic device without a semiconductor channel and its fabrication method. Background Technology

[0002] Semiconductor device technology based on silicon, especially complementary metal-oxide-semiconductor (CMOS) integrated circuit technology, has driven profound changes in human information society. Currently, silicon-based CMOS technology is entering the sub-3nm node stage, with device feature sizes approaching 10-20 nm physical dimensions. However, as device feature sizes shrink, new problems, such as the short-channel effect, severely affect the switching characteristics of devices. Larger gate leakage currents and gradually deteriorating subthreshold characteristics also pose significant challenges to further miniaturization, restricting further improvements in the overall performance of semiconductor devices. Therefore, to address issues such as the short-channel effect, high leakage current, and subthreshold swing limitations, CMOS devices have evolved from planar to FinFET (Fin Field-Effect Transistor) and the more complex three-dimensional transistor era. Although three-dimensional transistors can greatly increase the gate's control over the channel, they are susceptible to fluctuations in physical parameters, such as gate oxide thickness, fin thickness, gate length, and other parameters. Their subthreshold swing is also limited by the room-temperature Boltzmann distribution, with a limit of 60 mV / dec.

[0003] For these reasons, devices with new structures, materials, and principles will inevitably emerge. For example, silicon-based tunneling transistors operate on the band-to-band tunneling principle, and their subthreshold swing can break the theoretical limit of 60mV / dec for room-temperature subthreshold swing of MOSFETs, but their on-state current is relatively small. Much research aims to find a semiconductor material as a substitute for silicon to construct semiconductor transistors with higher performance and lower power consumption. Therefore, low-dimensional semiconductors with ultra-thin structures and high carrier mobility are attracting increasing attention. Some low-dimensional semiconductor material tunneling devices (such as GaAs, InAs, GaN, etc.) and semiconductor cold-source transistors have the potential to surpass the performance limits of traditional silicon-based transistors, but these only change the material characteristics and cannot alter the intrinsic physical properties of the semiconductor device structure or the bottlenecks in device performance. For example, the maximum current output capability of a semiconductor device is affected by the carrier density of the semiconductor channel material; the fastest speed is related to the carrier mobility of the semiconductor channel material; the fastest switching speed is determined by the charge transport characteristics of the gold-semiconductor interface; and the device driving voltage is related to the band gap of the semiconductor channel.

[0004] Vacuum / short-length air dielectrics, as channel materials with lower scattering than semiconductors, can effectively avoid the effects of channel scattering in vacuum / short-length air electronic devices, theoretically possessing higher ballistic transport characteristics than traditional semiconductor devices. However, the on-state current of vacuum / short-length air electronic devices is often determined by transport processes such as field emission and thermionic emission, resulting in excessively high turn-on voltages. Furthermore, the switching process of vacuum / short-length air electronic devices is slower than that of semiconductor channels, causing their overall device performance to often lag behind that of semiconductor devices. Summary of the Invention

[0005] This invention provides a three-terminal electronic device without a semiconductor channel and a method for fabricating the same.

[0006] According to one aspect of this disclosure, a three-terminal electronic device without a semiconductor channel is proposed, comprising: The gate control layer consists of a gate electrode and an insulating gate dielectric. The device includes a source electrode and a drain electrode, both made of nanoscale conductive material. The distance between the source and drain electrodes is in the range of interatomic spacing to sub-10 nm, and the space between them forms the channel region of the device. A metal interconnect layer is connected to the source electrode and the drain electrode.

[0007] According to at least one embodiment of the device disclosed herein, the conductive material electrode is formed from conductive materials such as metal nanoparticles, two-dimensional materials, or Weyl fermions through a self-assembly process or a micro / nano fabrication process.

[0008] According to at least one embodiment of the three-terminal electronic device of the present disclosure, the conductive material electrode has an atomically smooth surface.

[0009] According to at least one embodiment of the three-terminal electronic device of the present disclosure, the conductivity characteristics between the source electrode and the drain electrode can be adjusted by changing at least one of the interface band characteristics of the source electrode and the drain electrode and the gate voltage.

[0010] According to at least one embodiment of the present disclosure, the three-terminal electronic device is at least one of a bottom gate structure, a top gate structure, a side gate structure, a ring gate structure, and a three-dimensional multilayer stacked structure.

[0011] According to at least one embodiment of the three-terminal electronic device of the present disclosure, the insulating gate medium contains all or part of an oxide, a nitride, a fluoride, or a composite medium.

[0012] According to at least one embodiment of the present disclosure, the three-terminal electronic device has an on-state current density of not less than 0.5 mA / μA and a subthreshold swing of less than 60 mV / dec when the source-drain voltage is less than or equal to 0.3 V.

[0013] According to another aspect of the present invention, a method for fabricating a three-terminal electronic device as described in any of the preceding claims is provided, wherein the source electrode and drain electrode, the gate control layer and the metal interconnect layer are fabricated by a self-assembly process or a micro / nano fabrication process.

[0014] The three-terminal electronic device without a semiconductor channel according to the present invention exhibits an on-state current density of not less than 0.5 mA / μA and a subthreshold swing of less than 60 mV / dec when the source-drain voltage is less than or equal to 0.3 V. This surpasses the electrical performance of traditional silicon-based tunneling devices and on-chip vacuum / air electronic devices, solving the problems of low on-state current and slow switching speed. Simultaneously, the driving voltage of the device can be reduced to below 0.3 V, demonstrating high performance and low power consumption. Attached Figure Description

[0015] The accompanying drawings illustrate exemplary embodiments of the invention and, together with the description thereof, serve to explain the principles of the invention. These drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification.

[0016] Figure 1 This is an intentional description of a device according to one embodiment of the present invention.

[0017] Figure 2 The device structure of the bottom gate structure fabricated according to the present invention is shown by scanning electron microscopy (SEM).

[0018] Figure 3 The invention is shown Figure 4 The transfer characteristic curves of the device in the embodiment.

[0019] Figure 4 The diagram shows a device with a local bottom gate structure constructed on a substrate.

[0020] Figure 5 A schematic diagram of a device with a top grid structure constructed on a substrate is shown. Figure 6 This is a schematic diagram of a three-terminal electronic device with a side-gate structure according to another embodiment of the present invention. Detailed Implementation

[0021] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present invention are shown in the accompanying drawings.

[0022] It should be noted that, unless otherwise specified, the embodiments and features described in this invention can be combined with each other. The technical solution of this invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0023] Unless otherwise stated, the exemplary embodiments / exemplifications shown are to be understood as providing exemplary features of various details that provide ways in which the technical concept of the invention can be implemented in practice. Therefore, unless otherwise stated, the features of the various embodiments / exemplifications may be additionally combined, separated, interchanged and / or rearranged without departing from the technical concept of the invention.

[0024] For descriptive purposes, the present invention may use spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side (e.g., in a “sidewall”)” to describe the relationship between one component and another (other) component as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the equipment during use, operation, and / or manufacture.

[0025] The rapid development of semiconductor devices has driven profound changes in human information society. However, as the feature size of semiconductor devices gradually approaches their physical and engineering limits, the key performance characteristics of semiconductor devices, including complementary metal-oxide-semiconductor transistors (CMOS), traditional silicon-based tunneling transistors, and low-dimensional semiconductor material tunneling transistors, are difficult to further improve. Although vacuum tube devices, especially on-chip vacuum electronic devices, can effectively avoid the effects of channel dielectric scattering and, in principle, have higher ballistic transport characteristics than traditional semiconductor devices, their overall device performance, especially gate control characteristics, often lags behind semiconductor devices. Nanoscale metal electrodes, including those composed of metal nanomaterials, quasi-metallic materials such as graphene, and Weyl fermion materials, offer new opportunities to improve device performance through their characteristic band structures.

[0026] This invention proposes a novel three-terminal electronic device structure, constructed based on metal nanoelectrodes and gate dielectric materials, which eliminates the need for a semiconductor channel. The three-terminal electronic device according to this invention simultaneously achieves high on-state performance and fast switching, while maintaining high energy efficiency.

[0027] This invention proposes a three-terminal electronic device without a semiconductor channel and its fabrication method. The three-terminal electronic device is a device without a semiconductor channel, comprising a gate electrode, a source electrode, and a drain electrode. The three-terminal electronic device can be a global bottom-gate structure, a local bottom-gate structure, a top-gate structure, a side-gate structure, a global back-gate structure, a local back-gate structure, a ring-gate structure, a three-dimensional multilayer stacked structure, etc. The three-terminal electronic device can be a planar structure device or a vertical structure device.

[0028] exist Figure 1 In this paper, a detailed description of the non-semiconductor channel three-terminal electronic device of the present invention is given using a partial bottom-gate structure as an example. It should be understood that the principle is the same for other structural forms. The present invention does not use semiconductor materials to form channels (no semiconductor structure is used in the channel region, and the space between the source and drain electrodes is used as the channel region), but only uses conductive material electrodes and gate control layers to construct high-performance three-terminal electronic devices.

[0029] like Figure 1 As shown, a three-terminal electronic device 100 without a semiconductor channel according to an embodiment of the present invention may include a gate control layer, source and drain electrodes (source electrode and drain electrode) and a metal interconnect layer.

[0030] The gate control layer consists of a gate electrode 110 and an insulating gate dielectric 120. The gate electrode 110 can be formed by depositing a gate metal, which can be formed from suitable metal materials such as palladium (Pd) or gold (Au), or from materials such as metal nanoparticles, two-dimensional materials, or Weyl fermions through self-assembly or micro / nano fabrication processes. Two-dimensional materials can be, for example, graphene. The insulating gate dielectric 120 contains, in whole or in part, at least one of oxides, nitrides, fluorides, or composite dielectrics, such as at least one of silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, or lanthanum oxide. When the insulating gate dielectric does not cover the source or drain electrodes, the insulating gate dielectric 120 can be made of materials such as zinc oxide or titanium oxide.

[0031] The source and drain electrodes 130 are nanoscale conductive material electrodes. Figure 1 The example shown uses the upper electrode as the drain electrode and the lower electrode as the source electrode, with the spacing D between the source and drain electrodes ranging from atomic spacing to sub-10 nm. The spacing between the source and drain electrodes is set to be smaller than the mean free path of electrons in air. By setting the electrode spacing according to the present invention, electron scattering within the channel can be avoided, making it easier to achieve characteristics of low driving voltage and high output current.

[0032] The source / drain electrodes 130 can be fabricated from conductive materials at the nanoscale. Conductive materials include, for example, metallic materials, quasi-metallic materials (such as graphene), and semi-metallic materials (such as Weyl fermions). This paper will use metallic nanoparticles as an example; however, those skilled in the art will understand that appropriate processes can be employed when other materials are selected.

[0033] In this invention, the source and drain electrodes 130 are formed with atomically smooth surfaces. Based on these atomically smooth surfaces, losses at the electrode interfaces can be effectively reduced. Furthermore, by changing at least one of the interface band characteristics of the source and drain electrodes and the gate voltage, the conductivity characteristics between the source and drain electrodes can be adjusted, thereby achieving the purpose of regulating device performance.

[0034] The metal interconnect layer 140 is connected to the source electrode and the drain electrode, respectively. The metal interconnect layer 140 is used to connect the source electrodes together (or connect them to an external circuit) and connect the drain electrodes together (or connect them to an external circuit). The material of the metal interconnect layer 140 can be a Ti / Au bilayer metal, etc.

[0035] like Figure 1 As shown, the three-terminal electronic device 100 also includes a substrate, which may include a silicon layer 150 and a silicon dioxide layer 160.

[0036] Figure 2 The device structure of a bottom-gate structured three-terminal electronic device fabricated according to the present invention is shown by scanning electron microscopy (SEM), wherein the source and drain are fabricated from gold nanoparticles and the metal interconnect layer of Ti / Au material is shown.

[0037] Figure 3 The invention is shown Figure 2 The transfer characteristic curve of the three-terminal electronic device in the embodiment is shown. From the electrical test results of this device, it can be obtained that at the source-drain voltage V... ds When the voltage is 0.01V, the on-state current I of the device is... on The on-state current density is approximately 0.1 mA, greater than 0.5 mA / μA, and the average subthreshold swing is 46 mV / dec. It can be determined that the device fabricated according to the technical solution of this invention breaks through the limitation of subthreshold swing of traditional semiconductor CMOS devices, and also surpasses the on-state electrical performance of traditional silicon-based tunneling devices and on-chip vacuum electronic devices, solving the problems of low on-state voltage and slow switching speed.

[0038] In various embodiments of the present invention, a combination of top-down micro / nano fabrication and bottom-up self-assembly processes can be used to fabricate channelless three-terminal electronic devices. The top-down micro / nano fabrication process starts from macroscopic objects, gradually reducing material size through techniques such as photolithography and etching, deconstructing larger materials to generate nanostructures, and ultimately achieving the fabrication of micro / nano structures. The bottom-up self-assembly process, on the other hand, starts from the microscopic world, controlling the interaction forces of atoms, molecules, and other nanomaterials to build various units together to form micro / nano structures and devices.

[0039] This invention employs a combination of these two methods: a bottom-up self-assembly process using nanoparticle solutions to construct nano-gap electrodes, aiming to obtain electrodes with atomically smooth surfaces and enabling large-area fabrication. The other steps utilize top-down micro / nano fabrication methods. During device fabrication, techniques such as electron beam lithography (EBL), electron beam evaporation deposition (EBE), and atomic layer deposition (ALD) can be used.

[0040] Alternatively, in this invention, the entire device can be constructed using either a bottom-up self-assembly process or a top-down micro / nano fabrication process.

[0041] As an example, Figure 4 The diagram illustrates a three-terminal electronic device with a local bottom-gate structure constructed on a substrate. (See diagram for example.) Figure 4 As shown, a gate electrode 110 and an insulating gate dielectric 120 are fabricated on a substrate of silicon layer 150 and silicon dioxide layer 160, then a source / drain electrode 130 is fabricated, and finally a metal interconnect layer 140 is fabricated.

[0042] For example, firstly, a gate structure is patterned on a substrate using EBL (Electron Beam Printing) technology. After development and fixing, Ti / Pd = 0.3 / 30nm is deposited as the gate metal using EBE (Electron Beam Evaporation) technology. Then, 10nm hafnium oxide is grown at 90℃ using ALD (Alternating Discharge) technology to achieve the fabrication of a localized bottom gate. Trenchings for depositing gold nanoparticles are patterned using electron beam lithography (EBL), followed by a self-assembly process to form a gold nanoparticle array. 10μL of a colloidal solution of gold nanoparticles is dropped onto the sample surface using a pipette and allowed to evaporate completely. Finally, the PMMA template and the randomly distributed gold nanoparticles on the sample surface are removed using an acetone and isopropanol solution. The resulting gold nanoparticle assembly serves as the source and drain electrodes. Before the self-assembly of the gold nanoparticles, the gate oxide surface can be treated using inductively coupled plasma etching (ICP-E) to enhance the adhesion between the nanoparticles and the gate oxide surface, thereby improving the assembly yield of chemically synthesized gold nanoparticles in the trenches. The contact electrodes were then patterned using EBL technology, and after development and fixing, Ti / Au metal was deposited using EBE technology as the contact electrodes.

[0043] As another example, Figure 5 A schematic diagram of a three-terminal electronic device with a top-gate structure constructed on a substrate is shown. (Example) Figure 5 As shown, source and drain electrodes 130 are fabricated on a substrate of silicon layer 150 and silicon dioxide layer 160, then a metal interconnect layer 140 is fabricated, and finally a gate electrode 110 and an insulating gate dielectric 120 are fabricated.

[0044] For example, trenches for depositing gold nanoparticles are patterned using electron beam lithography (EBL), followed by the formation of a gold nanoparticle array using a self-assembly process. Next, contact electrodes are patterned using EBL, and after development and fixing, Ti / Au metal is deposited using EBE as the contact electrodes. Gate oxide is grown using ALD. Finally, the gate structure is patterned, and after development and fixing, gate metal is deposited using EBE to form the gate.

[0045] exist Figure 6 The diagram illustrates a three-terminal electronic device with a side-gate structure according to another embodiment of the present invention. Those skilled in the art should understand that the purpose of this invention is to provide a device structure without a semiconductor channel. The technical solution of this invention eliminates the need for a semiconductor channel and can be used in devices with various structures (global bottom-gate structure, local bottom-gate structure, top-gate structure, side-gate structure, global back-gate structure, local back-gate structure, ring gate structure, planar structure, vertical structure, etc.). Other device structures will not be described in detail in this invention.

[0046] The three-terminal electronic device according to the present invention features a simple structure, small feature spacing, and convenient fabrication process. The source and drain electrodes exhibit controllable interface curvature, atomic-level smoothness, diverse structures, and independence from the wettability of metal materials on semiconductor surfaces (significantly different from low-dimensional semiconductors). The subthreshold swing of the device fabricated by the present invention can overcome the limitations of traditional CMOS devices constrained by room-temperature Boltzmann distribution. Simultaneously, at source-drain voltages below 0.3V, the on-state current exceeds the electrical performance of traditional silicon tunneling devices and on-chip vacuum / air electronic devices. The device performance of the present invention is not constrained by the charge transport process and band structure of the semiconductor material. The key performance characteristics of the device of the present invention not only surpass the technical requirements of advanced node high-performance semiconductor transistors but also reduce the device driving voltage to below 0.3V, exhibiting high performance and low power consumption.

[0047] The device according to the present invention can be applied in various fields such as integrated circuits, optoelectronic communication, and biosensing.

[0048] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0049] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0050] Those skilled in the art should understand that the above embodiments are merely for illustrating the present invention and are not intended to limit the scope of the invention. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present invention.

Claims

1. A three-terminal electronic device without a semiconductor channel, characterized in that, include: The gate control layer consists of a gate electrode and an insulating gate dielectric. The device includes a source electrode and a drain electrode, both made of nanoscale conductive material. The distance between the source and drain electrodes is in the range of interatomic spacing to sub-10 nm, and the space between them forms the channel region of the device. A metal interconnect layer is connected to the source electrode and the drain electrode.

2. The three-terminal electronic device as described in claim 1, characterized in that, The conductive material electrode is formed from materials such as metal nanoparticles, two-dimensional materials, or Weyl fermions through self-assembly or micro / nano fabrication processes.

3. The three-terminal electronic device as described in claim 2, characterized in that, The conductive material electrode has an atomically smooth surface.

4. The three-terminal electronic device as described in claim 3, characterized in that, The conductivity between the source and drain electrodes can be adjusted by changing at least one of the interface band characteristics of the source and drain electrodes and the gate voltage.

5. The three-terminal electronic device as described in claim 1, characterized in that, The device is at least one of the following: bottom gate structure, top gate structure, side gate structure, ring gate structure, and three-dimensional multilayer stacked structure.

6. The three-terminal electronic device as described in claim 1, characterized in that, The insulating gate medium contains, in whole or in part, at least one of oxides, nitrides, fluorides, and composite media.

7. The three-terminal electronic device as described in any one of claims 1 to 6, characterized in that, The three-terminal electronic device has an on-state current density of not less than 0.5mA / μA and a subthreshold swing of less than 60mV / dec when the source-drain voltage is less than or equal to 0.3V.

8. A method for fabricating a three-terminal electronic device as described in any one of claims 1 to 7, characterized in that: The source electrode, drain electrode, gate control layer, and metal interconnect layer are fabricated using self-assembly or micro / nano fabrication processes.

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