A laser, a method for manufacturing a laser, and an optical module

Abstract

The disclosure provides a laser, a preparation method of the laser and an optical module, and relates to the technical field of optical elements, so as to meet the demand of the optical module for high-power lasers. The laser comprises a current blocking layer, and the current blocking layer comprises a P-InP blocking layer, an impurity freezing layer, a first N-InP blocking layer and a second N-InP blocking layer. The method comprises the following steps: introducing a first doping source into an epitaxial growth chamber to form the P-InP blocking layer on both sides of a BH mesa; stopping the introduction of the first doping source and reducing the temperature of the epitaxial growth chamber to a first preset temperature; introducing a second doping source into the epitaxial growth chamber, so that the second doping source penetrates into the surface at the top of the P-InP blocking layer, the top of the P-InP blocking layer is processed to form the impurity freezing layer, and the first N-InP blocking layer is formed above the impurity freezing layer; and the second N-InP blocking layer is formed above the first N-InP blocking layer.

Description

Technical Field

[0001] This disclosure relates to the field of optical fiber communication technology, and in particular to a laser, a method for fabricating the laser, and an optical module. Background Technology

[0002] With the development of new business and application models such as cloud computing, mobile internet, and video, advancements in optical communication technology have become increasingly important. In optical communication technology, the optical module, as one of the key components in optical communication equipment, enables photoelectric signal conversion; and in the development of optical communication technology, the data transmission rate of optical modules is required to continuously improve.

[0003] Some optical modules include a light source and an optical modulation chip. The light generated by the light source is transmitted to the optical modulation chip, which modulates the light to generate an optical signal. The light source is usually a laser, and the laser's luminous power directly affects the optical power intensity of the output optical signal from the optical modulation chip. Therefore, in order to meet the ever-increasing demand for optical power intensity of the output optical signal from the optical modulation chip, it is necessary to continuously improve the luminous power of the laser. Summary of the Invention

[0004] Some embodiments provide a laser, a method for fabricating the laser, and an optical module, which facilitates meeting the optical module's requirement for a high-power laser.

[0005] Some embodiments provide a method for fabricating a laser, the laser including a current blocking layer, the current blocking layer including a P-InP blocking layer, an impurity freezing layer, a first N-InP blocking layer and a second N-InP blocking layer; the method includes: A first doping source is introduced into the epitaxial growth chamber to form the P-InP barrier layer on both sides of the BH mesa; the first doping source is used to dope Zn. Stop the flow of the first doping source and lower the temperature of the epitaxial growth chamber to the first preset temperature; When the temperature of the epitaxial growth chamber drops to the first preset temperature, a second doping source is introduced into the epitaxial growth chamber, so that the second doping source penetrates into the surface of the top of the P-InP barrier layer to process the top of the P-InP barrier layer to form the impurity freezing layer, and the first N-InP barrier layer is formed above the impurity freezing layer. The second doping source is used to dope Si. The temperature of the epitaxial growth chamber is increased to form a second N-InP barrier layer above the first N-InP barrier layer. The doping concentration of the second N-InP barrier layer is greater than that of the first N-InP barrier layer.

[0006] One of the above technical solutions has the following advantages or beneficial effects: In the process of fabricating a laser, a first doping source is introduced into the epitaxial growth chamber to form P-InP barrier layers on both sides of the BH mesa, so that the formed P-InP barrier layers cover both sides of the BH mesa. After the P-InP barrier layers are formed, the introduction of the first doping source is stopped and the temperature of the epitaxial growth chamber is lowered; when the temperature of the epitaxial growth chamber is lowered to a first preset temperature, a second doping source is introduced, which will cause an impurity freezing layer to form on the top surface of the P-InP barrier layer, and then a first N-InP barrier layer is formed above the impurity freezing layer. Finally, the temperature of the epitaxial growth chamber is raised to form a second N-InP barrier layer above the first N-InP barrier layer. Firstly, because the temperature of the epitaxial growth chamber is lower than the temperature at which the P-InP barrier layer is grown, the lattice of the P-InP barrier layer is fixed, thus freezing the Zn in the P-InP barrier layer. Consequently, during subsequent growth, the Zn in the P-InP barrier layer does not easily diffuse, making it difficult for Zn in the P-InP barrier layer to diffuse into the subsequently grown first N-InP barrier layer. Secondly, during the growth of the P-InP barrier layer, the atomic bonds on the surface of the P-InP barrier layer are not fully filled. Because the temperature of the epitaxial growth chamber is reduced to a first preset temperature before the Si2H6 saturated gas is introduced into the epitaxial growth chamber, the surface lattice of the top of the P-InP barrier layer is fixed. Therefore, the diffusion rate of Si on the surface of the top of the P-InP barrier layer is much greater than its diffusion rate inside the P-InP barrier layer. When Si enters the surface of the top of the P-InP barrier layer, it prevents Si from continuing to diffuse into the P-InP barrier layer, thus forming an impurity frozen layer containing a very small amount of Si and Zn on the surface of the top of the P-InP barrier layer. As the Si₂H₆ saturated gas is introduced into the epitaxial growth chamber for an extended period, a first N-InP barrier layer grows above the impurity freezing layer. With the growth of this first N-InP barrier layer, the impurity freezing layer prevents the diffusion of Zn from the P-InP barrier layer into the first N-InP barrier layer, and also prevents the diffusion of Si from the first N-InP barrier layer into the P-InP barrier layer. This reduces the diffusion rates of Zn and Si in both the P-InP and first N-InP barrier layers, thereby minimizing interdiffusion between them. Furthermore, the impurity freezing layer creates a distinct interface between the P-InP and N-InP barrier layers and also prevents the diffusion of Zn and Si as the temperature increases, thus enhancing the current blocking effect of the current blocking layer. Therefore, by introducing an impurity freezing layer during the epitaxial growth of the current blocking layer, the mutual diffusion between P-type and N-type impurities can be effectively blocked, thereby ensuring a clear and steep PN junction interface of the current blocking layer, significantly improving the blocking performance of the current blocking layer, reducing the threshold current of the laser, and enhancing the high-temperature operating stability and lifespan of the device.

[0007] By increasing the temperature of the epitaxial growth chamber, a second N-InP barrier layer is formed above the first N-InP barrier layer. This allows the doping concentration of the second N-InP barrier layer to be higher than that of the first N-InP barrier layer, resulting in gradient doping of the N-InP barrier layer. Consequently, a high-resistivity region is formed between the second and first N-InP barrier layers, effectively limiting lateral current propagation. The first N-InP barrier layer uses a relatively low doping concentration and is combined with an impurity freezing layer, which helps ensure the interface quality between the P-InP and N-InP barrier layers. Furthermore, increasing the temperature of the epitaxial growth chamber to form the second N-InP barrier layer helps reduce defects in the second N-InP barrier layer, ensuring its quality.

[0008] In some embodiments, a method for fabricating a laser is provided, wherein reducing the temperature of the epitaxial growth chamber to a first preset temperature includes: reducing the temperature of the epitaxial growth chamber to the first preset temperature according to a preset cooling rate; Raising the temperature of the epitaxial growth chamber includes: raising the temperature of the epitaxial growth chamber to a second preset temperature at a preset heating rate, wherein the second preset temperature is greater than the first preset temperature, and the heating rate is greater than the cooling rate.

[0009] Another technical solution described above has the following advantages or beneficial effects: By setting different cooling and heating rates, the thermodynamic conditions of epitaxial growth can be more precisely controlled during the formation of the impurity freezing layer and the subsequent second N-InP barrier layer. A slower preset cooling rate allows impurity atoms more time to diffuse and rearrange when the epitaxial growth chamber temperature is lowered to the first preset temperature, thereby forming a high-quality impurity freezing layer with good impurity freezing effect, ensuring its effective blocking of the interdiffusion of P-type and N-type impurities. A faster preset heating rate can raise the epitaxial growth chamber temperature to the second preset temperature in a shorter time, reducing unnecessary impurity diffusion and interface reactions during the heating process. This helps maintain the interface integrity between the first N-InP barrier layer and the impurity freezing layer, while quickly reaching the high-temperature conditions required for the growth of the second N-InP barrier layer, ensuring its high doping concentration and smooth formation of the gradient doping structure, thereby improving the overall performance of the current blocking layer and the device characteristics of the laser.

[0010] In some embodiments, a method for fabricating a laser is provided in which the doping concentration of the first N-InP blocking layer is not higher than 2E18cm⁻¹. -3 The doping concentration of the second N-InP barrier layer is not less than 3E18cm. -3 The thickness of the first N-InP barrier layer is less than the thickness of the second N-InP barrier layer.

[0011] Another technical solution in the above-mentioned technical solution has the following advantages or beneficial effects: by setting the doping concentration of the first N-InP barrier layer to no higher than 2E18cm -3 This effectively reduces its own light absorption loss, minimizing its adverse impact on the laser's output efficiency. Simultaneously, the lower doping concentration also helps reduce the layer's conductivity, preventing interference with the device's electrical performance. The doping concentration of the second N-InP blocking layer is set to be no less than 3E18cm⁻¹. -3 This significantly enhances the current blocking layer's ability to block charge carriers, particularly holes, effectively limiting carrier diffusion outside the active region, improving recombination efficiency in the active region, ensuring good conductivity and current spread of the current blocking layer, and avoiding increased series resistance due to insufficient doping. Furthermore, differentiated doping concentrations help optimize the freezing effect of the impurity freezing layer. The Si atoms in the lower-doped first N-InP blocking layer interact more effectively with the impurity freezing layer, further enhancing the suppression of P-type and N-type impurity diffusion. This allows the current blocking layer to maintain stable PN junction characteristics under high-temperature operating conditions, effectively improving the output power stability and long-term reliability of the laser in high-temperature environments.

[0012] The thickness of the first N-InP blocking layer is less than that of the second N-InP blocking layer. This allows the relatively thinner first N-InP blocking layer to achieve initial blocking and transition functions without excessively increasing the series resistance of the device. The thicker second N-InP blocking layer, on the other hand, provides a stronger and more stable current blocking effect, ensuring that the current is effectively limited within the predetermined active region. This further optimizes the transverse mode characteristics and luminous efficiency of the laser, ultimately improving the overall performance of the laser.

[0013] In some embodiments, a method for fabricating a laser is provided, the method further comprising: An etching aid layer is formed on the top of the wafer body of the laser, the etching aid layer covering the top of the wafer body; wherein the longitudinal etching rate of the wafer body is greater than the lateral etching rate of the wafer body, and the lateral etching rate of the etching aid layer is greater than the lateral etching rate of the wafer body. The etching auxiliary layer and the wafer body are etched, and the residual etching auxiliary layer is removed after etching to form a BH mesa; Before introducing the first doping source into the epitaxial growth chamber, the surface of the BH mesa is cleaned.

[0014] Another technical solution described above has the following advantages or beneficial effects: In the laser fabrication process, by introducing an etching auxiliary layer and utilizing its lateral etching rate being greater than that of the wafer body, the etching auxiliary layer can preferentially expand laterally to both sides during the etching process to form the BH mesa. When the wafer body and the etching auxiliary layer form an inverted trapezoidal mesa, as etching continues, the width of the etching auxiliary layer continuously decreases, gradually exposing the top edge of the inverted trapezoidal mesa. The etching solution will then etch downwards from the gradually exposed mesa edge, removing the sharp corners at the top of the wafer body. This changes the width of the top of the wafer body, allowing for further adjustment of the width of the quantum well layer, forming a trapezoidal BH mesa. This solves the problem of easily forming an inverted trapezoidal cross-section BH mesa due to the longitudinal etching rate of the wafer body being greater than its lateral etching rate. As the etching depth increases, the width of the trapezoid continues to decrease, allowing the width of the quantum well layer to reach the preset width.

[0015] Thus, by setting an etching auxiliary layer, the limitation caused by the extremely low etching rate of the

[111] crystal plane of InP material can be effectively overcome, and the width of the quantum well layer can be precisely controlled. The isotropic etching characteristics of the etching auxiliary layer and the anisotropic etching characteristics of the wafer body work together to dynamically change the geometry of the mesa during the etching process, thereby breaking through the structural constraints of the traditional inverted trapezoidal mesa and making it easier to ensure the power of the fabricated laser.

[0016] In some embodiments, a method for fabricating a laser is provided in which the etching auxiliary layer is an InGaAsP layer.

[0017] Another technical solution mentioned above has the following advantages or beneficial effects: The InGaAsP used in the InGaAsP layer is a quaternary compound, which exhibits isotropic properties during etching and will not form difficult-to-etch crystal planes. Using an InGaAsP layer makes it easier to control the lateral etching rate of the InGaAsP layer and the etching rate of the sharp corners at the top of the wafer body, thereby facilitating the control of the width of the quantum well layer so that the width of the quantum well layer can reach the preset width.

[0018] In some embodiments, a method for fabricating a laser is provided, wherein the wafer body of the laser includes an N-InP substrate, an N-InP buffer layer, an AlInGaAs quantum well layer, a P-InP confinement layer, an InGaAsP grating layer, and a P-InP cladding layer; The method further includes: The N-InP buffer layer is formed on top of the N-InP substrate; The AlInGaAs quantum well layer is formed above the N-InP buffer layer; The P-InP confinement layer is formed above the AlInGaAs quantum well layer; The InGaAsP grating layer is formed above the P-InP confinement layer; The P-InP cladding layer is formed above the InGaAsP grating layer.

[0019] Another technical solution mentioned above has the following advantages or beneficial effects: By sequentially constructing a multilayer epitaxial structure consisting of an N-InP buffer layer, an AlInGaAs quantum well layer, a P-InP confinement layer, an InGaAsP grating layer, and a P-InP cladding layer, a complete laser active region and optical confinement structure are formed. The N-InP buffer layer effectively alleviates the lattice mismatch stress between the N-InP substrate and the subsequent epitaxial layers, providing a smooth crystal surface for high-quality epitaxial growth and reducing the extension of dislocation defects into the active region. As the core region for carrier recombination luminescence, the AlInGaAs quantum well layer's tunable bandgap allows the laser emission wavelength to precisely match the requirements of optical communication systems. Simultaneously, the three-dimensional confinement effect of the quantum well structure significantly enhances the differential gain coefficient of the active region. The P-InP confinement layer and the N-InP buffer layer together constitute a dual heterostructure, utilizing the large conduction band and valence band order between InP and AlInGaAs to achieve efficient confinement of carriers and reduce the threshold current density. The introduction of the InGaAsP grating layer provides the necessary Bragg grating structure for distributed feedback lasers. By precisely controlling the grating period and duty cycle, single-mode selection of the laser emission wavelength can be achieved, suppressing side-mode competition and obtaining single-mode laser output with a high side-mode suppression ratio. The P-InP cladding, as the uppermost epitaxial structure, not only completes the lateral expansion and injection of current, but its higher bandgap energy further enhances the longitudinal confinement of the optical field, reducing leakage losses towards the P-type electrode.

[0020] In some embodiments, a method for fabricating a laser is provided, the method further comprising: A first P-InP layer and a second P-InP layer are sequentially grown on top of the BH mesa and the current blocking layer. The doping concentration of the second P-InP layer is greater than that of the first P-InP layer, and the doping concentration of the first P-InP layer is no higher than 5E17cm⁻¹. -3 .

[0021] Another technical solution mentioned above has the following advantages or beneficial effects: by sequentially growing a low-doped first P-InP layer and a high-doped second P-InP layer on the BH mesa and the top of the current blocking layer, and controlling the doping concentration of the first P-InP layer to be no higher than 5E17cm⁻¹ -3This design effectively optimizes the electrical performance and carrier transport characteristics of the laser. The lightly doped first P-InP layer acts as a current spreading layer, reducing resistance during lateral current propagation and allowing for more uniform current injection into the active region. This avoids localized overheating caused by current concentration, thereby improving laser reliability. Simultaneously, the heavily doped second P-InP layer helps reduce contact resistance with subsequent electrodes, increasing carrier injection efficiency. The combination of the lightly doped first P-InP layer and the heavily doped second P-InP layer forms a gradient doping structure that balances uniform current spreading with good electrode contact, further optimizing the laser's threshold characteristics and output power. This provides a strong guarantee for the stable operation of the laser in applications such as optical modules.

[0022] In some embodiments, a method for fabricating a laser is provided, the method further comprising: An electrical contact layer is grown above the second P-InP layer. The electrical contact layer is a P-InGaAs electrical contact layer, and the doping concentration of the P-InGaAs electrical contact layer is not less than 2E18cm⁻¹. -3 .

[0023] Another technical solution mentioned above has the following advantages or beneficial effects: By setting a highly doped P-InGaAs electrical contact layer, the ohmic contact resistance between the metal electrode and the semiconductor material can be effectively reduced, and the Joule heat loss during current injection can be decreased, thereby improving the electro-optical conversion efficiency and operational stability of the laser. Simultaneously, the InGaAs material and the P-InP cladding have excellent lattice matching characteristics, which can avoid dislocation defects introduced by lattice mismatch, ensuring high-quality growth of the epitaxial layer and further optimizing the reliability of the device.

[0024] In some embodiments, a method for fabricating a laser is provided, wherein the first preset temperature is 550℃-600℃; and the second preset temperature is 600℃-630℃.

[0025] Another technical solution described above has the following advantages or beneficial effects: By precisely controlling the first preset temperature between 550℃ and 600℃, uniform growth and precise thickness control of the epitaxial layer can be achieved while ensuring the crystal quality of the InP material. 550℃-600℃ falls within the optimal growth window range for InP material, ensuring sufficient pyrolysis of the source material and providing adequate surface migration energy to promote the orderly arrangement of atoms on the growth surface. It also effectively suppresses thermal decomposition phenomena such as In element segregation or P element volatilization caused by excessively high temperatures, thereby maintaining the stability of the stoichiometry of the epitaxial layer. By controlling the second preset temperature between 600℃ and 630℃, defects in the second N-InP barrier layer are reduced, improving the crystal quality of the second N-InP barrier layer.

[0026] In some embodiments, a laser is provided, which is a laser prepared by the above-described preparation method, and the power of the laser is not less than 70mW.

[0027] Another technical solution described above has the following advantages or beneficial effects: By employing the optimized fabrication method, the obtained laser can achieve an output power of not less than 70mW, meeting the stringent power requirements of high-speed optical communication systems. This power level is achieved thanks to the significant improvement in the quality of the epitaxial layer crystal and the precise control of the active region quantum well structure, resulting in simultaneous optimization of carrier injection efficiency and optical field confinement factor. The high power output capability not only extends the transmission distance of optical signals in repeaterless transmission scenarios and reduces the system's dependence on optical amplifiers, but also provides ample margin for multi-channel power budget allocation in wavelength division multiplexing systems. Simultaneously, the stable power output characteristics help suppress chirp effects during modulation, improve signal transmission quality, and facilitate adaptation to the needs of optical module applications with speeds of 400G and above.

[0028] In some embodiments, an optical module is provided, including a laser, said laser being the laser provided in the above embodiments.

[0029] Another technical solution described above has the following advantages or beneficial effects: by integrating the high-power laser into the optical module, the optical module as a whole possesses excellent optical signal transmission capability. Since the laser itself has an output power of no less than 70mW, when the optical module is applied to a high-speed optical communication system, it can meet the power budget requirements for long-distance transmission without the need for an additional preamplifier, effectively simplifying the structural design of the optical module and reducing overall power consumption. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly introduced below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0031] Figure 1 This is a schematic diagram of the structure of an optical module access switch according to some embodiments; Figure 2 This is a partial structural diagram of a switch according to some embodiments; Figure 3 This is a structural diagram of an optical module according to some embodiments; Figure 4 An exploded view of an optical module according to some embodiments; Figure 5 This is an internal structural diagram of an optical module according to some embodiments; Figure 6 This is a cross-sectional structural diagram of a laser according to some embodiments; Figure 7 The following is a flowchart of a method for fabricating a laser according to some embodiments. Figure 1 ; Figure 8 Fabrication structure of a laser according to some embodiments Figure 1 ; Figure 9 Fabrication structure of a laser according to some embodiments Figure 2 ; Figure 10 This is a cross-sectional view of a mesa etching according to some embodiments; Figure 11 This is a cross-sectional view of another mesa etching according to some embodiments; Figure 12 The following is a flowchart of a method for fabricating a laser according to some embodiments. Figure 2 ; Figure 13 The following is a flowchart of a method for fabricating a laser according to some embodiments. Figure 3 ; Figure 14 Fabrication structure of a laser according to some embodiments Figure 3 ; Figure 15 The following is a flowchart of a method for fabricating a laser according to some embodiments. Figure 4 ; Figure 16 The following is a flowchart of a method for fabricating a laser according to some embodiments. Figure 5 . Detailed Implementation

[0032] The embodiments of this disclosure will now be described clearly and in detail with reference to the accompanying drawings. However, the described embodiments are merely some, and not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0033] Unless the context otherwise requires, throughout this specification, the term "comprising" is interpreted as open and inclusive, meaning "including, but not limited to"; the terms "first" and "second" should not be construed as indicating or implying relative importance or an upper limit on the number; the term "multiple" means two or more; the term "connection" should be interpreted broadly, for example, "connection" can be a fixed connection, a detachable connection, or an integral part, and can be a direct connection or an indirect connection through an intermediate medium; the use of the terms "applies to" or "configured to" implies open and inclusive language, which does not exclude the applicability to or configuration of devices to perform additional tasks or steps; descriptions such as "parallel," "perpendicular," "identical," "consistent," and "aligned" are not limited to absolute mathematical theoretical relationships, but also include acceptable error ranges arising in practice, as well as differences based on the same design concept but due to manufacturing reasons.

[0034] In optical communication technology, information is loaded onto light to generate optical signals, which are then used to transmit information between information processing devices. Connections are established between these devices via optical transmission equipment. Optical power loss is minimal during transmission through this equipment, allowing for long-distance transmission with relatively low power loss. Light boasts extremely high transmission speeds, and the cost of optical transmission equipment, such as fiber optic cables, is lower than that of electrical transmission equipment like copper wires. Using optical signals to transmit information offers advantages such as long-distance transmission, high speed, and low cost.

[0035] Information processing equipment typically includes switches, servers, optical network units (ONUs), optical distribution networks (ODNs), optical line terminals (OLTs), gateways, routers, mobile phones, computers, tablets, televisions, etc.; optical transmission equipment typically includes optical fibers and optical waveguides. Information processing equipment can recognize and process electrical signals, while optical transmission equipment can transmit optical signals. Therefore, optical modules are needed between the optical transmission equipment and the information processing equipment to perform the conversion between optical and electrical signals.

[0036] In some embodiments, the optical signal input and / or optical signal output of the optical module are connected to an optical fiber, and the electrical signal input and / or electrical signal output of the optical module are connected to a switch; a first optical signal from the optical fiber is transmitted to the optical module, the optical module converts the first optical signal into a first electrical signal, and transmits the first electrical signal to the switch; a second electrical signal from the switch is transmitted to the optical module, the optical module converts the second electrical signal into a second optical signal, and transmits the second optical signal to the optical fiber.

[0037] Information processing equipment connected to optical modules can also be referred to as the host computer for optical modules. In access network transmission scenarios, the host computer for optical modules is usually an ONU, ODN, or OLT; in data center transmission scenarios, the host computer for optical modules is usually a Switch or Server.

[0038] Figure 1 This is a schematic diagram of the structure of an optical module access switch according to some embodiments. For example... Figure 1 As shown, switch 100 has multiple optical module interfaces. Multiple optical modules are inserted into the switch through these interfaces, establishing electrical signal communication between the optical modules and the switch. Optical fiber 101 is connected to the optical modules, establishing optical signal communication between the optical fiber and the optical modules. One end of optical fiber 101 is connected to the optical module, and the other end of optical fiber 101 (…) Figure 1 (not shown in the image) connects to another optical module ( Figure 1 (Not shown in the image), another optical module accesses the server ( Figure 1 (not shown in the image) or another switch ( Figure 1 (Not shown in the image).

[0039] In some embodiments, the optical fiber 101 and the optical module 200 are detachably connected; in other embodiments, the optical fiber 101 and the optical module 200 are non-detachably connected.

[0040] The switch 100 is configured to provide data electrical signals to the optical module 200, or receive data electrical signals from the optical module 200, or monitor or control the operating status of the optical module 200.

[0041] In some embodiments, the optical module is a tool for converting optical signals to electrical signals. During the conversion process, the information does not change, but the encoding or decoding method of the information changes.

[0042] Figure 2 This is a partial structural diagram of a switch according to some embodiments. To clearly show the connection relationship between the optical module 200 and the switch 100, Figure 2 Only the structures related to the switch 100 and the optical module 200 are shown. (For example...) Figure 2As shown, in some embodiments, the switch 100 further includes a PCB circuit board 102 disposed in the receiving cavity, and a cage 103 disposed on the surface of the PCB circuit board 102; the optical module 200 is inserted into the cage 103 and fixed by the cage 103.

[0043] In some embodiments, a heat sink 104 is provided on the cage 103 to dissipate heat from light; in some embodiments, the heat sink 104 has protruding structures such as fins to increase the heat dissipation area.

[0044] In some embodiments, an electrical connector is provided inside the cage 103, which is configured to access the electrical interface of the optical module 200.

[0045] In some embodiments, the optical module 200 is inserted into the cage 103 of the switch 100, and the cage 103 fixes the optical module 200. The heat generated by the optical module 200 is conducted to the cage 103 and then diffused through the heat sink 104.

[0046] In some embodiments, the optical module 200 is inserted into the cage 103 of the switch 100, and the electrical interface of the optical module 200 is connected to the electrical connector inside the cage 103, thereby establishing an electrical signal connection between the optical module 200 and the switch 100.

[0047] In some embodiments, the optical interface of the optical module 200 is connected to the optical fiber 101, thereby enabling the optical module 200 to establish an optical signal connection with the optical fiber 101.

[0048] Figure 3 This is a structural diagram of an optical module according to some embodiments. Figure 4 This is an exploded view of an optical module according to some embodiments. Figure 3 and Figure 4 As shown, in some embodiments, the optical module 200 includes a housing. The housing may include an upper housing 201 and a lower housing 202. The upper housing 201 covers the lower housing 202, forming two openings 203 and 204, one of which is an electrical interface and the other is an optical interface. In some embodiments, the housing forms an opening that serves as both an electrical interface and an optical interface.

[0049] In some embodiments, the upper housing 201 and the lower housing 202 are made of metal materials, which is beneficial for achieving electromagnetic shielding and heat dissipation.

[0050] The assembly method of combining the upper housing 201 and the lower housing 202 facilitates the installation of circuit boards 300 and other components into the housing. The upper housing 201 and the lower housing 202 can encapsulate and protect the aforementioned devices.

[0051] The direction of the line connecting the two openings 203 and 204 can be consistent with or inconsistent with the length direction of the optical module 200. For example, opening 203 is located at the end of the optical module 200. Figure 3 (The right end), opening 204 is also located at the end of optical module 200 ( Figure 3 (The left end). Alternatively, opening 203 is located at the end of optical module 200, while opening 204 is located on the side of optical module 200.

[0052] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011, which covers the two lower side plates 2022 of the lower housing 202 to form the aforementioned housing.

[0053] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and perpendicular to the cover plate 2011. The two upper side plates and the two lower side plates 2022 are combined to realize that the upper housing 201 covers the lower housing 202.

[0054] like Figure 3 and Figure 4 As shown, in some embodiments, the optical module includes a circuit board 300 disposed within a housing. The circuit board 300 includes circuit traces, electronic components, and chips, etc. The electronic components and chips are connected according to the circuit design through the circuit traces to realize functions such as power supply, electrical signal transmission, and grounding. Electronic components may include, for example, capacitors, resistors, transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs). Chips may include microcontroller units (MCUs), laser driver chips, transimpedance amplifiers (TIAs), limiting amplifiers (LAs), clock and data recovery chips (CDRs), or power management chips, etc.

[0055] In some embodiments, the circuit board includes a rigid circuit board, which, due to its relatively rigid material, can also serve a load-bearing function, such as being able to stably support the aforementioned electronic components and chips; the rigid circuit board can also be inserted into an electrical connector in the cage 103 of the switch 100.

[0056] In some embodiments, the circuit board may also include a flexible circuit board, which can be used independently or in conjunction with a rigid circuit board.

[0057] In some embodiments, the circuit board further includes gold fingers 301 formed on its end surface, the gold fingers 301 being composed of a plurality of independent pins.

[0058] In some embodiments, the gold fingers 301 are disposed on a surface on one side of the circuit board 300 (e.g., Figure 4 (as shown on the upper surface); In some embodiments, the gold fingers 301 are disposed on the upper and lower surfaces of the circuit board 300 to provide a greater number of pins, thereby adapting to applications with high pin count requirements.

[0059] In some embodiments, the gold fingers 301 of the circuit board 300 extend from the electrical interface and are inserted into the electrical connector of the switch 100; the circuit board is inserted into the cage 103, and the gold fingers are connected to the electrical connector inside the cage 103. The gold fingers 301 are configured to establish an electrical connection with the switch, enabling electrical connection functions such as power supply, grounding, two-wire synchronous serial (Inter-Integrated Circuit, I2C) signal transmission, and data signal transmission.

[0060] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside its housing. The unlocking component 600 is configured to establish a fixed connection between the optical module 200 and the switch, or to release the fixed connection between the optical module 200 and the switch.

[0061] For example, the unlocking component 600 is located on the outside of the two lower side plates 2022 of the lower housing 202, and includes a locking component that matches the cage 103 of the switch 100. When the optical module 200 is inserted into the cage 103, the locking component of the unlocking component 600 fixes the optical module 200 in the cage 103; when the unlocking component 600 is pulled, the locking component of the unlocking component 600 moves accordingly, thereby changing the connection relationship between the locking component and the switch, so as to release the fixation between the optical module 200 and the switch, thereby allowing the optical module 200 to be pulled out of the cage 103.

[0062] Figure 5 This is an internal structural diagram of an optical module according to some embodiments. Figure 5 As shown, in some embodiments, the optical module 200 may include an optical emitting component 400. The optical emitting component 400 is used to generate optical signals. The optical emitting component 400 may generate 4 beams of optical signals or 8 beams of optical signals, etc.

[0063] In some embodiments, the optical module 200 may include a plurality of light emitting components 400. For example, the optical module 200 may include two, three, or four light emitting components 400.

[0064] In some embodiments, the light emitting component 400 may include an optical modulation chip 440 and a light source. The optical modulation chip 440 may be a silicon photonics chip or a thin-film lithium niobate chip, etc. The light source is used to generate light and may be used as the light source for the optical modulation chip 440. The light generated by the light source is coupled to the optical modulation chip 440, which can modulate the light to generate an optical signal. The optical modulation chip 440 can output multiple optical signals. For example, the optical modulation chip 440 can output 4 or 8 optical signals, etc.

[0065] In some embodiments, the optical module 200 may include an optical receiving component 500. The optical receiving component 500 is used to receive optical signals. The optical receiving component 500 may be located on the side of the optical emitting component 400. The optical receiving component 500 may receive 4 or 8 optical signals, etc.

[0066] In some embodiments, the optical module 200 may include a plurality of optical receiving components 500. For example, the optical module 200 may include two, three, or four optical receiving components 500. Exemplarily, the optical module 200 may include two optical receiving components 500, one optical receiving component 500 being located on one side of the optical emitting component 400 and the other optical receiving component 500 being located on the other side of the optical emitting component 400; or, the two optical receiving components 500 are located on the same side of the optical emitting component 400.

[0067] In some embodiments, the optical receiving component 500 may include a photodetector and a transimpedance amplifier. The optical receiving component 500 performs photoelectric conversion on the optical signal using the photodetector, and then amplifies the converted electrical signal using the transimpedance amplifier.

[0068] The lens can be located on the optical transmission path from the light source to the optical modulation chip 440 in order to ensure the coupling efficiency of the light generated by the light source to the optical modulation chip 440.

[0069] In some embodiments, the light source may include a laser 410. The laser 410 generates a beam of light, which is transmitted to an optical modulation chip 440. Inside the optical modulation chip 440, the beam of light may be split into 4 beams or 8 beams, etc.

[0070] In some embodiments, the light source may include multiple lasers 410. The multiple lasers 410 can generate multiple beams of light, which are transmitted to an optical modulation chip 440. The number of lasers 410 may be less than or equal to the number of beams of optical signals output by the optical modulation chip 440. For example, the light emitting component 400 may include four lasers 410. The four lasers 410 can generate four beams of light, which are transmitted to the optical modulation chip 440, and the optical modulation chip 440 modulates the four beams of light to generate four optical signals.

[0071] In some embodiments, the light emitting component 400 may include a lens 420. The lens 420 is located in the light output path of the laser 410. The lens 420 may be a converging lens, which can converge the diverging light emitted by the laser 410.

[0072] In some embodiments, the light emitting component 400 may include an isolator 430. The isolator 430 is located in the light output path of the lens 420 to reduce the amount of light emitted by the laser 410 returning to the laser 410, thereby ensuring the light output quality of the laser 410.

[0073] In some embodiments, the optical emitting component 400 may include a fiber optic array assembly 450. The fiber optic array assembly 450 includes a fiber optic array 450a and a fiber optic fixing head 450b. The fiber optic fixing head 450b is located at the end of the fiber optic array 450a and is connected to the surface of a substrate to fix one end of the fiber optic array 450a to the substrate, facilitating the coupling of the optical signal output from the optical modulation chip 440 into the fiber optic array 450a. The fiber optic array assembly 450 and the optical modulation chip 440 are end-face coupled. The fiber optic array assembly 450 is located in the output optical path of the optical modulation chip 440 to transmit the optical signal modulated by the optical modulation chip 440 to the outside.

[0074] In some embodiments, the light emitted by the laser 410 is transmitted to the optical modulation chip 440, where it is modulated to generate an optical signal. The optical signal is then output from the optical modulation chip 440 and transmitted via the fiber optic array assembly 450 to the optical port of the optical module. Exemplarily, the fiber optic array 450a may include multiple optical fibers, such as four or eight fibers. The optical fibers may be coupled to the output port of the optical modulation chip 440. The optical signal output from the output port of the optical modulation chip 440 is coupled to the fiber optic array 450a and then transmitted via the fiber optic array 450a to the optical port of the optical module.

[0075] In some embodiments, the laser 410, lens 420, and isolator 430 are located in the incident optical path of the optical modulation chip 440, providing the optical modulation chip 440 with the light to be modulated. The fiber array assembly 450 is coupled to the output optical port of the optical modulation chip 440. If the incident and output ports of the optical modulation chip 440 are formed on the same side, then the laser 410, lens 420, isolator 430, and fiber array assembly 450 are located on the same side of the optical modulation chip 440.

[0076] In some embodiments, laser 410 may be a buried heterostructure (BH) laser. BH lasers have a small beam divergence angle, which helps to ensure the coupling efficiency of the light generated by laser 410 to the optical modulation chip 440.

[0077] In recent years, with the rapid development of application markets such as big data, cloud computing and artificial intelligence, the demand for data communication optical modules has also increased rapidly. The communication rate requirements have gradually shifted from the original 200G to 800G and 1.6T, which has led to a continuous increase in the power requirements of lasers. Lasers with a power of 45mW are gradually unable to meet the needs.

[0078] Based on the optical module provided in the above embodiments, this disclosure also provides a laser with a power of not less than 70mW, which is convenient to meet the high-power laser requirements of high-speed optical modules.

[0079] Figure 6 This is a cross-sectional structural diagram of a laser according to some embodiments, where dashed arrows are used to indicate the direction of current. For example... Figure 6 As shown, in some embodiments, the laser 410 includes a laser body 411, within which a quantum well layer is included. A BH mesa is formed at the top of the laser body 411, and the bottom of the BH mesa extends below the quantum well layer. The BH mesa has a trapezoidal structure. The quantum well layer can be an AlInGaAs quantum well layer or an InGaAsP quantum well layer, etc. The trapezoidal structure of the BH mesa facilitates control over the width of the quantum well layer.

[0080] In some embodiments, the laser body 411 may include a substrate, a buffer layer, a confinement layer, a grating layer, and a cladding layer. The substrate, buffer layer, confinement layer, grating layer, and cladding layer may be made of InP material. Exemplarily, the substrate may be an N-InP substrate, the buffer layer may be an N-InP buffer layer, the confinement layer may be a P-InP confinement layer, the cladding layer may be a P-InP cladding layer, and the grating layer may be a P-InGaAsP grating layer. The doping elements of the N-InP substrate and the N-InP buffer layer may be Si or Sn, etc., and the doping elements of the P-InP confinement layer, P-InP cladding layer, and P-InGaAsP grating layer may be Zn or Mg, etc. The buffer layer is located above the substrate, the quantum well layer is located above the buffer layer, the confinement layer is located above the quantum well layer, the grating layer is located above the confinement layer, and the cladding layer is located above the grating layer.

[0081] Laser 410 includes a current blocking layer 412. The current blocking layer 412 is located on both sides of the BH mesa. The current blocking layer 412 forms a reverse PN junction, allowing current to flow into the quantum well layer. The quality of the current blocking layer 412 directly affects the efficiency of current injection into the quantum well layer. As the demand for optical power of laser 410 continues to increase, the current applied to laser 410 becomes increasingly higher, and the reverse current that the current blocking layer 412 needs to withstand becomes increasingly larger. When the current blocking layer 412 cannot withstand the current, causing reverse breakdown of the PN junction, the current blocking effect will fail. If the current blocking layer 412 conducts in reverse, the power of laser 410 will drop sharply, severely affecting the use of laser 410. Therefore, to ensure the use of laser 410, the current blocking layer 412 needs to have sufficient high current withstand capability.

[0082] In some embodiments, the current blocking layer 412 may include a P-InP blocking layer 4121, an impurity freezing layer 4122, and an N-InP blocking layer. The impurity freezing layer 4122 is located above the P-InP blocking layer 4121, and the N-InP blocking layer is located above the impurity freezing layer 4122. During the formation of the current blocking layer 412, the impurity freezing layer 4122 can prevent impurities in the P-InP blocking layer 4121 from diffusing into the N-InP blocking layer and prevent impurities in the N-InP blocking layer from diffusing into the P-InP blocking layer 4121. The doping element in the P-InP blocking layer 4121 may be Zn or Mg, etc., and the doping element in the N-InP blocking layer may be Si or Sn, etc.

[0083] The N-InP barrier layer may include a first N-InP barrier layer 4123 and a second N-InP barrier layer 4124, wherein the doping concentration in the second N-InP barrier layer 4124 is greater than the doping concentration in the first N-InP barrier layer 4123. The first N-InP barrier layer 4123 is located above the impurity freezing layer 4122, and the second N-InP barrier layer 4124 is located above the first N-InP barrier layer 4123. The impurity freezing layer 4122 is located at the interface between the P-InP barrier layer 4121 and the first N-InP barrier layer 4123. During the formation of the current blocking layer 412, the current blocking layer 412 can prevent impurities in the P-InP barrier layer 4121 from diffusing into the first N-InP barrier layer 4123 and prevent impurities in the first N-InP barrier layer 4123 from diffusing into the P-InP barrier layer 4121. The doping elements in the first N-InP barrier layer 4123 and the second N-InP barrier layer 4124 can be Si or Sn, etc.

[0084] In some embodiments, the doping concentration of the P-InP barrier layer 4121 is not less than 1E18cm⁻¹. -3 The doping concentration of the first N-InP barrier layer 4123 is no higher than 2E18cm. -3 The doping concentration of the second N-InP barrier layer 4124 is not less than 3E18cm. -3 .

[0085] In some embodiments, a P-InP layer 413 is formed above the laser body 411 and the current blocking layer 412. The doping concentration of the P-InP layer 413 is not higher than 5E17cm⁻¹. -3 .

[0086] In some embodiments, the P-InP layer 413 may include a first P-InP layer 4131 and a second P-InP layer 4132. The second P-InP layer 4132 is located above the first P-InP layer 4131. The doping concentration of the second P-InP layer 4132 is higher than that of the first P-InP layer 4131, and the doping concentration of the first P-InP layer 4131 is not higher than 5E17cm. -3 .

[0087] In some embodiments, the laser 410 includes a positive electrode layer 414 and a negative electrode layer 415. The positive electrode layer 414 is located above the P-InP layer 413, and the negative electrode layer 415 is located below the laser body 411. The positive electrode layer 414 and the negative electrode layer 415 provide good electrical connection for the laser 410.

[0088] In some embodiments, an electrical contact layer 416 may be disposed between the positive electrode layer 414 and the P-InP layer 413. The electrical contact layer 416 may be a P-InP electrical contact layer or a P-InGaAs electrical contact layer. The electrical contact layer 416 can form a good ohmic contact with the positive electrode layer 414, facilitating a stable, low-resistance, non-rectifying electrical connection between the positive electrode layer 414 and the P-InP layer 413. The doping concentration of the electrical contact layer 416 is higher than that of the P-InP layer 413.

[0089] To facilitate the fabrication of the laser provided in this embodiment, this embodiment also provides a method for fabricating the laser. Figure 7 The following is a flowchart of a method for fabricating a laser according to some embodiments. Figure 1 , Figure 8 Fabrication structure of a laser according to some embodiments Figure 1 , Figure 9 Fabrication structure of a laser according to some embodiments Figure 2 .like Figures 7-9 As shown, in some embodiments, the laser fabrication method provided in this disclosure includes: S100: An etching auxiliary layer is grown on the surface of the laser wafer body, wherein the longitudinal etching rate of the wafer body is greater than the lateral etching rate of the wafer body, and the lateral etching rate of the etching auxiliary layer is greater than the lateral etching rate of the wafer body.

[0090] The wafer body 401 may include a substrate, a buffer layer, a quantum well layer, a confinement layer, a grating layer, and a cladding layer. The principal elements of the substrate, buffer layer, quantum well layer, confinement layer, grating layer, and cladding layer may be In and P. Exemplarily, the principal elements of the substrate, buffer layer, quantum well layer, confinement layer, grating layer, and cladding layer may be grown using InP material. The longitudinal etching rate of the wafer body is greater than the lateral etching rate of the wafer body.

[0091] Because the longitudinal etching rate of wafer body 401 is greater than the lateral etching rate of wafer body 401, inverted trapezoidal BH mesa is easily formed during the etching process. To effectively reduce the possibility of forming inverted trapezoidal BH mesa, an etching aid layer is formed on the surface of wafer body 401 to adjust the lateral etching rate of wafer body 401.

[0092] In some embodiments, an etching aid layer 402 is formed on the surface of the wafer body 401, and the etching aid layer 402 is located on top of the wafer body 401. The lateral etching rate of the etching aid layer 402 is greater than the lateral etching rate of the wafer body 401. During the formation of the BH mesa, the high etching rate of the etching aid layer 402 allows for the formation of a lateral window at the top edge of the wafer body 401, thereby facilitating the control of the width of the quantum well layer in the BH mesa.

[0093] The etching auxiliary layer 402 can be formed using a multi-element compound, with the number of major elements in the etching auxiliary layer 402 being greater than the number of major elements in the wafer body 401; the etching auxiliary layer 402 can be a ternary compound or a quaternary compound, etc. During the etching process, the etching auxiliary layer 402 can exhibit isotropic behavior and will not form crystal planes that are difficult to etch. In some embodiments, the etching auxiliary layer 402 can be an InGaAsP layer, formed by growing InGaAsP material on top of the wafer body 401.

[0094] In some embodiments, the thickness of the etching auxiliary layer 402 can be 50nm-200nm, which facilitates control of the lateral etching rate of the etching auxiliary layer 402. For example, the thickness of the etching auxiliary layer 402 is 150nm.

[0095] S200: A mask layer is formed above the etching auxiliary layer, and the mask layer is pre-processed to form a BH pattern.

[0096] A mask layer 403 is formed above the etching aid layer 402. The mask layer 403 may be made of SiO2, and a SiO2 mask layer is deposited above the etching aid layer 402. Exemplarily, the mask layer 403 may be deposited on top of the wafer body using a PECVD method, and the thickness of the mask layer 403 is no greater than 200 nm.

[0097] In some embodiments, a preset mask can be used to cover the mask layer 403 and photolithography can be performed on the mask layer 403 covered by the preset mask to form a BH pattern. Exemplarily, the mask layer can be etched by an ICP-RIE dry etching method to form a BH pattern.

[0098] S300: Etch the BH pattern to etch the top of the wafer body into a BH mesa, with the etching depth extending below the quantum well layer.

[0099] The BH pattern is etched to form a BH mesa, thereby forming the laser body 411 below the etching auxiliary layer 402.

[0100] In some embodiments, an etchant can be used to etch the BH pattern to form BH mesa, with the etching depth extending below the quantum well, such as extending to the buffer layer. The etchant can be a mixture of hydrobromic acid, hydrogen peroxide, and water, or a mixture of hydrochloric acid, phosphoric acid, and hydrogen peroxide, etc.

[0101] Figure 10 This is a cross-sectional view of a mesa etching according to some embodiments. Figure 10 An etching process is shown where no etching auxiliary layer 402 is provided beneath the mask layer. For example... Figure 10 As shown, in some embodiments, due to the extremely low etching rate of the

[111] crystal plane of InP, the longitudinal etching rate of the wafer body is greater than the lateral etching rate of the wafer body, which makes it easy to form an inverted trapezoidal mesa after etching. Moreover, as etching continues, although the height of the mesa can gradually increase, the etching solution corrodes along the crystal plane, so that the width of the quantum well layer will not change with the etching process, resulting in the width of the quantum well layer not reaching the preset width.

[0102] Figure 11 This is a cross-sectional view of another mesa etching according to some embodiments. Figure 11 An etching process is shown where an etching auxiliary layer 402 is disposed beneath the mask layer. For example... Figure 11 As shown, in some embodiments, in the initial stage of etching, the etching solution etches the wafer body 401 and the etching auxiliary layer 402, initially forming an inverted trapezoidal mesa. As etching continues, when the etching solution reaches the etching auxiliary layer 402, because the compound used in the etching auxiliary layer 402 is a multi-component compound, it exhibits isotropy during etching, resulting in a greater lateral etching rate for the etching auxiliary layer 402 than for the wafer body 401. As etching continues, the width of the etching auxiliary layer 402 continuously decreases, gradually exposing the top edge of the inverted trapezoidal mesa. The etching solution etches downwards from the gradually exposed mesa edge, etching away the sharp corners at the top of the wafer body 401, thereby changing the width of the top of the wafer body 401. This allows for further adjustment of the width of the quantum well layer, forming a trapezoidal BH mesa. As the etching depth increases, the width of the trapezoid continues to decrease, allowing the width of the quantum well layer to reach a preset width.

[0103] Thus, by setting the etching auxiliary layer 402, the limitation caused by the extremely low etching rate of the

[111] crystal plane of InP material can be effectively overcome, and the width of the quantum well layer can be precisely controlled. The isotropic etching characteristics of the etching auxiliary layer 402 and the anisotropic etching characteristics of the wafer body 401 work together to dynamically change the geometry of the mesa during the etching process, thereby breaking through the structural constraints of the traditional inverted trapezoidal mesa.

[0104] S400: Current blocking layers are grown on both sides of the BH platform.

[0105] In some embodiments, current blocking layers 412 are grown on both sides of the BH mesa. The current blocking layers 412 may include P-InP blocking layers and N-InP blocking layers. The bottom surface of the P-InP blocking layer contacts both sides of the BH mesa, and the N-InP blocking layer is located above the P-InP blocking layer. Exemplarily, P-InP blocking layers are first grown on both sides of the BH mesa, and then an N-InP blocking layer is grown above the P-InP blocking layer. The P-InP blocking layers may include multiple P-InP blocking layers with different doping concentrations, and the N-InP blocking layers may be multiple N-InP blocking layers with different doping concentrations.

[0106] In some embodiments, an N-InP barrier layer can be formed directly above the P-InP barrier layer. Typically, the P-InP barrier layer is doped with Zn, and the N-InP barrier layer is doped with Si. During the formation of the N-InP barrier layer above the P-InP barrier layer, due to the strong attraction of Si atoms to Zn atoms, Zn atoms in the P-InP barrier layer are attracted to the N-InP barrier layer. When Zn atoms in the P-InP barrier layer are attracted to the N-InP barrier layer, the electron carriers in the N-InP barrier layer are neutralized by Zn atoms, and the hole concentration in the P-InP barrier layer decreases. This lowers the reverse PN junction barrier formed by the N-InP and P-InP barrier layers, making it easily break down under high current and high voltage conditions. Consequently, when the laser's operating current exceeds 700mA, the power drops sharply, a stable leakage current forms, and the current used for light emission remains constant. Even if the current is further increased, the optical power will not continue to increase.

[0107] In some embodiments, the N-InP barrier layer may include a first N-InP barrier layer and a second N-InP barrier layer. The second N-InP barrier layer is located above the first N-InP barrier layer, and the doping concentration of the second N-InP barrier layer is greater than that of the first N-InP barrier layer. The first N-InP barrier layer has a relatively low doping concentration, while the second N-InP barrier layer has a relatively high doping concentration. The first N-InP barrier layer can be directly disposed above the P-InP barrier layer. The lower doping concentration of the first N-InP barrier layer results in a relatively weak attraction for Zn atoms. Even if some Zn atoms diffuse into the first N-InP barrier layer, the number of neutralized electron carriers is relatively limited due to the low Si doping concentration, thereby mitigating the problem of reduced reverse PN junction barrier to some extent.

[0108] In some embodiments, the doping concentration of the first N-InP barrier layer is not higher than 2E18cm.-3 The doping concentration of the second N-InP barrier layer is not less than 3E18cm. -3 .

[0109] In some embodiments, the thickness of the P-InP barrier layer is 500nm-600nm, the thickness of the first N-InP barrier layer is 300nm-400nm, and the thickness of the second N-InP barrier layer is 600nm-700nm. For example, the thickness of the P-InP barrier layer is 550nm, the thickness of the first N-InP barrier layer is 350nm, and the thickness of the second N-InP barrier layer is 650nm.

[0110] In some embodiments, to suppress the diffusion of Zn atoms from the P-InP barrier layer to the N-InP barrier layer, a transition layer can be introduced between the P-InP and N-InP barrier layers. This transition layer can be formed using intrinsic InP material, i.e., undoped or with only very low doping concentration, thereby creating a certain degree of physical isolation between the P-type and N-type regions. The thickness of the transition layer can be optimized according to actual process conditions, typically controlled within the range of 10nm-50nm, to ensure isolation while avoiding excessive increase in the device's series resistance. The transition layer effectively alleviates the electric field concentration phenomenon at the PN junction and reduces junction widening caused by interdiffusion of dopants, thereby maintaining a high reverse breakdown voltage.

[0111] In some embodiments, the growth temperature can be appropriately reduced during the growth of the N-InP barrier layer to slow down the thermal diffusion rate of Zn atoms; or a low-temperature growth technique such as atomic layer deposition can be used to form a dense capping layer on the surface of the P-InP barrier layer before the growth of the N-InP barrier layer, thereby reducing the migration of Zn atoms through physical blocking.

[0112] S500: Remove the mask layer and the etching aid layer.

[0113] After etching to form the BH mesa, the surface of the BH mesa can be pre-cleaned to remove residual etching solution and reaction products, preventing these residues from having a long-term impact on device performance. After pre-cleaning the BH mesa, the mask layer 403 on top of the BH mesa is removed first, followed by the etching aid layer 402. In some embodiments, an organic solution of acetone and isopropanol can be used to clean the surface of the BH mesa.

[0114] In some embodiments, the mask layer 403 can be removed using hydrofluoric acid, and the etching aid layer 402 can be removed using a mixed solution of sulfuric acid, hydrogen peroxide, and water. Exemplarily, the mask layer 403 is first removed using hydrofluoric acid, and then the etching aid layer 402 is removed using a mixed solution of sulfuric acid, hydrogen peroxide, and water.

[0115] S600: A P-InP layer is formed on top of the BH platform and the current blocking layer.

[0116] After removing the mask layer 403 and etching aid layer 402 on top of the BH mesa, a P-InP layer 413 is formed on top of the BH mesa and on top of the current blocking layer 412. For example, a P-InP layer 413 is formed on top of the BH mesa and on top of the N-InP blocking layer.

[0117] Figure 12 The following is a flowchart of a method for fabricating a laser according to some embodiments. Figure 2 .like Figure 12 As shown, in some embodiments, S600: forming a P-InP layer on top of the BH mesa and the current blocking layer includes: S610: sequentially growing a first P-InP layer and a second P-InP layer on top of the BH mesa and the current blocking layer. In some embodiments, the P-InP layer 413 includes a first P-InP layer 4131 and a second P-InP layer 4132, with the second P-InP layer 4132 located above the first P-InP layer 4131. The doping concentration of the second P-InP layer 4132 is greater than the doping concentration of the first P-InP layer 4131. Exemplarily, the doping concentration of the first P-InP layer 4131 is not higher than 5E17cm. -3 The first P-InP layer 4131 employs a relatively low doping concentration, which effectively reduces the doping concentration gradient between the first P-InP layer 4131 and the laser body 411, thus weakening the driving force for thermal diffusion of Zn atoms towards the active region. Simultaneously, the PN junction formed at the interface between the lower-doped first P-InP layer 4131 and the current blocking layer 412 exhibits a more gradual impurity distribution, contributing to improved crystal quality and electrical properties of the interface and reducing defects caused by abrupt impurity changes.

[0118] In some embodiments, a first P-InP layer 4131 is formed on top of the BH mesa and on top of the current blocking layer 412, and the flow rate of the doping source introduced into the epitaxial growth chamber is increased or the concentration of the doping source is increased to form a second P-InP layer 4132 above the first P-InP layer 4131, such that the doping concentration of the second P-InP layer 4132 is greater than the doping concentration of the first P-InP layer 4131.

[0119] In some embodiments, an electrical contact layer 416 is formed above the P-InP layer 413. Exemplarily, the electrical contact layer 416 is formed directly above the second P-InP layer 4132. The second P-InP layer 4132 has a higher doping concentration, which facilitates ensuring a good ohmic contact between the second P-InP layer 4132 and the electrical contact layer 416, reducing contact resistance, and improving hole injection efficiency. Exemplarily, the doping concentration of the second P-InP layer 4132 can be 1E18cm⁻¹. -3 Up to 5E18cm -3 This concentration range helps to ensure low contact resistance.

[0120] In some embodiments, a positive electrode layer 414 is formed above the electrical contact layer 416, and a negative electrode layer 415 is formed below the laser body 411.

[0121] In some embodiments, the total thickness of the first P-InP layer 4131 and the second P-InP layer 4132 can be designed according to the specific requirements of the device. For example, the thickness of the first P-InP layer 4131 can be 100nm-300nm, and the thickness of the second P-InP layer 4132 can be 500nm-800nm. The first P-InP layer 4131 and the second P-InP layer 4132 form a gradient distribution of doping concentration in the vertical direction, which optimizes the interface characteristics with the active region and ensures good contact with the metal electrode.

[0122] In some embodiments, the thickness of the first P-InP layer 4131 can be 200 nm, and the thickness of the second P-InP layer 4132 can be 600 nm.

[0123] In some embodiments, after forming the first P-InP layer 4131 and the second P-InP layer 4132, a rapid thermal annealing process can also be performed. Annealing can repair crystal defects generated during growth, while promoting proper activation and uniform distribution of doped atoms. Exemplarily, the annealing temperature can be from 600°C to 700°C, and the annealing time can be from 30 seconds to 120 seconds, to control the annealing temperature and time to avoid excessive diffusion of Zn atoms due to excessively high annealing temperature or excessively long annealing time.

[0124] In some embodiments, the electrical contact layer 416 may be a P-InGaAs electrical contact layer, wherein the doping concentration of the P-InGaAs electrical contact layer is not less than 2E18cm⁻¹. -3 .

[0125] In some embodiments, the electrical contact layer 416 may be formed of heavily doped InGaAs material, with a doping concentration higher than 1E19cm⁻¹. -3This allows for low-resistance ohmic contact with the positive electrode metal layer. The thickness of the electrical contact layer 416 can be 100nm-300nm, ensuring sufficient carrier concentration without increasing unnecessary series resistance and absorption losses due to excessive thickness.

[0126] In some embodiments, the positive electrode layer 414 and the negative electrode layer 415 can be multilayer metal structures such as Ti / Pt / Au or Ti / Au. The positive electrode layer 414 can be formed above the electrical contact layer 416 by processes such as electron beam evaporation or sputtering, and a stable ohmic contact is formed after a lift-off process and alloying treatment. The negative electrode layer 415 can be formed below the laser body 411, i.e., on the back side of the substrate, and a low-resistance contact with the N-type substrate is achieved through processes such as thinning, polishing, and metal deposition.

[0127] Figure 13 The following is a flowchart of a method for fabricating a laser according to some embodiments. Figure 3 , Figure 14 Fabrication structure of a laser according to some embodiments Figure 3 .like Figure 13 and Figure 14 As shown, in some embodiments, S400: a current blocking layer is grown on both sides of the BH mesa, including: S410: Introduce a first doping source to form the P-InP barrier layer on both sides of the BH mesa.

[0128] S420: Stop the flow of the first dopant source and lower the temperature of the epitaxial growth chamber to the first preset temperature.

[0129] S430: When the temperature of the epitaxial growth chamber drops to a first preset temperature, a second doping source is introduced to form the impurity freezing layer, and the N-InP barrier layer is formed above the impurity freezing layer. The second doping source penetrates the surface of the top of the P-InP barrier layer to form the impurity freezing layer, and the impurity freezing layer prevents the second doping source from diffusing into the P-InP barrier layer below the impurity freezing layer.

[0130] In some embodiments, after the BH mesa is formed, a first doping source is introduced to dop InP, thereby forming a P-InP barrier layer 4121 on both sides of the BH mesa. The first doping source can be a gas such as Zn or Mg used to dope InP. Exemplarily, the first doping source can be a DEZn saturated gas used to dope Zn into InP.

[0131] In some embodiments, P-InP barrier layers 4121 are formed on both sides of the BH mesa. A P-InP barrier layer 4121 with a thickness of 550 nm can be grown using an Aixtron G4 MOCVD machine. The temperature of the epitaxial growth chamber can be 600°C-650°C. For example, the temperature of the epitaxial growth chamber is 600°C or 620°C, etc.

[0132] The supply of DEZn saturated gas to the epitaxial growth chamber is stopped to halt the continued growth of the P-InP barrier layer 4121. The temperature of the epitaxial growth chamber is lowered until it reaches a first preset temperature to provide a suitable temperature for the subsequent growth of the first N-InP barrier layer 4123. The first preset temperature is lower than the temperature at which the P-InP barrier layer 4121 was grown, which facilitates the fixation of the surface lattice on the top of the P-InP barrier layer 4121.

[0133] In some embodiments, the first preset temperature can be below 600°C, and the range of the first preset temperature can be 550°C-600°C, such as 560°C or 580°C. Within this temperature range, the decomposition efficiency of Si2H6 is moderate, which can form a continuous and dense impurity freezing layer 4122 on the surface of the P-InP barrier layer 4121, while avoiding the problem of slow epitaxial growth rate or surface quality deterioration of the first N-InP barrier layer 4123 due to excessively low temperature.

[0134] In some embodiments, the thickness of the impurity freezing layer 4122 is 1 nm to 5 nm. This thickness range effectively blocks the bidirectional diffusion of Zn and Si impurities without significantly affecting the electrical properties of the current blocking layer.

[0135] The Si₂H₆ saturated gas is introduced into the epitaxial growth chamber only after the temperature drops to a first preset temperature. Since the current temperature of the epitaxial growth chamber is lower than the temperature at which the P-InP barrier layer 4121 is grown, an impurity freezing layer 4122 will first form on the surface above the P-InP barrier layer 4121, followed by the formation of the N-InP barrier layer. Firstly, because the temperature of the epitaxial growth chamber is lower than the temperature at which the P-InP barrier layer 4121 is grown, the lattice of the P-InP barrier layer 4121 is fixed, thereby freezing the Zn in the P-InP barrier layer 4121. Consequently, during subsequent growth, the Zn in the P-InP barrier layer 4121 is less likely to diffuse, making it less likely for the Zn in the P-InP barrier layer 4121 to diffuse into the subsequently grown N-InP barrier layer. Secondly, during the growth of the P-InP barrier layer 4121, the atomic bonds on the surface of the P-InP barrier layer 4121 are not fully filled. Because the temperature of the epitaxial growth chamber is reduced to a first preset temperature before the Si₂H₆ saturated gas is introduced into the epitaxial growth chamber, the surface lattice of the top of the P-InP barrier layer 4121 is fixed. Therefore, the diffusion rate of Si on the top surface of the P-InP barrier layer 4121 is much greater than its diffusion rate inside the P-InP barrier layer 4121. When Si enters the top surface of the P-InP barrier layer 4121, it prevents Si from continuing to diffuse into the P-InP barrier layer 4121, thus forming an impurity freezing layer 4122 containing a very small amount of Si and Zn on the top surface of the P-InP barrier layer 4121. As the time of introducing Si₂H₆ saturated gas into the epitaxial growth chamber increases, an N-InP barrier layer grows above the impurity freezing layer 4122. By controlling the flow rate of the introduced Si₂H₆ saturated gas, the doping concentration in the N-InP barrier layer can be controlled. As the N-InP barrier layer grows, the impurity freezing layer 4122 can prevent the diffusion of Zn from the P-InP barrier layer 4121 into the N-InP barrier layer, and also prevent the diffusion of Si from the N-InP barrier layer into the P-InP barrier layer 4121. This reduces the diffusion rates of Zn and Si in the P-InP barrier layer 4121 and the N-InP barrier layer, thereby reducing the interdiffusion of Zn and Si in the P-InP barrier layer 4121 and the N-InP barrier layer. Furthermore, the impurity freezing layer 4122 can create a clear interface between the P-InP barrier layer 4121 and the N-InP barrier layer, and can also prevent the diffusion of Zn and Si after temperature increases, thus improving the current blocking effect of the current blocking layer. The doping concentration of the N-InP barrier layer can be no higher than 5E18cm⁻¹. -3 For example, the doping concentration of the N-InP barrier layer can be 1E18cm. -3 -3E18cm -3 .

[0136] Figure 15The following is a flowchart of a method for fabricating a laser according to some embodiments. Figure 4 .like Figure 15 As shown, in some embodiments, S430: when the temperature of the epitaxial growth chamber drops to a first preset temperature, a second doping source is introduced to form the impurity freezing layer, and the N-InP barrier layer is formed above the impurity freezing layer, including: S431: When the temperature of the epitaxial growth chamber drops to the first preset temperature, Si2H6 saturated gas is introduced into the epitaxial growth chamber so that Si penetrates into the surface of the top of the P-InP barrier layer to form the impurity freezing layer, and the first N-InP barrier layer is formed above the impurity freezing layer.

[0137] S432: Increase the temperature of the epitaxial growth chamber to form a second N-InP barrier layer above the first N-InP barrier layer, wherein the doping concentration of the second N-InP barrier layer is greater than that of the first N-InP barrier layer.

[0138] In some embodiments, after forming a first N-InP barrier layer 4123 of a certain thickness above the impurity freezing layer 4122, the temperature of the epitaxial growth chamber is increased to form a second N-InP barrier layer 4124 above the first N-InP barrier layer 4123. Forming the second N-InP barrier layer 4124 in the relatively high-temperature epitaxial growth chamber facilitates the control of defects in the second N-InP barrier layer 4124 and ensures the quality of the second N-InP barrier layer 4124.

[0139] In some embodiments, when the temperature of the epitaxial growth chamber is increased, the flow rate of the Si2H6 saturated gas is increased, and a second N-InP barrier layer 4124 is grown above the first N-InP barrier layer 4123. The doping concentration of the second N-InP barrier layer 4124 is higher than that of the first N-InP barrier layer 4123. The doping concentration of the second N-InP barrier layer 4124 is not less than 3E18cm⁻¹. -3 The doping concentration of the second N-InP barrier layer 4124 is 3E18cm. -3 -5E18cm -3 .

[0140] The doping concentration of the second N-InP barrier layer 4124 is greater than that of the first N-InP barrier layer 4123, resulting in gradient doping of the N-InP barrier layer. This creates a high-resistivity region between the second N-InP barrier layer 4124 and the first N-InP barrier layer 4123, effectively limiting the lateral current spread. The first N-InP barrier layer 4123 uses a relatively low doping concentration and is combined with the impurity freezing layer 4122 to ensure the interface quality between the P-InP barrier layer 4121 and the N-InP barrier layer.

[0141] In some embodiments, the temperature of the epitaxial growth chamber is raised to a second preset temperature, which is higher than the first preset temperature, and the flow rate of the Si2H6 saturated gas is increased to grow a second N-InP barrier layer 4124 above the first N-InP barrier layer 4123. The second preset temperature can be 600°C-650°C, such as 600°C-630°C. For example, the second preset temperature can be 620°C, 630°C, etc. Raising the temperature of the epitaxial growth chamber during the growth of the second N-InP barrier layer 4124 helps to reduce defects in the second N-InP barrier layer 4124 and improves the crystal quality of the second N-InP barrier layer 4124.

[0142] In some embodiments, when the temperature of the epitaxial growth chamber is reduced to a first preset temperature, the temperature can be reduced to the first preset temperature at a preset cooling rate. The preset cooling rate can be 3℃ / min-5℃ / min. This facilitates control of the cooling rate of the epitaxial growth chamber, ensuring temperature uniformity while avoiding lattice thermal stress damage caused by excessively rapid cooling.

[0143] In some embodiments, when the temperature of the epitaxial growth chamber is raised to a second preset temperature, the temperature can be raised to the second preset temperature at a preset heating rate. The preset heating rate can be 3°C / min to 8°C / min. This facilitates atomic rearrangement on the surface of the first N-InP barrier layer 4123, providing a good nucleation surface for the high-quality growth of the second N-InP barrier layer 4124.

[0144] In some embodiments, the heating rate is greater than the cooling rate. By making the heating rate greater than the cooling rate, the total time of the high-temperature process stage can be shortened during the rapid increase of the epitaxial growth chamber temperature, reducing the risk of excessive diffusion of impurity atoms at high temperatures. Simultaneously, the second preset temperature can be reached quickly to meet the temperature requirements for high-quality growth of the second N-InP barrier layer, avoiding growth interruptions or interface quality degradation caused by excessively slow heating. For example, if the cooling rate is 3°C / min, the heating rate can be set to 5°C / min or higher. When heating from the first preset temperature (e.g., 580°C) to the second preset temperature (e.g., 620°C), the temperature transition can be completed more quickly compared to a slower heating rate, thereby better ensuring the growth quality and doping accuracy of the second N-InP barrier layer 4124.

[0145] In some embodiments, S400: growing current blocking layers on both sides of the BH mesa may further include: reducing the flow rate of the Si2H6 saturated gas to grow a third N-InP blocking layer above the second N-InP blocking layer, wherein the doping concentration of the third N-InP blocking layer is lower than that of the first N-InP blocking layer. The doping concentration of the third N-InP blocking layer is not higher than 1E17cm⁻¹. -3 The thickness of the third N-InP barrier layer is less than 300 nm, such as 50 nm. The third N-InP barrier layer is lightly doped and can serve as a transition layer, which helps to reduce charge accumulation at the interface between the current barrier layer and the P-InP layer and reduce leakage current.

[0146] In some embodiments, S600: forming a P-InP layer on top of the BH mesa and the current blocking layer includes: stopping the introduction of Si2H6 saturated gas into the epitaxial growth chamber and introducing DEZn saturated gas into the epitaxial growth chamber to grow the P-InP layer above the current blocking layer. The P-InP layer is grown at a second preset temperature to ensure the crystal quality of the P-InP layer.

[0147] In some embodiments, the second P-InP layer 4132 can be a heavily doped P+-InP layer. The temperature of the epitaxial growth chamber is maintained at a second preset temperature, and the DEZn flow rate is increased to grow a heavily doped P+-InP layer above the first P-InP layer 4131. Subsequently, the temperature of the epitaxial growth chamber is lowered to a third preset temperature, and TMGa, TMIn, and AsH3 are introduced into the epitaxial growth chamber to grow an InGaAs electrical contact layer above the P+-InP layer. The third preset temperature is lower than the second preset temperature, and can be 550°C-600°C to suit the growth characteristics of the InGaAs material.

[0148] Figure 16 The following is a flowchart of a method for fabricating a laser according to some embodiments. Figure 5 .like Figure 16 As shown, in some embodiments, the method for fabricating the laser further includes: S01: An N-InP buffer layer is formed on top of the N-InP substrate.

[0149] S02: An AlInGaAs quantum well layer is formed above the N-InP buffer layer.

[0150] S03: A P-InP confinement layer is formed above the AlInGaAs quantum well layer.

[0151] S04: An InGaAsP grating layer is formed above the P-InP confinement layer.

[0152] S05: A P-InP cladding layer is formed above the InGaAsP grating layer.

[0153] In some embodiments, the wafer body 401 forms a complete laser active region and optical confinement structure by sequentially constructing a multilayer epitaxial structure consisting of an N-InP buffer layer, an AlInGaAs quantum well layer, a P-InP confinement layer, an InGaAsP grating layer, and a P-InP cladding layer. The N-InP buffer layer effectively alleviates the lattice mismatch stress between the N-InP substrate and the subsequent epitaxial layers, providing a smooth crystal surface for high-quality epitaxial growth and reducing the extension of dislocation defects into the active region. The AlInGaAs quantum well layer, as the core region for carrier recombination luminescence, has a tunable bandgap, allowing the laser emission wavelength to be precisely matched to the requirements of the optical communication system. Simultaneously, the three-dimensional confinement effect of the quantum well structure significantly enhances the differential gain coefficient of the active region. The P-InP confinement layer and the N-InP buffer layer together constitute a dual heterostructure, utilizing the large conduction band and valence band order between InP and AlInGaAs to achieve efficient confinement of carriers and reduce the threshold current density. The introduction of the InGaAsP grating layer provides the necessary Bragg grating structure for distributed feedback lasers. By precisely controlling the grating period and duty cycle, single-mode selection of the laser emission wavelength can be achieved, suppressing side-mode competition and obtaining single-mode laser output with a high side-mode suppression ratio. The P-InP cladding, as the uppermost epitaxial structure, not only completes the lateral expansion and injection of current, but its higher bandgap energy further enhances the longitudinal confinement of the optical field, reducing leakage losses towards the P-type electrode.

[0154] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a laser, characterized in that, The laser includes a current blocking layer, which comprises a P-InP blocking layer, an impurity freezing layer, a first N-InP blocking layer, and a second N-InP blocking layer; the method includes: A first doping source is introduced into the epitaxial growth chamber to form the P-InP barrier layer on both sides of the BH mesa; the first doping source is used to dope Zn. Stop the flow of the first doping source and lower the temperature of the epitaxial growth chamber to the first preset temperature; When the temperature of the epitaxial growth chamber drops to the first preset temperature, a second doping source is introduced into the epitaxial growth chamber, so that the second doping source penetrates into the surface of the top of the P-InP barrier layer to process the top of the P-InP barrier layer to form the impurity freezing layer, and the first N-InP barrier layer is formed above the impurity freezing layer. The second doping source is used to dope Si. The temperature of the epitaxial growth chamber is increased to form a second N-InP barrier layer above the first N-InP barrier layer. The doping concentration of the second N-InP barrier layer is greater than that of the first N-InP barrier layer.

2. The method according to claim 1, characterized in that, Lowering the temperature of the epitaxial growth chamber to a first preset temperature includes: lowering the temperature of the epitaxial growth chamber to the first preset temperature according to a preset cooling rate; Raising the temperature of the epitaxial growth chamber includes: raising the temperature of the epitaxial growth chamber to a second preset temperature at a preset heating rate, wherein the second preset temperature is greater than the first preset temperature, and the heating rate is greater than the cooling rate.

3. The method according to claim 1, characterized in that, The doping concentration of the first N-InP barrier layer is no higher than 2E18cm. -3 The doping concentration of the second N-InP barrier layer is not less than 3E18cm. -3 The thickness of the first N-InP barrier layer is less than the thickness of the second N-InP barrier layer.

4. The method according to claim 1, characterized in that, The method further includes: An etching aid layer is formed on the top of the wafer body of the laser, the etching aid layer covering the top of the wafer body; wherein the longitudinal etching rate of the wafer body is greater than the lateral etching rate of the wafer body, and the lateral etching rate of the etching aid layer is greater than the lateral etching rate of the wafer body. The etching auxiliary layer and the wafer body are etched, and the residual etching auxiliary layer is removed after etching to form a BH mesa; Before introducing the first doping source into the epitaxial growth chamber, the surface of the BH mesa is cleaned.

5. The method according to claim 1, characterized in that, The wafer body of the laser includes an N-InP substrate, an N-InP buffer layer, an AlInGaAs quantum well layer, a P-InP confinement layer, an InGaAsP grating layer, and a P-InP cladding layer. The method further includes: The N-InP buffer layer is formed on top of the N-InP substrate; The AlInGaAs quantum well layer is formed above the N-InP buffer layer; The P-InP confinement layer is formed above the AlInGaAs quantum well layer; The InGaAsP grating layer is formed above the P-InP confinement layer; The P-InP cladding layer is formed above the InGaAsP grating layer.

6. The method according to claim 1, characterized in that, The method further includes: A first P-InP layer and a second P-InP layer are sequentially grown on top of the BH mesa and the current blocking layer. The doping concentration of the second P-InP layer is greater than that of the first P-InP layer, and the doping concentration of the first P-InP layer is no higher than 5E17cm⁻¹. -3 .

7. The method according to claim 6, characterized in that, The method further includes: An electrical contact layer is grown above the second P-InP layer. The electrical contact layer is a P-InGaAs electrical contact layer, and the doping concentration of the P-InGaAs electrical contact layer is not less than 2E18cm⁻¹. -3 .

8. The method according to claim 2, characterized in that, The first preset temperature is 550℃-600℃, and the second preset temperature is 600℃-630℃.

9. A laser, characterized in that, The laser is a laser prepared by the method described in any one of claims 1-8, and the power of the laser is not less than 70mW.

10. An optical module, characterized in that, Includes a laser, wherein the laser is the laser described in claim 9 above.

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