Multiplexed frequency compensation circuit suitable for constant on-time control

Abstract

The application relates to a multiplexed frequency compensation circuit suitable for constant on-time control, comprising a control module, an under-voltage detection module, a frequency compensation module and a hiccup protection module; the frequency compensation module and the hiccup protection module multiplex a main pole compensation capacitor; the frequency compensation module is used for compensating zero-poles of a switching power supply caused by a power stage and a current sampling part through the main pole compensation capacitor according to a frequency compensation signal; the hiccup protection module is used for performing hiccup protection on the switching power supply within preset time by charging and discharging the main pole compensation capacitor according to a hiccup protection enable signal and counting the charging and discharging times. The embodiment of the application realizes efficient utilization of on-chip capacitors, effectively reduces chip area cost, and solves the demand for large capacitors of compensation networks and hiccup protection circuits under the premise of using less chip area.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a multiplexed frequency compensation circuit suitable for constant on-time control. Background Technology

[0002] In recent years, with the continuous development of switching power supply technology, market demand has also increased, leading to its widespread application. However, in the closed-loop control system of a DC-DC converter, the inherent zeros and poles of the power stage cause phase shifts, which can easily trigger positive feedback self-oscillations in the system. To ensure the stability of the converter under various load conditions and input voltage fluctuations, a frequency compensation network must be introduced. The frequency compensation network, by configuring specific zeros and poles in the loop, compensates for the phase loss caused by the power stage poles and, while ensuring sufficient phase and gain margins, improves the system's crossover frequency, thereby optimizing the converter's transient response speed and steady-state voltage regulation accuracy. However, the capacitors in the compensation network often need to be implemented off-chip or integrated on-chip. The former increases external components and introduces reliability risks, while the latter requires a larger chip area. In addition, electronic devices may experience unexpected situations such as overvoltage, overcurrent, and overtemperature during operation, which may lead to damage to the circuit or even the entire electronic device. Therefore, protection for the switching power supply is necessary. Hiccup protection is a common switching power supply protection method, which periodically starts and stops the switching power supply system to protect the electronic device when an abnormal operating state of the circuit is detected. However, traditional on-chip integrated hiccup protection circuits require large capacitors and counters to achieve large hiccup cycles.

[0003] Therefore, how to address the need for large capacitors in compensation networks and hiccup protection circuits while using less chip area has become an urgent problem to be solved. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a multiplexed frequency compensation circuit suitable for constant on-time control. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a multiplexed frequency compensation circuit suitable for constant on-time control, comprising: a control module, an undervoltage detection module, a frequency compensation module, and a hiccup protection module. The frequency compensation module and the hiccup protection module share a dominant pole compensation capacitor. The undervoltage detection module is used to output an abnormal signal when an abnormality is detected in the output voltage of the switching power supply, and to output a normal operation signal when no abnormality is detected in the output voltage of the switching power supply. The control module is used to output a frequency compensation signal according to the normal operation signal and to output a hiccup protection enable signal according to the abnormal signal. The frequency compensation module is used to compensate for the zeros and poles of the switching power supply caused by the power stage and current sampling section by the main pole compensation capacitor according to the frequency compensation signal. The hiccup protection module is used to protect the switching power supply from hiccups within a preset time by charging and discharging the main pole compensation capacitor and counting the number of charging and discharging operations according to the hiccup protection enable signal.

[0005] In one embodiment of the present invention, the undervoltage detection module includes: a first resistor, a second resistor, and a first comparator, wherein, The first terminal of the first resistor receives the output voltage of the switching power supply, the second terminal of the first resistor is connected to the first terminal of the second resistor and outputs a feedback voltage to the inverting input terminal of the first comparator; the second terminal of the second resistor is grounded. The first comparator receives a preset voltage value at its non-inverting input terminal and outputs an undervoltage feedback signal to the control module at its output terminal.

[0006] In one embodiment of the present invention, the frequency compensation module includes: an error amplifier and a compensation network, wherein the compensation network includes: a first capacitor, a third resistor, a first NMOS transistor, a second NMOS transistor, and the main pole compensation capacitor, wherein, The error amplifier receives a reference voltage at its non-inverting input, a feedback voltage at its inverting input, and its output is connected to the first terminal of the first capacitor and the first terminal of the third resistor, and outputs an amplified voltage; the second terminal of the first capacitor is grounded. The second end of the third resistor is connected to the drain of the first NMOS transistor, the source of the first NMOS transistor is connected to the source of the second NMOS transistor, the gate of the first NMOS transistor is connected to the gate of the second NMOS transistor and inputs a control loop enable signal, and the control loop enable signal is output by the control module. The drain of the second NMOS transistor is connected to the first terminal of the main pole compensation capacitor.

[0007] In one embodiment of the present invention, the hiccup protection module includes: a ramp generation module, a ramp voltage detection module, and a counter, wherein the ramp generation module includes the main pole compensation capacitor, wherein, The counter is used to count the number of switching cycles that the system maintains normal operation after an abnormality occurs, based on the hiccup protection enable signal. When the number of switching cycles reaches a preset number of cycles, a node status signal is output to the control module to control the system to enter sleep mode. The ramp generation module is used to cyclically charge and discharge the main pole compensation capacitor between the first reference voltage and the second reference voltage in the system sleep mode to generate a ramp voltage. The ramp voltage detection module is used to detect the relationship between the ramp voltage and the first reference voltage and the second reference voltage, respectively, and output the comparison result to the control module to generate a counter counting signal. The counter is also used to count the number of cycles of charging and discharging of the main pole compensation capacitor according to the counter counting signal. When the number of cycles of charging and discharging reaches a preset number, an exit sleep signal is output to the control module.

[0008] In one embodiment of the present invention, the ramp generation module includes: a main pole compensation capacitor, a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, an inverter, a first reference current source, and a second reference current source, wherein... The first end of the main pole compensation capacitor is connected to the drain of the first PMOS transistor, and the second end of the main pole compensation capacitor is connected to the source of the fifth NMOS transistor, the current outflow terminal of the first reference current source, and grounded. The source of the first PMOS transistor is connected to the source of the second PMOS transistor, and the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor and inputs a control loop enable signal. The control loop enable signal is output by the control module. The drain of the second PMOS transistor is connected to the source of the third NMOS transistor and the drain of the fourth NMOS transistor, and outputs a ramp voltage. The output terminal of the second reference current source is connected to the power supply voltage, and the current output terminal of the second reference current source is connected to the drain of the third NMOS transistor; the gate of the third NMOS transistor receives the clock signal. The gate of the fourth NMOS transistor receives an inverted clock signal, and the source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor and the output of the first reference current source; the input of the inverter receives a first enable signal, and the output is connected to the gate of the fifth NMOS transistor.

[0009] In one embodiment of the present invention, one charging cycle of the main pole compensation capacitor cyclically charging and discharging between the first reference voltage and the second reference voltage is the time taken for the voltage on the main pole compensation capacitor to be charged from the first reference voltage to the second reference voltage and then discharged back to the first reference voltage.

[0010] In one embodiment of the present invention, the ramp voltage rise slope during the charging phase is: ,in, This represents the voltage during the rising phase. For the reference current source, The capacitance value of the main pole compensation capacitor; The slope of the voltage drop during the discharge phase is: ,in, This indicates the voltage during the falling phase; One charging cycle is:

[0011] in, Indicates the second reference voltage. Indicates the first reference voltage; The discharge time within one charging cycle is:

[0012] in, This represents the amplified voltage output by the error amplifier. In one embodiment of the present invention, the ramp voltage detection module includes: a second comparator and a third comparator, wherein, The ramp voltage is input to the non-inverting input terminals of both the second comparator and the third comparator; The second comparator receives a first reference voltage at its inverting input and outputs a first comparison voltage to the control module at its output. The second reference voltage is input to the inverting input terminal of the third comparator, and the second comparison voltage is output to the control module at the output terminal.

[0013] In one embodiment of the present invention, the counter includes: a first-cycle counter and a second-cycle counter, wherein, The first cycle counter is used to input the second enable signal and the power switch waveform signal. After an abnormality occurs, the system maintains normal operation for the number of switching cycles. When the number of switching cycles reaches the preset number of cycles, the node status signal is output to the control module. The first cycle counter is used to input the first enable signal and the clock signal to count the number of cycles of charging and discharging of the main pole compensation capacitor. When the number of cycles of charging and discharging reaches the preset number, an exit sleep signal is output to the control module.

[0014] In one embodiment of the present invention, the control module is composed of logic gates.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: The frequency compensation circuit of this invention employs a frequency compensation module and a hiccup protection module, and the frequency compensation module and hiccup protection module reuse the main pole compensation capacitor, which has a large capacitance and on-chip area. During normal system operation, the main pole compensation capacitor is used to compensate for the zeros and poles caused by the power stage and current sampling section of the switching power supply, maintaining stable system operation through frequency compensation. During hiccup protection, by charging and discharging the main pole compensation capacitor and counting the number of charge and discharge cycles, a long-term timing can be achieved, thereby using a smaller chip area to achieve a longer hiccup protection function with a longer sleep time. Therefore, this invention achieves efficient utilization of on-chip capacitors, effectively reduces chip area costs, and solves the requirement for large capacitors in the compensation network and hiccup protection circuit while using less chip area. Attached Figure Description

[0016] Figure 1 A schematic diagram of the architecture of a multiplexed frequency compensation circuit suitable for constant on-time control provided in an embodiment of the present invention; Figure 2 A circuit structure diagram of a multiplexed frequency compensation circuit suitable for constant on-time control is provided in an embodiment of the present invention; Figure 3 A schematic diagram illustrating the working process of a multiplexed frequency compensation circuit suitable for constant on-time control, provided in an embodiment of the present invention; Figure 4 is a circuit timing diagram of a multiplexed frequency compensation circuit suitable for constant on-time control provided by an embodiment of the present invention. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0018] Example 1 Please see Figure 1 , Figure 1 This is a schematic diagram of the architecture of a multiplexed frequency compensation circuit suitable for constant on-time control, provided by an embodiment of the present invention.

[0019] The circuit in this embodiment includes a control module, an undervoltage detection module, a frequency compensation module, and a hiccup protection module. The frequency compensation module and the hiccup protection module share a main pole compensation capacitor. The undervoltage detection module outputs an abnormal signal when an abnormality is detected in the output voltage of the switching power supply, and outputs a normal operation signal when no abnormality is detected. The control module outputs a frequency compensation signal based on the normal operation signal and a hiccup protection enable signal based on the abnormal signal. The frequency compensation module, based on the frequency compensation signal, compensates for the zeros and poles of the switching power supply caused by the power stage and current sampling section through the main pole compensation capacitor, setting the main pole at the output of the error amplifier to ensure a low-frequency crossover frequency and maintain system stability. The hiccup protection module, based on the hiccup protection enable signal, charges and discharges the main pole compensation capacitor, counts the number of charges and discharges, and provides hiccup protection for the switching power supply within a preset time.

[0020] Please see Figure 2 , Figure 2 This is a circuit structure diagram of a multiplexed frequency compensation circuit suitable for constant on-time control, provided in an embodiment of the present invention.

[0021] In one specific implementation, the frequency compensation module includes an error amplifier EA and a compensation network. The error amplifier EA is a module in the switching power supply used to amplify the error between the feedback voltage and the reference voltage. It reduces the error through a negative feedback loop to maintain accurate output voltage. The compensation network uses capacitors to compensate for the zeros and poles introduced by the power stage and current sampling section of the switching power supply. The dominant pole is set at the output of the error amplifier EA, placing it in the low-frequency range to select a suitable crossover frequency and ensure system stability.

[0022] The compensation network includes: a first capacitor C1, a third resistor R1, and a first NMOS transistor M. N1 The second NMOS transistor M N2 and the principal pole compensation capacitor C c The non-inverting input of the error amplifier EA is connected to a reference voltage V. REF The inverting input terminal receives the feedback voltage V. FB The output terminal is connected to the first terminal of the first capacitor C1 and the first terminal of the third resistor R1, and the output amplified voltage V is obtained. EA The second terminal of the first capacitor C1 is grounded; the second terminal of the third resistor R1 is connected to the first NMOS transistor M. N1 The drain of the first NMOS transistor M N1 The source is connected to the second NMOS transistor M. N2 The source of the first NMOS transistor M N1 The gate of the second NMOS transistor M is connected. N2The gate of the second NMOS transistor is connected to the control loop enable signal LOOP_EN, which is output by the control module; the second NMOS transistor M... N2 The drain is connected to the main pole compensation capacitor C. c The first end.

[0023] In one specific embodiment, the undervoltage detection module includes: a first resistor R FB1 Second resistor R FB2 And the first comparator CMP, the first resistor R FB1 Second resistor R FB2 This forms a voltage divider resistor string.

[0024] First resistor R FB1 The first input terminal is the output voltage V of the switching power supply. OUT First resistor R FB1 The second end is connected to the second resistor R FB2 The first terminal and the output feedback voltage V FB To the inverting input of the first comparator CMP; the second resistor R FB2 The second terminal is grounded; a preset voltage value is input to the non-inverting input terminal of the first comparator CMP. a *V REF The output terminal outputs an undervoltage feedback signal FB_UVP to the control module. Wherein, V REF The reference voltage value. a For example, [the coefficient]. a It is 0.1.

[0025] Specifically, the undervoltage detection module is used to detect the output voltage V of the switching power supply. OUT Whether an abnormality has occurred is determined by the voltage divider resistor R in series. FB1 and R FB2 Output voltage V OUT The feedback voltage V after voltage division FB Provided to the first comparator CMP, the first comparator CMP takes V FB and V FB Target voltage value V REF Compare with 10% of the output voltage V. OUT Below the target voltage value V REF A value of 10% is considered abnormal. The feedback undervoltage signal FB_UVP output from the first comparator CMP represents V. OUT Is the undervoltage caused by a short circuit or other abnormality? V FB and V OUT The relationship can be represented as: .

[0026] In one specific embodiment, the hiccup protection module includes: a ramp generation module, a ramp voltage detection module, and a counter. The ramp generation module includes a main pole compensation capacitor. The counter is used to count the number of switching cycles during which the system maintains normal operation after an abnormality occurs, based on the hiccup protection enable signal. When the number of switching cycles reaches a preset number of cycles, it outputs a node status signal to the control module to control the system to enter a sleep mode. The ramp generation module is used to cyclically charge and discharge the main pole compensation capacitor between a first reference voltage and a second reference voltage in the system sleep mode to generate a ramp voltage. The ramp voltage detection module is used to detect the relationship between the ramp voltage and the first reference voltage and the second reference voltage, respectively, and outputs the comparison result to the control module to generate a counter counting signal. The counter is also used to count the number of cyclic charging and discharging cycles of the main pole compensation capacitor based on the counter counting signal. When the number of cyclic charging and discharging cycles reaches a preset number, it outputs an exit sleep signal to the control module.

[0027] The ramp-generating mold block includes: the main pole compensation capacitor C. c The first PMOS transistor M P1 The second PMOS transistor M P2 The third NMOS transistor M N3 The fourth NMOS transistor M N4 The fifth NMOS transistor M N5 Inverter INV, First reference current source I REF Second reference current source 2*I REF The third NMOS transistor M N3 The fourth NMOS transistor M N4 For charging and discharging switching, the first PMOS transistor M P1 The second PMOS transistor M P2 This is a mode switching switch.

[0028] Dominant pole compensation capacitor C c The first end is connected to the first PMOS transistor M P1 The drain, the main pole compensation capacitor C c The second end is connected to the fifth NMOS transistor M. N5 The source of the first reference current source I REF The current-out terminal is grounded; the first PMOS transistor M P1 The source is connected to the second PMOS transistor M. P2 The source of the first PMOS transistor M P1 The gate of the second PMOS transistor M is connected. P2 The gate of the second PMOS transistor is connected to the control loop enable signal LOOP_EN, which is output by the control module; the second PMOS transistor M... P2 The drain of the third NMOS transistor M is connected. N3The source of the fourth NMOS transistor M N4 The drain and output ramp voltage V RAMP Second reference current source 2*I REF The output terminal is connected to the power supply voltage V. CC Second reference current source 2*I REF The current output terminal is connected to the third NMOS transistor M. N3 The drain of the third NMOS transistor M N3 The gate input clock signal CLK; the fourth NMOS transistor M N4 The gate input is the inverted clock signal CLKN, and the fourth NMOS transistor M N4 The source of the fifth NMOS transistor M is connected. N5 The drain of the first reference current source I REF The output terminal of the inverter INV receives the first enable signal EN at its input terminal, and its output terminal is connected to the fifth NMOS transistor M. N5 The gate.

[0029] Specifically, during normal system operation, the main pole compensation capacitor C included in the ramp generation module... c Used for frequency compensation. During system hibernation in hibernation mode, the ramp generation module supplies C... c The charging and discharging process generates a ramp voltage, which is controlled by a timer switch M. P1 and M P2 The charge / discharge switch is controlled by the control module. This can be achieved by changing I... REF The size causes the ramp slope to differ during charging and discharging of the module, and the ramp voltage V during the charging phase. RAMP The rising slope can be expressed as:

[0030] in, This represents the voltage during the rising phase. For the reference current source, The capacitance value of the main pole compensation capacitor.

[0031] Compared to traditional timing structures that directly discharge the capacitor to ground during discharge, this invention uses a fixed current I. REF The extended discharge time is more conducive to long-term timing. The ramp voltage V during the discharge phase... RAMP The descent slope is:

[0032] in, This indicates the voltage during the descent phase.

[0033] The dominant pole compensation capacitor C c The voltage on the first reference voltage VREF1 Charged to the second reference voltage V REF2 Then it is discharged to the first reference voltage V. REF1 The time taken is called a charging cycle T. charge , can be represented as:

[0034] in, Indicates the second reference voltage. This represents the first reference voltage.

[0035] The specific module for slope voltage detection includes: a second comparator CMP1 and a third comparator CMP2, wherein the non-inverting input terminals of both the second comparator CMP1 and the third comparator CMP2 are input with slope voltage V. RAMP The inverting input of the second comparator CMP1 is input to the first reference voltage V. REF1 The output terminal outputs the first comparison voltage V. CMP1 The control module; the inverting input of the third comparator CMP2 receives the second reference voltage V. REF2 The output terminal outputs the second comparison voltage V. CMP2 To the control module. It can be understood that the ramp voltage detection module is used to detect the ramp voltage generated by the ramp generation module in hiccup protection mode. The two comparators it contains respectively detect whether the ramp voltage reaches V. REF1 and V REF2 The comparator outputs V CMP1 and V CMP2 After being processed by the control module, a square wave CLK with a fixed period is generated and transmitted to the counter.

[0036] The counters are used to count the number of switching cycles of the switching power supply and the number of fixed-period square waves generated by the ramp voltage detection module, respectively. Once the count reaches the required number (i.e., after a set time), an output signal is sent to the control module. Specifically, the counters include a first-cycle counter and a second-cycle counter. The first-cycle counter is used to input the second enable signal EN1 and the power switching waveform signal PWM. It counts the number of switching cycles during which the system maintains normal operation after an anomaly. When the number of switching cycles reaches the preset number of cycles, it outputs the node status signal Q. 10 The first cycle counter is used to input the first enable signal EN and the clock signal CLK to count the number of charge-discharge cycles of the main pole compensation capacitor. When the number of charge-discharge cycles reaches a preset number, an exit sleep signal EXIT_SLEPP is output to the control module. For example, the preset number of cycles is 512 and the preset number of cycles is 15.

[0037] It can be understood that the counter consists of two periodic counters: one for counting the number of switching cycles the system takes to maintain normal operation after an anomaly occurs, and the time of one switching cycle is defined as T. SW Another capacitor C is used to count the capacitors in sleep mode. SS In V REF1 and V REF2 The number of times the charging cycle is repeated. After the required number of cycles is reached, i.e., after the set time is reached, an output signal is sent to the control module.

[0038] In one specific implementation, the control module, based on the outputs of the undervoltage detection module and the counter, controls the implementation of frequency compensation and hiccup protection functions. It is the core control unit for switching the operating mode of the main pole compensation capacitor and hiccup protection. The control module consists of logic gates and is responsible for controlling C based on the outputs of the detection module and the counter module. C The system handles charging / discharging, loop enabling, and system mode switching. Upon undervoltage detection triggering, the control module enables a cycle counter to count switching cycles. After counting 512 switching cycles, the counter output sends a signal to the control module to put the system into sleep mode. The system then enters sleep mode, and the control module will control C... C Switch from the frequency compensation module to the ramp generation module, V RAMP The voltage becomes C C The capacitor stores the output voltage V of EA. EA C C First, it is discharged to below V. REF1 Then, it begins a cyclic charging and discharging process, counted by a cycle counter. After 15 cycles, the timer output sends a signal to the control module, causing the system to exit sleep mode and the loop to be enabled. C The slope generation module was switched to the frequency compensation module as the dominant pole compensation capacitor.

[0039] Please see Figure 3 , Figure 3 This is a schematic diagram illustrating the workflow of a multiplexed frequency compensation circuit suitable for constant on-time control, provided by an embodiment of the present invention. After the switching power supply system is enabled, a soft start is first performed. After the soft start is completed, the system operates normally, at which point the output voltage V is detected. OUT If undervoltage occurs, the system continues normal operation if no undervoltage occurs. If undervoltage occurs, the enable counter counts the switching cycles of the power supply until the count reaches 512, at which point the system enters sleep mode and stops working. At this time, the ramp generation module controls C... C Cyclic charging and discharging is used because the charging and discharging current is relatively small, so each charge and discharge cycle takes a relatively long time. A counter is used to count the number of cycles until 15 are reached, at which point the sleep mode is exited. CAfter being switched back to the frequency compensation module, the system performs a soft restart and re-establishes the EA output operating point. After the soft restart ends, it continues to monitor the output voltage V. OUT Check for undervoltage and repeat the above steps.

[0040] Please refer to Figure 4, which is a circuit timing diagram of a multiplexed frequency compensation circuit suitable for constant on-time control provided by an embodiment of the present invention. When the EN signal goes high, the system is enabled, and CLK, EXIT_SLEPP, and LOOP_EN go high, causing C... C Upon connection to the frequency compensation module, system soft start and power supply switching are enabled. After time T... SS After the soft start ends, SS_OVER goes high, and the switching power supply enters steady-state operation. Upon detecting the output voltage V... OUT After an anomaly occurs, FB_UVP goes high, which in turn causes EN1 to go high via the control module, enabling the 512-cycle counter to count the number of switching cycles of the power switching waveform (PWM). After 512 switching cycles are reached, Q... 10 The high value is controlled by the control module to lower CLK, causing the system to enter sleep mode. RAMP The voltage becomes C C The stored EA output voltage V EA C C First, it is discharged to below V. REF1 Only then will V CMP1 The CLK value decreases, and the control module raises CLK and lowers EXIT_SLEEP. This discharge time T... fall It can be represented as:

[0041] in, This represents the amplified voltage output by the error amplifier.

[0042] After C C It begins to charge when the voltage V RAMP Reaching V REF2 V CMP2 When CLK rises, the control module lowers CLK, causing the capacitor to start discharging again. After 15 charge-discharge cycles, when CLK rises again, it begins to discharge C. C When charging, EXIT_SLEEP and LOOP_EN go high, indicating that the system has exited hibernation mode. C Switched back to frequency compensation circuit, V RAMP The voltage is directly pulled up to the power supply voltage V. CC The loop starts working, re-performing the soft start and switching actions. The soft start process continues until SS_OVER goes high, indicating the soft start is complete. If the output voltage V... OUTStill undervoltage, FB_UVP remains high, EN1 flips high again to enable the 512-cycle counter, counting the PWM switching cycles and repeating the above steps. Until V... OUT The system only resumed normal operation once the voltage drop was resolved.

[0043] The frequency compensation circuit in this embodiment employs a frequency compensation module and a hiccup protection module, and the frequency compensation module and hiccup protection module reuse the main pole compensation capacitor, which has a large capacitance and on-chip area. During normal system operation, the main pole compensation capacitor is used to compensate for the zeros and poles caused by the power stage and current sampling section of the switching power supply, maintaining stable system operation through frequency compensation. During hiccup protection, by charging and discharging the main pole compensation capacitor and counting the number of charge and discharge cycles, a long-term timing can be achieved, thereby using a smaller chip area to achieve a longer hiccup protection function with a longer sleep time. Therefore, this invention achieves efficient utilization of on-chip capacitors, effectively reduces chip area costs, and solves the requirement for large capacitors in the compensation network and hiccup protection circuit while using less chip area.

[0044] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A multiplexed frequency compensation circuit suitable for constant on-time control, characterized in that, include: The system comprises a control module, an undervoltage detection module, a frequency compensation module, and a hiccup protection module. The frequency compensation module and the hiccup protection module share a main pole compensation capacitor. The undervoltage detection module is used to output an abnormal signal when an abnormality is detected in the output voltage of the switching power supply, and to output a normal operation signal when no abnormality is detected in the output voltage of the switching power supply. The control module is used to output a frequency compensation signal according to the normal operation signal and to output a hiccup protection enable signal according to the abnormal signal. The frequency compensation module is used to compensate for the zeros and poles of the switching power supply caused by the power stage and current sampling section by the main pole compensation capacitor according to the frequency compensation signal. The hiccup protection module is used to protect the switching power supply from hiccups within a preset time by charging and discharging the main pole compensation capacitor and counting the number of charging and discharging operations according to the hiccup protection enable signal.

2. The multiplexed frequency compensation circuit suitable for constant on-time control according to claim 1, characterized in that, The undervoltage detection module includes: a first resistor (R) FB1 ), second resistor (R) FB2 ) and the first comparator (CMP), where, The first resistor (R) FB1 The first terminal of the input is the output voltage (V) of the switching power supply. OUT ), the first resistor (R) FB1 The second terminal of ) is connected to the second resistor (R) FB2 The first terminal of the output feedback voltage (V) FB The second resistor (R) is connected to the inverting input of the first comparator (CMP); FB2 The second end of the terminal is grounded; The non-inverting input of the first comparator (CMP) receives a preset voltage value. a *V REF The output terminal outputs a feedback undervoltage signal (FB_UVP) to the control module.

3. The multiplexed frequency compensation circuit suitable for constant on-time control according to claim 1, characterized in that, The frequency compensation module includes an error amplifier (EA) and a compensation network, wherein the compensation network includes a first capacitor (C1), a third resistor (R1), and a first NMOS transistor (M). N1 ), second NMOS transistor (M) N2 ) and the principal pole compensation capacitor (C c ),in, The error amplifier (EA) receives a reference voltage (V) at its non-inverting input. REF The inverting input terminal receives the feedback voltage (V). FB The output terminal is connected to the first terminal of the first capacitor (C1) and the first terminal of the third resistor (R1), and outputs an amplified voltage (V). EA The second terminal of the first capacitor (C1) is grounded. The second end of the third resistor (R1) is connected to the first NMOS transistor (M). N1 The drain of the first NMOS transistor (M) N1 The source of ) is connected to the second NMOS transistor (M) N2 The source of the first NMOS transistor (M) N1 The gate of the second NMOS transistor (M) is connected to the gate of the second NMOS transistor (M). N2 The gate of the control module is connected to the input control loop enable signal (LOOP_EN), which is output by the control module. The second NMOS transistor (M) N2 The drain of the capacitor is connected to the main pole compensation capacitor (C). c The first end of ).

4. The multiplexed frequency compensation circuit suitable for constant on-time control according to claim 1, characterized in that, The hiccup protection module includes: a ramp generation module, a ramp voltage detection module, and a counter. The ramp generation module includes the main pole compensation capacitor. The counter is used to count the number of switching cycles that the system maintains normal operation after an abnormality occurs, based on the hiccup protection enable signal. When the number of switching cycles reaches a preset number of cycles, a node status signal is output to the control module to control the system to enter sleep mode. The ramp generation module is used to cyclically charge and discharge the main pole compensation capacitor between the first reference voltage and the second reference voltage in the system sleep mode to generate a ramp voltage. The ramp voltage detection module is used to detect the relationship between the ramp voltage and the first reference voltage and the second reference voltage, respectively, and output the comparison result to the control module to generate a counter counting signal. The counter is also used to count the number of cycles of charging and discharging of the main pole compensation capacitor according to the counter counting signal. When the number of cycles of charging and discharging reaches a preset number, an exit sleep signal is output to the control module.

5. The multiplexed frequency compensation circuit suitable for constant on-time control according to claim 4, characterized in that, The ramp generation module includes: the dominant pole compensation capacitor (C) c ), first PMOS transistor (M) P1 ), second PMOS transistor (M) P2 ), the third NMOS transistor (M) N3 ), the fourth NMOS transistor (M) N4 ), the fifth NMOS transistor (M) N5 ), inverter (INV), first reference current source (I) REF ) and second reference current source (2*I REF ),in, The main pole compensation capacitor (C) c The first end of the first PMOS transistor (M) is connected to the first PMOS transistor (M). P1 The drain of the main pole, the main pole compensation capacitor (C) c The second end of the transistor is connected to the fifth NMOS transistor (M). N5 The source of ) and the first reference current source (I REF The current outlet of the terminal is grounded; The first PMOS transistor (M) P1 The source of ) is connected to the second PMOS transistor (M) P2 The source of the first PMOS transistor (M) P1 The gate of the second PMOS transistor (M) is connected to the gate of the second PMOS transistor. P2 The gate of the second PMOS transistor (M) is connected to the control loop enable signal (LOOP_EN), which is output by the control module; P2 The drain of the third NMOS transistor (M) is connected to the drain of the third NMOS transistor. N3 The source of the fourth NMOS transistor (M) N4 The drain of the ) and the output ramp voltage (V) RAMP ); The second reference current source (2*I) REF The output terminal is connected to the power supply voltage (V). CC ), the second reference current source (2*I REF The current output terminal of the ) is connected to the third NMOS transistor (M) N3 The drain of the third NMOS transistor (M); N3 The gate input clock signal (CLK) of the gate; The fourth NMOS transistor (M) N4 The gate input of the fourth NMOS transistor (M) is an inverted clock signal (CLKN). N4 The source of the fifth NMOS transistor (M) is connected to the source of the fifth NMOS transistor. N5 The drain of ) and the first reference current source (I) REF The output terminal of the inverter (INV) is connected to the first enable signal (EN), and the output terminal is connected to the fifth NMOS transistor (M). N5 ) gate.

6. The multiplexed frequency compensation circuit for constant on-time control according to claim 5, characterized in that, One charging cycle of the main pole compensation capacitor between the first reference voltage and the second reference voltage is: the main pole compensation capacitor (C) is charged and discharged repeatedly between the first reference voltage and the second reference voltage for one charging cycle. c The voltage on the first reference voltage (V) is from the voltage on the first reference voltage (V) REF1 Charged to the second reference voltage (V) REF2 ), and then discharged to the first reference voltage (V REF1 The time taken.

7. The multiplexed frequency compensation circuit for constant on-time control according to claim 6, characterized in that, Charging phase ramp voltage (V) RAMP The rising slope of ) is: ,in, This represents the voltage during the rising phase. For the reference current source, The capacitance value of the main pole compensation capacitor; Discharge phase ramp voltage (V) RAMP The descending slope of ) is: ,in, This indicates the voltage during the falling phase; One charging cycle is: in, Indicates the second reference voltage. Indicates the first reference voltage; The discharge time within one charging cycle is: in, This represents the amplified voltage output by the error amplifier.

8. The multiplexed frequency compensation circuit for constant on-time control according to claim 4, characterized in that, The ramp voltage detection module includes: a second comparator (CMP1) and a third comparator (CMP2), wherein, The ramp voltage (V) is input to the non-inverting input of both the second comparator (CMP1) and the third comparator (CMP2). RAMP ); The inverting input of the second comparator (CMP1) is input with a first reference voltage (V). REF1 The output terminal outputs the first comparison voltage (V). CMP1 (to the control module;) The inverting input of the third comparator (CMP2) is input to the second reference voltage (V). REF2 The output terminal outputs a second comparison voltage (V). CMP2 ) to the control module.

9. The multiplexed frequency compensation circuit for constant on-time control according to claim 4, characterized in that, The counter includes: a first-cycle counter and a second-cycle counter, wherein, The first cycle counter is used to input the second enable signal (EN1) and the power switching waveform signal (PWM). It counts the number of switching cycles the system maintains normal operation after an anomaly occurs. When the number of switching cycles reaches a preset number of cycles, it outputs a node status signal (Q). 10 (to the control module;) The first cycle counter is used to input the first enable signal (EN) and the clock signal (CLK) to count the number of cycles of charging and discharging of the main pole compensation capacitor. When the number of cycles of charging and discharging reaches the preset number, an exit sleep signal (EXIT_SLEPP) is output to the control module.

10. The multiplexed frequency compensation circuit for constant on-time control according to claim 1, characterized in that, The control module consists of logic gates.

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