A single amplifier multiplexed voltage controlled oscillator that can be externally synchronized to a wide range of clocks
By introducing a comparator structure with dual positive inputs and dual outputs and an RS flip-flop into a voltage-controlled oscillator, external synchronization operation without a phase-locked loop is achieved, solving the problem of increased chip area and power consumption in the prior art, and realizing a wide synchronization range and low power consumption external synchronization function.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2026-02-11
- Publication Date
- 2026-06-05
AI Technical Summary
Existing voltage-controlled oscillators suffer from increased chip area and power consumption when implementing external synchronization functions, making it difficult to meet the requirements of miniaturization and low power consumption, especially in highly integrated power supply systems.
It adopts a comparator structure with dual positive input and dual output, combined with RS flip-flops and multiplexed single amplifiers to achieve external synchronous operation without the need for a phase-locked loop. The charging and discharging signal of the oscillating charging capacitor is amplified and shaped, and output to the RS flip-flop to control the trigger timing and oscillation frequency.
It achieves a wide synchronization range of external synchronization clock input frequency between half and twice the intrinsic oscillation frequency, improves circuit integration and compatibility, reduces power consumption, and outputs a square wave clock signal with a 50% duty cycle.
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Figure CN122159798A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of switching power supply technology, and more specifically to a single amplifier multiplexed voltage-controlled oscillator with an externally synchronized wide-range clock. Background Technology
[0002] As a core component of modern wireless communication and radio frequency systems, highly integrated voltage-controlled oscillators (VCOs) are developed in close accordance with the advancement of integrated circuit technology and the evolution of market demands. Early VCOs mostly adopted discrete component designs, relying on LC resonant circuits or crystal resonant structures. Although they could achieve basic functions, they suffered from problems such as large size, high power consumption, and difficulty in integration, especially facing significant technical bottlenecks in high-frequency applications such as millimeter waves and terahertz.
[0003] With the maturation of CMOS technology, especially the shrinking of feature sizes (e.g., below 0.18μm), transistor cutoff frequencies have significantly increased, making it possible to integrate high-performance RF circuits on a single chip, thus driving the emergence of fully integrated CMOS voltage-controlled oscillators (VCOs). For example, an LC-VCO structure using accumulator-type MOS varactors and planar spiral inductors, through optimization of tuning linearity and phase noise, has achieved a fully integrated design in the 2.4GHz band, meeting the miniaturization and low-power requirements of wireless communication standards such as Bluetooth and WLAN. However, integration requires overcoming issues such as process deviations, parasitic effects, and thermal management. To address this, researchers have introduced thin-film hybrid integration technology, encapsulating modules such as coarse and fine tuning circuits, oscillation circuits, and power divider circuits within a fully sealed metal casing. Inductors and resistors are fabricated using thin-film processes, significantly reducing device size and improving isolation. Furthermore, the ultra-integrated miniaturized power supplies required for the Internet of Things (IoT) place increasingly stringent area requirements on power supplies with phase-locked loops (PLLs) and external synchronization functions. In recent years, the introduction of intelligent control technology (such as tail current adjustable modules) and digital auxiliary calibration algorithms has further enhanced the environmental adaptability and flexibility of integrated VCOs, enabling them to show broader application prospects in 5G communication, Internet of Things and radar systems.
[0004] Zhang Kefeng (Zhang Kefeng, Lin Yingyan, Zhang Jing, et al. Design of a window comparator CMOS oscillator with external synchronization function [J]. Microelectronics & Computer, 2007, (12): 183-186. DOI: 10.19304 / j.cnki.issn1000-7180.2007.12.053.) proposed a window comparator CMOS oscillator with external synchronization function. The oscillator can operate stably at its natural frequency of 550kHz in non-external synchronization mode, and can follow the frequency of external synchronization signal in the range of 585kHz-750kHz in external synchronization mode. It achieves external synchronization function while minimizing difference frequency noise. However, due to the circuit structure of using two comparators, there are shortcomings such as increased chip area and power consumption. Summary of the Invention
[0005] To overcome the shortcomings of the existing technology, the present invention aims to provide a single amplifier multiplexed voltage-controlled oscillator with a wide range of externally synchronized clocks. By introducing a comparator structure with dual positive input and dual output, it can independently complete the external clock synchronization operation without the need for a phase-locked loop, and can achieve a wide synchronization range between half and twice the intrinsic oscillation frequency of the external synchronization clock input frequency. It has good performance in some small-scale, low-volume, and highly integrated power supply systems that require external synchronization functions.
[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A single-amplifier multiplexed voltage-controlled oscillator with an externally synchronized wide-range clock, including a bias current source I. B Multiplexed single amplifier, oscillation charging capacitor, external synchronization input and RS trigger; the bias current source I B A multiplexed single amplifier is connected to provide bias current to each stage transistor in the multiplexed single amplifier, so that each transistor operates in a preset linear amplification region; the multiplexed single amplifier is connected to an oscillating charging capacitor, an external synchronization input, and an RS flip-flop, respectively, to receive the synchronization trigger signal output by the external synchronization input, amplify and shape it in combination with the charging and discharging signal of the oscillating charging capacitor, and output it to the RS flip-flop to control the trigger timing and oscillation frequency of the RS flip-flop; the oscillating charging capacitor is connected to the external synchronization input and the RS flip-flop, and is used to generate an oscillation timing signal through its own charging and discharging process to provide a frequency reference for the RS flip-flop.
[0007] Furthermore, the multiplexed single amplifier includes NMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M1. 10 PMOS transistor M 11 PMOS transistor M 12 NMOS transistor M 13 NMOS transistor M 14 The source of the PMOS transistor M3, and the PMOS transistor M 10 The source of the PMOS transistor M 11 The source of the PMOS transistor M 12The sources are all connected to the power supply voltage V. CC The gate of PMOS transistor M3 is connected to PMOS transistor M. 10 The gate of PMOS transistor M3 is connected to the drain of PMOS transistor M3, and the connection points between the gate and drain of PMOS transistor M3 are respectively connected to the drain of PMOS transistor M4. 11 The gate of the PMOS transistor M 12 The gate of PMOS transistor M3 is connected to the drain of NMOS transistor M2. 10 The drains of the transistors are connected to the sources of PMOS transistors M4, M5, and M6, respectively. 11 The drain of the NMOS transistor M is connected 13 The drain of the PMOS transistor M 12 The drain of the NMOS transistor M is connected 14 The drain of PMOS transistor M4 is connected to the drain of NMOS transistor M7 and NMOS transistor M8, respectively. 13 The gate of PMOS transistor M5 and the drain of PMOS transistor M8 are respectively connected to the drain of NMOS transistor M8 and NMOS transistor M9. 14 The gate of PMOS transistor M6 is connected to the drain of NMOS transistor M9, and the gate of PMOS transistor M6 is connected to a DC reference voltage V. REF The gate of NMOS transistor M2 is connected to the gate of NMOS transistor M1, and the gate of NMOS transistor M1 is connected to the drain of NMOS transistor M1. The connection point between the gate and drain of NMOS transistor M1 is connected to the gates of NMOS transistors M7, M8, and M9, respectively. The source of NMOS transistor M1 is connected to the sources of NMOS transistors M2, M7, M8, and M9, respectively. 13 The source of the NMOS transistor M 14 The source pole.
[0008] Furthermore, the bias current source I B The output terminal is connected to the drain of NMOS transistor M1.
[0009] Furthermore, the oscillation charging capacitor includes capacitor C1, capacitor C2, and NMOS transistor M. 15 NMOS transistor M 16 First voltage-controlled current source I V1 Second voltage-controlled current source I V2 One end of capacitor C1 is grounded and connected to NMOS transistor M. 15 The source of the capacitor is connected to the other end of the capacitor C1, which is connected to the NMOS transistor M. 15 The drain of the first voltage-controlled current source I V1The output terminal, the gate of PMOS transistor M4, and one end of capacitor C1 connected to NMOS transistor M 15 The connection points between the sources of the NMOS transistor and capacitor C2 are respectively connected to one end of capacitor C2 and the other end of NMOS transistor M. 16 The source of NMOS transistor M1 and the source of NMOS transistor M2 are connected to the other end of capacitor C2 respectively. 16 The drain of the second voltage-controlled current source I V2 The output terminal and the gate of PMOS transistor M5.
[0010] Furthermore, the capacitance values of capacitor C1 and capacitor C2 are equal.
[0011] Furthermore, the external synchronization input and RS flip-flop include a 2-input NOR gate (NOR2), a NOT gate (NOT), and an RS flip-flop; the output of the 2-input NOR gate (NOR2) is connected to the input of the NOT gate (NOT), the output of the NOT gate (NOT) is connected to the R terminal of the RS flip-flop, and the first input of the 2-input NOR gate (NOR2) is connected to the PMOS transistor M. 12 The drain of the NMOS transistor M 14 The connection point between the drains of the two inputs is used as the second input of the 2-input NOR2 gate as the synchronous clock input SYNC IN. The S-terminal of the RS flip-flop is connected to the PMOS transistor M. 11 The drain of the NMOS transistor M 13 The connection point between the drains of the RS flip-flop is connected to the QN terminal of the NMOS transistor M. 16 The gate of the RS flip-flop is used as the clock output CLKOUT of the voltage-controlled oscillator, and is connected to the NMOS transistor M. 15 The gate.
[0012] Furthermore, the voltage-controlled oscillator can perform external clock synchronization independently without the need for a phase-locked loop, and can achieve a wide synchronization range between half and twice the intrinsic oscillation frequency of the external synchronization clock input frequency.
[0013] Furthermore, the voltage-controlled oscillator can output a square wave clock signal with a duty cycle of 50%.
[0014] Wireless communication / RF systems, including any of the single-amplifier multiplexed voltage-controlled oscillators capable of externally synchronizing a wide-range clock as described above.
[0015] Compared with the prior art, the advantages of the present invention are as follows: 1. This invention utilizes the synergistic operation of an RS flip-flop and a multiplexed single amplifier to reconstruct a group of voltage comparators at different voltage levels using a multiplexed single amplifier structure. This achieves hardware function multiplexing. Compared to existing voltage-controlled oscillators with multiple comparators, the single comparator multiplexing of this invention features small area and low power consumption, greatly improving the integration of the circuit.
[0016] 2. This invention utilizes the switching of the multiplexed amplifier in different half-cycle states and operating areas to trigger RS flip-flops to generate self-oscillating clocks. It automatically synchronizes the second half-cycle of the external clock based on the change time of the edge of the external synchronization clock signal. Combined with the linear charging and discharging control of the oscillation charging capacitor and the continuously adjustable intrinsic frequency, it achieves a wide synchronization range of the external synchronization clock input frequency between one-half and two times the intrinsic oscillation frequency, thereby improving the compatibility, adaptability, and robustness of the voltage-controlled oscillator.
[0017] 3. The voltage-controlled oscillator of the present invention can realize a triangular wave and has the advantages of high waveform linearity, simplified hardware structure, continuously adjustable frequency and wide synchronization range.
[0018] 4. The voltage-controlled oscillator of the present invention can achieve a 50% duty cycle signal and has the advantages of waveform symmetry, cost reduction and simplified structure, and functional decoupling and stability.
[0019] In summary, the voltage-controlled oscillator of this invention introduces a comparator structure with dual positive input and dual output, which can independently complete the external clock synchronization operation without the need for a phase-locked loop. It can also achieve a wide synchronization range between half and twice the intrinsic oscillation frequency of the external synchronization clock input frequency, and has good performance in some small-scale, low-volume, and highly integrated power supply systems that require external synchronization functions. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the circuit structure of the single-amplifier multiplexed voltage-controlled oscillator with externally synchronized wide-range clock of the present invention. Figure 1 .
[0021] Figure 2 This is a schematic diagram of the circuit structure of the single-amplifier multiplexed voltage-controlled oscillator with externally synchronized wide-range clock of the present invention. Figure 2 .
[0022] Figure 3 This is a schematic diagram of the integrated circuit structure of the bias current source and voltage-controlled current source of the present invention.
[0023] Figure 4 The waveform diagram shows the operation of the single-amplifier multiplexed voltage-controlled oscillator with externally synchronized wide-range clock of the present invention.
[0024] Among them, V CC Indicates the power supply voltage, M1, M2, M7, M8, M9, M 13 M 14 M 15 M 16 M 17 All of these represent NMOS transistors, M3, M4, M5, M6, and M... 10 M11 M 12 M 18 M 19 M 20 M 21 Both refer to PMOS transistors, I B This indicates the bias current source; C1 and C2 both represent capacitors; V REF Indicates the DC reference voltage, I V1 Indicates the first voltage-controlled current source, I V2 This indicates the second voltage-controlled current source; NOR 2 indicates a 2-input NOR gate; NOT indicates a NOT gate; V C1 This represents the voltage across capacitor C1, in V. C2 This indicates the voltage across capacitor C2. SYNC IN indicates the synchronous clock input, and CLKOUT indicates the clock output of the voltage-controlled oscillator. Detailed Implementation
[0025] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments: See Figure 1 and Figure 2 A single-amplifier multiplexed voltage-controlled oscillator capable of externally synchronizing a wide-range clock, including a bias current source I. B Multiplexed single amplifier, oscillation charging capacitor, external synchronization input and RS trigger; the bias current source I B A multiplexed single amplifier is connected to provide bias current to each stage transistor in the multiplexed single amplifier, so that each transistor operates in a preset linear amplification region; the multiplexed single amplifier is connected to an oscillating charging capacitor, an external synchronization input, and an RS flip-flop, respectively, to receive the synchronization trigger signal output by the external synchronization input, amplify and shape it in combination with the charging and discharging signal of the oscillating charging capacitor, and output it to the RS flip-flop to control the trigger timing and oscillation frequency of the RS flip-flop; the oscillating charging capacitor is connected to the external synchronization input and the RS flip-flop, and is used to generate an oscillation timing signal through its own charging and discharging process to provide a frequency reference for the RS flip-flop.
[0026] The multiplexed single amplifier includes NMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M1. 10 PMOS transistor M 11 PMOS transistor M 12 NMOS transistor M 13 NMOS transistor M 14 The source of the PMOS transistor M3, and the PMOS transistor M 10 The source of the PMOS transistor M 11 The source of the PMOS transistor M12 The sources are all connected to the power supply voltage V. CC The gate of PMOS transistor M3 is connected to PMOS transistor M. 10 The gate of PMOS transistor M3 is connected to the drain of PMOS transistor M3, and the connection points between the gate and drain of PMOS transistor M3 are respectively connected to the drain of PMOS transistor M4. 11 The gate of the PMOS transistor M 12 The gate of PMOS transistor M3 is connected to the drain of NMOS transistor M2. 10 The drains of the transistors are connected to the sources of PMOS transistors M4, M5, and M6, respectively. 11 The drain of the NMOS transistor M is connected 13 The drain of the PMOS transistor M 12 The drain of the NMOS transistor M is connected 14 The drain of PMOS transistor M4 is connected to the drain of NMOS transistor M7 and NMOS transistor M8, respectively. 13 The gate of PMOS transistor M5 and the drain of PMOS transistor M8 are respectively connected to the drain of NMOS transistor M8 and NMOS transistor M9. 14 The gate of PMOS transistor M6 is connected to the drain of NMOS transistor M9, and the gate of PMOS transistor M6 is connected to a DC reference voltage V. REF The gate of NMOS transistor M2 is connected to the gate of NMOS transistor M1, and the gate of NMOS transistor M1 is connected to the drain of NMOS transistor M1. The connection point between the gate and drain of NMOS transistor M1 is connected to the gates of NMOS transistors M7, M8, and M9, respectively. The source of NMOS transistor M1 is connected to the sources of NMOS transistors M2, M7, M8, and M9, respectively. 13 The source of the NMOS transistor M 14 The source pole.
[0027] In this embodiment, PMOS transistors M4, M5, M6, M7, M8, M9, and M1 are used. 10 PMOS transistor M 11 PMOS transistor M 12 NMOS transistor M 13 NMOS transistor M 14Controlled by mode switching (i.e., when no external synchronization clock is input, when the external synchronization clock input is kept high, when the external synchronization clock input frequency is half to one time the intrinsic oscillation frequency, and when the external synchronization clock input frequency is one time to two times the intrinsic oscillation frequency), it is multiplexed into a set of comparators (PMOS transistor M5, NMOS transistor M8, PMOS transistor M6, NMOS transistor M9, and PMOS transistor M1 during the positive half-cycle). 10 PMOS transistor M 12 NMOS transistor M 14 Multiplexing as the first comparator, during the negative half-cycle, PMOS transistors M4, M7, M6, and M9, and PMOS transistor M... 10 PMOS transistor M 11 NMOS transistor M 13 (Reused as a second comparator), it achieves oscillation signal threshold detection, zero-point marker generation, and phase synchronization functions without adding a new independent comparator circuit, effectively improving chip integration and reducing the number of devices and power consumption. NMOS transistors M1, M2, and M3 provide bias current for the multiplexed single amplifier, stabilize the oscillation loop gain, and ensure that the voltage-controlled oscillator can reliably start and maintain stable oscillation under different control voltages.
[0028] The bias current source I B The output terminal is connected to the drain of NMOS transistor M1.
[0029] See Figure 3 This invention provides a bias current source I B One implementation: the bias current source I B Including operational amplifiers (OP) and NMOS transistors (M) 17 Resistor R, PMOS transistor M 18 PMOS transistor M 19 The non-inverting input (+) of the operational amplifier OP is connected to a DC reference voltage V. REF The inverting input (-) of the operational amplifier OP is connected to the NMOS transistor M. 17 The source of the NMOS transistor is connected to one end of resistor R, and the other end of resistor R is grounded. 17 The gate of the NMOS transistor is connected to the output of the operational amplifier (OP). 17 The drain of the PMOS transistor M is connected. 18 The drain of the PMOS transistor M 18 The gates of the two transistors are respectively connected to the PMOS transistor M. 18 The drain of the PMOS transistor M 19 The gate of the PMOS transistor M 18 The source and PMOS transistor M 19 The sources are all connected to the power supply voltage V. CCPMOS transistor M 19 The drain is used as the bias current source I B The output terminal is connected to the drain of NMOS transistor M1.
[0030] The oscillation charging capacitor includes capacitor C1, capacitor C2, and NMOS transistor M. 15 NMOS transistor M 16 First voltage-controlled current source I V1 Second voltage-controlled current source I V2 One end of capacitor C1 is grounded and connected to NMOS transistor M. 15 The source of the capacitor is connected to the other end of the capacitor C1, which is connected to the NMOS transistor M. 15 The drain of the first voltage-controlled current source I V1 The output terminal, the gate of PMOS transistor M4, and one end of capacitor C1 connected to NMOS transistor M 15 The connection points between the sources of the NMOS transistor and capacitor C2 are respectively connected to one end of capacitor C2 and the other end of NMOS transistor M. 16 The source of NMOS transistor M1 and the source of NMOS transistor M2 are connected to the other end of capacitor C2 respectively. 16 The drain of the second voltage-controlled current source I V2 The output terminal and the gate of PMOS transistor M5.
[0031] The first voltage-controlled current source I V1 Second voltage-controlled current source I V2 All are capacitor charging currents controlled by DC voltage; see [link / reference] Figure 3 The present invention provides a first voltage-controlled current source I. V1 Second voltage-controlled current source I V2 One implementation method: The first voltage-controlled current source I V1 Including operational amplifiers (OP) and NMOS transistors (M) 17 PMOS transistor M 18 PMOS transistor M 20 The operational amplifier OP and NMOS transistor M 17 PMOS transistor M 18 With the above bias current source I B Reuse; the PMOS transistor M 18 The gate of the PMOS transistor M 18 The connection point between the drain and the PMOS transistor M 20 The gate of the PMOS transistor M 20 The source is connected to the power supply voltage V. CC PMOS transistor M 20 The drain of the first voltage-controlled current source I V1 Connect the output terminal of the capacitor to the other end of capacitor C1.
[0032] The second voltage-controlled current source IV2 includes an operational amplifier OP and an NMOS transistor M. 17 PMOS transistor M 18 PMOS transistor M 21 The operational amplifier OP and NMOS transistor M 17 PMOS transistor M 18 With the above bias current source I B Reuse; the PMOS transistor M 18 The gate of the PMOS transistor M 18 The connection point between the drain and the PMOS transistor M 21 The gate of the PMOS transistor M 21 The source is connected to the power supply voltage V. CC PMOS transistor M 21 The drain of the second voltage-controlled current source I V2 Connect the output terminal of and the other end of capacitor C2.
[0033] The capacitance values of capacitors C1 and C2 are equal.
[0034] The external synchronization input and RS flip-flop include a 2-input NOR gate (NOR2), a NOT gate (NOT), and an RS flip-flop; the output of the 2-input NOR gate (NOR2) is connected to the input of the NOT gate (NOT), the output of the NOT gate (NOT) is connected to the R terminal of the RS flip-flop, and the first input of the 2-input NOR gate (NOR2) is connected to the PMOS transistor M. 12 The drain of the NMOS transistor M 14 The connection point between the drains of the two inputs is used as the second input of the 2-input NOR2 gate as the synchronous clock input SYNC IN. The S-terminal of the RS flip-flop is connected to the PMOS transistor M. 11 The drain of the NMOS transistor M 13 The connection point between the drains of the RS flip-flop is connected to the QN terminal of the NMOS transistor M. 16 The gate of the RS flip-flop is used as the clock output CLKOUT of the voltage-controlled oscillator, and is connected to the NMOS transistor M. 15 The gate.
[0035] Wireless communication / RF systems, including any of the single-amplifier multiplexed voltage-controlled oscillators capable of externally synchronizing a wide-range clock as described above.
[0036] The working principle of this invention is as follows: The voltage-controlled oscillator of this invention can perform external clock synchronization independently without the need for a phase-locked loop, and can achieve a wide synchronization range between half and twice the intrinsic oscillation frequency of the external synchronization clock input frequency, specifically with the following four modes: Mode 1, without external synchronization clock input: When the Q output of the RS flip-flop (i.e., the clock output CLKOUT of the voltage-controlled oscillator) is low, the QN output of the RS flip-flop is high, and the NMOS transistor M... 16 Turn on, NMOS transistor M 15 When the capacitor is turned off, the voltage V across capacitor C1 is... C1 As the charge gradually increases, capacitor C2 remains at zero. PMOS transistors M5, M8, M6, M9, and M1... 10 PMOS transistor M 12 NMOS transistor M 14 When the capacitor C1 voltage reaches the DC reference voltage V, the NMOS transistor M7 is turned off as the first comparator. REF At that time, the first comparator output voltage V S The switching from low to high level causes the RS flip-flop to respond to the rising edge of the clock signal, latching the Q input of the RS flip-flop high and latching the QN input of the RS flip-flop low. This then activates the NMOS transistor M. 15 Turn on, NMOS transistor M 16 When the circuit is turned off, capacitor C1 discharges instantaneously to 0, and capacitor C2 repeats the same charging process as C1. At this time, PMOS transistors M4, M7, M6, and M9, and PMOS transistor M... 10 PMOS transistor M 11 NMOS transistor M 13 When multiplexed as a second comparator, NMOS transistor M8 is turned off until the output voltage V of the second comparator is reached. R The low-level to high-level transition causes the Q input of the RS flip-flop to be latched low upon the rising edge of its R input, thus completing one oscillation cycle. This alternation continues, and in the default state without an external clock input, a square wave clock signal with a 50% duty cycle can be output.
[0037] When the voltage-controlled oscillator is in its intrinsic oscillation state without external clock input, since the charging of capacitors C1 and C2 is approximately constant current charging, and the switching time of the voltage-controlled oscillator of this invention is negligible, the oscillation period of the voltage-controlled oscillator of this invention is... for: in, C This indicates the capacitance value of capacitor C1 or capacitor C2, in V. REF IV represents the DC reference voltage, and IV represents the voltage across capacitor C1 or capacitor C2. Mode 2, when the external synchronization clock input is kept high: After being ANDed and NOTed with the output signal of the second comparator in the second negative half-cycle, the level change of the second comparator in the second negative half-cycle is shielded, thereby keeping the R terminal of the RS flip-flop high and stopping the voltage-controlled oscillator from oscillating.
[0038] Mode 3, when the external synchronization clock input frequency is half to one time the intrinsic oscillation frequency: when the Q output of the RS flip-flop (i.e., the clock output CLKOUT of the voltage-controlled oscillator) is low, the QN output of the RS flip-flop is high, and the NMOS transistor M... 16 Turn on, NMOS transistor M 15 When the capacitor is turned off, the voltage V across capacitor C1 is... C1 As the charge gradually increases, capacitor C2 remains at zero. PMOS transistors M5, M8, M6, M9, and M1... 10 PMOS transistor M 12 NMOS transistor M 14 When multiplexed as the first comparator, M7 is turned off; when the voltage across capacitor C1 reaches the DC reference voltage V... REF At that time, the first comparator output voltage V S The transition from low to high level causes the RS flip-flop to respond to the rising edge of the clock signal, latching the Q input of the RS flip-flop high and the QN input low. This positive half-cycle oscillation mode is the same as the positive half-cycle behavior in mode one without an external synchronization clock. Therefore, the NMOS transistor M... 15 Turn on, NMOS transistor M 16 When the circuit is turned off, capacitor C1 discharges instantaneously to 0. At this time, PMOS transistors M4, M7, M6, M9, and M1 are in operation. 10 PMOS transistor M 11 NMOS transistor M 13 When the NMOS transistor M8 is turned off, it is used as the second comparator, and capacitor C2 charges to the DC reference voltage V. REF It will not stop there; the second comparator outputs voltage V. R The flip-flop is shielded by a high level of the external clock until the falling edge of the external clock arrives, causing the Q input of the RS flip-flop to be latched low based on the rising edge of its R input, thus completing one oscillation cycle. When the phase between the intrinsic oscillation and the external clock is arbitrary, the voltage-controlled oscillator of this invention will continuously and automatically adjust until it is in sync with the frequency of the external clock, and the phase difference is maintained at 180 degrees. Mode 4, when the external synchronization input clock frequency is one to two times the intrinsic oscillation frequency: when the Q output of the RS flip-flop (i.e., the clock output CLKOUT of the voltage-controlled oscillator) is low, the QN output of the RS flip-flop is high, and the NMOS transistor M... 16 Turn on, NMOS transistor M15 When the capacitor is turned off, the voltage V across capacitor C1 is... C1 As the charge gradually increases, capacitor C2 remains at zero. PMOS transistors M5, M8, M6, and M9, and PMOS transistor M... 10 PMOS transistor M 12 NMOS transistor M 14 When the capacitor C1 voltage reaches the DC reference voltage V, the NMOS transistor M7 is turned off as the first comparator. REF At that time, the first comparator output voltage V S The transition from low to high level causes the RS flip-flop to respond to the rising edge of the clock signal, latching the Q input of the RS flip-flop high and the QN input low. This positive half-cycle oscillation mode is the same as the positive half-cycle behavior in mode one without an external synchronization clock. Therefore, the NMOS transistor M... 15 Turn on, NMOS transistor M 16 When the circuit is turned off, capacitor C1 discharges instantaneously to 0. At this time, PMOS transistors M4, M7, M6, M9, and M1 are discharged. 10 PMOS transistor M 11 NMOS transistor M 13 When the NMOS transistor M8 is turned off, it is used as the second comparator, and capacitor C2 charges to the DC reference voltage V. REF Before, the output voltage V of the second comparator R Even though the external clock has not flipped, the falling edge of the external clock has already arrived, directly causing the Q input of the RS flip-flop to be latched low based on the rising edge of its R input. This forces capacitor C1 to discharge, shortening the duration of the negative half-cycle, thus completing one oscillation cycle at a frequency lower than the intrinsic frequency. When the phase between the intrinsic oscillation and the external clock is arbitrary, the voltage-controlled oscillator of this invention will continuously and automatically adjust until it matches the frequency of the external clock, maintaining a phase difference of 180 degrees.
[0039] Furthermore, the voltage-controlled oscillator of this invention introduces a comparator structure with dual positive inputs and dual outputs, significantly improving circuit integration; when the Q input of the RS flip-flop, i.e., CLKOUT, is low, and the QN input of the RS flip-flop is high, the NMOS transistor M... 16 Turn on, NMOS transistor M 15 When the circuit is turned off, capacitor C1 gradually charges, and the voltage V across capacitor C1... C1 As the voltage rises, the voltage V across capacitor C2 increases. C2 The value remains 0. At this time, PMOS transistor M5, NMOS transistor M8, PMOS transistor M6, NMOS transistor M9, and PMOS transistor M... 10 PMOS transistor M 12 NMOS transistor M 14The first comparator is formed by turning off NMOS transistor M7, which temporarily disables the branch of NMOS transistor M7; when the voltage across capacitor C1 is greater than or equal to the DC reference voltage V... REF At that time, the output voltage V of the first comparator S When the voltage level flips from low to high, since the RS flip-flop is edge-triggered, the Q output of the RS flip-flop is latched high, and the QN output is latched low. Therefore, the NMOS transistor M... 15 Turn on, NMOS transistor M 16 When the circuit is turned off, capacitor C1 discharges instantaneously to 0, and capacitor C2 repeats the same charging process as C1. At this time, PMOS transistors M4, M7, M6, M9, and M1 are in operation. 10 PMOS transistor M 11 NMOS transistor M 13 To form the second comparator, the NMOS transistor M8 is turned off, temporarily deactivating its branch until the output voltage V of the second comparator is reached. R The low-level to high-level transition resets the RS flip-flop output Q, latching it low and completing one oscillation cycle. This alternating cycle outputs a square wave clock signal with a 50% duty cycle and its inverted signal, with the frequency determined by the output voltage of the charge pump.
[0040] Performance simulation See Figure 4 By performing transient simulation of the voltage-controlled oscillator of this invention using Spectre software under Cadence, the working waveform curve of the output in continuous mode was obtained. It can be seen that since capacitors C1 and C2 are approximately charged with constant current, the voltage across capacitors C1 and C2 increases uniformly with time at a constant slope and then decreases uniformly with a constant slope. This is represented by two alternating straight line segments on the waveform curve, forming a typical triangular wave. It has the advantages of high waveform linearity, simplified hardware structure, continuously adjustable frequency, and wide synchronization range.
[0041] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions or improvements made by those skilled in the art within the spirit and principles of the present invention should be covered within the scope of protection of the present invention.
Claims
1. A single-amplifier multiplexed voltage-controlled oscillator capable of externally synchronizing a wide-range clock, characterized in that: Including bias current source I B Multiplexed single amplifier, oscillation charging capacitor, external synchronization input and RS trigger; the bias current source I B A multiplexed single amplifier is connected to provide bias current to each stage transistor in the multiplexed single amplifier, so that each transistor operates in a preset linear amplification region; the multiplexed single amplifier is connected to an oscillation charging capacitor, an external synchronization input, and an RS flip-flop, respectively, to receive the synchronization trigger signal output by the external synchronization input, amplify and shape it in combination with the charging and discharging signal of the oscillation charging capacitor, and output it to the RS flip-flop to control the triggering timing and oscillation frequency of the RS flip-flop; The oscillating charging capacitor is connected to an external synchronization input and an RS flip-flop, and is used to generate an oscillating timing signal through its own charging and discharging process, providing a frequency reference for the RS flip-flop.
2. The single-amplifier multiplexed voltage-controlled oscillator with externally synchronized wide-range clock according to claim 1, characterized in that: The multiplexed single amplifier includes NMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M1. 10 PMOS transistor M 11 PMOS transistor M 12 NMOS transistor M 13 NMOS transistor M 14 The source of the PMOS transistor M3, and the PMOS transistor M 10 The source of the PMOS transistor M 11 The source of the PMOS transistor M 12 The sources are all connected to the power supply voltage V. CC The gate of PMOS transistor M3 is connected to PMOS transistor M. 10 The gate of PMOS transistor M3 is connected to the drain of PMOS transistor M3, and the connection points between the gate and drain of PMOS transistor M3 are respectively connected to the drain of PMOS transistor M4. 11 The gate of the PMOS transistor M 12 The gate of PMOS transistor M3 is connected to the drain of NMOS transistor M2. 10 The drains of the transistors are connected to the sources of PMOS transistors M4, M5, and M6, respectively. 11 The drain of the NMOS transistor M is connected 13 The drain of the PMOS transistor M 12 The drain of the NMOS transistor M is connected 14 The drain of PMOS transistor M4 is connected to the drain of NMOS transistor M7 and NMOS transistor M8, respectively. 13 The gate of PMOS transistor M5 and the drain of PMOS transistor M8 are respectively connected to the drain of NMOS transistor M8 and NMOS transistor M9. 14 The gate of PMOS transistor M6 is connected to the drain of NMOS transistor M9, and the gate of PMOS transistor M6 is connected to a DC reference voltage V. REF The gate of NMOS transistor M2 is connected to the gate of NMOS transistor M1, and the gate of NMOS transistor M1 is connected to the drain of NMOS transistor M1. The connection point between the gate and drain of NMOS transistor M1 is connected to the gates of NMOS transistors M7, M8, and M9, respectively. The source of NMOS transistor M1 is connected to the sources of NMOS transistors M2, M7, M8, and M9, respectively. 13 The source of the NMOS transistor M 14 The source pole.
3. The single-amplifier multiplexed voltage-controlled oscillator with externally synchronized wide-range clock as described in claim 1 or 2, characterized in that: The bias current source I B The output terminal is connected to the drain of NMOS transistor M1.
4. The single-amplifier multiplexed voltage-controlled oscillator with an externally synchronized wide-range clock according to claim 1 or 2, characterized in that: The oscillation charging capacitor includes capacitor C1, capacitor C2, and NMOS transistor M. 15 NMOS transistor M 16 First voltage-controlled current source I V1 Second voltage-controlled current source I V2 One end of capacitor C1 is grounded and connected to NMOS transistor M. 15 The source of the capacitor is connected to the other end of the capacitor C1, which is connected to the NMOS transistor M. 15 The drain of the first voltage-controlled current source I V1 The output terminal, the gate of PMOS transistor M4, and one end of capacitor C1 connected to NMOS transistor M 15 The connection points between the sources of the NMOS transistor and capacitor C2 are respectively connected to one end of capacitor C2 and the other end of NMOS transistor M. 16 The source of NMOS transistor M1 and the source of NMOS transistor M2 are connected to the other end of capacitor C2 respectively. 16 The drain of the second voltage-controlled current source I V2 The output terminal and the gate of PMOS transistor M5.
5. The single-amplifier multiplexed voltage-controlled oscillator with an externally synchronized wide-range clock according to claim 4, characterized in that: The capacitance values of capacitors C1 and C2 are equal.
6. The single-amplifier multiplexed voltage-controlled oscillator with externally synchronized wide-range clock according to claim 4, characterized in that: The external synchronization input and RS flip-flop include a 2-input NOR gate (NOR2), a NOT gate (NOT), and an RS flip-flop; the output of the 2-input NOR gate (NOR2) is connected to the input of the NOT gate (NOT), the output of the NOT gate (NOT) is connected to the R terminal of the RS flip-flop, and the first input of the 2-input NOR gate (NOR2) is connected to the PMOS transistor M. 12 The drain of the NMOS transistor M 14 The connection point between the drains of the two inputs is used as the second input of the 2-input NOR2 gate as the synchronous clock input SYNC IN. The S-terminal of the RS flip-flop is connected to the PMOS transistor M. 11 The drain of the NMOS transistor M 13 The connection point between the drains of the RS flip-flop is connected to the QN terminal of the NMOS transistor M. 16 The gate of the RS flip-flop is used as the clock output CLKOUT of the voltage-controlled oscillator, and is connected to the NMOS transistor M. 15 The gate.
7. The single-amplifier multiplexed voltage-controlled oscillator with an externally synchronized wide-range clock according to claim 1, characterized in that: The voltage-controlled oscillator can perform external clock synchronization independently without the need for a phase-locked loop, and can achieve a wide synchronization range between half and twice the intrinsic oscillation frequency of the external synchronization clock input frequency.
8. The single-amplifier multiplexed voltage-controlled oscillator with an externally synchronized wide-range clock according to claim 1, characterized in that: The voltage-controlled oscillator can output a square wave clock signal with a duty cycle of 50%.
9. A wireless communication / radio frequency system comprising a single amplifier multiplexed voltage-controlled oscillator capable of externally synchronizing a wide-range clock as described in any of claims 1-8.