Improved on-off time slot protection circuit for GaN devices
By introducing a Zener diode reverse bias circuit into the time slot circuit of GaN devices, the gate voltage is used to control the drain time slot switch and perform clamping protection, which solves the problems of damage caused by lack of gate protection and increased static current, and improves the stability and reliability of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INNOGRATION SUZHOU
- Filing Date
- 2024-12-04
- Publication Date
- 2026-06-05
AI Technical Summary
In existing GaN device time-slot circuits, the gate lacks overvoltage protection design, which can easily lead to device damage. Furthermore, the increase in static current during power-on and power-off processes can cause the device temperature to rise, potentially resulting in thermal effects and burnout.
A Zener diode reverse bias circuit design is introduced, which uses the gate voltage of the GaN device to control the drain time slot switch, and uses the forward bias characteristic of the diode to clamp and protect the gate voltage, limiting the gate voltage to within 0.3V, and ensuring that the drain voltage is turned off.
This effectively avoids gate breakdown and thermal burnout caused by excessive static current, improving the stability and reliability of GaN devices and reducing damage risk and maintenance costs.
Smart Images
Figure CN122159805A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of power amplifier time slot circuit technology, and specifically relates to an improved power-on / off time slot protection circuit for GaN devices. Background Technology
[0002] In modern electronic communications, GaN RF power devices have been widely used in numerous applications due to their superior performance. Especially in communication base stations where high back-off efficiency is required, GaN Doherty power amplifiers are the preferred choice due to their excellent performance. However, GaN is a depletion-type device, requiring a negative voltage to be applied to its gate, and there are strict time interval requirements during power-on and power-off processes; otherwise, the power device will be damaged. During power-on, the gate voltage must be applied first, followed by the drain voltage; during power-off, the drain voltage should be cut off first, followed by the gate voltage. Although the time-slot power-on / off switching function of existing GaN devices can be largely guaranteed, other functions require further improvement.
[0003] First, in existing GaN device time-slot circuits, the GaN device gate lacks overvoltage protection. However, the maximum voltage a GaN device gate can typically withstand is approximately 1-2V (slight variations may occur between different semiconductor manufacturers). If the gate voltage is not properly protected, a positive high voltage can easily cause the gate to break down, leading to device damage. Second, in traditional time-slot circuits, the device gate is set to V... GS When the voltage is too high, the drain voltage does not turn off. This can easily lead to a high negative gate voltage in the GaN device due to improper operation when setting the gate voltage. As the gate voltage V increases... GS If the static current of the device is suddenly increased, it will increase rapidly. This rapid increase in current will cause the internal temperature of the device to rise, which will lead to a thermal effect and may eventually burn out the device. This is why sometimes devices burn out when static current is applied (especially high-power surface-mount devices with poor heat dissipation). Summary of the Invention
[0004] To address the aforementioned technical problems, the present invention aims to provide an improved power-on / off time-slot protection circuit for GaN devices. This circuit uses the gate voltage of the GaN device as the control level to control the opening or closing of the drain time-slot switch. A reverse-biased Zener diode circuit is introduced. When the negative voltage at the device gate exceeds the normal voltage, the drain voltage is turned off. Furthermore, the forward-biased characteristic of the diode is used to clamp and protect the device gate voltage, ensuring that the maximum gate voltage is limited to within 0.3V. This avoids gate breakdown and significantly improves the stability and reliability of the GaN device.
[0005] To address these problems in the prior art, the technical solution provided by this invention is as follows:
[0006] An improved power-on / off time slot protection circuit for a GaN device includes a gate protection circuit and a drain time slot power-on / off switching circuit. The gate protection circuit includes a supply voltage, a gate negative voltage generation circuit, and a diode. The positive terminal of the diode is connected to both the gate negative voltage generation circuit and the gate of the GaN device, while the other terminal is grounded. The gate negative voltage generation circuit is connected to the drain time slot power-on / off switching circuit through a Zener diode. The negative terminal of the Zener diode is connected to the supply voltage through a first pull-up resistor. The drain time slot power-on / off switching circuit is connected to the drain of the GaN device. The supply voltage is connected to both the gate negative voltage generation circuit and the drain time slot power-on / off switching circuit.
[0007] In a preferred embodiment, the drain time-slot power-on / off switching circuit includes a first transistor and a second transistor. The negative terminal of the Zener diode is connected to the base of the first transistor. The collector of the first transistor is connected to the supply voltage through a second pull-up resistor. The collector of the first transistor is connected to the base of the second transistor. The collector of the second transistor is connected to a fourth resistor. The emitters of the first and second transistors are grounded. The fourth resistor is connected to a third resistor. One end of the third resistor is connected to the gate of the MOSFET, and the other end is connected to the supply voltage. The source of the MOSFET is connected to the supply voltage, and the drain is connected to the drain of the GaN device.
[0008] In a preferred embodiment, the drain time-slot power-on / off switching circuit includes a first P-channel MOSFET and a second P-channel MOSFET. The cathode of the Zener diode is connected to the gate of the first P-channel MOSFET. The source of the first P-channel MOSFET is grounded. The drain of the first P-channel MOSFET is connected to the gate of the second P-channel MOSFET through a seventh resistor. The source of the second P-channel MOSFET is connected to the power supply voltage, and the drain is connected to the drain of the GaN device. The gate of the second P-channel MOSFET is also connected to a sixth resistor, which is connected to the power supply voltage.
[0009] In a preferred embodiment, the drain time-slot power-on / off switching circuit includes a PNP transistor and a P-channel MOSFET. The negative terminal of the Zener diode is connected to the base of the PNP transistor, the emitter of the PNP transistor is grounded, the collector of the PNP transistor is connected to the gate of the P-channel MOSFET through a seventh resistor, the source of the P-channel MOSFET is connected to the power supply voltage, and the drain is connected to the drain of the GaN device. The gate of the P-channel MOSFET is also connected to a sixth resistor, which is connected to the power supply voltage.
[0010] In a preferred embodiment, the diode is a germanium diode.
[0011] In a preferred embodiment, the reverse bias voltage of the Zener diode is V. D2 =-V GS -0.5V, V GS This represents the device gate voltage.
[0012] In a preferred embodiment, the resistance values of the first pull-up resistor and the second pull-up resistor are 50KΩ-100KΩ.
[0013] In a preferred embodiment, the resistance of the third resistor is 50KΩ and the resistance of the fourth resistor is 100KΩ.
[0014] Compared with existing solutions, the advantages of this invention are:
[0015] Based on the traditional timing protection circuit, this invention achieves the following key improvements: First, the gate voltage of the GaN device is used as the control level to control the opening or closing of the drain time slot switch, and a Zener diode reverse bias circuit design is introduced. When a high negative voltage appears at the device gate, higher than the device gate voltage V during normal operation... GS When the voltage is adjusted, the drain voltage of the device is turned off, which effectively avoids thermal burnout caused by excessive quiescent current and rising internal temperature, reducing the risk of device instability and burnout. Secondly, the forward bias characteristic of the diode is used to clamp the gate voltage, limiting the maximum gate voltage to below 0.3V, thus effectively preventing gate breakdown. These improvements significantly enhance the stability and reliability of GaN devices, avoid damage caused by misoperation when setting the gate voltage, reduce maintenance costs, and have significant practical application value. Attached Figure Description
[0016] The present invention will be further described below with reference to the accompanying drawings and embodiments:
[0017] Figure 1 The circuit diagram for power-on / off time-slot protection of existing GaN devices;
[0018] Figure 2 This is a circuit diagram of the improved power-on / off time-slot protection circuit for GaN devices according to the present invention;
[0019] Figure 3 This is an equivalent circuit diagram of an improved GaN device power-on / off time slot protection circuit according to an embodiment of the present invention;
[0020] Figure 4 This is a power-on voltage waveform diagram of the improved GaN device power-on / off time slot protection circuit of this invention;
[0021] Figure 5 This is a diagram of the power-down voltage waveform of the improved GaN device power-up and power-down time slot protection circuit of this invention.
[0022] Figure 6 This is an equivalent circuit diagram of the GaN device power-on / off time slot protection circuit according to the second embodiment of the present invention;
[0023] Figure 7 This is an equivalent circuit diagram of the GaN device power-on / off time slot protection circuit according to the third embodiment of the present invention. Detailed Implementation
[0024] The above-described solution will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. The implementation conditions used in the embodiments may be further adjusted according to the conditions of specific manufacturers, and the implementation conditions not specified are generally those in routine experiments.
[0025] Example:
[0026] like Figure 2 As shown, an improved power-on / off time slot protection circuit for a GaN device includes a gate protection circuit and a drain time slot power-on / off switching circuit. The gate protection circuit includes a power supply voltage, a gate negative voltage generation circuit, and a diode. The positive terminal of the diode is connected to both the gate negative voltage generation circuit and the gate G of the GaN device, while the other terminal is grounded. The gate negative voltage generation circuit is connected to the drain time slot power-on / off switching circuit through a Zener diode. The negative terminal of the Zener diode is connected to the power supply voltage through a first pull-up resistor. The drain time slot power-on / off switching circuit is connected to the drain D of the GaN device. The power supply voltage is connected to both the gate negative voltage generation circuit and the drain time slot power-on / off switching circuit.
[0027] Gate protection circuits are used to limit the gate voltage of GaN devices to prevent the gate from breaking down and burning out.
[0028] Specifically, such as Figure 3 As shown, the drain-stage time-slot power-on / off switching circuit mainly consists of the supply voltage VDD, Zener diode D2, transistors (Q1, Q2), resistors, and a MOSFET. The positive terminal of diode D1 is connected to the gate negative voltage generation circuit, the positive terminal of Zener diode D2, and the gate of the GaN device, while the other end is grounded. The positive terminal of Zener diode D2 is connected to the gate negative voltage generation circuit, and the negative terminal is connected to the supply voltage through pull-up resistor R1, and also to the base of transistor Q1. The collector of transistor Q1 is connected to the supply voltage through pull-up resistor R2, and also to the base of transistor Q2. The collector of transistor Q2 is connected to resistor R4. Resistor R4 is connected to resistor R3. The gate of MOSFET Q3 is connected to R3, its source is connected to the supply voltage, and its drain is connected to the drain of the GaN device. The other ends of R1, R2, and R3 are all connected to the supply voltage.
[0029] The gate negative voltage generation circuit is mainly used to generate a negative voltage, which is produced by a purely analog power conversion chip. The diode is a germanium diode.
[0030] The resistors R1 and R2 in the drain time-slot power-on / off switching circuit are used to limit the base current of the transistors (Q1, Q2) to prevent them from burning out. They are usually packaged in 0805 and the resistance value is usually 50K-100K.
[0031] Transistors (Q1, Q2) are NPN germanium transistors, mainly used as switches to output high or low levels.
[0032] The MOSFET Q3 is a P-channel enhancement-type MOSFET switch with low on-resistance and high load current, used as a power-on / off time-slot switch for GaN devices.
[0033] Resistors R3 and R4 are used as a voltage divider circuit for the gate of the P-channel MOSFET (Q3), serving as the gate voltage of the MOSFET. They are typically packaged in 0805 packages, with R3 usually being 50KΩ and R4 typically being 100KΩ.
[0034] The power supply voltage is mainly used to power the system, and can be 48V or 28V.
[0035] Figure 3 As shown, the drain time-slot power-on / off switching circuit mainly consists of a power supply voltage, a Zener diode, a transistor, a resistor, and a MOSFET. For ease of explanation, we first define the transistors (Q1, Q2) as NPN germanium transistors, the power supply voltage VDD as 48V, Q3 as a P-channel MOSFET, and the voltage across the Zener diode when it breaks down in reverse as V. D2 The voltage corresponding to the quiescent current when the device is operating normally is V. GS (Negative voltage). Selecting the appropriate Zener diode is crucial here, considering that the gate turn-on voltage of a GaN device is V. TH The voltage fluctuation is ±0.5V, so we can select the reverse bias voltage of the Zener diode as V. D2 =-V GS -0.5V, the specific implementation can be described in three states: after VDD is powered on, the gate negative voltage generation circuit immediately generates a negative voltage V. - .
[0036] State 1: When -8V ≤ V - ≤V GS At +0.5V, since VDD reaches point A1 through pull-up resistor R1, the Zener diode breaks down in reverse, and the voltage across the Zener diode is fixed at V. D2 According to the reverse bias characteristic of the Zener diode, the voltage at point A1 is V. A1 =V - +V D2Since the voltage is ≤0V, transistor Q1 is cut off. VDD reaches point A2 through pull-up resistor R2, meaning transistor Q2 is turned on. Point A3 is where the voltage is divided by the series resistors R3 and R4. In other words, when the gate voltage of the P-channel MOSFET is less than the source voltage, the Q3 switch is turned on. VDD is output from the source to the drain of the MOSFET, and then to the drain voltage of the GaN device. This process ensures the normal power-on sequence of the GaN device and realizes the normal operation of the GaN device. The power-on voltage waveform is as follows: Figure 4 As shown, the red line represents the drain voltage, and the blue line represents the gate voltage.
[0037] State 2: V GS +1.0V≤V - When VDD is ≤-0.5V, it reaches point A1 through pull-up resistor R1. At this time, the Zener diode breaks down in reverse, and the voltage across it is V. D2 According to the reverse bias characteristic of the Zener diode, the voltage drop at point A1 is V. A1 =V - +V D2 When V ≥ 0.5V, transistor Q1 conducts, and the 0V emitter voltage of Q1 is sent to the collector, forcibly pulling the voltage at point A2 low. At this time, transistor Q2 is cut off, and the voltage at point A3 is VDD, meaning the gate voltage of the P-channel MOSFET equals the source voltage. Q3 is cut off, and VDD is not output. We can conclude that when V... GS When the gate voltage is set too high, the device leakage voltage is shut off, which avoids errors when setting the gate voltage and sudden changes in V. GS Setting the value too high can cause excessive static current at the drain of the device, leading to thermal effects, unstable operation of the tube, and even burnout of the device.
[0038] State 3: After the power supply voltage VDD is applied, if the gate negative voltage generation circuit malfunctions and there is no negative voltage output, the positive terminal of the Zener diode is equivalent to a high-impedance state, and the Zener diode D2 is not reverse biased. At this time, the voltage at point A is still VDD, the transistor Q1 is turned on, and the 0V voltage at the emitter of Q1 is sent to the collector. The voltage at point A2 is forcibly pulled down, at this time the transistor Q2 is turned off, and the voltage at point A3 is VDD. That is, the gate voltage of the P-channel MOSFET is equal to the source voltage. Q3 is turned off, and VDD is not output, which effectively protects the GaN power device.
[0039] Figure 3 The gate protection circuit in the diagram mainly consists of a power supply voltage, a gate negative voltage generation circuit, and a diode. For ease of explanation, we will first define diode D1 as a germanium diode, and the power supply voltage VDD as 48V. Specifically, after VDD is powered on, the gate negative voltage generation circuit outputs a variable negative voltage V. - V -Connect one end of the diode to the positive terminal, and the other end of the diode to ground. When there is interference in the gate negative voltage generation circuit or improper human operation that results in a positive voltage (e.g., 1V), due to the conduction of diode D1, the voltage at point A4 is clamped to the diode's conduction voltage of 0.3V. That is, the GaN gate voltage is controlled within 0.3V, protecting the gate. Combined with the above state two, it can be seen that the device drain voltage is also turned off at this time, further protecting the gate of the GaN device.
[0040] VDD power-down process analysis: The gate negative voltage generation circuit is completed by VDD through the power conversion chip. If VDD is powered down first, but the gate negative voltage generation circuit has no output, the power-down voltage waveform is as follows. Figure 5 As shown, ensure that the power-down time slot is normal. The red line represents leakage voltage, and the blue line represents gate voltage.
[0041] In the second embodiment, such as Figure 6 As shown, in order to further simplify circuit design and reduce BOM costs, the following can be done: Figure 3 The two NPN transistors (Q1, Q2) in the circuit are replaced with a P-channel MOSFET.
[0042] Specifically, the drain time-slot power-on / off switching circuit includes a first P-channel MOSFET Q1 and a second P-channel MOSFET Q2. The cathode of the Zener diode D2 is connected to the gate Q1 of the first P-channel MOSFET. The source of the first P-channel MOSFET Q1 is grounded. The drain of the first P-channel MOSFET Q1 is connected to the gate of the second P-channel MOSFET Q2 through a seventh resistor R7. The source of the second P-channel MOSFET Q2 is connected to the supply voltage VDD, and the drain is connected to the drain of the GaN device. The gate of the second P-channel MOSFET Q2 is also connected to a sixth resistor R6, which is connected to the supply voltage.
[0043] For a specific implementation method, refer to the state analysis of the first embodiment.
[0044] In the third embodiment, such as Figure 7 As shown, to further simplify circuit design and reduce BOM costs, it is also possible to... Figure 3 The two NPN transistors (Q1, Q2) in the transistor can be replaced with a PNP transistor.
[0045] Specifically, the drain time-slot power-on / off switching circuit includes a PNP transistor Q1 and a P-channel MOSFET Q2. The cathode of the Zener diode D2 is connected to the base of the PNP transistor Q1, the emitter of the PNP transistor Q1 is grounded, the collector of the PNP transistor Q1 is connected to the gate of the P-channel MOSFET Q2 through the seventh resistor R7, the source of the P-channel MOSFET Q2 is connected to the supply voltage VDD, and the drain is connected to the drain of the GaN device. The gate of the P-channel MOSFET Q2 is also connected to the sixth resistor R6, which is connected to the supply voltage VDD.
[0046] For a specific implementation method, refer to the state analysis of the first embodiment.
[0047] It should be understood that the specific embodiments described above are merely illustrative or explanatory of the principles of the invention and do not constitute a limitation thereof. Therefore, any modifications, equivalent substitutions, improvements, etc., made without departing from the spirit and scope of the invention should be included within the protection scope of the invention. Furthermore, the appended claims are intended to cover all variations and modifications falling within the scope and boundaries of the appended claims, or equivalent forms of such scope and boundaries.
Claims
1. An improved power-on / off time-slot protection circuit for GaN devices, characterized in that, The device includes a gate protection circuit and a drain time-slot power-on / off switch circuit. The gate protection circuit includes a power supply voltage, a gate negative voltage generation circuit, and a diode. The positive terminal of the diode is connected to both the gate negative voltage generation circuit and the gate of the GaN device, while the other terminal is grounded. The gate negative voltage generation circuit is connected to the drain time-slot power-on / off switch circuit through a Zener diode. The negative terminal of the Zener diode is connected to the power supply voltage through a first pull-up resistor. The drain time-slot power-on / off switch circuit is connected to the drain of the GaN device. The power supply voltage is connected to both the gate negative voltage generation circuit and the drain time-slot power-on / off switch circuit.
2. The improved GaN device power-on / off time-slot protection circuit according to claim 1, characterized in that, The drain time-slot power-on / off switching circuit includes a first transistor and a second transistor. The negative terminal of the Zener diode is connected to the base of the first transistor. The collector of the first transistor is connected to the supply voltage through a second pull-up resistor. The collector of the first transistor is connected to the base of the second transistor. The collector of the second transistor is connected to a fourth resistor. The emitters of the first and second transistors are grounded. The fourth resistor is connected to a third resistor. One end of the third resistor is connected to the gate of the MOSFET, and the other end is connected to the supply voltage. The source of the MOSFET is connected to the supply voltage, and the drain is connected to the drain of the GaN device.
3. The improved GaN device power-on / off time-slot protection circuit according to claim 1, characterized in that, The drain time-slot power-on / off switching circuit includes a first P-channel MOSFET and a second P-channel MOSFET. The cathode of the Zener diode is connected to the gate of the first P-channel MOSFET. The source of the first P-channel MOSFET is grounded. The drain of the first P-channel MOSFET is connected to the gate of the second P-channel MOSFET through a seventh resistor. The source of the second P-channel MOSFET is connected to the power supply voltage, and the drain is connected to the drain of the GaN device. The gate of the second P-channel MOSFET is also connected to a sixth resistor, which is connected to the power supply voltage.
4. The improved GaN device power-on / off time slot protection circuit according to claim 1, characterized in that, The drain time-slot power-on / off switching circuit includes a PNP transistor and a P-channel MOSFET. The cathode of the Zener diode is connected to the base of the PNP transistor, the emitter of the PNP transistor is grounded, the collector of the PNP transistor is connected to the gate of the P-channel MOSFET through a seventh resistor, the source of the P-channel MOSFET is connected to the power supply voltage, and the drain is connected to the drain of the GaN device. The gate of the P-channel MOSFET is also connected to a sixth resistor, which is connected to the power supply voltage.
5. The improved GaN device power-on / off time-slot protection circuit according to claim 1, characterized in that, The diode is a germanium diode.
6. The improved GaN device power-on / off time-slot protection circuit according to claim 1, characterized in that, The reverse bias voltage of the Zener diode is , This represents the device gate voltage.
7. The improved GaN device power-on / off time slot protection circuit according to claim 2, characterized in that, The resistance values of the first pull-up resistor and the second pull-up resistor are 50KΩ-100KΩ.
8. The improved GaN device power-on / off time-slot protection circuit according to claim 2, characterized in that, The third resistor has a resistance of 50KΩ, and the fourth resistor has a resistance of 100KΩ.