Adaptive voltage equalization control system and method for series SiC MOSFETs

Abstract

The application belongs to the technical field of SiC MOSFET voltage-sharing control, and particularly relates to a self-adaptive voltage-sharing control system and method for series-connected SiC MOSFETs. The system comprises series-connected SiC MOSFET transistors Q1 and Q2, a voltage control current source and an absorption circuit connected in parallel to the gate drive circuit of the SiC MOSFET transistor Q2; a state detection circuit collects the drain-source voltage of the SiC MOSFET transistors Q1 and Q2, outputs a switching state pulse to an FPGA to adjust the drive pulse timing sequence of the SiC MOSFET transistor Q2, and simultaneously outputs a voltage signal to a current circuit to dynamically inject and extract the gate current of the SiC MOSFET transistor Q2; through the collection of the voltage signal, the FPGA adjusts the drive pulse timing sequence after the processing of the state detection circuit, and the current circuit adjusts the gate current of Q2, so that the self-adaptive voltage-sharing is achieved in a cycle.

Description

Technical Field

[0001] This invention belongs to the field of SiC MOSFET voltage equalization control technology, specifically relating to an adaptive voltage equalization control system and method for series-connected SiC MOSFETs. Background Technology

[0002] The core value of SiC MOSFET voltage equalization control technology lies in solving problems such as insufficient voltage withstand capability of single devices and excessive cost of high-voltage devices by connecting multiple devices in series, thereby overcoming the application limitations of SiC MOSFETs in different voltage levels and power scenarios. Currently, this technology has gradually expanded from traditional high-voltage power systems to multiple fields such as new energy, flexible DC transmission, industrial control, transportation, data centers and energy storage, and high-voltage industrial and special power supplies.

[0003] To achieve voltage equalization in SiC MOSFETs connected in series, various technical solutions have been proposed in the industry. Among them, the most similar existing technology is the active closed-loop feedback method based on drain-source voltage change rate detection. This solution obtains information on voltage imbalance between devices by connecting a sampling capacitor in parallel across the drain and source terminals of the SiC MOSFETs. Then, it achieves voltage equalization control throughout the entire cycle by adjusting the gate drive current. This sampling method does not introduce additional parasitic parameters into the main circuit, ensuring the circuit's operational stability to a certain extent. However, it still has significant drawbacks and cannot meet the high-performance requirements of practical applications. In existing solutions, adaptive voltage equalization control cannot be achieved. When faced with complex operating conditions such as device parameter dispersion, temperature drift, and load fluctuations, the voltage equalization accuracy is easily affected. Furthermore, its drain-source voltage change rate detection circuit has a complex structure, requires extremely high matching degree of circuit parameters, and is highly sensitive to parameters, resulting in high difficulty in circuit debugging. Thirdly, the complex detection circuit design increases the hardware cost and size of the system, which is not conducive to large-scale promotion and application.

[0004] Therefore, in view of the problems of lack of adaptive capability, complex detection circuit, parameter sensitivity and high cost of existing active closed-loop feedback voltage equalization schemes based on drain-source voltage change rate detection, there is an urgent need to propose a SiC MOSFET voltage equalization control technology with simpler structure, more precise control and stronger adaptability, so as to further improve the operational reliability and economy of high-voltage SiC MOSFET series systems and promote their widespread application in various fields. Summary of the Invention

[0005] This invention provides an adaptive voltage equalization control system and method for series SiC MOSFETs, which solves the technical problems of existing active closed-loop feedback methods based on drain-source voltage change rate detection that cannot achieve adaptive voltage equalization, and that the drain-source voltage change rate detection circuit is complex, parameter-sensitive, and costly.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: An adaptive voltage equalization control system for series-connected SiC MOSFETs includes SiC MOSFET transistors Q1 and Q2 connected in series. The source s1 of SiC MOSFET transistor Q1 is connected to the drain d2 of SiC MOSFET transistor Q2; the source s2 of SiC MOSFET transistor Q2 is directly grounded; the gate g1 of the drain d1 of SiC MOSFET transistor Q1 is connected to the gate drive pulse V through a gate drive resistor Rg1. P1 This forms the gate drive circuit for SiC MOSFET transistor Q1; the gate g2 of SiC MOSFET transistor Q2 is connected to the gate drive pulse V through the gate drive resistor Rg2. P2 The gate drive circuit of SiC MOSFET transistor Q2 is formed. A voltage-controlled current source circuit and a voltage-controlled current sink circuit are connected in parallel within the gate drive circuit of SiC MOSFET transistor Q2. The voltage V between the drain d1 and source s1 of SiC MOSFET transistor Q1 is... d1s1 And the voltage V between the drain d2 and source s2 of the SiC MOSFET transistor Q2. d2s2 The input is sent to the state detection circuit, which then determines the state based on the voltage V. d1s1 and voltage V d2s2 The switch status pulse signal is output to the FPGA, and the FPGA outputs a timing control signal to the gate drive pulse V based on the switch status pulse signal. P2 Timing adjustment signal adjusts gate drive pulse V P2 The state detection circuit determines the timing of the rising edge of the turn-on pulse and the falling edge of the turn-off pulse based on the voltage V. d1s1 and voltage V d2s2 The output voltages v1 and v2 are fed to the voltage-controlled current source circuit and the voltage-controlled current absorption circuit. The voltage-controlled current source circuit and the voltage-controlled current absorption circuit dynamically adjust the switching process of the SiC MOSFET transistor Q2 by injecting and extracting the gate current of the SiC MOSFET transistor Q2 according to the output voltages v1 and v2.

[0007] A Miller capacitor C is connected between the gate g1 and the drain d1 of the SiC MOSFET transistor Q1. g1d1 The gate g1 and source s1 of the SiC MOSFET transistor Q1 are connected by a gate-source parasitic capacitance C. g1s1 The drain-source parasitic capacitance C is connected between the drain d1 and source s1 of the SiC MOSFET transistor Q1. d1s1A Miller capacitance C is connected between the gate g2 and the drain d2 of the SiC MOSFET transistor Q2. g2d2 The gate g2 and source s2 of the SiC MOSFET transistor Q2 are connected by a gate-source parasitic capacitance C. g2s2 The drain-source parasitic capacitance C is connected between the drain d2 and source s2 of the SiC MOSFET transistor Q2. d2s2 .

[0008] The drain d1 of the SiC MOSFET transistor Q1 is connected to the anode of the diode D. The cathode of the diode D is connected to one end of the RL load, and the other end of the RL load is connected to the positive terminal of the DC bus voltage VDC. The inductor L and the resistor R are connected in series to form the RL load. The positive terminal of the DC bus voltage VDC is also connected to one end of the DC bus capacitor CDC. The other end of the DC bus capacitor CDC is grounded. The DC bus voltage VDC and the DC bus capacitor CDC are connected in parallel to provide a stable DC bus voltage.

[0009] The gate drive circuit of the SiC MOSFET transistor Q1 is specifically as follows: the gate g1 of the SiC MOSFET transistor Q1 is connected to one end of the gate drive resistor Rg1, the other end of the gate drive resistor Rg1 is connected to the gate drive signal terminal of the gate drive pulse VP1, and the source reference terminal of the gate drive pulse VP1 is connected to the source s1 of the SiC MOSFET transistor Q1, thus forming the gate drive circuit of the SiC MOSFET transistor Q1.

[0010] The gate drive circuit of the SiC MOSFET transistor Q2 is specifically as follows: the gate g2 of the SiC MOSFET transistor Q2 is connected to one end of the gate drive resistor Rg2, and the other end of the gate drive resistor Rg2 is connected to the gate drive signal terminal of the gate drive pulse VP2. At the same time, the source reference terminal of the gate drive pulse VP2 is connected to the source s2 of the SiC MOSFET transistor Q2, thus forming the gate drive circuit of the SiC MOSFET transistor Q2.

[0011] The state detection circuit integrates a voltage conversion rate detection circuit. Specifically, the voltage between the drain d1 and source s1 of the SiC MOSFET transistor Q1 is connected to the high-side RC micro-branch. The output of the high-side RC micro-branch is connected to one end of the primary winding of the 1:1 pulse transformer, and the other end of the primary winding of the pulse transformer is connected to the gate g2 of the SiC MOSFET transistor Q2. The voltage between the drain d2 and source s2 of the SiC MOSFET transistor Q2 is connected to the low-side RC micro-branch. The output of the low-side RC micro-branch is connected to one end of the primary winding of the 1:1 pulse transformer, and the other end of the primary winding of the pulse transformer is connected to the gate g2 of the SiC MOSFET transistor Q2.

[0012] The state detection circuit also integrates on and off state detection circuits. Specifically, the on and off state detection circuits further integrate the voltage slew rate detection circuit. The output of the voltage slew rate detection circuit is further integrated in the RC integration branch of the on and off state detection circuit to reconstruct the voltage slew rate detection circuit relative to the original drain-source voltage V. d1s1 and V d2s2 A scaled voltage signal with an amplitude proportional relationship; the scaled voltage signal is connected to the signal input terminal of a comparator, and the reference input terminal of the comparator is connected to a preset reference voltage V. ref By comparing voltages, a switching status pulse signal is output.

[0013] An adaptive voltage equalization control method for series-connected SiC MOSFETs includes the following steps: The state detection circuit acquires signals in real time to obtain the voltage V between the drain d1 and source s1 of the SiC MOSFET transistor Q1. d1s1 And the voltage V between the drain d2 and source s2 of the SiC MOSFET transistor Q2. d2s2 ; The state detection circuit is based on voltage V d1s1 and voltage V d2s2 The output switch status pulse signal is transmitted to the FPGA, and the output voltages v1 and v2 are transmitted to the voltage-controlled current source circuit and the voltage-controlled current absorption circuit. The FPGA receives the switch status pulse signal from the status detection circuit, processes it logically, and then outputs a timing control signal to the gate drive pulse V. P2 The timing control terminal controls the timing of the gate drive pulse VP2, setting the rising edge of the turn-on pulse or the falling edge of the turn-off pulse. Based on the rising edge of the turn-on pulse, the voltage-controlled current source circuit and the voltage-controlled current sink circuit inject current Isource into the gate g2 of the SiC MOSFET transistor Q2 according to the voltages v1 and v2 output by the state detection circuit, thereby accelerating the rise rate of the gate-source voltage of the SiC MOSFET transistor Q2. Based on the falling edge of the turn-off pulse, the voltage-controlled current sink circuit extracts current Isink from the gate g2 of the SiC MOSFET transistor Q2, thereby accelerating the fall rate of the gate-source voltage of the SiC MOSFET transistor Q2.

[0014] The FPGA receives the switch status pulse signal output by the state detection circuit, processes it logically, and then outputs a timing control signal to the gate drive pulse V. P2 The timing control terminal adjusts the timing of the gate drive pulse VP2. Specifically, the output of the state detection circuit is connected to the signal acquisition port of the FPGA, and the control signal output port of the FPGA is connected to the gate drive pulse V of the SiC MOSFET transistor Q2. p2 The timing control terminal, gate drive pulse V p2 The drive signal is interrupted by R g2 The gate g2 of the SiC MOSFET transistor Q2 is connected to the gate g2. The FPGA receives the on and off state pulse signals output by the state detection circuit. The FPGA integrates a pulse rising edge capture unit and a processing unit. The pulse rising edge capture unit records the rising edge time of each pulse according to the on and off state pulse signals. The processing unit reads the rising edge time of each pulse through the internal bus and calculates the time difference between the rising edge trigger times. The FPGA adjusts the gate drive pulse V according to the time difference between the rising edge trigger times. P2 The gate drive pulse VP2 signal, after timing adjustment, is transmitted to the drain gate g2 of the SiC MOSFET transistor Q2 at the falling edge of the turn-off pulse and the rising edge of the turn-on pulse, so as to delay or advance the turn-on.

[0015] The pulse rising edge capture unit records the rising edge times t(ST1_off), t(ST2_off), t(ST1_on), and t(ST2_on) of each pulse based on the on and off state pulse signals. The arithmetic unit reads the rising edge times of each pulse through the internal bus and calculates the time differences Δt between the rising edge trigger times of ST1_off and ST2_off, and ST1_on and ST2_on, respectively. off and Δt on , Δt off and Δt on The calculation formula is as follows:

[0016] Where t represents the rising edge trigger time of pulse ST.

[0017] Compared with the prior art, the present invention has the following beneficial effects: This invention proposes an adaptive voltage equalization control system for series-connected SiC MOSFETs. Through the synergistic design of the series structure and targeted gate drive regulation, it achieves adaptive voltage equalization of the series devices, effectively overcoming the voltage withstand limitations of single devices and ensuring the safe and stable operation of the devices in high-voltage scenarios. The state detection circuit adopts an integrated design, combining voltage conversion rate detection and conduction / turn-off detection functions into one, eliminating the need for additional independent detection modules. This significantly simplifies the circuit structure, reduces the difficulty of circuit debugging, and reduces the stringent dependence on parameter matching, thereby improving the stability and anti-interference capability of circuit operation. The collaborative working mode of FPGA timing control, voltage control current source, and current absorption circuit enables precise dynamic adjustment of the switching process. Timing control can set a stable starting reference for the switching process, ensuring the consistency of switching timing. The dynamic injection and extraction of gate current can optimize the switching speed in real time, keeping the switching characteristics of the series devices synchronized. This ensures voltage equalization accuracy from both the starting time and process speed aspects, effectively avoiding the problem of uneven voltage distribution during switching transients. The entire circuit system design, including a stable DC power supply circuit and an adaptable load connection method, further enhances the system's operational stability under different operating conditions and strengthens its environmental adaptability. Simultaneously, the simplified circuit structure and efficient collaborative control logic help reduce the system's hardware costs and operating energy consumption, improving overall economic efficiency and providing favorable conditions for its widespread application in various high-voltage power scenarios. Specifically, the pulse capture and arithmetic unit design within the FPGA can quickly and accurately process status detection signals and calculate relevant time differences, ensuring the timeliness and accuracy of timing adjustments, improving the system's response speed, and enabling voltage equalization control to follow changes in operating conditions in real time. This further strengthens the system's adaptive capability, ensuring that good voltage equalization performance is maintained even under complex conditions such as device parameter fluctuations or load changes. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of an adaptive voltage equalization control system circuit structure of a series SiC MOSFET in an embodiment of the present invention; Figure 2 Top view of the upper module; Figure 3 This is a schematic diagram of the voltage conversion efficiency detection circuit in an embodiment of the present invention; Figure 4 This is a schematic diagram of the voltage-controlled current source circuit structure in an embodiment of the present invention; Figure 5This is a schematic diagram of the voltage-controlled current absorption circuit structure in an embodiment of the present invention; Figure 6 This is a schematic diagram of the conduction and off state detection circuit structure in an embodiment of the present invention; Figure 7 This is a schematic diagram of the FPAG timing control process in an embodiment of the present invention. Detailed Implementation

[0019] To further understand the content of this invention, the invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments are merely illustrative and not limiting of the invention.

[0020] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0021] like Figure 1 The diagram shown is an adaptive voltage equalization control system circuit for a series SiC MOSFET proposed in an embodiment of the present invention, employing a resistor-inductor (... RL A dual-pulse test circuit (DPT) for the load is used to replace the traditional purely inductive load. In the diagram, Q1 and Q2 are two SiC MOSFET transistors connected in series, where... D This indicates a freewheeling diode. The circuit includes a Miller capacitor (the upper component is C). g1d1 The next device is C g2d2 Gate-source parasitic capacitance (C) g1s1 C g2s2 ) and drain-source parasitic capacitance (C d1s1 C d2s2 Rg1 and Rg2 represent the gate drive resistors, while V p1 and V p2 Indicates the gate drive pulse. V DC C represents the DC bus voltage. DC This represents the DC bus capacitor. ST1_off and ST2_off represent the turn-off transient pulses of the high-side and low-side devices detected by the state detection circuit, respectively; while ST1_on and ST2_on represent the turn-on transient pulses of the high-side and low-side devices detected by the state detection circuit, respectively. The terminal names are: drain (d1, d2), gate (g1, g2), and source (s1, s2).

[0022] An inductor L and a resistor R are connected in series to form an RL load. One end of the RL load is connected to the positive terminal of the DC bus voltage VDC, and the other end is connected to the cathode of a diode D. The positive terminal of the DC bus voltage VDC is also connected to one end of a DC bus capacitor CDC, and the other end of the DC bus capacitor CDC is grounded. The DC bus voltage VDC and the DC bus capacitor CDC are connected in parallel to provide a stable DC bus voltage. The anode of the diode D is connected to the drain d1 of the SiC MOSFET transistor Q1. SiC MOSFET transistors Q1 and Q2 are connected in series to form a series SiC MOSFET branch. The source s1 of SiC MOSFET transistor Q1 is connected to the drain d2 of SiC MOSFET transistor Q2; the source s2 of SiC MOSFET transistor Q2 is directly grounded.

[0023] A Miller capacitance C is connected between the gate g1 and the drain d1 of the SiC MOSFET transistor Q1. g1d1 The gate g1 and source s1 of the SiC MOSFET transistor Q1 are connected by a gate-source parasitic capacitance C. g1s1 The drain-source parasitic capacitance C is connected between the drain d1 and source s1 of the SiC MOSFET transistor Q1. d1s1 A Miller capacitance C is connected between the gate g2 and the drain d2 of the SiC MOSFET transistor Q2. g2d2 The gate g2 and source s2 of the SiC MOSFET transistor Q2 are connected by a gate-source parasitic capacitance C. g2s2 The drain-source parasitic capacitance C is connected between the drain d2 and source s2 of the SiC MOSFET transistor Q2. d2s2 .

[0024] The gate g1 of the SiC MOSFET transistor Q1 is connected to one end of the gate drive resistor Rg1, and the other end of the gate drive resistor Rg1 is connected to the gate drive pulse V. P1 The gate drive signal terminal, gate drive pulse V P1 The source reference terminal of the SiC MOSFET transistor Q1 is connected to the source s1 of the SiC MOSFET transistor Q1, forming the gate drive circuit of the SiC MOSFET transistor Q1. The gate g2 of the SiC MOSFET transistor Q2 is connected to one end of the gate drive resistor Rg2, and the other end of the gate drive resistor Rg2 is connected to the gate drive pulse V. P2 The gate drive signal terminal, and simultaneously, the gate drive pulse V P2 The source reference terminal is connected to the source s2 of the SiC MOSFET transistor Q2, forming the gate drive circuit of the SiC MOSFET transistor Q2.

[0025] The voltage V between the drain d1 and source s1 of the SiC MOSFET transistor Q1 d1s1 And the voltage V between the drain d2 and source s2 of the SiC MOSFET transistor Q2. d2s2 The input signal is fed into the state detection circuit, which acquires the voltage conversion rate and outputs switching state pulse signals based on the input signal. The state detection circuit integrates a voltage conversion rate detection circuit and on / off state detection circuits.

[0026] In this embodiment, the voltage conversion rate monitoring circuit uses an RC micro-branch for differentiation between the drain and source terminals to obtain the voltage conversion rate between the high-voltage and low-voltage side switches; the RC micro-branch is connected to capacitor C. f and resistance R f The configuration is as follows: To accurately sample the voltage slew rate, the resistance and capacitance values ​​in the RC branches of both switches are identical. Since the two switches are connected in series, the voltage across the high-side switch being directly sampled has a high common-mode voltage and cannot be directly used for comparison. Therefore, a pulse transformer is used in a subsequent stage to convert the R... f The pulse voltages at both ends are isolated to a safe voltage referenced to g2. To ensure symmetry between the voltage conversion rate sampling circuits of the high-voltage and low-voltage side switches, a pulse transformer is also used in the low-voltage side circuit to convert R... f The pulse voltage signals at both ends are isolated to the safe voltage of reference g2. Specifically, as follows: Figure 3 As shown, the voltage between the drain d1 and source s1 of SiC MOSFET transistor Q1 is connected to the high-side RC micro-branch. The output of the high-side RC micro-branch is connected to one end of the primary winding of the 1:1 pulse transformer, and the other end of the primary winding of the pulse transformer is connected to the gate g2 of SiC MOSFET transistor Q2. The voltage between the drain d2 and source s2 of SiC MOSFET transistor Q2 is connected to the low-side RC micro-branch. The output of the low-side RC micro-branch is connected to one end of the primary winding of the 1:1 pulse transformer, and the other end of the primary winding of the pulse transformer is connected to the gate g2 of SiC MOSFET transistor Q2. The voltage conversion rate monitoring circuit uses capacitor C... f The response characteristics to the rate of change of voltage (dv / dt), combined with the resistance R fThe detection circuit, which uses a 1:1 transformer for signal conversion, differentiates the voltage between the drain and source of SiC MOSFET transistors Q1 and Q2 via an RC micro-branch, extracting the pulse signal corresponding to its voltage conversion rate. The pulse transformer then isolates the high common-mode differential signal into a safe voltage signal with SiC MOSFET transistor Q2 gate g2 as a reference, which is then converted into output voltages v1 and v2, respectively.

[0027] In this embodiment, the on and off state detection circuit is as follows: Figure 6 As shown, further integration is performed based on the voltage slew rate detection circuit, which reconstructs Vds (drain-source voltage) to some extent. However, there is a certain amplitude proportionality relationship with the actual Vds, and it can also reflect the voltage change corresponding to transients. It can be considered that the scaling factor of Vds is proportional to the safe input voltage range of the comparator. The comparator compares with the reference voltage Vref, thus outputting a high level during the turn-off process. The start time of the high level indicates the moment when Vds begins to change. The main purpose of the current sink and current source circuit is to change the switching rate, that is, to adjust the slew rate of Vds of the SiC MOSFET. By dynamically adjusting the turn-on and turn-off delays of the low-side switch in each switching cycle, voltage balance between the two switches is achieved, completely eliminating the remaining voltage imbalance. Specifically, the output voltages v1 and v2 output by the voltage slew rate detection circuit are respectively connected to the corresponding RC integration branches for further integration processing to reconstruct the voltage slew rate relative to the original drain-source voltage Vds. d1s1 and V d2s2 A scaled voltage signal with a proportional amplitude relationship is then input to the signal input terminal of a comparator, and a preset reference voltage V is connected to the reference input terminal of the comparator. ref By voltage comparison: when the scaled voltage signal reaches the preset reference voltage V ref When the comparator outputs a high-level pulse, the comparator outputs ST1_off and ST1_on on the high-side, and ST2_off and ST2_on on the low-side. ST1_off, ST2_off, ST1_on, and ST2_on represent the on and off states of SiC MOSFET transistors Q1 and Q2, respectively. Specifically, ST1_off represents the off-state pulse signal of SiC MOSFET transistor Q1, ST2_off represents the off-state pulse signal of SiC MOSFET transistor Q2, ST1_on represents the on-state pulse signal of SiC MOSFET transistor Q1, and ST2_on represents the on-state pulse signal of SiC MOSFET transistor Q2.

[0028] The output of the state detection circuit is connected to the signal acquisition port of the FPGA, and the control signal output port of the FPGA is connected to the gate drive pulse V of the SiC MOSFET transistor Q2. p2 The timing control terminal, gate drive pulse V p2 The drive signal is interrupted by R g2 It is connected to the gate g2 of the SiC MOSFET transistor Q2. Specifically, as shown... Figure 7 As shown, the FPGA receives the on and off state pulse signals (ST1_off, ST2_off, ST1_on, and ST2_on) output by the state detection circuit. The FPGA integrates a pulse rising edge capture unit and a processing unit. The pulse rising edge capture unit records the rising edge times t(ST1_off), t(ST2_off), t(ST1_on), and t(ST2_on) of each pulse based on the on and off state pulse signals. The processing unit reads the rising edge times of each pulse through the internal bus and calculates the time differences Δt between the rising edge trigger times of ST1_off and ST2_off, and ST1_on and ST2_on, respectively. off and Δt on , Δt off and Δt on The calculation formula is as follows:

[0029] Where t represents the rising edge trigger time of pulse ST. The FPGA determines this based on Δt. off The calculation results are used to output a timing adjustment signal to the gate drive pulse V. P2 The timing control terminal is used to adjust the gate drive pulse V. P2 At the falling edge of the turn-off pulse, the gate drive pulse V after timing adjustment... P2 The signal is transmitted to the drain-gate g2 of the SiC MOSFET transistor Q2, where it is either delayed or turned off prematurely. The FPGA determines the turn-off time based on Δt. on The calculation results are used to output a timing adjustment signal to the gate drive pulse V. P2 The timing control terminal is used to adjust the gate drive pulse V. P2 The rising edge of the turn-on pulse; the gate drive pulse V after timing adjustment. P2 The signal is transmitted to the drain gate g2 of the SiC MOSFET transistor Q2 for delayed or early turn-on. After a single control operation is completed based on the above steps, the signal flow returns to the Start node, waiting for the input of the switching state pulse signal for the next switching process, and then the above steps continue to cycle.

[0030] In this embodiment, a voltage-controlled current source circuit and a voltage-controlled current absorption circuit are connected in parallel on the gate drive circuit of the SiC MOSFET transistor Q2. The voltage-controlled current source circuit is as follows: Figure 4 As shown, the voltage-controlled current absorption circuit is as follows: Figure 5 As shown. Specifically, the output of the voltage-controlled current source circuit is connected to the gate g2 of the SiC MOSFET transistor Q2, and the input of the voltage-controlled current absorption circuit is connected to the gate g2 of the SiC MOSFET transistor Q2. The power supply for the voltage-controlled current source circuit is connected to the supply voltage V. DD Internally, it consists of transistors T1, T2, and T3 forming a current mirror structure. The collector of transistor T3 is connected in series with resistor R1 and then fed into the output voltage v1. The output terminal of the voltage-controlled current source circuit is connected to the gate g2 of the SiC MOSFET transistor Q2, and simultaneously receives the output voltage v2. The power supply terminal of the voltage-controlled current absorption circuit is connected to the supply voltage V. GG Internally, it consists of transistors T4, T5 and T6 forming a current mirror structure. The collector of transistor T6 is connected in series with resistor R2 and then connected to the output voltage v1. The input terminal of the voltage-controlled current absorption circuit is connected to the gate g2 of SiC MOSFET transistor Q2.

[0031] Output voltages v1 and v2 are input to a voltage-controlled current source circuit composed of current mirrors. This circuit generates a current Isource, which is injected into the gate g2 of the SiC MOSFET transistor Q2, replenishing the charging current of the gate and accelerating the rise rate of its gate-source voltage. A voltage-controlled current sink circuit composed of current mirrors extracts a current Isink from the gate g2 of the SiC MOSFET transistor Q2 based on the amplitude of the output voltage v1, accelerating the fall rate of the gate-source voltage of the SiC MOSFET transistor Q2. Simultaneously, the FPGA calculates the time difference Δt. off and Δt on Output timing adjustment signal to gate drive pulse V P2 The timing control terminal adjusts the gate drive pulse V using the timing adjustment signal. P2 The rising edge of the turn-on pulse and the falling edge of the turn-off pulse are used to set the starting reference for the switching process of the SiC MOSFET transistor Q2; the injection and extraction of the gate current of the SiC MOSFET transistor Q2 are achieved through a voltage-controlled current source circuit and a voltage-controlled current sink circuit, and the gate drive pulse V is controlled by the FPGA. P2 The timing adjustment and coordinated control of the two processes jointly realize the dynamic regulation of the Q2 switching process of the SiC MOSFET transistor.

[0032] After dynamically adjusting the switching process of the SiC MOSFET transistor Q2, the voltage waveform change in this embodiment is as follows: Figure 2 As shown, Figure 2 As shown in (a), the solid red line represents the original gate drive pulse VP1 signal of SiC MOSFET transistor Q1, and the dashed red line represents the gate drive pulse V'P1 signal after timing adjustment of the original gate drive pulse VP1 signal of SiC MOSFET transistor Q1; the solid blue line represents the original gate drive pulse VP2 signal of SiC MOSFET transistor Q2, and the dashed blue line represents the gate drive pulse V'P2 signal after timing adjustment of the original gate drive pulse VP2 signal of SiC MOSFET transistor Q2. Figure 2 As shown in (b), the gate-source voltage waveforms of SiC MOSFET transistors Q1 and Q2 during the turn-off process are as follows: the red solid line corresponds to the original gate-source voltage Vgs1 of SiC MOSFET transistor Q1, and the blue solid line corresponds to the original gate-source voltage Vgs2 of SiC MOSFET transistor Q2; the red dashed line corresponds to the gate-source voltage V'gs1 of SiC MOSFET transistor Q1 after adjustment, and the blue dashed line corresponds to the gate-source voltage V'gs2 of SiC MOSFET transistor Q2 after adjustment; the waveform changes reflect the gradual decrease of the gate-source voltage from a high level to the threshold voltage during the turn-off process. Figure 2 As shown in (c), the drain-source voltage changes of SiC MOSFET transistors Q1 and Q2 during the turn-off process are illustrated. The red solid line corresponds to the original drain-source voltage Vds1 of SiC MOSFET transistor Q1, and the blue solid line corresponds to the original drain-source voltage Vds2 of SiC MOSFET transistor Q2. The red dashed line corresponds to the drain-source voltage V'ds1 of SiC MOSFET transistor Q1 after adjustment, and the blue dashed line corresponds to the drain-source voltage V'ds2 of SiC MOSFET transistor Q2 after adjustment. The waveform changes demonstrate the gradual increase of the drain-source voltage from the on-state voltage drop to the bus voltage during the turn-off process. Figure 2As shown in (d), the transient state pulse signal output by the state detection circuit during the turn-off process changes. The blue solid line corresponds to the original turn-off transient pulse signal ST1_off of SiC MOSFET transistor Q1, and the green solid line corresponds to the original turn-off transient pulse signal ST2_off of SiC MOSFET transistor Q2. The blue dashed line corresponds to the adjusted turn-off transient pulse signal ST'1_off of SiC MOSFET transistor Q1, and the green dashed line corresponds to the adjusted turn-off transient pulse signal ST'2_off of SiC MOSFET transistor Q2. Δt in the waveform represents the rise time difference between the turn-off pulses of SiC MOSFET transistor Q1 and SiC MOSFET transistor Q2. The time nodes in the figure extend from t0 to t4, including t'4. These nodes correspond to different stages of the turn-off process, visually demonstrating the effect of the control on the pulse timing correction.

[0033] In this embodiment, using SiC MOSFET transistor Q1 as a reference device, continuous pulses with a constant duty cycle and period are applied to SiC MOSFET transistor Q1. Furthermore, the turn-on and turn-off pulses of SiC MOSFET transistor Q2 are finely adjusted based on the comparator detection signal.

[0034] During the current switching cycle, the voltage transition rate detection circuit detects ST1_off, ST1_on, ST2_off, and ST2_on, and then inputs these signals to the FPGA. The FPGA identifies these four pulses and distinguishes the rising edge trigger times. It calculates the time difference Δt between the rising edge trigger times of ST1_off and ST2_off, and ST1_on and ST2_on, respectively. off and Δt on .

[0035] If Δt off If the value is greater than 0, the controlled device SiC MOSFET transistor Q2 will be delayed by Δt in the next switching cycle. off Close; otherwise, it will be closed via -Δt. off Close early. If Δt on If the value is greater than 0, the controlled device SiC MOSFET transistor Q2 will be delayed by Δt in the next switching cycle. off It will conduct; otherwise, it will conduct through -Δt. off The process is initiated early. Simultaneously, in the next cycle, the pulses from all four channels will continue to be detected, and the delay time required for the next cycle will be calculated; this process is repeated.

[0036] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be appropriately combined to form other embodiments that can be understood by those skilled in the art. The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. An adaptive voltage equalization control system for series-connected SiC MOSFETs, characterized in that, This includes SiC MOSFET transistors Q1 and Q2 connected in series. The source s1 of SiC MOSFET transistor Q1 is connected to the drain d2 of SiC MOSFET transistor Q2; the source s2 of SiC MOSFET transistor Q2 is directly grounded; the gate g1 of the drain d1 of SiC MOSFET transistor Q1 is connected to the gate drive pulse V through the gate drive resistor Rg1. P1 This forms the gate drive circuit for SiC MOSFET transistor Q1; the gate g2 of SiC MOSFET transistor Q2 is connected to the gate drive pulse V through the gate drive resistor Rg2. P2 The gate drive circuit of SiC MOSFET transistor Q2 is formed. A voltage-controlled current source circuit and a voltage-controlled current sink circuit are connected in parallel within the gate drive circuit of SiC MOSFET transistor Q2. The voltage V between the drain d1 and source s1 of SiC MOSFET transistor Q1 is... d1s1 And the voltage V between the drain d2 and source s2 of the SiC MOSFET transistor Q2. d2s2 The input is sent to the state detection circuit, which then determines the state based on the voltage V. d1s1 and voltage V d2s2 The switch status pulse signal is output to the FPGA, and the FPGA outputs a timing control signal to the gate drive pulse V based on the switch status pulse signal. P2 Timing adjustment signal adjusts gate drive pulse V P2 The state detection circuit determines the timing of the rising edge of the turn-on pulse and the falling edge of the turn-off pulse based on the voltage V. d1s1 and voltage V d2s2 The output voltages v1 and v2 are fed to the voltage-controlled current source circuit and the voltage-controlled current absorption circuit. The voltage-controlled current source circuit and the voltage-controlled current absorption circuit dynamically adjust the switching process of the SiC MOSFET transistor Q2 by injecting and extracting the gate current of the SiC MOSFET transistor Q2 according to the output voltages v1 and v2.

2. The adaptive voltage equalization control system for series-connected SiC MOSFETs according to claim 1, characterized in that, A Miller capacitor C is connected between the gate g1 and the drain d1 of the SiC MOSFET transistor Q1. g1d1 The gate g1 and source s1 of the SiC MOSFET transistor Q1 are connected by a gate-source parasitic capacitance C. g1s1 The drain-source parasitic capacitance C is connected between the drain d1 and source s1 of the SiC MOSFET transistor Q1. d1s1 A Miller capacitance C is connected between the gate g2 and the drain d2 of the SiC MOSFET transistor Q2. g2d2 The gate g2 and source s2 of the SiC MOSFET transistor Q2 are connected by a gate-source parasitic capacitance C. g2s2 The drain-source parasitic capacitance C is connected between the drain d2 and source s2 of the SiC MOSFET transistor Q2. d2s2 .

3. The adaptive voltage equalization control system for series-connected SiC MOSFETs according to claim 2, characterized in that, The drain d1 of the SiC MOSFET transistor Q1 is connected to the anode of the diode D, the cathode of the diode D is connected to one end of the RL load, the other end of the RL load is connected to the positive terminal of the DC bus voltage VDC, and the inductor L and the resistor R are connected in series to form the RL load; the positive terminal of the DC bus voltage VDC is also connected to one end of the DC bus capacitor CDC, the other end of the DC bus capacitor CDC is grounded, and the DC bus voltage VDC and the DC bus capacitor CDC are connected in parallel to provide a stable DC bus voltage.

4. The adaptive voltage equalization control system for series-connected SiC MOSFETs according to claim 1, characterized in that, The gate drive circuit of the SiC MOSFET transistor Q1 is specifically as follows: the gate g1 of the SiC MOSFET transistor Q1 is connected to one end of the gate drive resistor Rg1, the other end of the gate drive resistor Rg1 is connected to the gate drive signal terminal of the gate drive pulse VP1, and the source reference terminal of the gate drive pulse VP1 is connected to the source s1 of the SiC MOSFET transistor Q1, thus forming the gate drive circuit of the SiC MOSFET transistor Q1.

5. The adaptive voltage equalization control system for series-connected SiC MOSFETs according to claim 1, characterized in that, The gate drive circuit of the SiC MOSFET transistor Q2 is specifically as follows: the gate g2 of the SiC MOSFET transistor Q2 is connected to one end of the gate drive resistor Rg2, and the other end of the gate drive resistor Rg2 is connected to the gate drive signal terminal of the gate drive pulse VP2. At the same time, the source reference terminal of the gate drive pulse VP2 is connected to the source s2 of the SiC MOSFET transistor Q2, thus forming the gate drive circuit of the SiC MOSFET transistor Q2.

6. The adaptive voltage equalization control system for series-connected SiC MOSFETs according to claim 1, characterized in that, The state detection circuit integrates a voltage conversion rate detection circuit. Specifically, the voltage between the drain d1 and source s1 of the SiC MOSFET transistor Q1 is connected to the high-side RC micro-branch. The output of the high-side RC micro-branch is connected to one end of the primary winding of the 1:1 pulse transformer, and the other end of the primary winding of the pulse transformer is connected to the gate g2 of the SiC MOSFET transistor Q2. The voltage between the drain d2 and source s2 of the SiC MOSFET transistor Q2 is connected to the low-side RC micro-branch. The output of the low-side RC micro-branch is connected to one end of the primary winding of the 1:1 pulse transformer, and the other end of the primary winding of the pulse transformer is connected to the gate g2 of the SiC MOSFET transistor Q2.

7. The adaptive voltage equalization control system for series-connected SiC MOSFETs according to claim 6, characterized in that, The state detection circuit also integrates on and off state detection circuits. Specifically, the on and off state detection circuits further integrate the voltage slew rate detection circuit. The output of the voltage slew rate detection circuit is further integrated in the RC integration branch of the on and off state detection circuit to reconstruct the original drain-source voltage V. d1s1 and V d2s2 A scaled voltage signal with an amplitude proportional relationship; the scaled voltage signal is connected to the signal input terminal of a comparator, and the reference input terminal of the comparator is connected to a preset reference voltage V. ref By comparing voltages, a switching status pulse signal is output.

8. An adaptive voltage equalization control method for series-connected SiC MOSFETs, based on the adaptive voltage equalization control system for series-connected SiC MOSFETs according to any one of claims 1 to 7, characterized in that, Includes the following steps: The state detection circuit acquires signals in real time to obtain the voltage V between the drain d1 and source s1 of the SiC MOSFET transistor Q1. d1s1 And the voltage V between the drain d2 and source s2 of the SiC MOSFET transistor Q2. d2s2 ; The state detection circuit is based on voltage V d1s1 and voltage V d2s2 The output switch status pulse signal is transmitted to the FPGA, and the output voltages v1 and v2 are transmitted to the voltage-controlled current source circuit and the voltage-controlled current absorption circuit. The FPGA receives the switch status pulse signal from the status detection circuit, processes it logically, and then outputs a timing control signal to the gate drive pulse V. P2 The timing control terminal controls the timing of the gate drive pulse VP2, setting the rising edge of the turn-on pulse or the falling edge of the turn-off pulse. Based on the rising edge of the turn-on pulse, the voltage-controlled current source circuit and the voltage-controlled current sink circuit inject current Isource into the gate g2 of the SiC MOSFET transistor Q2 according to the voltages v1 and v2 output by the state detection circuit, thereby accelerating the rise rate of the gate-source voltage of the SiC MOSFET transistor Q2. Based on the falling edge of the turn-off pulse, the voltage-controlled current sink circuit extracts current Isink from the gate g2 of the SiC MOSFET transistor Q2, thereby accelerating the fall rate of the gate-source voltage of the SiC MOSFET transistor Q2.

9. The adaptive voltage equalization control method for a series SiC MOSFET according to claim 8, characterized in that, The FPGA receives the switch status pulse signal output by the state detection circuit, processes it logically, and then outputs a timing control signal to the gate drive pulse V. P2 The timing control terminal adjusts the timing of the gate drive pulse VP2. Specifically, the output of the state detection circuit is connected to the signal acquisition port of the FPGA, and the control signal output port of the FPGA is connected to the gate drive pulse V of the SiC MOSFET transistor Q2. p2 The timing control terminal, gate drive pulse V p2 The drive signal is interrupted by R g2 The gate g2 of the SiC MOSFET transistor Q2 is connected to the gate g2. The FPGA receives the on and off state pulse signals output by the state detection circuit. The FPGA integrates a pulse rising edge capture unit and a processing unit. The pulse rising edge capture unit records the rising edge time of each pulse according to the on and off state pulse signals. The processing unit reads the rising edge time of each pulse through the internal bus and calculates the time difference between the rising edge trigger times. The FPGA adjusts the gate drive pulse V according to the time difference between the rising edge trigger times. P2 The gate drive pulse VP2 signal, after timing adjustment, is transmitted to the drain gate g2 of the SiC MOSFET transistor Q2 at the falling edge of the turn-off pulse and the rising edge of the turn-on pulse, so as to delay or advance the turn-on.

10. The adaptive voltage equalization control method for a series SiC MOSFET according to claim 9, characterized in that, The pulse rising edge capture unit records the rising edge times t(ST1_off), t(ST2_off), t(ST1_on), and t(ST2_on) of each pulse based on the on and off state pulse signals. The arithmetic unit reads the rising edge times of each pulse through the internal bus and calculates the time differences Δt between the rising edge trigger times of ST1_off and ST2_off, and ST1_on and ST2_on, respectively. off and Δt on , Δt off and Δt on The calculation formula is as follows: Where t represents the rising edge trigger time of pulse ST.

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