Enhanced-gan power device crosstalk suppression driving circuit and method

Abstract

The application relates to the technical field of gate driving, and discloses an enhanced GaN power device crosstalk suppression driving circuit and method.The circuit comprises a pulse generation module, a driving signal generation module and a negative voltage clamping module.The pulse generation module generates three-way PWM signals;the negative voltage clamping module utilizes a monostable trigger circuit to process an upper tube control signal to generate a clamping trigger signal, and constructs a negative voltage generation circuit through a driving chip, a capacitor and a MOS tube; and the driving signal generation module combines the above signals into a multi-level driving signal to act on a lower tube gate.The application effectively suppresses false conduction by utilizing negative voltage when positive crosstalk occurs, rapidly clamps the gate voltage to 0V after the crosstalk is over, so as to adapt to different dead time applications and avoid threshold voltage drift caused by long-term negative voltage; and the gate-source voltage is clamped to a low positive level in the dead time, so as to significantly reduce the reverse conduction loss of the GaN device.Only a small number of devices are used to realize high reliability, low loss and crosstalk suppression.

Description

Technical Field

[0001] This invention relates to the field of gate drive technology, and in particular to an enhanced GaN power device crosstalk suppression drive circuit and method. Background Technology

[0002] Currently, against the backdrop of the global "dual-carbon" strategy and energy structure transformation, popular fields such as electric vehicles, AI data centers, and robotics are driving a profound revolution in power device technology—the core driving force being the ultimate pursuit of "efficiency." These applications require power electronic devices to continuously evolve towards higher frequencies, higher efficiency, and higher power densities, and traditional silicon-based power devices are gradually approaching their material physics limits. Wide-bandgap semiconductor materials, represented by silicon carbide (SiC) and gallium nitride (GaN), with their larger bandgap width, higher critical field strength, excellent high-frequency characteristics, and outstanding thermal stability, enable the power devices manufactured from them to possess excellent characteristics such as high withstand voltage and low on-resistance. This makes them no longer merely supplements or substitutes for existing technologies, but rather gradually becoming key enabling technologies defining the next generation of power electronic architectures.

[0003] Despite the promising applications of GaN devices, many technical challenges remain to be addressed. The high switching speed of GaN HEMTs is both an advantage and a challenge. GaN devices have a lower threshold voltage compared to Si and SiC devices and a narrower gate-source voltage range. If the unavoidable parasitic inductance in the power circuit resonates with the device's junction capacitance, causing overshoot and oscillation of the drain-source voltage and current, this oscillation can easily couple to the driver side through the junction capacitance and common-source inductance, leading to gate-source voltage exceeding the threshold voltage and causing false turn-on. This can reduce system efficiency or even cause system failure. In common half-bridge topologies used in popular fields such as electric vehicles, AI data centers, and robotics, false turn-on caused by positive crosstalk is even more dangerous, as bridge arm shoot-through can directly damage the device. Due to the fragility of GaN gates, the spike negative voltage of negative crosstalk can reduce gate reliability. While continuous negative voltage for negative turn-off can suppress positive crosstalk, it exacerbates negative crosstalk, and long-term negative voltage can cause the device's threshold voltage to drift, reducing gate reliability. Therefore, bridge arm crosstalk suppression requires greater attention. Summary of the Invention

[0004] To address the problems of bridge arm crosstalk and gate reliability degradation in existing technologies, this invention provides an enhanced GaN power device crosstalk suppression driving circuit and method.

[0005] To solve the above problems, the technical solution of the present invention is as follows:

[0006] This invention provides an enhanced GaN power device crosstalk suppression driving circuit, the driving circuit including a pulse generation module, a driving signal generation module, and a negative voltage clamping module. The pulse generation module is connected to the drive signal generation module and the negative pressure clamping module, respectively. The drive signal generation module is connected to the pulse generation module, the negative pressure clamping module, and the lower tube, respectively. The negative pressure clamping module is connected to the drive signal generation module. The pulse generation module is used to generate a first pulse signal PWM1, a second pulse signal PWM2, and an upper MOSFET control signal PWM6 for controlling the upper MOSFET. The negative voltage clamping module is used to generate a low positive level clamping signal PWM4 based on the second pulse signal PWM2, and to generate a lower MOSFET negative voltage clamping trigger signal PWM3 based on the upper MOSFET control signal PWM6. The drive signal generation module is used to generate a negative pressure clamping drive signal PWM5 based on the negative pressure clamping trigger signal PWM3 of the lower tube, and to synthesize a multi-level drive signal PWML for driving the lower tube based on the negative pressure clamping drive signal PWM5 and the first pulse signal PWM1.

[0007] This invention provides a crosstalk suppression driving method for enhanced GaN power devices, based on the aforementioned enhanced GaN power device crosstalk suppression driving circuit, comprising the following steps: S1. The pulse generation module generates a first pulse signal PWM1, a second pulse signal PWM2, and an upper MOSFET control signal PWM6; the first pulse signal PWM1 is input to the drive signal generation module; the second pulse signal PWM2 is input to the negative voltage clamping module to generate a low positive level clamping signal PWM4; the upper MOSFET control signal PWM6 is input to the negative voltage clamping module to generate an upper MOSFET drive signal PWMH and a lower MOSFET negative voltage clamping trigger signal PWM3. S2, The lower transistor negative voltage clamping trigger signal PWM3 is input to the drive signal generation module to generate the negative voltage clamping drive signal PWM5; The negative voltage clamping drive signal PWM5 is input to the drive signal generation module through node P of the negative voltage clamping module, and is combined with the first pulse signal PWM1 to form a multi-level drive signal PWML; The multi-level drive signal PWML is input to the gate of the lower transistor. S3. When the upper transistor drive signal PWMH changes from low to high, positive crosstalk occurs. The negative voltage clamping module adjusts the multi-level drive signal PWML to a negative level to suppress the positive crosstalk. After the positive crosstalk ends, the negative voltage clamping module clamps the multi-level drive signal PWML to 0V, thereby clamping the gate-source voltage of the lower transistor to 0V. S4. Negative crosstalk occurs during the dead time when the upper transistor is turned off and the lower transistor is about to be turned on. When the negative crosstalk signal arrives, the multi-level drive signal PWML is kept at 0V.

[0008] Compared with existing technologies, its advantages are as follows: This invention precisely controls the duration of the negative voltage application through a monostable trigger circuit. The negative voltage is applied during positive crosstalk and immediately clamped to 0V after the crosstalk ends. This effectively prevents false turn-on, adapts to applications with different dead times, and eliminates the damage to gate reliability caused by prolonged negative voltage. Addressing the issue of high reverse conduction voltage drop and losses in GaN devices due to the lack of a body diode, this invention utilizes a MOSFET in the negative voltage generation circuit to clamp the gate-source voltage of the lower transistor to a low positive level during the dead time. Compared to traditional negative voltage turn-off, this measure significantly reduces the reverse conduction voltage drop, thereby significantly reducing reverse conduction losses during synchronous rectification and improving system efficiency. This invention requires only two capacitors, one MOSFET, and simple logic gates to achieve complex negative voltage generation, clamping, and multi-level driving functions. It is easy to integrate, has low hardware costs, and has extremely high application value. Attached Figure Description

[0009] Figure 1 This is a flowchart of an enhanced GaN power device crosstalk suppression driving method provided by the present invention; Figure 2 This is a circuit diagram of an enhanced GaN power device crosstalk suppression driving circuit provided by the present invention; Figure 3 This is a schematic diagram of the NAND gate in Embodiment 1 of the present invention; Figure 4 This is a simulation waveform diagram of the first pulse signal PWM1, the second pulse signal PWM2, and the upper MOSFET control signal PWM6 in Embodiment 2 of the present invention; Figure 5 This is a simulation waveform diagram of the upper transistor drive signal PWMH, the lower transistor negative voltage clamp trigger signal PWM3, the negative voltage clamp drive signal PWM5, the multi-level drive signal PWML, and the node P voltage in Embodiment 2 of the present invention. Detailed Implementation

[0010] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0011] Example 1 like Figure 2 As shown, this embodiment provides an enhanced GaN power device crosstalk suppression driving circuit. The driving circuit includes a pulse generation module, a driving signal generation module, and a negative voltage clamping module. The pulse generation module is connected to the drive signal generation module and the negative pressure clamping module, respectively. The drive signal generation module is connected to the pulse generation module, the negative voltage clamping module, and the gate of the lower transistor, respectively. The negative pressure clamping module is connected to the drive signal generation module. The pulse generation module generates a first pulse signal PWM1, a second pulse signal PWM2, and an upper MOSFET control signal PWM6. The first pulse signal PWM1 serves as the lower MOSFET control signal, controlling the lower MOSFET's on / off state. The upper MOSFET control signal PWM6 controls the upper MOSFET's on / off state. The negative voltage clamping module is used to generate a low positive level clamping signal PWM4 based on the second pulse signal PWM2, and to generate a negative voltage clamping trigger signal PWM3 for the lower MOSFET based on the upper MOSFET control signal. The drive signal generation module is used to generate a negative voltage clamp drive signal PWM5 based on the negative voltage clamp trigger signal PWM3 of the lower tube, and to synthesize a multi-level drive signal PWML for driving the lower tube based on the negative voltage clamp drive signal PWM5 and the first pulse signal PWM1.

[0012] In this optional embodiment, the pulse generation module uses an FPGA chip, the drive signal generation module includes a first gate drive chip Driver1, and the negative voltage clamping module includes a second gate drive chip Driver2, a monostable trigger circuit, and a negative voltage generation circuit.

[0013] The FPGA chip is connected to the first gate driver chip Driver1 and the second gate driver chip Driver2 respectively; the first gate driver chip Driver1 is connected to the FPGA chip, the monostable trigger circuit, the negative voltage generation circuit and the lower transistor respectively; the second gate driver chip Driver2 is connected to the FPGA chip, the negative voltage generation circuit and the upper transistor respectively.

[0014] In the drive signal generation module, for the first gate driver chip Driver1, The INB pin of the first gate driver chip Driver1 is connected to the FPGA chip, the VDDB pin is connected to the positive voltage source, the GNDB pin is connected to the output of the negative voltage generation circuit through node P, the OUTB pin is connected to the gate of the lower transistor, the OUTA pin is connected to the input of the negative voltage generation circuit, the GNDA pin is connected to the negative voltage source, the VDDA pin is grounded, and the INA pin is connected to the output of the monostable trigger circuit.

[0015] In the negative voltage clamping module, the monostable trigger circuit includes a resistor R1, a capacitor C1, and a logic gate NAND gate, while the negative voltage generation circuit includes a capacitor C2 and a transistor PMOS.

[0016] For monostable trigger circuits One end of resistor R1 is connected to the first input terminal of the FPGA chip and the NAND gate, and the other end of resistor R1 is connected to the second input terminal of the NAND gate. One end of capacitor C1 is connected to resistor R1 and the second input terminal of the NAND gate, and the other end of capacitor C1 is grounded. The output terminal of the NAND gate is connected to the INA pin of the first gate driver chip Driver1.

[0017] The NAND gate is used to toggle the voltage level, outputting the lower transistor's negative voltage clamping trigger signal PWM3. Specifically, the component diagram of the NAND gate is shown below. Figure 3 As shown in the diagram, pin A is the first input terminal of the NAND gate, pin B is the second input terminal of the NAND gate, and pin Y is the output terminal of the NAND gate. Pin V CC This is the power supply terminal, connected to the power supply, with the GND pin grounded.

[0018] For negative voltage generation circuits The gate of the PMOS transistor is connected to the OUTA pin of the first gate driver chip Driver1, the source of the PMOS transistor is grounded, the drain of the PMOS transistor is connected to the first end of capacitor C2, and the second end of capacitor C2 is connected to the OUTA pin of the second gate driver chip Driver2; node P is located at the connection between capacitor C2 and the PMOS transistor. For the second gate driver chip Driver2 The second gate driver chip, Driver2, has its INA pin connected to the FPGA chip, its VDDA pin connected to the positive voltage source, its GNDA pin grounded, its OUTA pin connected to the second end of capacitor C2, its OUTB pin connected to the upper transistor, its GNDB pin grounded, and its VDDB pin connected to the positive voltage source.

[0019] In this embodiment, the positive voltage source is a 5V power supply, and the negative voltage source is a -5V power supply. It should be noted that the capacitance of capacitor C2 is greater than the parasitic capacitance C of the PMOS transistor. OSS The capacitance value.

[0020] In the drive signal generation module and the negative voltage clamping module, to ensure that the duration of the negative voltage can completely suppress positive crosstalk, the drivers and devices used must meet the following requirements:

[0021] in, T tri The delay time of PWM3 output by the monostable multivibrator relative to PWM6; This refers to the time for the upper-level Miller platform.

[0022] Specifically, in this embodiment, the first gate driver chip Driver1, resistor R1, and capacitor C1 must satisfy the following:

[0023] in, For the input / output delay of the first gate driver chip Driver1, VIH is the high-level input voltage of the NAND gate. For driving voltage, The Miller plateau voltage, VGS is the sum of the resistance of the first gate driver chip Driver1 and the internal resistance of the device; VGS is the gate-source voltage of the upper transistor. Q GD This represents the gate drain charge of the upper GaN device.

[0024] In this embodiment, the signal input and output are: The FPGA chip generates the first pulse signal PWM1, the second pulse signal PWM2, and the upper MOSFET control signal PWM6. The first pulse signal PWM1 is input to the INB pin of the first gate driver chip Driver1; the second pulse signal PWM2 is input to the INA pin of the second gate driver chip Driver2, and a low positive level clamping signal PWM4 is output from the OUTA pin; the upper MOSFET control signal PWM6 is input to the INB pin of the second gate driver chip Driver2, and an upper MOSFET drive signal PWMH is output from the OUTB pin. The upper MOSFET control signal PWM6 is also input to the monostable trigger circuit, and a lower MOSFET negative voltage clamping trigger signal PWM3 is output.

[0025] The negative voltage clamping trigger signal PWM3 of the lower transistor is input to the INA pin of the first gate driver chip Driver1 to obtain the negative voltage clamping drive signal PWM5. The negative voltage clamping drive signal PWM5 is input from the OUTA pin of the first gate driver chip Driver1 to the negative voltage generation circuit. It is input through node P to the GNDB pin of the first gate driver chip Driver1 and combined with the first pulse signal PWM1 to form a multi-level drive signal PWML. The multi-level drive signal PWML is input from the OUTB pin of the first gate driver chip Driver1 to the gate of the lower transistor.

[0026] Example 2 This embodiment provides a crosstalk suppression driving method for enhanced GaN power devices, based on the enhanced GaN power device crosstalk suppression driving circuit described in Embodiment 1, including the following steps: S1. The pulse generation module generates a first pulse signal PWM1, a second pulse signal PWM2, and an upper MOSFET control signal PWM6; the first pulse signal PWM1 is input to the drive signal generation module; the second pulse signal PWM2 is input to the negative voltage clamping module to generate a low positive level clamping signal PWM4; the upper MOSFET control signal PWM6 is input to the negative voltage clamping module to generate an upper MOSFET drive signal PWMH and a lower MOSFET negative voltage clamping trigger signal PWM3. S2, The lower transistor negative voltage clamping trigger signal PWM3 is input to the drive signal generation module to generate the negative voltage clamping drive signal PWM5; The negative voltage clamping drive signal PWM5 is input to the drive signal generation module through node P of the negative voltage clamping module, and is combined with the first pulse signal PWM1 to form a multi-level drive signal PWML; The multi-level drive signal PWML is input to the gate of the lower transistor. S3. When the upper transistor drive signal PWMH changes from low to high, positive crosstalk occurs. The negative voltage clamping module adjusts the multi-level drive signal PWML to a negative level to suppress the positive crosstalk. After the positive crosstalk ends, the negative voltage clamping module clamps the multi-level drive signal PWML to 0V, thereby clamping the gate-source voltage of the lower transistor to 0V. S4. Negative crosstalk occurs during the dead time when the upper transistor is turned off and the lower transistor is about to be turned on. When the negative crosstalk signal arrives, the multi-level drive signal PWML is kept at 0V.

[0027] This embodiment uses a synchronous rectifier Buck circuit (48V to 12V, 2A; dead time 30ns) as an example. The switching frequency is 1MHz. The upper transistor control signal PWM6 is input to the second gate driver chip Driver2. The driven signal after driving is the upper transistor drive signal PWMH. The voltage level switches between 0V and 5V. The delay time from the start of the simulation to the rising edge of the pulse is 750 nanoseconds. The pulse width is 250 nanoseconds and the period is 1 microsecond. Preferably, the duty cycle of the PWM waveform is determined by the ratio of the pulse width to the period, that is, 250 nanoseconds divided by 1 microsecond, which yields a 25% duty cycle, suitable for precise control of power output. The waveform repeats periodically.

[0028] In step S1, the pulse generation module generates a first pulse signal PWM1, a second pulse signal PWM2, and an upper MOSFET control signal PWM6; the first pulse signal PWM1 is input to the drive signal generation module; the second pulse signal PWM2 is input to the negative voltage clamping module to generate a low positive level clamping signal PWM4; the upper MOSFET control signal PWM6 is input to the negative voltage clamping module to generate an upper MOSFET drive signal PWMH and a lower MOSFET negative voltage clamping trigger signal PWM3.

[0029] In this circuit, the frequencies of the first pulse signal PWM1, the second pulse signal PWM2, and the upper-side control signal PWM6 are all 1MHz. The first pulse signal PWM1 becomes active after a period start delay Td1 (0ns in this embodiment) and lasts for Ton1 (approximately 680ns in this embodiment). The second pulse signal PWM2 is a short pulse generated after a period start delay Td2 (approximately 660ns in this embodiment), and its pulse width Ton3 (approximately 30ns in this embodiment) is much smaller than that of the first pulse signal PWM1 and the upper-side control signal PWM6. The first pulse signal PWM1 and the upper-side control signal PWM6 are the main power pulses.

[0030] In step S2, the lower transistor negative voltage clamp trigger signal PWM3 is input to the drive signal generation module to generate a negative voltage clamp drive signal PWM5. The negative voltage clamp drive signal PWM5 is input to the drive signal generation module through node P of the negative voltage clamp module and combined with the first pulse signal PWM1 to form a multi-level drive signal PWML. The multi-level drive signal PWML is input to the gate of the lower transistor. The multi-level drive signal can suppress crosstalk and reduce the reverse conduction voltage drop during the dead time, thereby reducing the reverse conduction loss.

[0031] In step S3, when the upper transistor drive signal PWMH changes from low to high, positive crosstalk occurs; the negative voltage clamping module adjusts the multi-level drive signal PWML to a negative level to suppress the positive crosstalk; after the positive crosstalk ends, the negative voltage clamping module clamps the multi-level drive signal PWML to 0V, thereby clamping the gate-source voltage of the lower transistor to 0V.

[0032] The causes of positive crosstalk are as follows: Assume the initial state is the upper transistor Q of the synchronous rectification buck circuit. H Turn on, lower tube Q L In the off state, Vbus and upper Q are connected. H The load inductance L, output capacitor Cout, and GND form a current loop, and the voltage V at node SW is... SW ≈Vbus (V BUS (This refers to the DC bus voltage).

[0033] To prevent straight-through of the bridge arm, on the upper pipe Q H From power on to power off and down-tube Q L Between shutdown and startup, there needs to be an upper-side Q. H and lower tube Q L The time during which both are turned off is set to the dead time DT1. Since the current in the load inductor L cannot change abruptly, the load inductor L and the output capacitor C... out Q of reverse guidance L To form a freewheeling loop, let Q L The reverse conduction voltage drop is V R1Then V SW From V bus The jump to -VR1 produces a large dv / dt, according to Miller capacitance C of the lower transistor rss Displacement current appears on , According to Ohm's Law The resistor R flowing through the inside of the driver chip LO The lower tube resistor R GL The gate resistance R inside the GaN device GI In Q L The gate generates a negative voltage spike, i.e., negative crosstalk. It should be noted that due to the unique device structure of GaN HEMT, the device has no body diode, resulting in relatively large losses during reverse conduction.

[0034] After the dead time DT1, Q L Turn on, load inductor L, output capacitor C out Q of reverse guidance L The resulting freewheeling loop still provides freewheeling, but the reverse conduction loss is reduced. Let Q... L The reverse conduction loss during conduction is VR2, at which point V SW =- VR2.

[0035] lower tube Q L When closed, to prevent bridge arm shoot-through, in Q L From turning on to turning off and Q H There is a dead time DT2 between shutdown and startup. During this time, it is still a reverse continuous flow, V SW =- VR1, reverse conduction loss is relatively large.

[0036] After the dead time DT2, the upper tube Q H When turned on, the load current loop flows from the load inductor L and the output capacitor C. out Q of reverse guidance L Transform into V bus Upper pipe Q H Load inductance L, output capacitor C out GND. Therefore, V SW Jump from -VR2 to V bus This produces a large dv / dt, according to Q L Displacement current appears on Miller capacitor Crss According to Ohm's Law Flow through R LO R GL R GI In Q L The gate generates a positive voltage spike, i.e., positive crosstalk.

[0037] In this embodiment, the negative voltage clamping module includes a negative voltage generation circuit and a monostable trigger circuit. The negative voltage generation circuit includes a capacitor C2 and a transistor PMOS. The monostable trigger circuit includes a resistor R1, a capacitor C1, and a logic gate NAND gate. The process of adjusting the multi-level drive signal PWML to a negative level to suppress positive crosstalk through the negative voltage clamping module is as follows: When the output low positive level clamping signal PWM4 is high, it represents the parasitic capacitance C of capacitor C2 and transistor PMOS. OSS During charging, since capacitor C2 is connected in parallel with transistor PMOS, capacitor C2 clamps the PMOS transistor after it is turned on. The clamping node P potential of the PMOS transistor is a low positive voltage, and the clamping voltage at node P is less than the threshold voltage of the next transistor. Let the clamping voltage be V. body_f And V body_f <V th (The typical threshold voltage of GaN HEMT is Vth≈1.4V~1.7V, Vbody_f≈0.4~0.5V), which will not turn on the GaN HEMT. When the low positive level clamping signal PWM4 turns low, since the voltage across capacitor C2 cannot change abruptly, the voltage at node P becomes negative, keeping the multi-level drive signal PWML in a negative state.

[0038] When a GaN HEMT is in the off state, if a reverse voltage exists and V GD >V GDTH When the gate and drain voltages reach a certain value, reverse conduction occurs. Since GaN HEMTs lack a body diode, their reverse conduction voltage drop cannot be clamped like that of a MOSFET. The expression for the reverse conduction voltage drop of a GaN device is: V rev =V GDTH +I D *R DSON -V GS Therefore, when the negative pressure is turned off, V GS The more negative the voltage, the greater the reverse conduction voltage drop and the higher the reverse conduction loss.

[0039] When using negative voltage turn-off in a synchronous rectification Buck circuit with the lower transistor reverse-biased, during the dead time DT2 when crosstalk suppression is not required, the PMOS transistor is turned on, clamping node P to V. body_f Then, it is transmitted to the multi-level drive signal PWML through the GNDA pin of the first driver chip DRIVER1, thereby slightly increasing V. GS This effectively reduces reverse conduction losses.

[0040] The process of clamping the multi-level drive signal PWML to 0V through the negative voltage clamping module to achieve crosstalk suppression is as follows: When the upper transistor control signal PWM6 is high, current charges capacitor C1 until its voltage reaches the minimum high-level threshold of the NAND gate. The NAND gate then outputs the lower transistor negative voltage clamping trigger signal PWM3. The time delay of this process is determined by resistor R1 and capacitor C1. The lower transistor negative voltage clamping trigger signal PWM3 is input to the first gate driver chip Driver1 and outputs the negative voltage clamping drive signal PWM5. When the voltage of the negative voltage clamping drive signal PWM5 is lower than the threshold voltage of the transistor PMOS, the transistor PMOS is turned on, clamping the voltage at node P to 0V, and the multi-level drive signal PWML is also clamped to 0V.

[0041] Specifically, positive crosstalk occurs when the upper transistor drive signal PWMH changes from low to high.

[0042] Upper tube Q H When conducting, when V GS (Gate-source voltage of upper transistor) > V th When the threshold voltage of the GaN device is reached, the drain current increases until it reaches the load current. Since the load is inductive and the channel has already been formed, in the constant current region, the drain current is only related to V. GS Relatedly, an inductive load prevents the current from changing abruptly, therefore V GS Entering a plateau phase, the Miller plateau is formed, and the Miller plateau lasts for [duration not specified]. In the Miller plateau region, the gate current affects C. GD Charging, making V DS Rapid descent. Due to the upper pipe V DS The rapid descent generates a large dv / dt at the SW node, causing positive crosstalk. Therefore, the duration of positive crosstalk in the lower tube's QL is approximately equal to the Miller plateau time of the upper tube. .

[0043] In the monostable trigger circuit, resistor R1 and capacitor C1 create a delay. The purpose is to allow the positive crosstalk to pass before the negative voltage clamp drive signal PWM5 starts the transistor PMOS. When the transistor PMOS is turned on, the node P potential is grounded, and the positive crosstalk ends.

[0044] Because PWM5 has a phase delay compared to PWMH, after the positive crosstalk ends, the negative voltage clamping drive signal PWM5 controls the PMOS transistor to turn on, bypassing capacitor C2. The negative voltage signal of the multi-level drive signal PWML is then quickly clamped to 0V.

[0045] To ensure that the duration of negative pressure can completely suppress positive crosstalk, the following must be satisfied:

[0046] in, T triThe delay time of the lower transistor negative voltage clamping trigger signal PWM3 output by the monostable multivibrator relative to the upper transistor control signal PWM6.

[0047] Due to the different drivers and devices used, specifically in this embodiment, the following needs to be met:

[0048] in, For the input / output delay of the first gate driver chip Driver1, V IH The high-level input voltage of the NAND gate is [the voltage level of the logic gate]. For driving voltage, The Miller plateau voltage, This is the sum of the resistance of the first gate driver chip Driver1 and the internal resistance of the device; V GS This is the gate-source voltage of the upper transistor; Q GD This represents the gate drain charge of the upper GaN device.

[0049] Negative crosstalk occurs during the dead time when the upper transistor is turned off and the lower transistor is about to be turned on. When the negative crosstalk signal arrives, step S4 keeps the multi-level drive signal PWML at 0V to prevent the negative voltage spike from reducing the reliability of the GaN HEMT gate.

[0050] The simulation results of this embodiment are as follows: Figure 4 and Figure 5 As shown, Figure 4 This is a schematic diagram of the simulated waveforms of the first pulse signal PWM1, the second pulse signal PWM2, and the upper MOSFET control signal PWM6 in Embodiment 2 of the present invention. Figure 5 This is a simulation waveform diagram of the upper MOSFET control signal PWMH, the lower MOSFET negative voltage clamp trigger signal PWM3, the negative voltage clamp drive signal PWM5, the multi-level drive signal PWML, and the key node voltage in Embodiment 2 of the present invention.

[0051] This demonstrates that the multi-level drive signal for the lower transistor proposed in this invention can suppress crosstalk and optimize reverse conduction loss.

[0052] In summary, this invention provides an enhanced GaN power device crosstalk suppression driving circuit and method. The pulse generation module generates three PWM high-frequency pulses; the driving signal generation module combines two dual-level driving signals into a multi-level driving signal, using multi-level driving to optimize reverse conduction loss and suppress positive crosstalk; the negative voltage clamping module uses a designed monostable trigger circuit, taking the upper MOSFET control signal as input and the output signal as a clamping signal to clamp the negative voltage, thereby preventing threshold voltage drift caused by long-term negative voltage and optimizing reverse conduction loss. In this invention, negative voltage clamping is performed in the negative voltage generation circuit instead of at the GaN HEMT gate. For the first time, the upper-side control signal is processed and made into a negative voltage clamping trigger signal for the lower-side transistor. Complex negative voltage generation, clamping, and multi-level driving functions can be achieved with only two capacitors, one MOSFET, and simple logic gate circuits. For the first time, a monostable trigger circuit is used as a component of the negative voltage clamping circuit. The driving circuit and method of this invention take into account both crosstalk suppression and reverse conduction loss optimization. High reliability and low loss crosstalk suppression are achieved with only a few components. It is easy to integrate and has low hardware cost, making it suitable for high-frequency and high-efficiency power systems.

[0053] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention.

Claims

1. An enhanced GaN power device crosstalk suppression driving circuit, characterized in that, The driving circuit includes a pulse generation module, a driving signal generation module, and a negative pressure clamping module. The pulse generation module is connected to the drive signal generation module and the negative pressure clamping module, respectively. The drive signal generation module is connected to the pulse generation module, the negative pressure clamping module, and the lower tube, respectively. The negative pressure clamping module is connected to the drive signal generation module. The pulse generation module is used to generate a first pulse signal PWM1, a second pulse signal PWM2, and an upper MOSFET control signal PWM6 for controlling the upper MOSFET. The negative voltage clamping module is used to generate a low positive level clamping signal PWM4 based on the second pulse signal PWM2, and to generate a lower MOSFET negative voltage clamping trigger signal PWM3 based on the upper MOSFET control signal PWM6. The drive signal generation module is used to generate a negative pressure clamping drive signal PWM5 based on the negative pressure clamping trigger signal PWM3 of the lower tube, and to synthesize a multi-level drive signal PWML for driving the lower tube based on the negative pressure clamping drive signal PWM5 and the first pulse signal PWM1.

2. The driving circuit according to claim 1, characterized in that, The pulse generation module uses an FPGA chip, the drive signal generation module includes a first gate drive chip Driver1, and the negative voltage clamping module includes a second gate drive chip Driver2, a monostable trigger circuit, and a negative voltage generation circuit. The FPGA chip is connected to the first gate driver chip Driver1 and the second gate driver chip Driver2 respectively. The first gate driver chip, Driver1, is connected to the FPGA chip, the monostable trigger circuit, the negative voltage generation circuit, and the lower transistor, respectively. The second gate driver chip Driver2 is connected to the FPGA chip, the negative voltage generation circuit and the upper transistor respectively.

3. The driving circuit according to claim 2, characterized in that, In the drive signal generation module, for the first gate driver chip Driver1, The INB pin of the first gate driver chip Driver1 is connected to the FPGA chip, the VDDB pin is connected to the positive voltage source, the GNDB pin is connected to the output of the negative voltage generation circuit through node P, the OUTB pin is connected to the gate of the lower transistor, the OUTA pin is connected to the input of the negative voltage generation circuit, the GNDA pin is connected to the negative voltage source, the VDDA pin is grounded, and the INA pin is connected to the output of the monostable trigger circuit.

4. The driving circuit according to claim 3, characterized in that, In the negative voltage clamping module, the monostable trigger circuit includes a resistor R1, a capacitor C1, and a logic gate NAND gate, and the negative voltage generation circuit includes a capacitor C2 and a transistor PMOS; For the monostable trigger circuit One end of the resistor R1 is connected to the FPGA chip and the first input terminal of the NAND gate, and the other end of the resistor R1 is connected to the second input terminal of the NAND gate. One end of the capacitor C1 is connected to the resistor R1 and the second input terminal of the NAND gate, and the other end of the capacitor C1 is grounded. The output terminal of the NAND gate is connected to the INA pin of the first gate driver chip Driver1. For the aforementioned negative pressure generating circuit The gate of the PMOS transistor is connected to the OUTA pin of the first gate driver chip Driver1, the source of the PMOS transistor is grounded, the drain of the PMOS transistor is connected to the first terminal of the capacitor C2, and the second terminal of the capacitor C2 is connected to the OUTA pin of the second gate driver chip Driver2; the node P is located at the connection between the capacitor C2 and the PMOS transistor. For the second gate driver chip Driver2 The second gate driver chip Driver2 has its INA pin connected to the FPGA chip, its VDDA pin connected to the positive voltage source, its GNDA pin grounded, its OUTA pin connected to the second end of the capacitor C2, its OUTB pin connected to the upper transistor, its GNDB pin grounded, and its VDDB pin connected to the positive voltage source.

5. The driving circuit according to claim 4, characterized in that, The capacitance value of capacitor C2 is greater than the parasitic capacitance C of the PMOS transistor. OSS The capacitance value.

6. The circuit according to claim 4, characterized in that, In the drive signal generation module and the negative voltage clamping module, the first gate drive chip Driver1, the resistor R1, and the capacitor C1 must satisfy the following: in, For the input / output delay of the first gate driver chip Driver1, V IH The high-level input voltage of the NAND gate is [the voltage level of the logic gate]. For driving voltage, The Miller plateau voltage, This is the sum of the resistance of the first gate driver chip Driver1 and the internal resistance of the device; V GS This is the gate-source voltage of the upper transistor; Q GD This represents the gate drain charge of the upper GaN device.

7. A crosstalk suppression driving method for enhanced GaN power devices, based on the crosstalk suppression driving circuit for enhanced GaN power devices according to any one of claims 1-6, characterized in that, Includes the following steps: S1, the pulse generation module generates a first pulse signal PWM1, a second pulse signal PWM2, and an upper MOSFET control signal PWM6; the first pulse signal PWM1 is input to the drive signal generation module; The second pulse signal PWM2 is input to the negative voltage clamping module to generate a low positive level clamping signal PWM4; the upper MOSFET control signal PWM6 is input to the negative voltage clamping module to generate the upper MOSFET drive signal PWMH and the lower MOSFET negative voltage clamping trigger signal PWM3. S2, The lower transistor negative voltage clamping trigger signal PWM3 is input to the drive signal generation module to generate the negative voltage clamping drive signal PWM5; The negative voltage clamping drive signal PWM5 is input to the drive signal generation module through node P of the negative voltage clamping module, and is combined with the first pulse signal PWM1 to form a multi-level drive signal PWML; The multi-level drive signal PWML is input to the gate of the lower transistor. S3. When the upper transistor drive signal PWMH changes from low to high, positive crosstalk occurs. The negative voltage clamping module adjusts the multi-level drive signal PWML to a negative level to suppress the positive crosstalk. After the positive crosstalk ends, the negative voltage clamping module clamps the multi-level drive signal PWML to 0V, thereby clamping the gate-source voltage of the lower transistor to 0V. S4. Negative crosstalk occurs during the dead time when the upper transistor is turned off and the lower transistor is about to be turned on. When the negative crosstalk signal arrives, the multi-level drive signal PWML is kept at 0V.

8. The method according to claim 7, characterized in that, In step S1, the frequencies of the first pulse signal PWM1, the second pulse signal PWM2, and the upper MOSFET control signal PWM6 are all 1MHz. The first pulse signal PWM1 becomes active after a period start delay Td1 and lasts for Ton1. The second pulse signal PWM2 is a short pulse generated after a period start delay Td2, and its pulse width Ton3 is smaller than that of the first pulse signal PWM1 and the upper MOSFET control signal PWM6.

9. The method according to claim 7, characterized in that, In step S3, the negative voltage clamping module includes a negative voltage generation circuit, which includes a capacitor C2 and a transistor PMOS. The process of adjusting the multi-level drive signal PWML to a negative level to suppress positive crosstalk through the negative voltage clamping module is as follows: When the output low positive level clamping signal PWM4 is high, it represents the parasitic capacitance C of capacitor C2 and transistor PMOS. OSS Charging causes the PMOS transistor to be turned on and clamped. The PMOS clamping node P potential is a low positive voltage, and the node P clamping voltage is less than the lower threshold voltage. When the low positive level clamping signal PWM4 turns low, since the voltage across the capacitor C2 cannot change abruptly, the node P voltage becomes negative, keeping the multi-level drive signal PWML in a negative state.

10. The method according to claim 7, characterized in that, In step S3, the negative voltage clamping module includes a negative voltage generation circuit and a monostable trigger circuit. The negative voltage generation circuit includes a capacitor C2 and a transistor PMOS. The monostable trigger circuit includes a resistor R1, a capacitor C1, and a logic gate NAND gate. The process of clamping the multi-level drive signal PWML to 0V through the negative voltage clamping module is as follows: When the upper transistor control signal PWM6 is high, the current charges the capacitor C1 until the voltage across it reaches the minimum high-level threshold of the NAND gate. The NAND gate outputs the lower transistor negative voltage clamping trigger signal PWM3. The time delay of this process is determined by the resistor R1 and the capacitor C1. The lower transistor negative voltage clamping trigger signal PWM3 is input to the first gate driver chip Driver1 and outputs the negative voltage clamping drive signal PWM5. When the voltage of the negative voltage clamping drive signal PWM5 is lower than the threshold voltage of the transistor PMOS, the transistor PMOS is turned on, clamping the voltage of node P to 0V, and the multi-level drive signal PWML is clamped to 0V.

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