Logic gated input circuit

Abstract

The application provides a logic gate input circuit, comprising an input port, an output port, a power supply port, a controllable switch and a gate threshold identification circuit. The breakdown voltage between the controllable end and the first end and the breakdown voltage between the first end and the second end are both greater than the maximum voltage of the input port. The threshold voltage of the controllable switch is less than the difference between the voltage of the power supply port and the high gate threshold voltage of the logic gate input circuit. The gate threshold identification circuit is connected to the second end and the output port. The gate threshold identification circuit is used to: when the voltage of the input port is lower than the low gate threshold voltage, make the output port output a low level and pull down the voltage of the second end; when the voltage of the input port is higher than the high gate threshold voltage, make the output port output a high level and pull up the voltage of the second end; and when the voltage of the input port is between the low gate threshold voltage and the high gate threshold voltage, the level output by the output port remains unchanged. The logic gate input circuit provided by the application can withstand high voltage.

Description

Technical Field

[0001] This application relates to the field of input circuit technology, and in particular to a logic gated input circuit. Background Technology

[0002] For receiving signals that are compatible with common TTL levels, logic gated input circuits generally use low-voltage circuits. However, when the input signal of the logic gated input circuit is a high-voltage signal, the voltage difference between the external high voltage and the internal low voltage system will cause the device to break down.

[0003] Currently, there are generally two solutions for high-voltage input signals. The first solution is to implement the input circuit using pure high-voltage integrated circuit technology. For example, traditional general-purpose logic gated input circuits are implemented using Schmitt gates. To achieve high-voltage withstand capability, all MOSFETs are manufactured using pure high-voltage technology, meaning the MOSFETs have high gate-source and high gate-drain withstand voltages. This process is relatively complex, requires more high-voltage transistors, and consumes more chip resources. Furthermore, the threshold voltage of high-voltage MOSFETs is relatively high. If the internal power supply of the logic gated input circuit is low, as low as 2V or even lower, the high threshold voltage of the high-voltage MOSFETs will cause them to be in a non-conducting state, affecting signal recognition and easily causing signal recognition errors.

[0004] The second approach uses voltage clamping, employing a current-limiting resistor and clamping circuit to restrict the voltage reaching the input transistor. When a high voltage appears at the input port, the clamping circuit activates, limiting the voltage to a certain value. The current-limiting resistor then withstands an additional high voltage to ensure the input transistor's voltage remains low and prevents breakdown. However, this approach easily leads to continuous current flow in the branch containing the current-limiting resistor. Therefore, the pre-amplifier driver must provide a continuous current to ensure the clamping circuit functions properly, placing higher demands on the pre-amplifier driver. Furthermore, the continuous current flow causes additional losses, resulting in higher branch power, chip heating, and affecting circuit stability. Summary of the Invention

[0005] This application provides a logic gated input circuit that is low in cost and power consumption, and is compatible with TTL level signals and high voltage signals.

[0006] This application provides a logic gated input circuit, including:

[0007] Input port, output port, power supply port; the output port is connected to a logic gate circuit;

[0008] A controllable switch includes a controllable terminal, a first terminal, and a second terminal. The controllable terminal is connected to the power supply port, and the first terminal is connected to the input port. The breakdown voltage between the controllable terminal and the first terminal, and the breakdown voltage between the first terminal and the second terminal, are both greater than the maximum voltage of the input port. The threshold voltage of the controllable switch is less than the difference between the voltage of the power supply port and the high gate threshold voltage of the logic gate circuit.

[0009] A gate threshold recognition circuit is connected to the second terminal and the output port; the gate threshold recognition circuit is used to: when the voltage of the input port is lower than the low gate threshold voltage, cause the output port to output a low level and pull down the voltage of the second terminal; when the voltage of the input port is higher than the high gate threshold voltage, cause the output port to output a high level and pull up the voltage of the second terminal; when the voltage of the input port is between the low gate threshold voltage and the high gate threshold voltage, the output level of the output port remains unchanged; the low gate threshold voltage is less than the high gate threshold voltage.

[0010] Optionally, the gate threshold voltage recognition circuit includes a low gate threshold voltage recognition branch and a high gate threshold voltage recognition branch. The input terminals of both the low and high gate threshold voltage recognition branches are connected to the second terminal, and the output terminals of both branches are connected to the output port. The low gate threshold voltage recognition branch is used to: when the voltage at the input port is lower than the low gate threshold voltage, cause the output port to output a low level and pull down the voltage at the second terminal; the high gate threshold voltage recognition branch is used to: when the voltage at the input port is higher than the high gate threshold voltage, cause the output port to output a high level and pull up the voltage at the second terminal; when the voltage at the input port is between the low and high gate threshold voltages, the output level of the output port remains unchanged.

[0011] Optionally, the low gate threshold voltage identification branch includes a first inverter circuit and a first NOR gate; the first inverter circuit includes an odd number of inverters connected in series; the high gate threshold voltage identification branch includes a second inverter circuit and a second NOR gate; the second inverter circuit includes an even number of inverters connected in series; the input terminal of the first inverter circuit is connected to the second terminal. ， The output of the first inverter circuit is connected to the input of the first NOR gate; the input of the second inverter circuit is connected to the second terminal, and the output of the second inverter circuit is connected to the input of the second NOR gate.

[0012] The output of the first NOR gate is connected to the other input of the second NOR gate, the output of the second NOR gate is connected to the other input of the first NOR gate, and the output of the first NOR gate is connected to the output port.

[0013] Optionally, the logic gated input circuit further includes a ground port; the first inverter circuit includes a first inverter; the first inverter includes a first transistor, a second transistor, and a first feedback transistor; the first transistor and the second transistor are connected in series between the power supply port and the ground port, the controllable terminals of the first transistor and the second transistor are both connected to the second terminal, the output terminal of the first inverter is connected between the first transistor and the second transistor, and is connected to the controllable terminal of the first feedback transistor, the first feedback transistor is connected in series between the second terminal and the ground port.

[0014] Optionally, the first transistor includes a PMOS transistor, the second transistor includes an NMOS transistor, and the first feedback transistor includes an NMOS transistor.

[0015] Optionally, the logic gated input circuit further includes a ground port; the second inverter circuit includes a second inverter; the second inverter includes a third transistor, a fourth transistor, and a second feedback transistor; the third transistor and the fourth transistor are connected in series between the power supply port and the ground port, the controllable terminals of the third transistor and the fourth transistor are both connected to the second terminal, the output terminal of the second inverter is connected between the third transistor and the fourth transistor, and is connected to the controllable terminal of the second feedback transistor, the second feedback transistor is connected in series between the power supply port and the second terminal.

[0016] Optionally, the third transistor includes a PMOS transistor, the fourth transistor includes an NMOS transistor, and the second feedback transistor includes a PMOS transistor.

[0017] Optionally, the logic gated input circuit includes a pressure resistor connected to the first terminal and the input port.

[0018] Optionally, the logic gated input circuit includes a standby circuit and a ground port, wherein the standby circuit is connected to the input port and the ground port.

[0019] Optionally, the breakdown voltage between the controllable terminal and the second terminal of the controllable switch is greater than the maximum voltage of the input port.

[0020] In some embodiments, the controllable terminal of the controllable switch is connected to the power supply port, the first terminal of the controllable switch is connected to the input port, and the gate threshold recognition circuit is connected to the second terminal of the controllable switch and the output port. The breakdown voltage between the controllable terminal and the first terminal, as well as the breakdown voltage between the first terminal and the second terminal, are both greater than the maximum voltage of the input port, and the threshold voltage of the controllable switch is less than the difference between the voltage of the power supply port and the high gate threshold voltage of the logic gate input circuit. When the voltage of the input port is higher than the recognized high gate threshold voltage or even higher than the voltage of the power supply port, the controllable switch will not break down due to its high withstand voltage characteristics. The output port outputs a high level, and the gate threshold recognition circuit pulls up the voltage of the second terminal. When the voltage of the second terminal is pulled up to a certain value, the controllable switch is turned off, the circuit current drops to a very small value, and the circuit power consumption is reduced. This makes the logic gate input circuit withstand high voltage and has low power consumption. Except for the controllable switch, no other high voltage-resistant components are required in the circuit, resulting in low circuit cost.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0023] Figure 1 The diagram shown is a circuit diagram of one embodiment of the logic gated input circuit of this application.

[0024] Figure 2 As shown Figure 1 The circuit diagram shown is of one embodiment of the first inverter.

[0025] Figure 3 As shown Figure 1 The circuit diagram shown is of one embodiment of the second inverter.

[0026] Figure 4 As shown Figure 1 The diagram shows the waveforms of the input and output signals of the logic gated input circuit.

[0027] Figure 5 As shown Figure 1 The circuit diagram shows another embodiment of the logic gated input circuit.

[0028] Figure 6 As shown Figure 1 The circuit diagram shows another embodiment of the logic gated input circuit. Detailed Implementation

[0029] This application provides a logic gated input circuit. The logic gated input circuit of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.

[0030] Figure 1 The diagram shown is a circuit diagram of one embodiment of the logic gated input circuit 10 of this application. Figure 1 As shown, the logic gated input circuit 10 includes: an input port IN, an output port OUT, a power supply port VDD, a controllable switch MN0, and a gate threshold recognition circuit 11.

[0031] The input port IN is used to receive input signals. The power port VDD is connected to the power supply.

[0032] The controllable switch MN0 includes a controllable terminal C, a first terminal T1, and a second terminal T2. The controllable terminal C is connected to the power supply port VDD. The first terminal T1 is connected to the input port IN. The breakdown voltage between the controllable terminal C and the first terminal T1, and the breakdown voltage between the first terminal T1 and the second terminal T2, are both greater than the maximum voltage of the input port. The threshold voltage of the controllable switch is less than the difference between the voltage at the power supply port VDD and the high gate threshold voltage of the logic gate input circuit 10.

[0033] The controllable switch MN0 includes an NMOS transistor. When the voltage between the controllable terminal C and the second terminal T2 of the controllable switch MN0 is greater than the threshold voltage of the controllable switch MN0, the controllable switch MN0 is turned on, and current flows from the first terminal T1 to the second terminal T2. At this time, the voltage at the first terminal T1 is transferred to the second terminal T2, and the voltage signal is used for identification by the internal gate threshold recognition circuit. When the voltage between the controllable terminal C and the second terminal T2 of the controllable switch MN0 is not greater than the threshold voltage of the controllable switch MN0, the controllable switch MN0 is almost turned off. At this time, the controllable switch MN0 can be regarded as a very large resistor, and a very small current flows from the first terminal T1 to the second terminal T2. The controllable terminal C of the controllable switch MN0 is connected to the power supply port VDD. When a high voltage is input to the first terminal T1 of the controllable switch MN0, and this high voltage exceeds the difference between the voltage of the power supply port VDD and the threshold voltage of the controllable switch MN0, the voltage of the second terminal T2 is controlled by the controllable terminal C to a suitable voltage value. A high voltage appears between the first terminal T1 and the second terminal T2 of the controllable switch MN0. The high voltage appearing at the first terminal T1 of the controllable switch MN0 is borne by the controllable switch MN0, thereby protecting the subsequent circuits connected to the second terminal T2 from breakdown.

[0034] The gate threshold recognition circuit 11 is connected to the second terminal T2 and the output port OUT. The gate threshold recognition circuit 11 is used to: enable the output port OUT to output a low level and pull down the voltage of the second terminal T2 when the voltage of the input port IN is lower than the low gate threshold voltage; and enable the output port OUT to output a high level and pull up the voltage of the second terminal T2 when the voltage of the input port IN is higher than the high gate threshold voltage. When the voltage of the input port IN is between the low and high gate threshold voltages, the output level of the output port OUT remains unchanged. That is, when the output port OUT originally outputs a low level, it remains low; when the output port OUT originally outputs a high level, it remains high. The low gate threshold voltage is less than the high gate threshold voltage.

[0035] The gate threshold identification circuit 11 is used to determine whether the voltage of the input signal is high or low, and controls the output port OUT to output the corresponding level signal. When the voltage of the input port IN is higher than the high gate threshold voltage, the gate threshold identification circuit 11 pulls up the voltage of the second terminal T2. When the voltage of the second terminal T2 is pulled up to a certain value, the controllable switch MN0 is turned off, the circuit current drops to a very small value, and the circuit power consumption is reduced.

[0036] In some embodiments, the controllable terminal C of the controllable switch MN0 is connected to the power supply port VDD, the first terminal T1 of the controllable switch MN0 is connected to the input port IN, and the gate threshold identification circuit 11 is connected to the second terminal T2 of the controllable switch MN0 and the output port OUT. The breakdown voltage between the controllable terminal C and the first terminal T1, and the breakdown voltage between the first terminal T1 and the second terminal T2, are both greater than the maximum voltage of the input port IN, and the threshold voltage of the controllable switch is less than the difference between the voltage of the power supply port VDD and the high gate threshold voltage of the logic gate input circuit 10. When the voltage of the input port IN is higher than the high gate threshold voltage, the controllable switch MN0 has voltage withstand capability and will not break down. The output port OUT outputs a high level, and the gate threshold identification circuit 11 pulls up the voltage of the second terminal T2. When the voltage of the second terminal T2 is pulled up to a certain value, the controllable switch MN0 is turned off, the circuit current drops to a very small value, the circuit power consumption is reduced, the circuit heat generation is reduced, and the reliability is improved. Thus, the logic gate input port IN withstands high voltage and has low power consumption. Except for the controllable switch MN0, no other high voltage-resistant components are required in the circuit, resulting in low circuit cost.

[0037] The logic gated input circuit 10 also includes a ground port GND for grounding.

[0038] The logic gated input circuit 10 also includes a resistor R1, which acts as a secondary protection against electrostatic discharge when electrostatic discharge occurs at the input port IN, preventing damage to subsequent circuits from electrostatic shock. Resistor R1 can be an independent resistor or a clamping resistor included in the controllable switch MN0.

[0039] The gate threshold voltage recognition circuit 11 includes a low gate threshold voltage recognition branch 12 and a high gate threshold voltage recognition branch 13. The inputs of both the low gate threshold voltage recognition branch 12 and the high gate threshold voltage recognition branch 13 are connected to the second terminal T2, and the outputs of both are connected to the output port OUT. The low gate threshold voltage recognition branch 12 is used to: enable the output port OUT to output a low level and pull down the voltage of the second terminal T2 when the voltage at the input port IN is lower than the low gate threshold voltage. The high gate threshold voltage recognition branch 13 is used to: enable the output port OUT to output a high level and pull up the voltage of the second terminal T2 when the voltage at the input port IN is higher than the high gate threshold voltage.

[0040] The input signal is input to the low gate threshold voltage recognition branch 12 and the high gate threshold voltage recognition branch 13 through the second terminal T2. The low gate threshold voltage recognition branch 12 identifies whether the input signal voltage is lower than the low gate threshold voltage. When the input signal is lower than the low gate threshold voltage, it pulls down the voltage at the second terminal T2, quickly cutting off the current between the input port IN and the second terminal T2 to prevent leakage. The high gate threshold voltage recognition branch 13 identifies whether the input signal voltage is higher than the high gate threshold voltage. When the input signal is higher than the high gate threshold voltage, it pulls up the voltage at the second terminal T2, causing the controllable switch MN0 to turn off, protecting subsequent circuits from damage due to excessive voltage.

[0041] The low gate threshold voltage identification branch 12 includes a first inverter circuit 121 and a first NOR gate I6. The first inverter circuit 121 includes an odd number of inverters connected in series. The high gate threshold voltage identification branch 13 includes a second inverter circuit 131 and a second NOR gate I7. The second inverter circuit 131 includes an even number of inverters connected in series. The input terminal of the first inverter circuit 121 is connected to the second terminal T2. ， The output of the first inverter circuit 121 is connected to the input of the first NOR gate I6. The input of the second inverter circuit 131 is connected to the second terminal T2, and the output of the second inverter circuit 131 is connected to the input of the second NOR gate I7. The output of the first NOR gate I6 is connected to the other input of the second NOR gate I7, the output of the second NOR gate I7 ​​is connected to the other input of the first NOR gate I6, and the output of the first NOR gate I6 is connected to the output port OUT.

[0042] exist Figure 1In the illustrated embodiment, the first inverter circuit 121 includes three inverters connected in series: a first inverter I1, a fourth inverter I4, and a third inverter I3. The second inverter circuit 131 includes two inverters connected in series: a second inverter I2 and a fifth inverter I5. The input terminal of the first inverter I1 is connected to the second terminal T2, the output terminal of the first inverter I1 is connected to the input terminal of the fourth inverter I4, the output terminal of the fourth inverter I4 is connected to the input terminal of the third inverter I3, and the output terminal of the third inverter I3 is connected to the input terminal of the first NOR gate I6. The input terminal of the second inverter I2 is connected to the second terminal T2, the output terminal of the second inverter I2 is connected to the input terminal of the fifth inverter I5, and the output terminal of the fifth inverter I5 is connected to the input terminal of the second NOR gate I7.

[0043] The first inverter I1, the fourth inverter I4, the third inverter I3, the second inverter I2, and the fifth inverter I5 invert the signal. When the input voltage is greater than the gate threshold voltage, the inverter outputs a low level; otherwise, it outputs a high level. The first NOR gate I6 and the second NOR gate I7 ​​are used to perform NOR operations on their respective input signals.

[0044] The gate threshold voltage of the first inverter I1 is a low gate threshold voltage. The gate threshold voltage of the second inverter I2 is a high gate threshold voltage.

[0045] Figure 2 As shown Figure 1 The circuit diagram shown is of one embodiment of the first inverter I1.

[0046] The first inverter circuit 121 includes a first inverter I1. The first inverter I1 includes a first transistor S1, a second transistor S2, and a first feedback transistor M1. The first transistor S1 and the second transistor S2 are connected in series between the power supply port VDD and the ground port GND. The controllable terminals of both the first transistor S1 and the second transistor S2 are connected to the second terminal T2. The output terminal YN1 of the first inverter I1 is connected between the first transistor S1 and the second transistor S2, and is also connected to the controllable terminal of the first feedback transistor M1, which is connected in series between the second terminal T2 and the ground port GND.

[0047] In some embodiments, the first transistor S1 includes a PMOS transistor, the second transistor S2 includes an NMOS transistor, and the first feedback transistor M1 includes an NMOS transistor.

[0048] The first transistor S1 and the second transistor S2 form an inverter, making the output signal at the output terminal YN1 the inverse of the signal at the second terminal T2. When the output terminal YN1 of the first inverter I1 outputs a high level, the first feedback transistor M1 is turned on, pulling the voltage at the second terminal T2 down to the ground port GND. This quickly cuts off the current flow between the input port IN and the second terminal T2, preventing leakage.

[0049] Figure 3 As shown Figure 1 The circuit diagram shows one embodiment of the second inverter I2.

[0050] The second inverter circuit 131 includes a second inverter I2. The second inverter I2 includes a third transistor S3, a fourth transistor S4, and a second feedback transistor M2. The third transistor S3 and the fourth transistor S4 are connected in series between the power supply port VDD and the ground port GND. The controllable terminals of both the third transistor S3 and the fourth transistor S4 are connected to the second terminal T2. The output terminal YN4 of the second inverter I2 is connected between the third transistor S3 and the fourth transistor S4, and is also connected to the controllable terminal of the second feedback transistor M2, which is connected in series between the power supply port VDD and the second terminal T2.

[0051] In some embodiments, the third transistor S3 includes a PMOS transistor, the fourth transistor S4 includes an NMOS transistor, and the second feedback transistor M2 includes a PMOS transistor.

[0052] The third transistor S3 and the fourth transistor S4 form an inverter, making the output signal at the output terminal YN4 the inverse of the signal at the second terminal T2. When the output terminal YN4 of the second inverter I2 outputs a low level, the second feedback transistor M2 is turned on, pulling the voltage at the second terminal T2 up to the power supply port VDD. This causes the controllable switch MN0 to be turned off, and the controllable switch MN0 presents a high-impedance state. When the voltage at the input port IN is less than the breakdown voltage of the controllable switch MN0, the voltage will not enter the subsequent circuit through the controllable switch MN0, thus protecting the subsequent circuit and preventing breakdown due to high voltage.

[0053] Figure 4 As shown Figure 1 The diagram shows the waveforms of the input and output signals of the logic gated input circuit 10. IN represents the signal waveform at the input port IN, OUT represents the signal waveform at the output port OUT, VTH_H is the high gate threshold voltage, and VTH_L is the low gate threshold voltage. When the input signal IN is higher than the high gate threshold voltage VTH_H, the output signal OUT is high; when the input signal IN is lower than the low gate threshold voltage VTH_L, the output signal OUT is low.

[0054] like Figure 4As shown, when the power supply port VDD and the ground port GND are powered on, the input signal IN is first set to a low level. At this time, the input voltage of the first inverter I1 (i.e., the voltage at the second terminal T2) is lower than the gate threshold voltage of the first inverter I1, so the first inverter I1 outputs a high level, the fourth inverter I4 outputs a low level, and the third inverter I3 outputs a high level. Figure 2 It can be seen that when the output terminal YN1 outputs a high level, the first feedback transistor M1 is turned on, pulling the voltage at the second terminal T2 down to the ground terminal GND. At this time, the input voltage of the second inverter I2 (i.e., the voltage at the second terminal T2) is lower than the gate threshold voltage of the second inverter I2, so the second inverter I2 outputs a high level, and the fifth inverter I5 outputs a low level. Figure 3 As can be seen, the output terminal YN4 outputs a high level, and the second feedback transistor M2 is cut off. The output port OUT outputs a low level.

[0055] When the input signal IN gradually rises from a low level to a high level, the threshold voltage of the controllable switch MN0 is V. THN When the input signal IN is lower than (VDD-V THN When IN is turned on, the controllable switch MN0 is turned on. The controllable switch MN0 can be regarded as a resistor with a very small resistance. The input port IN and the second terminal T2 form a low-impedance path. The voltage V at the second terminal T2 is V. T2 Voltage V at input port IN IN They can be considered equal. When V IN When the voltage rises to the gate threshold voltage VTH_L of the first inverter I1, the output of the first inverter I1 goes low, the first feedback transistor M1 is turned off, and the voltage V at the second terminal T2 is no longer pulled down. T2 The fourth inverter I4 outputs a high level, and the third inverter I3 outputs a low level. At this time, the output of the first NOR gate I6 is only controlled by the output of the second NOR gate I7. When V... IN When the voltage rises to the gate threshold voltage VTH_H of the second inverter I2, the second inverter I2 outputs a low level, the fifth inverter I5 outputs a high level, the second NOR gate I7 ​​outputs a low level, and the first NOR gate I6 outputs a high level, meaning the output port OUT outputs a high level. After the output port OUT outputs a high level, the output of the second NOR gate I7 ​​no longer affects the output of the output port OUT; the output of the output port OUT is now only controlled by the output of the first inverter I1.

[0056] When V IN When the voltage rises to a level greater than the gate threshold voltage VTH_H of the second inverter I2, the output of the second inverter I2 goes low, and the second feedback transistor M2 turns on, turning on VTH_H. T2 Pull it up to VDD, so that when V INWhen the voltage is greater than VTH_H and less than VDD, leakage current caused by the conduction of the first transistor S1, second transistor S2, third transistor S3, and fourth transistor S4 inside the first inverter I1 and the second inverter I2 can be prevented. Furthermore, because V... T2 Pulling the switch up to VDD cuts off the controllable switch MN0. At this point, MN0 can be considered a resistor with a very high resistance, and the current in its branch is very small. If VDD is pulled up, the controllable switch MN0 will be cut off. IN Even with continued voltage increases, the high voltage cannot reach the second terminal T2 through the controllable switch MN0, thus protecting the subsequent circuitry and enabling the logic gate input circuit 10 to withstand high voltage. Since the controllable switch MN0 is a voltage-resistant component, V... IN To prevent leakage of the controllable switch MN0 due to high voltage, thus preventing circuit breakdown and damage, the pre-stage drive of the logic gate input circuit 10 will not generate additional losses, thereby reducing power consumption.

[0057] When V IN The voltage level flips from high to low when V IN Decrease to V T2 When the voltage difference is approximately equal to the forward conduction voltage of the controllable switch MN0, the controllable switch MN0 conducts, V T2 With V IN The decrease is due to the decrease in V. IN When the voltage drops to the gate threshold voltage VTH_H of the second inverter I2, the output of the second inverter I2 goes high, the second feedback transistor M2 turns off, and the pull-up of VTH_H stops. T2 When V IN The voltage continues to drop to the gate threshold voltage VTH_L of the first inverter I1. The first inverter I1 outputs a high level, the second inverter I4 outputs a low level, and the third inverter I3 outputs a high level. The output port OUT flips from high to low. After the output port OUT outputs a low level, because the second inverter I2 outputs a high level and the second NOR gate I7 ​​outputs a high level, the output port OUT remains low.

[0058] When V IN When the voltage drops to the gate threshold voltage VTH_L of the first inverter I1, the first inverter I1 outputs a high level, the first feedback transistor M1 turns on, and V... T2 Pull down to GND, so that V T2 With V IN The potential difference is less than the forward conduction voltage of the controllable switch MN0, preventing slow leakage of the parasitic diode between the second terminal T2 and the input port IN.

[0059] Figure 5 As shown Figure 1 A circuit diagram of another embodiment of the logic gated input circuit 10 shown.

[0060] The logic gated input circuit 10 includes a clamping resistor (not shown) connected to the first terminal T1 and the input port IN. The controllable switch MN0 includes a clamping resistor to absorb electrostatic discharge (ESD) at the input port IN.

[0061] Figure 6 As shown Figure 1 A circuit diagram of another embodiment of the logic gated input circuit 10 shown.

[0062] The logic gated input circuit 10 also includes a standby circuit 14, which is connected to the input port IN and the ground port GND.

[0063] The standby circuit 14 is used to put the logic gated input circuit 10 into a low-power sleep mode. When there is no input signal at the input port IN, the logic gated input circuit 10 does not need to work and enters a sleep state. When there is an input signal at the input port IN, the standby circuit can quickly wake up the logic gated input circuit 10 and put it into working state.

Claims

1. A logic gated input circuit, characterized in that, include: Input port, output port, power port; A controllable switch includes a controllable terminal, a first terminal, and a second terminal. The controllable terminal is connected to the power supply port, and the first terminal is connected to the input port. The breakdown voltage between the controllable terminal and the first terminal, and the breakdown voltage between the first terminal and the second terminal, are both greater than the maximum voltage of the input port. The threshold voltage of the controllable switch is less than the difference between the voltage of the power supply port and the high gate threshold voltage of the logic gate input circuit. A gate threshold recognition circuit is connected to the second terminal and the output port; the gate threshold recognition circuit is used to: when the voltage of the input port is lower than the low gate threshold voltage, cause the output port to output a low level and pull down the voltage of the second terminal; when the voltage of the input port is higher than the high gate threshold voltage, cause the output port to output a high level and pull up the voltage of the second terminal; when the voltage of the input port is between the low gate threshold voltage and the high gate threshold voltage, the output level of the output port remains unchanged; the low gate threshold voltage is less than the high gate threshold voltage.

2. The logic gated input circuit according to claim 1, characterized in that, The gate threshold voltage recognition circuit includes a low gate threshold voltage recognition branch and a high gate threshold voltage recognition branch. The input terminals of both the low gate threshold voltage recognition branch and the high gate threshold voltage recognition branch are connected to the second terminal. The output terminals of both the low gate threshold voltage recognition branch and the high gate threshold voltage recognition branch are connected to the output port. The low gate threshold voltage recognition branch is used to: when the voltage of the input port is lower than the low gate threshold voltage, cause the output port to output a low level and pull down the voltage of the second terminal; the high gate threshold voltage recognition branch is used to: when the voltage of the input port is higher than the high gate threshold voltage, cause the output port to output a high level and pull up the voltage of the second terminal; when the voltage of the input port is between the low gate threshold voltage and the high gate threshold voltage, the output level of the output port remains unchanged.

3. The logic gated input circuit according to claim 2, characterized in that, The low gate threshold voltage identification branch includes a first inverter circuit and a first NOR gate; the first inverter circuit includes an odd number of inverters connected in series; the high gate threshold voltage identification branch includes a second inverter circuit and a second NOR gate; the second inverter circuit includes an even number of inverters connected in series; the input terminal of the first inverter circuit is connected to the second terminal. ， The output of the first inverter circuit is connected to the input of the first NOR gate; the input of the second inverter circuit is connected to the second terminal, and the output of the second inverter circuit is connected to the input of the second NOR gate. The output of the first NOR gate is connected to the other input of the second NOR gate, the output of the second NOR gate is connected to the other input of the first NOR gate, and the output of the first NOR gate is connected to the output port.

4. The logic gated input circuit according to claim 3, characterized in that, The logic gated input circuit further includes a ground port; the first inverter circuit includes a first inverter; the first inverter includes a first transistor, a second transistor, and a first feedback transistor; the first transistor and the second transistor are connected in series between the power supply port and the ground port, the controllable terminals of the first transistor and the second transistor are both connected to the second terminal, the output terminal of the first inverter is connected between the first transistor and the second transistor, and is connected to the controllable terminal of the first feedback transistor, the first feedback transistor is connected in series between the second terminal and the ground port.

5. The logic gated input circuit according to claim 4, characterized in that, The first transistor includes a PMOS transistor, the second transistor includes an NMOS transistor, and the first feedback transistor includes an NMOS transistor.

6. The logic gated input circuit according to claim 3, characterized in that, The logic gated input circuit further includes a ground port; the second inverter circuit includes a second inverter; the second inverter includes a third transistor, a fourth transistor, and a second feedback transistor; the third transistor and the fourth transistor are connected in series between the power supply port and the ground port, the controllable terminals of the third transistor and the fourth transistor are both connected to the second terminal, the output terminal of the second inverter is connected between the third transistor and the fourth transistor, and is connected to the controllable terminal of the second feedback transistor, the second feedback transistor is connected in series between the power supply port and the second terminal.

7. The logic gated input circuit according to claim 6, characterized in that, The third transistor includes a PMOS transistor, the fourth transistor includes an NMOS transistor, and the second feedback transistor includes a PMOS transistor.

8. The logic gated input circuit according to claim 1, characterized in that, The logic gated input circuit includes a pressure resistor connected to the first terminal and the input port.

9. The logic gated input circuit according to claim 1, characterized in that, The logic gated input circuit includes a standby circuit and a ground port, and the standby circuit is connected to the input port and the ground port.

10. The logic gated input circuit according to claim 1, characterized in that, The breakdown voltage between the controllable terminal and the second terminal is greater than the maximum voltage of the input port.

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