A dual-channel asynchronous clocking circuit for a successive approximation analog-to-digital converter

Abstract

The application belongs to the technical field of analog integrated circuit design, and particularly discloses a double-channel asynchronous clock circuit for a successive approximation type analog-digital converter, which is used for providing a working clock for the internal circuit of the analog-digital converter; the double-channel asynchronous clock circuit comprises an NAND gate, an NOR gate, an AND gate, a first data selector, a second data selector, a long delay path and a short delay path; in the working process of the analog-digital converter, the application selects different delay paths through the data selectors to provide different working cycle lengths for the circuit; compared with the traditional asynchronous clock circuit, the application can adapt to the different working time requirements brought by different stages of the circuit to optimize the circuit speed and area; meanwhile, the application has a simple structure, is easy to implement and does not need additional external control ports.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit design technology, specifically relating to a dual-channel asynchronous clock circuit for a successive approximation analog-to-digital converter. Background Technology

[0002] Analog-to-digital converters (ADCs) serve as a bridge connecting the real world and the digital world, occupying the front end of the processing chain and playing a crucial role in modern electronic systems. In order to monitor and exchange different types of information in the environment and transmit them to the back-end digital processing system, the required ADC conversion rates range from hundreds of Hz to hundreds of MHz.

[0003] Among various types of analog-to-digital converters (ADCs), the successive approximation register (SAR) ADC has become a hot topic in current ADC research due to its advantages such as high degree of digitization, good compatibility with advanced processes, and low power consumption.

[0004] The bit-by-bit quantization operation of SAR ADCs requires an additional control clock besides the system clock for internal circuitry. This can be achieved in two ways: synchronous clock and asynchronous clock. A synchronous clock refers to a fixed-frequency external clock input. This method requires an external clock generation circuit for the ADC. This approach has poor time allocation flexibility, limiting speed improvements and diminishing the power consumption advantages of the SAR ADC structure. An asynchronous clock is generated internally by the SAR ADC, using simple logic gates and delay circuits to generate the clock signal. The clock speed can be dynamically adjusted according to the progress of the internal circuitry, which can compensate for some of the shortcomings of synchronous clocks, but some problems still exist.

[0005] In the operation of a SAR ADC, the voltage build-up of the capacitor array is the main factor limiting the operating speed. Since there is no significant flag signal indicating the completion of voltage build-up on the capacitor array, the traditional approach is to add a delay to the asynchronous clock to estimate the build-up time. However, in classic SAR ADC structures, the capacitor array often uses a binary structure, and the capacitance size increases exponentially with the number of bits. This leads to an exponential increase in the capacitor build-up time constant RC, resulting in a significant difference in the build-up time required for high-order and low-order capacitors. Due to the single-delay structure in traditional asynchronous clocks, this delay must meet the worst-case build-up time requirement of the high-order bits, which significantly slows down the ADC's operating speed, wastes the build-up time of the low-order capacitors, and leads to a dilemma similar to that of synchronous clocks, which can only be improved by increasing the size of the switches in the high-order bits. Therefore, there is an urgent need for an improved asynchronous clock circuit to reduce the waste of build-up time, optimize and improve the ADC's operating speed, and reduce the circuit area. Summary of the Invention

[0006] To address the problems existing in the prior art, this invention proposes a dual-channel asynchronous clock circuit for successive approximation analog-to-digital converters. Based on the traditional asynchronous clock, it adds an additional short-delay path and a corresponding path selection circuit to reduce clock delay at appropriate times, providing different settling times for the high and low level capacitors of the SAR ADC capacitor array, thereby optimizing the operating speed and reducing the size of the switching circuit. Furthermore, the path switching utilizes the internal logic unit signals of the SAR ADC, eliminating the need for additional external port control.

[0007] Specifically, the present invention provides a dual-channel asynchronous clock circuit for a successive approximation analog-to-digital converter (ADC), which is connected between the comparator and the SAR logic circuit of the ADC. The output of the dual-channel asynchronous clock circuit outputs a comparator control signal and a SAR logic circuit control signal to the comparator and the SAR logic circuit, respectively. The SAR logic circuit outputs a selector control signal and an ADC quantization completion flag signal to the dual-channel asynchronous clock circuit. At the same time, the system clock signal and the differential output of the comparator are both connected to the dual-channel asynchronous clock circuit. The dual-channel asynchronous clock circuit includes a NAND gate, a NOR gate, an AND gate, a first data selector, a second data selector, a long delay path, and a short delay path. The first and second inputs of the NAND gate are respectively connected to the differential output of the comparator, used to output SAR logic circuit control signals to the SAR logic circuit, and simultaneously connected to the input of the first data selector. The input of the first data selector is connected to the output of the NAND gate. The input of the long delay path is connected to the first output of the first data selector, and the output of the long delay path is connected to the first input of the second data selector. The input of the short delay path is connected to the second output of the first data selector, and the output of the short delay path is connected to the second input of the second data selector. The output of the second data selector is connected to the input of the NOR gate. The other input of the NOR gate is connected to the system clock signal. The output of the NOR gate is connected to the input of the AND gate. The other input of the AND gate is connected to the quantization completion flag signal of the analog-to-digital converter. The output of the AND gate generates a comparator control signal and is connected to the clock input of the comparator. After the comparator completes its operation, the output of the NAND gate generates a SAR logic circuit control signal and outputs it to the SAR logic circuit. The SAR logic circuit is used to complete the shifting and storage of digital codes by the successive approximation analog-to-digital converter. During the establishment of high and low level capacitors by the successive approximation analog-to-digital converter, the switching between the long delay path and the short delay path is controlled by the selector control signal generated by the SAR logic circuit itself.

[0008] Furthermore, the control terminals of both the first data selector and the second data selector are connected to a selector control signal; the selector control signal is used to control the first data selector to select one output terminal to output the signal received at its input terminal, and to control the second data selector to select one input terminal to input; When the selector control signal is low, the first data selector selects the first output terminal for output, and the second data selector selects the first input terminal for input. When the selector control signal is high, the first data selector selects the second output terminal for output, and the second data selector selects the second input terminal for input.

[0009] Furthermore, the long delay path is composed of an even number of cascaded basic delay units, and each basic delay unit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The source of the first PMOS transistor is connected to a power supply, and the source of the second PMOS transistor is connected to the gate and drain of the first PMOS transistor; the gate of the second PMOS transistor is connected to the gate of the first NMOS transistor and serves as the input terminal of each stage of the basic delay unit; the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor and serves as the output terminal of each stage of the basic delay unit; the source of the first NMOS transistor is connected to the gate and drain of the second NMOS transistor, and the source of the second NMOS transistor is grounded; The input terminal of the first-level basic delay unit is the input terminal of the long delay path. The input terminal of each level of the basic delay unit is connected to the output terminal of the previous level of the basic delay unit. The output terminal of the last level of the basic delay unit is the output terminal of the long delay path.

[0010] Furthermore, the short delay path consists of a basic delay unit and an inverter cascaded together, the inverter including a third PMOS transistor and a third NMOS transistor; The source of the third PMOS transistor is connected to the power supply, the gate of the third PMOS transistor is connected to the gate of the third NMOS transistor and is the input terminal of the inverter; the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor and is the output terminal of the inverter; the source of the third NMOS transistor is grounded. The input terminal of the basic delay unit is the input terminal of the short delay path, the output terminal of the basic delay unit is connected to the input terminal of the inverter, and the output terminal of the inverter is the output terminal of the short delay path.

[0011] Compared with the prior art, the present invention has the following beneficial technical effects: The dual-channel asynchronous clock circuit of this invention can switch between long delay paths and short delay paths, reduce clock delay at appropriate times, and provide different setup times for the high and low level capacitors of the SAR ADC capacitor array, so as to optimize the working speed and reduce the size of the switching circuit, achieving a trade-off between working speed and setup accuracy. The switching of the delay path is controlled by the internal signal of the circuit, requiring only a small amount of circuit cost and no additional external port control. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein: Figure 1 A schematic diagram of the dual-channel asynchronous clock circuit provided by the present invention in an ADC; Figure 2 The dual-channel asynchronous clock circuit structure provided by this invention; Figure 3 The timing cycle composition of the asynchronous clock generation signal in the SAR ADC working process provided by the present invention; Figure 4 This invention provides a long delay path structure in a dual-channel asynchronous clock. Figure 5 This invention provides a short-delay path structure in a dual-channel asynchronous clock. Figure 6 A timing comparison diagram of the dual-channel asynchronous clock and the traditional asynchronous clock provided by this invention. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0014] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0015] In the description of this invention, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings, or the orientation or positional relationships commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0016] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0017] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0018] like Figure 1 As shown, this invention proposes a dual-channel asynchronous clock circuit for a successive approximation analog-to-digital converter (ADC). The circuit is connected between the comparator and the SAR logic circuit of the ADC. The dual-channel asynchronous clock circuit outputs the comparator control signal CLKC and the SAR logic circuit control signal Valid to the comparator and SAR logic circuit, respectively. The SAR logic circuit outputs the selector control signal SEL and the ADC quantization completion flag signal FIN to the dual-channel asynchronous clock circuit. Simultaneously, the system clock signal CLKS and the differential output of the comparator are both connected to the dual-channel asynchronous clock circuit. In some embodiments of the present invention, in the analog-to-digital converter (ADC), the input signal Vin is connected to a capacitor array via a sampling switch. The sampling switch controls the input signal Vin to be sampled onto the capacitor array. The differential input terminal of the comparator is connected to the output terminal of the capacitor array and the power supply voltage. The differential output terminal of the comparator is connected to the SAR logic circuit and the dual-channel asynchronous clock circuit. The dual-channel asynchronous clock circuit provides the comparator control signal CLKC and the SAR logic circuit control signal Valid to the comparator and the SAR logic circuit. At the same time, the system clock signal CLKS, the differential output terminal of the comparator, and the output terminal of the SAR logic circuit serve as the input signals of the dual-channel asynchronous clock circuit to control the generation of the comparator control signal CLKC. The SAR logic circuit control signal Valid is used to control the operation of the SAR logic circuit. When the dual-channel asynchronous clock circuit outputs the SAR logic circuit control signal Valid to the SAR logic circuit, the SAR logic circuit completes the shifting and storage of digital code in the successive approximation ADC and outputs the digital code <1:N>, as well as the output selector control signal SEL and the quantization completion flag signal FIN of the ADC to the dual-channel asynchronous clock circuit.

[0019] like Figure 2 As shown, the dual-channel asynchronous clock circuit includes a NAND gate, a NOR gate, an AND gate, a first data selector, a second data selector, a long delay path, and a short delay path. The first and second inputs of the NAND gate are connected to the differential output of the comparator, respectively, to output SAR logic circuit control signals to the SAR logic circuit, and are also connected to the input of the first data selector. The input of the first data selector is connected to the output of the NAND gate. The input of the long delay path is connected to the first output of the first data selector, and the output of the long delay path is connected to the first input of the second data selector. The input of the short delay path is connected to the second output of the first data selector, and the output of the short delay path is connected to the second input of the second data selector. The output of the second data selector is connected to the input of the NOR gate. The other input of the NOR gate is connected to the system clock signal CLKS. The output of the NOR gate is connected to the input of the AND gate. The other input of the AND gate is connected to the quantization completion flag signal FIN of the analog-to-digital converter. The output of the AND gate generates a comparator control signal CLKC and is connected to the clock input of the comparator.

[0020] In some embodiments of the present invention, the input terminal of the first data selector is a single-port terminal, and the output terminal is a dual-port terminal. The first output terminal of the first data selector is the "0" terminal of its dual-port terminal, and the second output terminal is the "1" terminal of its dual-port terminal. The input terminal of the second data selector is a dual-port terminal, and the output terminal is a single-port terminal. The first input terminal of the second data selector is the "0" terminal of its dual-port terminal, and the second input terminal is the "1" terminal of its dual-port terminal. In the dual-channel asynchronous clock circuit, after the comparator completes its operation, the output terminal of the NAND gate generates the SAR logic circuit control signal Valid, which controls the operation of the SAR logic circuit. During the establishment of high and low level capacitors in the successive approximation analog-to-digital converter, the SAR logic circuit realizes the switching between the long delay path and the short delay path, thereby improving the operating speed of the analog-to-digital converter. When the dual-channel asynchronous clock circuit is not working, the differential outputs of the comparator are all high, connected to the first and second inputs of the NAND gate respectively, controlling the output of the NAND gate to be low. The output of the NAND gate is the SAR logic circuit control signal Valid, controlling the operation of the SAR logic circuit. Simultaneously, the SAR logic circuit control signal Valid is connected to the input of the first data selector. The control terminals of the first and second data selectors are connected to the selector control signal SEL generated by the SAR logic circuit itself during shift operations, controlling the switching between long and short delay paths. When the selector control signal SEL is low, the first output "0" of the first data selector is turned on. After passing through an even number of basic delay units (long delay path), it generates a low level, which is connected to the first input "0" of the second data selector. The output of the second data selector outputs a low level and is connected to the input of the NOR gate. The other input of the NOR gate is connected to the system clock signal CLKS, which is high. The NOR gate output is fixed at a low level and connected to the AND gate input. The other output of the AND gate is connected to the quantization completion flag signal FIN of the analog-to-digital converter (ADC), which is high. The comparator control signal CLKC output from the AND gate is fixed at a low level and connected to the comparator output. The dual-channel asynchronous clock circuit starts working when the system clock signal CLKS changes from high to low. The system clock signal CLKS is connected to the NOR gate input, and the other input of the NOR gate is connected to the output of the second data selector, which is low when not working. Therefore, the NOR gate output changes from low to high and is connected to the AND gate input. The output voltage is controlled by the voltage at the other end. The ADC quantization completion flag signal FIN of the AND gate is also high, so the output also changes from low to high and is controlled by the voltage at the other end. The arrival of the rising edge of the comparator control signal CLKC at the AND gate output controls the comparator to start working.

[0021] Specifically, the control terminals of both the first and second data selectors are connected to the selector control signal SEL. The selector control signal SEL is used to control the first data selector to select one output terminal to output the signal received at its input terminal, and to control the second data selector to select one input terminal to input. When the selector control signal SEL is low, the first data selector selects the first output terminal "0" to output, and the second data selector selects the first input terminal "0" to input. When the selector control signal SEL is high, the first data selector selects the second output terminal "1" to output, and the second data selector selects the second input terminal "1" to input.

[0022] In some embodiments of the present invention, a first data selector is used as a gating switch; the single-port terminal of the first data selector is connected to the output terminal of a NAND gate, the "0" terminal of its two-port terminal is connected to the input terminal of a long delay path, and the "1" terminal of its two-port terminal is connected to the input terminal of a short delay path; the control port of the first data selector is connected to the selector control signal SEL; the single-port terminal of the second data selector is connected to the input terminal of a NOR gate, the "0" terminal of its two-port terminal is connected to the output terminal of a long delay path, and the "1" terminal of its two-port terminal is connected to the output terminal of a short delay path; the control port of the second data selector is connected to the selector control signal SEL.

[0023] like Figure 3 As shown, CLKS is the system clock signal, CLKC is the comparator control signal, Valid is the SAR logic circuit control signal, and V... DACp and V DACn These are the time-domain waveforms of the positive and negative input signals of the comparator, respectively; V DACp and V DACn This reflects the charging process of the capacitor, and its working principle is equivalent to a first-order RC circuit model. The longer the charging time, the more fully the capacitor is built up; in the figure, τ set The charging time for the capacitor; the dual-channel asynchronous clock circuit starts working when the system clock signal CLKS changes from high to low. From the drop in the system clock signal CLKS to the generation of the comparator control signal CLKC, the time elapsed is τ2, which includes a short delay of one NOR gate and one AND gate. After the comparator comparison is complete, one end of the differential output will become low, while the other end remains high. After inputting into the NAND gate, the SAR logic circuit control signal Valid at the NAND gate output becomes high, indicating that the comparator comparison is complete. Figure 3As shown, the rise of the comparator control signal CLKC to the SAR logic circuit control signal Valid is delayed by τ3, including a comparator comparison delay and a NAND gate delay, with the comparator delay being the main part. The SAR logic circuit control signal Valid is connected to the input of the first data selector. Under the control of the selector control signal SEL, it is output through the first output terminal "0" and connected to the input of the long delay path. After the long delay, it is output from the output of the long delay path and input to the first input terminal "0" of the second data selector. The output of the second data selector is high and connected to the input of the NOR gate. The high-level signal at the input of the NOR gate controls the output to become low and is input to the input of the AND gate. The low-level signal at the gate input controls the comparator control signal CLKC at the output to go low. The rise of the SAR logic circuit control signal Valid and the fall of the comparator control signal CLKC are followed by a delay τ1, which mainly includes a long delay path delay, a first data selector delay, a second data selector delay, and a logic gate delay, with the long delay path delay being the dominant factor. After the comparator control signal CLKC falls, the differential output of the comparator is reset to a high level, and the NAND gate output is low, thus completing one working cycle. The fall of the comparator control signal CLKC and the fall of the SAR logic circuit control signal Valid are followed by a delay τ4, which includes a comparator reset delay and a NAND gate delay, with the comparator reset delay being the dominant factor. For the switching between long and short delay paths in a dual-channel asynchronous clock circuit, the clock circuit first operates in the long delay path. This is because the switching of the SAR ADC occurs first at the large capacitor in the high-order bit, requiring a longer setup time. After several quantization cycles, the size of the quantization capacitor decreases significantly, and the setup time requirement also decreases significantly. At this time, the selector control signal SEL generated internally by the SAR logic circuit in the corresponding bit becomes high. Under the control of the selector control signal SEL, the first data selector outputs through the second output terminal "1" and connects to the input terminal of the short delay path. After a short delay, the output terminal of the short delay path outputs and inputs to the second input terminal "1" of the second data selector, outputting a high level at the single-port terminal. Then, based on this short delay, subsequent quantization with small capacitors is performed until quantization is complete. Except for the long and short delay paths, the workflow of the low and high orders is the same, realizing the switching of its own operating mode by using the circuit's own working progress, that is, the signals inside the circuit, without the need to add additional detection circuits or external configuration pins to distinguish between high and low orders.

[0024] Therefore, the operating cycle of a dual-channel asynchronous clock circuit includes delays from two delay circuits, comparator comparison and reset delays, and logic gate delays. The delays from the two delay circuits are dominant, thus adjusting the delay circuits significantly affects the ADC's operating speed. Furthermore, capacitor build-up occurs during capacitor charging τ.set During this period, there are two delay circuits, a comparator reset delay, and a NAND gate delay. The delay circuits are the dominant part, so the settling time reserved for the capacitor can be adjusted by adjusting the delay circuits.

[0025] like Figure 4 As shown, the long delay path consists of an even number of cascaded basic delay units. Each basic delay unit includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, and a second NMOS transistor N2. The source of the first PMOS transistor P1 is connected to the power supply, and the source of the second PMOS transistor P2 is connected to the gate and drain of the first PMOS transistor P1. The gate of the second PMOS transistor P2 is connected to the gate of the first NMOS transistor N1 and serves as the output for each basic delay unit. The input terminal is connected to the drain of the first NMOS transistor N1, and is also the output terminal of each basic delay unit. The source of the first NMOS transistor N1 is connected to the gate of the second NMOS transistor N2 and the drain of the second NMOS transistor N2, and the source of the second NMOS transistor N2 is grounded. The input terminal of the first basic delay unit is the input terminal of the long delay path. The input terminal of each basic delay unit is connected to the output terminal of the previous basic delay unit. The output terminal of the last basic delay unit is the output terminal of the long delay path.

[0026] like Figure 5 As shown, the short delay path consists of a basic delay unit and an inverter cascaded together. The inverter includes a third PMOS transistor P3 and a third NMOS transistor N3. The source of the third PMOS transistor P3 is connected to the power supply, and the gate of the third PMOS transistor P3 is connected to the gate of the third NMOS transistor N3, serving as the input terminal of the inverter. The drain of the third PMOS transistor P3 is connected to the drain of the third NMOS transistor N3, serving as the output terminal of the inverter. The source of the third NMOS transistor N3 is grounded. The input terminal of the basic delay unit is the input terminal of the short delay path, the output terminal of the basic delay unit is connected to the input terminal of the inverter, and the output terminal of the inverter is the output terminal of the short delay path.

[0027] In some embodiments of the present invention, the basic delay unit is an inverter with a tail current transistor, wherein the drain and gate of the first PMOS transistor P1 are connected to the source of the second PMOS transistor P2 to form a diode connection, and the drain and gate of the second NMOS transistor N2 are connected to the source of the first NMOS transistor N1 to form a diode connection. The delay of the basic delay unit has a more obvious delay effect, lower power consumption and stronger stability compared with the delay of the inverter.

[0028] like Figure 6The diagram shows a timing comparison between the present invention and a traditional asynchronous clock. When the circuit described in this invention operates, after multiple quantization cycles, the corresponding SAR logic circuit generates a high-level shift signal to control the operation of the next logic unit. This invention utilizes this signal as the selector control signal SEL. Under the control of the selector control signal SEL, the first data selector outputs through its second output terminal "1" and connects to the input terminal of the short delay path. After a short delay, the output terminal of the short delay path outputs and inputs to the second input terminal "1" of the second data selector, resulting in a high-level output at the single-port terminal. Subsequent small-capacitor quantization is then performed based on this short delay until quantization is complete. Figure 6 It can be seen that the high-bit speed is comparable to the traditional structure, but it is significantly faster in the low-bit stage, shortening the low-bit cycle that does not require long waiting. After quantization, the last bit of the SAR logic circuit outputs a high-level signal, which is used as the quantization completion flag signal FIN of the analog-to-digital converter. After being turned low by an inverter, it controls the output of the AND gate to go low, and the asynchronous clock stops working.

[0029] In SAR ADC capacitor arrays, the capacitance size increases exponentially from low to high bits, resulting in significant differences in voltage settling time. Traditional asynchronous clocks use a coarse structure with a single delay, which easily leads to wasted time. The dual-channel asynchronous clock circuit of this invention sets different delays for the high and low bit capacitors based on this situation. By switching between long and short delay paths, the speed and switching circuit area are optimized, achieving a trade-off between operating speed and settling accuracy. It is controlled by internal circuit signals, requiring only a small amount of circuit cost and no external ports.

[0030] The embodiments given above are preferred examples for implementing the present invention, and the present invention is not limited to the above embodiments. Any non-essential additions or substitutions made by those skilled in the art based on the technical features of the present invention are within the protection scope of the present invention.

Claims

1. A dual-channel asynchronous clock circuit for a successive approximation analog-to-digital converter, connected between the comparator and the SAR logic circuit of the successive approximation analog-to-digital converter, characterized in that, The output terminal of the dual-channel asynchronous clock circuit outputs comparator control signal and SAR logic circuit control signal to the comparator and the SAR logic circuit respectively. The SAR logic circuit outputs selector control signal and analog-to-digital converter quantization completion flag signal to the dual-channel asynchronous clock circuit. At the same time, the system clock signal and the differential output terminal of the comparator are both connected to the dual-channel asynchronous clock circuit. The dual-channel asynchronous clock circuit includes NAND gates, NOR gates, AND gates, a first data selector, a second data selector, a long delay path, and a short delay path. The first and second inputs of the NAND gates are respectively connected to the differential output of the comparator, used to output SAR logic circuit control signals to the SAR logic circuit, and simultaneously connected to the input of the first data selector. The input of the long delay path is connected to the first output of the first data selector, and the output of the long delay path is connected to the first input of the second data selector. The input of the short delay path... The output of the short delay path is connected to the second output of the first data selector, and the output of the short delay path is connected to the second input of the second data selector. The output of the second data selector is connected to the input of the NOR gate, the other input of the NOR gate is connected to the system clock signal, the output of the NOR gate is connected to the input of the AND gate, the other input of the AND gate is connected to the quantization completion flag signal of the analog-to-digital converter, and the output of the AND gate generates a comparator control signal and is connected to the clock input of the comparator. Both the long delay path and the short delay path are composed of basic delay units. After the comparator completes its operation, the output of the NAND gate generates a SAR logic circuit control signal and outputs it to the SAR logic circuit. The SAR logic circuit is used to complete the shifting and storage of digital codes by the successive approximation analog-to-digital converter. During the process of establishing high and low level capacitors in the successive approximation analog-to-digital converter, the switching between the long delay path and the short delay path is controlled by the selector control signal generated by the SAR logic circuit itself.

2. The dual-channel asynchronous clock circuit for a successive approximation analog-to-digital converter according to claim 1, characterized in that, The control terminals of both the first data selector and the second data selector are connected to a selector control signal; the selector control signal is used to control the first data selector to select one output terminal to output the signal received at its input terminal, and to control the second data selector to select one input terminal to input, thereby controlling the switching of the delay path; When the selector control signal is low, the first data selector selects its first output terminal to output, and the second data selector selects its first input terminal to input. When the selector control signal is high, the first data selector selects its second output terminal for output, and the second data selector selects its second input terminal for input.

3. The dual-channel asynchronous clock circuit for a successive approximation analog-to-digital converter according to claim 1, characterized in that, The long delay path is composed of an even number of cascaded basic delay units, and each basic delay unit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The source of the first PMOS transistor is connected to a power supply, and the source of the second PMOS transistor is connected to the gate and drain of the first PMOS transistor; the gate of the second PMOS transistor is connected to the gate of the first NMOS transistor and serves as the input terminal of each stage of the basic delay unit; the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor and serves as the output terminal of each stage of the basic delay unit; the source of the first NMOS transistor is connected to the gate and drain of the second NMOS transistor, and the source of the second NMOS transistor is grounded; The input terminal of the first-level basic delay unit is the input terminal of the long delay path. The input terminal of each level of the basic delay unit is connected to the output terminal of the previous level of the basic delay unit. The output terminal of the last level of the basic delay unit is the output terminal of the long delay path.

4. A dual-channel asynchronous clock circuit for a successive approximation analog-to-digital converter according to claim 3, characterized in that, The short delay path consists of a basic delay unit and an inverter cascaded together, the inverter including a third PMOS transistor and a third NMOS transistor; The source of the third PMOS transistor is connected to the power supply, the gate of the third PMOS transistor is connected to the gate of the third NMOS transistor and is the input terminal of the inverter; the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor and is the output terminal of the inverter; the source of the third NMOS transistor is grounded. The input terminal of the basic delay unit is the input terminal of the short delay path, the output terminal of the basic delay unit is connected to the input terminal of the inverter, and the output terminal of the inverter is the output terminal of the short delay path.

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