A method for implementing an efficient general reed-solomon decoder on a chip

Abstract

The application discloses a method for realizing an efficient general Reed-Solomon decoder on a chip, and solves the technical problems of poor generality, low decoding rate and low code reuse rate of the existing RS decoder on the chip. The method is based on the Galois field operation principle, and a five-module parallel architecture composed of an accompanying polynomial calculation, a key equation solving, a Chien search, a Forney transformation and an error calculation is constructed. The core parameters and operation logic of different RS codes are uniformly managed through a pre-defined general header file. The decoding rate is improved through parallel design, and multiple RS codes are compatible through the general header file. The code utilization rate is high, the hardware implementation complexity is low, the chip-level high-speed decoding scene is adapted, the method can be widely applied to various digital communication and storage systems requiring error control, the chip design cost and development cycle are significantly reduced, and the decoding efficiency and system reliability are improved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design and digital signal processing technology, and particularly relates to a method for implementing a high-efficiency, general-purpose Reed-Solomon decoder on a chip. Background Technology

[0002] Reed-Solomon (RS) error correction coding is a linear block code built on the Galois field (GF). First created by Reed and Solomon in 1960, it is one of the most effective and widely used error control codes. RS codes possess excellent random and burst error correction capabilities, and have low encoding and decoding complexity. They are recommended by the Institute of Electrical and Electronics Engineers (IEEE) and the International Telecommunication Union (ITU) as the preferred forward error correction (FEC) code, and are widely used in fields with high data transmission reliability requirements, such as fiber optic communication, satellite communication, storage devices, and the Internet of Things (IoT).

[0003] RS codes have various polynomial specifications. Taking the IEEE 802.3 protocol as an example, there are multiple specifications with different coding lengths and error correction capabilities, such as RS(255,239), RS(528,514), RS(544,514), RS(450,406), RS(192,186), and RS(360,326). The Galois field size, coding length, and error correction capability are different for different RS code specifications.

[0004] The implementation of existing RS decoders on chips has fundamental defects and shortcomings, making it difficult to meet the needs of practical applications: First, it has extremely poor versatility. Traditional RS decoders require different decoding core codes to be written for different RS code specifications. Each code needs to be expanded separately for different encoding formats. When implemented on chips, the decoding logic for different RS codes cannot be reused, resulting in high chip design complexity, large resource consumption, and long development cycles. Second, the decoding rate is low. Traditional chip-level RS decoders mostly adopt a serial decoding architecture, with each module performing operations sequentially. This cannot fully utilize the parallel processing capabilities of the chip and is difficult to meet the high-speed decoding requirements of scenarios such as fiber optic communication and high-speed storage.

[0005] In summary, existing chip-level RS decoders cannot simultaneously meet the three core requirements of versatility, high speed, and high code reusability. There is an urgent need for a new implementation method to solve the problem of universal decoding of different RS codes on the chip, while improving the decoding speed, reducing chip design costs, and adapting to various high-reliability data transmission scenarios.

[0006] Therefore, it is necessary to provide a new method for implementing an efficient and general-purpose Reed-Solomon decoder on a chip to solve the above-mentioned technical problems. Summary of the Invention

[0007] The technical problem solved by this invention is to provide a method for implementing a high-efficiency, universal Reed-Solomon decoder on a chip by improving decoding speed through parallel design, achieving multi-RS code compatibility through a universal header file, having high code utilization, low hardware implementation complexity, adapting to chip-level high-speed decoding scenarios, and being widely applicable to various digital communication and storage systems that require error control, significantly reducing chip design costs and development cycles, and improving decoding efficiency and system reliability.

[0008] To address the aforementioned technical problems, this invention provides a method for implementing a high-efficiency, universal Reed-Solomon decoder on a chip, applicable to ASIC or FPGA chips. Its key feature is the construction of a parallel decoding architecture based on the Galois domain operation principle. It achieves multi-RS code adaptation through a predefined universal header file, eliminating the need to modify the core decoding code; decoding of different RS codes can be completed simply by adjusting header file parameters. Specifically, the method includes the following steps: S1. Initialization: Start the RS decoder on the chip, import the predefined general header file, configure the core macro definition parameters in the header file, initialize the Galois field operation table and general functions according to the target RS code specification, and enable the parallel decoding function; the general header file contains macro definitions, Galois field operation table and general functions, which are used to uniformly manage the core parameters and operation logic of different RS codes; S2, Data Input: Input the erroneous RS-encoded data according to the preset parallelism. The data is input to the decoder in parallel, and the length of each data stream matches the size of the Galois field element. S3. Parallel computation of the adjoint polynomial: The adjoint polynomial computation module calls the parameters and functions in the general header file to generate general multiplication coefficients, calculates the adjoint polynomial coefficients through parallel multiplication operations, and transmits the results to the key equation solving module. S4. Parallel solution of key equations: The key equation solution module adopts the parallel RIBM algorithm, calls the operation functions in the general header file, and obtains the characteristic roots in parallel based on the coefficients of the adjoint polynomial. The characteristic roots are then transmitted to the Qian search module and the Forney transformation module respectively. S5. Parallel search for error locations: The search module calls the parameters and functions in the general header file to generate general multiplication coefficients, searches for error locations through parallel multiplication operations, and transmits the results to the error calculation module. S6. Parallel error value calculation: The Forney Transform module calls the parameters and functions in the general header file to generate general multiplication coefficients, calculates the error value through parallel multiplication operations, and transmits the result to the error calculation module; S7. Error Correction and Data Output: The error calculation module calls the Galois field inverse element table in the general header file to generate an error matrix. It then corrects the input error data through parallel XOR operations and outputs the correct original data. S8. Repeated execution or specification switching: Repeat steps S2-S7 for subsequent input RS-encoded data; if it is necessary to switch RS code specifications, only the macro definition parameters in the general header file need to be modified, and the core decoding code does not need to be modified to complete the decoding of the new specification RS code.

[0009] As a further aspect of the present invention, the macro definition parameters in the general header file include: Macro The size of the Galois field containing the original polynomial, corresponding to the Galois field. ; Macro The error-correcting code length of the RS code, i.e., the parity bit length, is calculated using the following formula: t is the maximum number of errors to be corrected in the RS code; Macro Parallelism, or the number of data streams processed in a single parallel operation, can be flexibly configured according to chip hardware resources. Macro _ The total length of the RS code, including the length of the original data and the length of the error correction code; Macro The total number of elements in the Galois field is calculated using the following formula: ; The Galois field operation table in the general header file includes: array Size is Storage Galois Domain All elements are used for quick querying of element values ​​within the Galois domain; array _inf: size is Storage Galois Domain The inverse of each element in the set is used to quickly solve the inverse operation.

[0010] As a further aspect of the present invention, the general functions in the general header file include: function The Galois field element descending order function is used to descend elements greater than or equal to TOTAL-1 to the Galois field range. The formula is: ; function The Galois field multiplication function is used to perform multiplication of two elements within the Galois field. The formula is: ; Where α is the Galois domain The fundamental element, Let be the logarithm of element a in the Galois field; The accompanying polynomial calculation module, key equation solving module, Qian search module, Forney transformation module, and error calculation module are all implemented in parallel using Verilog language. Each module works synchronously and in parallel, and data is transmitted in a pipeline manner.

[0011] As a further aspect of the present invention, the multiplication coefficients of the accompanying polynomial calculation module and the Qian search module are obtained through... The nested for loop generates statements, combined with those in the general header file. arrays and Function generation enables universal adaptation to different RS codes; It also includes an error rate detection module, which is used to collect error data from the error calculation module in real time and calculate the current data error rate. The parallelism DAT_NUM is dynamically adjusted based on the error rate to achieve a balance between decoding efficiency and chip resource usage.

[0012] As a further aspect of the present invention, it also includes an error feedback module, which is used to feed back the error correction result of the error calculation module to the accompanying polynomial calculation module and the key equation solving module. If the error correction fails, the operation parameters are adjusted and the decoding is performed again to improve the error correction success rate. The RS code specifications include, but are not limited to, RS(255,239), RS(528,514), RS(544,514), RS(450,406), RS(192,186), and RS(360,326); The parallelism It can be configured to any of 2, 4, 8, or 16, and can be flexibly adjusted according to chip hardware resources and decoding rate requirements.

[0013] As a further solution of the present invention, the Galois domain arithmetic table adopts a segmented storage + dynamic wake-up mechanism, which only wakes up the arithmetic table segments required by the current RS code specification, and the unused segments enter a low-power sleep state to reduce the static power consumption of the chip. The The multiplication function introduces a result caching mechanism to cache frequently used multiplication results in a high-speed register, reducing operation table lookup and dynamic power consumption. It also includes a dynamic power consumption control module, which dynamically adjusts the clock frequency of the computing module according to the current decoding rate to achieve a balance between decoding efficiency and power consumption.

[0014] As a further aspect of the present invention, an exception handling mechanism is also included to handle four typical exceptions: data loss, operation table reading exception, module failure, and parameter configuration exception, so as to ensure the stable operation of the decoder. The Galois domain operation table adopts a storage unit reuse design. and The _inf array reuses the same storage unit and is distinguished by read and write control signals, reducing storage resource consumption; In low parallelism scenarios ( (≤4), the operation logic of the Qian search module and the Furni transformation module is time-division multiplexed to reduce the occupation of logic units.

[0015] As a further aspect of the present invention, a shift register is used to store the intermediate results of parallel operations, thereby reducing the amount of registers occupied and reducing dynamic power consumption. The decoder is compatible with TSMC ASIC chips using 28nm and 14nm process nodes, as well as Xilinx Kintex-7 and Altera Cyclone V series FPGA chips, without requiring additional dedicated hardware resources.

[0016] Compared with related technologies, the method for implementing a high-efficiency, universal Reed-Solomon decoder on a chip provided by this invention has the following advantages: This invention encapsulates the core parameters, Galois field tables, and general functions of different RS codes using a predefined universal header file. Each decoding module achieves a universal design by calling the header file. Without modifying the core code of the five major decoding modules, only the macro-defined parameters in the header file need to be adjusted to adapt to RS codes with different Galois field sizes and encoding lengths (such as RS(255,239), RS(450,406)). This completely solves the pain points of poor versatility and the need for separate design for different RS codes in traditional RS decoders, significantly reducing chip design workload and development cycle.

[0017] By utilizing DAT_NUM parallel computing, the parallel processing resources of the chip are fully utilized, resulting in a decoding speed increase of several times or even tens of times compared to the traditional serial decoding architecture (reaching 8Gbps in this embodiment, a 700% improvement). Simultaneously, the parallel computing logic is simple and can be implemented through the hardware pipeline of ASIC / FPGA chips, adapting to the high-speed decoding requirements of scenarios such as fiber optic communication and high-speed storage, thereby improving the overall system transmission efficiency.

[0018] The core decoding code (five modules) of this invention is 100% reusable. The decoding logic for different RS codes only needs to be adjusted through header file parameters, resulting in extremely low code redundancy (below 5%). Compared to traditional solutions (code redundancy exceeding 60%), this significantly improves code utilization. Simultaneously, the parallel architecture offers high resource reuse, reducing chip resource consumption by more than 50% compared to traditional multiple serial decoders. This significantly reduces chip design costs and hardware overhead, making it highly valuable for engineering implementation.

[0019] The decoding logic of this invention is implemented based on a general header file and parallel computing, eliminating the need for complex dedicated logic design. Core operations are performed by calling functions and arrays in the header file, resulting in a concise and easy-to-understand logic that facilitates later maintenance and upgrades. Furthermore, it is implemented using the Verilog hardware description language, allowing direct adaptation to various chip platforms such as ASICs and FPGAs without extensive modifications. This strong adaptability makes it widely applicable to various digital communication and storage systems requiring error control, improving the reliability of system data transmission. Attached Figure Description

[0020] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to the accompanying drawings.

[0021] Figure 1 This is a schematic diagram of error calculation provided by the present invention; Figure 2 The first parallel computing logic provided by the present invention Core code: Figure 3 The second parallel computing logic provided by the present invention Core code: Figure 4 The third parallel computing logic provided by the present invention Core code. Detailed Implementation

[0022] Please refer to the following: Figure 1 and Figure 4 ,in, Figure 1 This is a schematic diagram of error calculation provided by the present invention; Figure 2 The first parallel computing logic provided by the present invention Core code: Figure 3 The second parallel computing logic provided by the present invention Core code: Figure 4 The third parallel computing logic provided by the present invention Core code. A method for implementing a high-efficiency, general-purpose Reed-Solomon decoder on a chip, applicable to ASIC or FPGA chips, is characterized by constructing a parallel decoding architecture based on the Galois domain operation principle. It achieves multi-RS code adaptation through a predefined general header file, requiring no modification to the core decoding code; decoding of different RS codes can be completed simply by adjusting header file parameters. Specifically, it includes the following steps: S1. Initialization: Start the RS decoder on the chip, import the predefined general header file, configure the core macro definition parameters in the header file, initialize the Galois field operation table and general functions according to the target RS code specification, and enable the parallel decoding function; the general header file contains macro definitions, Galois field operation table and general functions, which are used to uniformly manage the core parameters and operation logic of different RS codes; S2, Data Input: Input the erroneous RS-encoded data according to the preset parallelism. The data is input to the decoder in parallel, and the length of each data stream matches the size of the Galois field element. S3. Parallel computation of the adjoint polynomial: The adjoint polynomial computation module calls the parameters and functions in the general header file to generate general multiplication coefficients, calculates the adjoint polynomial coefficients through parallel multiplication operations, and transmits the results to the key equation solving module. S4. Parallel solution of key equations: The key equation solution module adopts the parallel RIBM algorithm, calls the operation functions in the general header file, and obtains the characteristic roots in parallel based on the coefficients of the adjoint polynomial. The characteristic roots are then transmitted to the Qian search module and the Forney transformation module respectively. S5. Parallel search for error locations: The search module calls the parameters and functions in the general header file to generate general multiplication coefficients, searches for error locations through parallel multiplication operations, and transmits the results to the error calculation module. S6. Parallel error value calculation: The Forney Transform module calls the parameters and functions in the general header file to generate general multiplication coefficients, calculates the error value through parallel multiplication operations, and transmits the result to the error calculation module; S7. Error Correction and Data Output: The error calculation module calls the Galois field inverse element table in the general header file to generate an error matrix. It then corrects the input error data through parallel XOR operations and outputs the correct original data. S8. Repeated execution or specification switching: Repeat steps S2-S7 for subsequent input RS-encoded data; if it is necessary to switch RS code specifications, only the macro definition parameters in the general header file need to be modified, and the core decoding code does not need to be modified to complete the decoding of the new specification RS code.

[0023] The macro definition parameters in the general header file include: Macro The size of the Galois field containing the original polynomial, corresponding to the Galois field. ; Macro The error-correcting code length of the RS code, i.e., the parity bit length, is calculated using the following formula: t is the maximum number of errors to be corrected in the RS code; Macro Parallelism, or the number of data streams processed in a single parallel operation, can be flexibly configured according to chip hardware resources. Macro _NUM: The total length of the RS code, including the length of the original data and the length of the error correction code; Macro The total number of elements in the Galois field is calculated using the following formula: ; The Galois field operation table in the general header file includes: array Size is Storage Galois Domain All elements are used for quick querying of element values ​​within the Galois domain; array _inf: size is Storage Galois Domain The inverse of each element in the set is used to quickly solve the inverse operation.

[0024] The generic functions in the generic header file include: function The Galois field element descending order function is used to descend elements greater than or equal to TOTAL-1 to the Galois field range. The formula is: ; function The Galois field multiplication function is used to perform multiplication of two elements within the Galois field. The formula is: ; Where α is the Galois domain The fundamental element, Let be the logarithm of element a in the Galois field; The accompanying polynomial calculation module, key equation solving module, Qian search module, Furniture transformation module, and error calculation module all adopt... The language is implemented in parallel, with each module working synchronously and in parallel, and data is transmitted in a pipeline manner.

[0025] The multiplication coefficients of the adjoint polynomial calculation module and the Qian search module are obtained through... The nested for loop generates statements, combined with those in the general header file. arrays and Function generation enables universal adaptation to different RS codes; It also includes an error rate detection module, which is used to collect error data from the error calculation module in real time and calculate the current data error rate. And dynamically adjust the parallelism based on the error rate. This achieves a balance between decoding efficiency and chip resource usage.

[0026] It also includes an error feedback module, which feeds back the error correction results of the error calculation module to the accompanying polynomial calculation module and the key equation solving module. If the error correction fails, the operation parameters are adjusted and the decoding is performed again to improve the success rate of error correction. The RS code specifications include, but are not limited to, RS(255,239), RS(528,514), RS(544,514), RS(450,406), RS(192,186), and RS(360,326); The parallelism It can be configured to any of 2, 4, 8, or 16, and can be flexibly adjusted according to chip hardware resources and decoding rate requirements.

[0027] The Galois domain arithmetic table adopts a segmented storage + dynamic wake-up mechanism, which only wakes up the arithmetic table segments required by the current RS code specification, and the unused segments enter a low-power sleep state to reduce the static power consumption of the chip. The rs_mul multiplication function introduces a result caching mechanism to cache frequently used multiplication results in a high-speed register, reducing operation table lookup and dynamic power consumption. It also includes a dynamic power consumption control module, which dynamically adjusts the clock frequency of the computing module according to the current decoding rate to achieve a balance between decoding efficiency and power consumption.

[0028] It also includes an exception handling mechanism to handle four typical exceptions: data loss, operation table reading error, module failure, and parameter configuration error, to ensure stable operation of the decoder; The Galois domain arithmetic table adopts a storage unit reuse design, gf_table and The _inf array reuses the same storage unit and is distinguished by read and write control signals, reducing storage resource consumption; In low parallelism scenarios ( (≤4), the operation logic of the Qian search module and the Furni transformation module is time-division multiplexed to reduce the occupation of logic units.

[0029] By using shift registers to store the intermediate results of parallel operations, the number of registers occupied is reduced, and dynamic power consumption is lowered. The decoder is compatible with TSMC ASIC chips using 28nm and 14nm process nodes, as well as Xilinx Kintex-7 and Altera Cyclone V series FPGA chips, without requiring additional dedicated hardware resources.

[0030] The core technology of this invention is as follows: Based on the operational characteristics of the Galois field, a standardized five-module parallel decoding architecture is constructed. Through a predefined general header file, the core parameters (Galois field size, encoding length) and general operational logic (multiplication, descending order processing, etc.) of different RS codes are uniformly encapsulated. Each decoding module achieves a generalized design by calling the header file, requiring no modification to the core code; only the header file parameters need to be adjusted to adapt to different RS code specifications. Simultaneously, parallelization is employed. The code implements the operations of each module, making full use of the chip's parallel processing capabilities to improve the decoding rate, and ultimately achieving efficient and universal RS decoding on the chip.

[0031] The present invention is implemented based on a chip-level hardware platform (ASIC chip or FPGA chip), and adopts... The hardware description language implementation needs to support functions such as Galois domain operations, parallel data processing, and data interaction between modules. The following describes the embodiments of the present invention in detail with specific implementation parameters, complete working principles and processes.

[0032] The universal header file is the core of this invention for achieving the universality of the RS decoder. It is used to uniformly manage the core parameters, Galois field operation tables, and universal functions for different RS codes. Each decoding module can adapt to different RS codes by importing this header file without modifying the module's core code. The header file adopts... Macro definitions and array / function encapsulation formats are detailed below: Core macro definition: Macro GF_SIZE: The size of the Galois field containing the original polynomial, corresponding to the Galois field. For example, the Galois field corresponding to RS(255,239) is Therefore The Galois field corresponding to RS(450,406) is Therefore .

[0033] Macro The error correction code length of the RS code (i.e., the length of the parity bits, excluding the original data length) is calculated using the following formula: (t is the maximum number of error corrections in the RS code), for example, the error correction code length of RS(255,239) is 255-239=16, therefore The error correction code length of RS(450,406) is 450-406=44, therefore .

[0034] Macro DAT_NUM: Parallelism, i.e., the number of data streams processed in a single parallel operation. Higher parallelism results in higher decoding efficiency and can be flexibly configured based on chip hardware resources (e.g., ...). =4, 8, 16, etc.).

[0035] Macro The total length of the RS code (including the original data length and the error correction code length), for example, the total length of RS(255,239) is 255. The total encoding length of RS(450,406) is 450, therefore .

[0036] Macro The total number of elements in the Galois field is calculated using the following formula: Corresponding to the Gara Hua Domain The number of all elements.

[0037] Among them, the Galois field operation table: array The array size is TOTAL, storing Galois domains. All elements are sorted according to the Galois field operation rules, which is used to quickly query the element values ​​within the Galois field and support subsequent multiplication, descending order and other operations.

[0038] array _inf: The array size is TOTAL, storing Galois fields. The inverse of each element is used to quickly solve the inverse operation of elements in the Galois field, avoiding the speed loss caused by real-time calculation of the inverse element, and is the core support of the error calculation module.

[0039] Among them, general functions The function `gen_gf(x)` is a function for descending ordering elements in a Galois field. It is used to perform a descending order operation on Galois field elements greater than or equal to `TOTAL-1`, ensuring that the element values ​​are within the Galois field range (i.e., less than `TOTAL`). Its core logic is: since the value is within the Galois field... In the expression, any element a satisfies Therefore, for an input value x, if x ≥ TOTAL-1, then repeatedly subtract... until a value less than is obtained. The element value is given, and this value is output as the result of the descending sorting. The formula is expressed as: ; function Galois multiplication function, used to implement Galois multiplication. The multiplication operation of two elements a and b is based on the following logic: This implementation uses an array to quickly retrieve the multiplication result by querying the array, avoiding complex real-time calculations and improving multiplication efficiency. Its core formula is: ; Where α is the Galois domain The fundamental element, Represents the logarithm of element a in the Galois field (which can be expressed as the logarithm of element a in the Galois field). (Reverse array lookup).

[0040] The RS decoder of this invention consists of five parallel sub-modules, each operating independently in parallel while collaboratively completing the decoding process through data interaction. The five modules are: an adjoint polynomial calculation module, a key equation solving module, a Qian search module, a Forney transform module, and an error calculation module. Each module achieves universal adaptation to different RS codes by importing a common header file. The core working principle is as follows: Among them, the adjoint polynomial calculation module: The core function of this module is to receive input RS-encoded data (including erroneous data), calculate the adjoint polynomial, and provide a foundation for subsequent error detection and correction. Its key challenge lies in the fact that the multiplication coefficients for different RS codes need to be calculated separately, which traditional methods cannot generalize. This invention addresses this by using a universal header file and... Generate statements to achieve a generalized expansion of multiplication by coefficients without modifying the core code.

[0041] Parallel computing logic: For DAT_NUM parallel input data, each data point is multiplied by its corresponding Galois field multiplication coefficient. All multiplication operations are executed in parallel to improve computational efficiency. Core code implementation ( )like Figure 2 As shown; Working principle: Statements are generated using a nested for loop, based on GF_NUM (error correction code length) in the header file and... The parameter (parallelism) automatically generates the corresponding multiplication coefficient (gf[i][j]), which is determined by... The array and the gen_gf function are used to generate and adapt to different RS codes. Then, the rs_mul function is used to perform parallel multiplication of the input data (din) and the multiplication coefficients, and output the multiplication result (mul) to complete the parallel computation of the adjoint polynomial.

[0042] The key equation solving module: The core function of this module is to solve the key equations based on the results of the adjoint polynomial calculation, obtaining the coefficients (i.e., eigenvalues) of the error location polynomial and the error value polynomial, providing a basis for subsequent calculations of the error location and error value. This invention employs the parallel RIBM (Improved Berlekamp-Massey) algorithm, which significantly improves computational efficiency compared to the traditional serial RBM algorithm. It can be multiplied by 100%, and by calling a common header file, it can adapt to the key equation solving requirements of different RS codes.

[0043] Parallel working principle: The solution process of the key equations is broken down into... The algorithm performs parallel operations, with each operation corresponding to a set of adjoint polynomial coefficients. The eigenvalues ​​are solved in parallel using the RIBM algorithm. The Galois field multiplication and descending order operations involved in the algorithm all call the rs_mul and gen_gf functions in the header file. There is no need to modify the core logic of the algorithm. The eigenvalues ​​can be solved by adapting the header file parameters to the eigenvalues ​​of different RS codes.

[0044] Core advantages: The parallel RIBM algorithm avoids the bottleneck of sequential operation in traditional serial algorithms, makes full use of the chip's parallel processing resources, and the generalized design ensures that the key equation solving logic for different RS codes can be reused, reducing the complexity of chip design.

[0045] The Qian search module's core function is to search for and determine error locations in RS-encoded data based on the eigenvalues ​​obtained from solving the key equations. Its core challenge is the same as the adjoint polynomial calculation module: the multiplication coefficient calculations for different RS codes need to be expanded separately, which traditional methods cannot generalize. This invention achieves a generalized expansion of the multiplication coefficients through a universal header file and generation statements, while employing parallel computation to improve search efficiency.

[0046] Parallel computing logic: Statements are generated using a double for loop, automatically generating the multiplication coefficient (chien_gf[i][j]) for the corresponding path based on header parameters. Then, the rs_mul function performs parallel multiplication of the multiplication coefficient with the current position value (cur_pos[i]), outputting the search result (chien_result), and determining the error location based on the result. Core code implementation ( )like Figure 3 What it means: Working principle: The multiplication coefficient chien_gf[i][j] is generated by the gf_table array and the gen_gf function to adapt to the error position search requirements of different RS codes; The parallel multiplication operation is executed synchronously to quickly obtain the search result. When chien_result[i] is 0, the corresponding position is the error position, realizing parallel and fast search of error positions.

[0047] The Forney Transform Module: The core function of this module is to solve for the error value based on the error location and the eigenvalues ​​of the key equation. Its core challenge lies in the calculation and expansion of the multiplication coefficients and the solution for the inverse elements corresponding to different RS codes. Traditional solutions require separate design and are not universally applicable. This invention achieves a universal expansion of the multiplication coefficients and fast access to the inverse elements through a general header file, while employing parallel computation to improve transformation efficiency.

[0048] Parallel computing logic: Statements are generated using nested for loops, automatically generating the multiplication coefficients for the corresponding number of paths based on header file parameters. The multiplication coefficient is generated by the `gen_gf` function and the `gf_table` array; then, the `rs_mul` function performs parallel multiplication of the multiplication coefficient with the current value (`cur_num[i]`), outputting the Forney transformation result (`forney_result`), i.e., the error value). Core code implementation ( )like Figure 4 As shown: Working principle: Generated via the gen_gf function, and then via... The array is mapped to Galois field elements to obtain the general multiplication coefficient forney_gf[i][j]; the inverse element is quickly accessed through the gf_table_inf array in the header file without real-time calculation; the DAT_NUM-way parallel operation is performed synchronously to quickly obtain the error value, providing a basis for subsequent error correction.

[0049] Error Calculation Module: The core function of this module is to correct errors in the input RS-encoded data based on the error locations obtained from the Qian search module and the error values ​​obtained from the Forney transform module, outputting the correct original data. Its core challenge lies in calculating the error matrix. Traditional solutions require designing separate error matrices for different RS codes. This invention uses a predefined error matrix in the header file. An array (Galois field inverse element table) can be directly imported and used to achieve generalized calculation of error matrices.

[0050] Working principle: Receives the error location output by the Qian search module and the error value output by the Forney transform module, and calls the header file... The `_inf` array quickly retrieves the inverse elements needed for the error matrix, generating the error matrix through parallel computation. Then, the error matrix is ​​XORed with the input error data to complete error correction, outputting the correct original data. The entire process requires no modification to the core code; only header files are adapted to meet the error calculation needs of different RS codes.

[0051] Complete Decoding Workflow: The RS decoder of this invention adopts a parallel pipeline architecture, with five modules working synchronously and in parallel. Data is pipelined between modules. The complete decoding flow is as follows, achieving efficient decoding from erroneous data input to correct data output: Initialization: Start the RS decoder on the chip, import the predefined general header file, and configure GF_SIZE, GF_NUM, and other parameters in the header file according to the target RS code specification (e.g., RS(255,239)). Core parameters, initialization , The _inf array and the gen_gf and rs_mul functions enable parallel decoding.

[0052] Data input: Input the RS encoded data (din) containing errors to the decoder. The data is input in parallel in DAT_NUM paths, and the length of each data path is GF_SIZE bits, which is adapted to the size of the Galois field element.

[0053] Parallel computation of the adjoint polynomial: The adjoint polynomial computation module calls the parameters and functions in the header file to generate general multiplication coefficients, calculates the adjoint polynomial coefficients (mul) through parallel multiplication operations, and transmits the results to the key equation solving module.

[0054] Parallel solution of key equations: The key equation solution module receives the coefficients of the adjoint polynomial, uses the parallel RIBM algorithm, calls the operation functions in the header file, and obtains the eigenvalues ​​in parallel. The eigenvalues ​​are then transmitted to the Qian search module and the Forney transform module respectively.

[0055] Parallel search for error location: The chien search module receives the feature roots, calls the parameters and functions in the header file, generates general multiplication coefficients, searches for the error location (chien_result) through parallel multiplication operations, and transmits the result to the error calculation module.

[0056] Parallel error value calculation: The Forney transform module receives the eigenvalues, calls the parameters and functions in the header file, generates universal multiplication coefficients, calculates the error value (forney_result) through parallel multiplication operations, and transmits the result to the error calculation module.

[0057] Error correction and data output: The error calculation module receives the error location and error value, and calls the header file... The _inf array generates an error matrix, which corrects the erroneous input data through parallel XOR operations and outputs the correct original data (dout).

[0058] Loop execution: For each subsequent set of RS-encoded data, repeat steps 2-6 to achieve continuous and efficient parallel decoding. At the same time, different RS code specifications can be switched by modifying the header file parameters without restarting the decoder or modifying the core decoding logic.

[0059] This embodiment uses an ASIC chip platform. The RS decoder of this invention is implemented in a language, and the parallelism is configured. =8, adapted to two typical RS codes, RS(255,239) and RS(450,406), respectively. Compared with traditional serial RS decoders (designed separately for the two RS codes), the universality, decoding speed and code utilization of the present invention are verified. The test results are as follows: Universality verification: By modifying only the GF_SIZE, GF_NUM, and TOTAL_NUM parameters in the general header file (RS(255,239): GF_SIZE=8, GF_NUM=16, TOTAL_NUM=255; RS(450,406): GF_SIZE=9, GF_NUM=44, TOTAL_NUM=450), without modifying the core code of the five major modules, the decoder can correctly decode both RS codes, with a decoding accuracy of 100%, verifying the universality of the invention.

[0060] Decoding rate verification: The parallel decoder of this invention achieves a decoding rate of 8Gbps, which is 700% higher than the traditional serial decoder (1Gbps). Furthermore, with increasing parallelism... With the addition of [unclear], the decoding rate can be further improved, adapting to the needs of high-speed data transmission.

[0061] Code utilization verification: The core decoding code (five modules) of this invention is 100% reusable. Only the header file parameters need to be modified to adapt to different RS codes, and the code redundancy rate is less than 5%. In contrast, traditional solutions require writing two independent core codes for two RS codes, with a code redundancy rate of more than 60%. The code utilization rate of this invention is significantly improved.

[0062] Chip resource usage verification: Parallel decoder of this invention ( The chip resource usage (number of logic units) of the 8-bit chip is 12,000, which is 52% lower than the traditional two sets of serial decoders (total number of logic units 25,000), significantly reducing chip design costs.

[0063] Test results show that the RS decoder of the present invention achieves efficient and universal decoding function on the chip, solves the core defects of traditional solutions, and has strong engineering practicality and advanced features. Example 1:

[0064] This embodiment adds a real-time data error rate detection module to the original fixed parallelism, thereby achieving parallelism... The dynamic adaptive adjustment solves the problem that decoding efficiency and chip resource consumption cannot be balanced when the data error rate fluctuates with a fixed parallelism.

[0065] Core improvement: An error rate detection module is introduced to collect error data from the error calculation module in real time and calculate the current data error rate. (Number of erroneous data bits / total number of data bits); Design a dynamic parallelism adjustment algorithm based on the error rate. Adjusting parallelism A higher error rate corresponds to a lower degree of parallelism (reducing chip resource consumption), while a lower error rate corresponds to a higher degree of parallelism (increasing decoding speed).

[0066] Core Algorithm: ; in, , , The preset parallelism level (e.g., 8, 4, 2) can be configured via the header file.

[0067] Performance verification: When the data error rate increased from 3% to 25%, the parallelism was dynamically adjusted from 8 to 2, chip resource consumption was reduced by 60%, and although the decoding rate decreased (from 8Gbps to 2Gbps), it still met the needs of medium and low speed scenarios; when the error rate dropped to below 5%, the parallelism was automatically restored to 8, achieving a dynamic balance between decoding efficiency and resource consumption, and further improving the adaptability of the decoder. Example 2:

[0068] This embodiment adds an error feedback module to the original decoding architecture, which feeds back the error correction results of the error calculation module to the adjoint polynomial calculation module and the key equation solving module, thereby achieving adaptive error correction optimization and solving the problems of low error correction accuracy and false error correction in traditional decoders under high error rate scenarios.

[0069] Core improvements: The error feedback module collects the error correction results from the error calculation module in real time and determines whether the error correction is successful (verified by a check code). If the error correction fails, the error information (error location, error value) is fed back to the accompanying polynomial calculation module and the key equation solving module. The multiplication coefficient generation logic and key equation solving parameters are adjusted, and the decoding operation is performed again until the error correction is successful or the maximum number of retries is reached.

[0070] Performance verification: In high error rate scenarios (25% error rate), the error correction success rate of traditional decoders is only 75%, and the false error correction rate is 10%. This embodiment improves the error correction success rate to 98% and reduces the false error correction rate to below 1% through adaptive adjustment of error feedback, which significantly improves the decoding reliability in high error rate scenarios and further improves the technical solution.

[0071] Example 3: This embodiment optimizes the operation table storage and multiplication operation logic based on the original Galois domain operation logic, and introduces a dynamic power consumption control module to solve the technical pain point of excessive power consumption of chip-level RS decoders in high-speed decoding scenarios, achieving the dual goals of "high-efficiency decoding + low power consumption", and further improving the engineering practicality and inventiveness of the present invention.

[0072] Core improvements: First, the storage of the Galois domain operation table is optimized by adopting a "segmented storage + dynamic wake-up" mechanism. and The _inf array is segmented according to the Galois field size, waking up only the operation table segments required for the current RS code specification, while unused segments enter a low-power sleep state, reducing the static power consumption of the storage unit; secondly, the rs_mul multiplication function is optimized by introducing an "operation result caching" mechanism, which caches frequently used multiplication results in high-speed registers to avoid repeated lookups of the operation table and reduce the dynamic power consumption of the operation logic; thirdly, a dynamic power consumption control module is added to dynamically adjust the clock frequency of the operation module according to the decoding rate requirements, automatically reducing the clock frequency when the decoding rate decreases, further reducing power consumption.

[0073] Core optimization details: Segmented storage of the arithmetic table: array by The size of the segments, for example, when GF_SIZE=8, will be divided into segments. (256 elements) are divided into 4 segments, each with 64 elements; when decoding RS(255,239) ( When the power consumption is equal to 8, only the corresponding segment is woken up, while the other segments go into sleep mode, reducing static power consumption by more than 40%.

[0074] Multiplication result caching: A cache register set is configured to cache the most recent 128 multiplication results, achieving a cache hit rate of over 85%, reducing arithmetic table lookup operations by over 80%, and lowering dynamic power consumption by over 35%; when a cache miss occurs, a lookup is performed. The array is updated and the cache is updated without affecting the decoding speed.

[0075] Dynamic clock adjustment: Design a clock frequency adjustment algorithm, the formula is as follows. ,in The reference clock frequency is 1 GHz in this embodiment. The current decoding rate, To achieve the maximum decoding rate, the clock frequency is dynamically adjusted according to the decoding rate, and the power consumption is positively correlated with the clock frequency, further reducing ineffective power consumption.

[0076] Effect verification: In =8. In a scenario with a decoding rate of 8Gbps, the power consumption of the decoder in this embodiment is 1.2W, which is 40% lower than the original parallel decoder (power consumption of 2.0W). When the decoding rate drops to 2Gbps, the power consumption automatically drops to 0.3W, achieving a balance between high-efficiency decoding and low power consumption, and is suitable for portable, low-power chip application scenarios (such as IoT terminal chips).

[0077] The hardware mapping, timing constraints, and resource utilization optimization schemes for each module are clearly defined to ensure that this invention can be directly implemented on existing chip platforms, as detailed below: Hardware Platform Compatibility: This invention is compatible with mainstream ASIC and FPGA chips. Specific compatible models and parameters are as follows: ASIC Chips: Compatible with TSMC 28nm and 14nm process nodes, core voltage 1.0V~1.2V, clock frequency support 500MHz~1.2GHz, logic unit occupancy varies with parallelism. change( When the value is 8, there are approximately 12,000 logic units and approximately 5KB of storage units. FPGA chip: Compatible with Xilinx Kintex-7, Zynq-7000 series, Altera Cyclone V series. No additional dedicated hardware resources are required. It only needs to occupy the FPGA's logic units, high-speed registers, and Block RAM. The Block RAM is used to store the Galois domain arithmetic table and occupies about 4KB~8KB.

[0078] Timing Constraint Design: To ensure the stability of high-speed decoding, reasonable timing constraints are designed. The core constraint parameters are as follows: Clock period: The reference clock period is 1ns (1GHz), and the timing margin of each module is ≥0.2ns to avoid timing violations; Data transmission latency: The data transmission latency between modules is ≤0.1ns. Pipeline register cascading is used to reduce data transmission latency. Operational latency: The latency of a single Galois domain multiplication operation is ≤0.3ns, and the latency of a single operation in the key equation solving module is ≤1ns, ensuring that the overall decoding rate meets the design requirements.

[0079] Resource utilization optimization scheme: For scenarios with limited chip resources, a supplementary resource utilization optimization scheme is provided to further reduce hardware overhead: Operation table reuse: and The _inf array reuses the same storage unit and is distinguished by read / write control signals, reducing storage resource usage by 30%. Module time-sharing multiplexing: in low parallelism scenarios ( ≤4), the operation logic of the money search module and the Fony transformation module is time-division multiplexed, reducing the logic unit occupancy by 25%; Register optimization: Shift registers are used instead of ordinary registers to store intermediate results of parallel operations, reducing register usage by 40% and reducing dynamic power consumption.

[0080] Among them, fiber optic communication application scenarios Application scenario: Forward error correction (FEC) module for high-speed optical fiber communication systems, adapted to 100Gbps and 200Gbps optical fiber transmission rates, using RS (528,514) and RS (544,514) standard RS codes, requiring a decoding rate ≥10Gbps and power consumption ≤1.5W.

[0081] Implementation: The RS decoder of the present invention is integrated into an optical fiber communication chip (ASIC process, 14nm), and configured... =16, adopting the low-power optimization scheme of the third creative embodiment, with a clock frequency of 1.2GHz, a decoding rate of 12Gbps, and a power consumption of 1.3W; it can quickly switch between RS(528,514) and RS(544,514) specifications through a common header file to adapt to the needs of different optical fiber transmission distances, with an error correction success rate of 99.99%, meeting the reliability requirements of high-speed optical fiber communication.

[0082] Among them, high-speed storage scenarios are used; Application scenarios: Error control modules for high-speed storage devices such as SSDs and USB flash drives, compatible with RS (255,239) standard RS codes, requiring a decoding rate of ≥8Gbps and chip resource usage of ≤15000 logic units.

[0083] Implementation: The RS decoder of the present invention is integrated into a storage control chip (FPGA chip, Xilinx Kintex-7), and configured... =8, employing a resource optimization scheme, occupying 12,000 logic units, with a decoding rate of 8Gbps; through parallel error correction in the error calculation module, the bit error rate of the stored data is reduced from Down to This improves the reliability of stored data, while achieving 100% code reuse and reducing the design cost of storage chips.

[0084] Among them, satellite communication is an application scenario; Application scenario: Error correction module for receivers in satellite communication systems, adapted to RS (360, 326) specification RS code, requiring low power consumption and high reliability, power consumption ≤0.8W, decoding rate ≥4Gbps.

[0085] Implementation: The RS decoder of the present invention is integrated into a satellite communication dedicated chip (ASIC process, 28nm), configured... =4, adopting the low-power optimization scheme of the third creative embodiment, with a clock frequency of 800MHz, a decoding rate of 4.5Gbps, and a power consumption of 0.7W; through the error feedback module (the second creative embodiment), the error correction success rate still reaches 97% in scenarios with weak satellite signals and a high error rate (30%), meeting the harsh environment requirements of satellite communication.

[0086] Among them, IoT terminal application scenarios; Application scenario: Error control module for IoT terminals (such as smart sensors and IoT gateways), adapted to RS (192,186) specification RS code, requiring low power consumption and small size, power consumption ≤0.3W, and chip resource occupation ≤8000 logic units.

[0087] Implementation: The RS decoder of the present invention is integrated into an IoT terminal chip (ASIC process, 40nm), and configured... =2, adopts resource optimization and low power consumption optimization scheme, occupies 7500 logic units, has a decoding rate of 2Gbps and power consumption of 0.25W; through the general header file, it can quickly switch to RS(255,239) specification to adapt to the communication needs of different IoT terminals, with a code reuse rate of 100%, reducing the development cost of IoT terminal chips.

[0088] Among them, the exception handling mechanism To further enhance the robustness of this invention, a handling mechanism for four typical abnormal situations is added to ensure the decoder operates stably in complex chip environments, as follows: Data loss anomaly: When the input RS encoded data is lost (such as transmission interruption), the decoder automatically detects the integrity of the data frame. If data loss is detected, a data retransmission request is immediately triggered, and the decoding operation is paused. Decoding is restarted after the data is replenished to avoid invalid operation and false error correction. Operation table read error: When an error occurs while reading the gf_table or gf_table_inf array (such as a storage unit failure), the decoder automatically activates the backup operation table (pre-stored in the backup storage unit). The switching time is ≤1μs, which does not affect the decoding continuity. At the same time, the error information is recorded for easy maintenance later. Module Failure / Abnormality: When a decoding module (such as the key equation solving module) fails, the decoder automatically switches to a redundant module (a pre-designed backup module). The redundant module has the same logic as the main module, and the switching time is ≤0.5μs, ensuring that the decoding process is not interrupted and improving system reliability. Parameter configuration error: When the parameters in the general header file are configured incorrectly (e.g., ... When the RS code specification is mismatched, the decoder automatically checks the parameter validity. If an anomaly is detected, it immediately outputs a configuration error message and uses the default parameters (e.g., ...). =8, DAT_NUM=4) to start decoding and prevent the decoder from malfunctioning.

[0089] Among them, the comparison with existing technologies A detailed comparison between the present invention and the prior art clarifies the technical improvements and advantages of the present invention, as shown in the table below: As can be seen from the comparison, the present invention is significantly superior to the existing technology in terms of versatility, decoding rate, resource consumption, power consumption control, error correction reliability and robustness, and breaks through the technical bottleneck of traditional RS decoders.

[0090] This invention, through a universal header file design and parallel architecture, overcomes the technical bottlenecks of existing chip-level RS decoders, and its beneficial effects are as follows: This invention encapsulates the core parameters, Galois field tables, and general functions of different RS codes through a predefined universal header file. Each decoding module achieves a universal design by calling the header file. Without modifying the core code of the five major decoding modules, only the macro-defined parameters in the header file need to be adjusted to adapt to RS codes with different Galois field sizes and encoding lengths (such as RS(255,239), RS(450,406), etc.). This completely solves the pain points of poor universality and the need for separate design for different RS codes in traditional RS decoders, significantly reducing chip design workload and development cycle.

[0091] All five decoding modules of this invention are parallelized. Code implementation, through Parallel computing fully utilizes the chip's parallel processing resources, increasing the decoding speed by several times or even tens of times compared to traditional serial decoding architectures (reaching 8Gbps in this embodiment, a 700% improvement). Simultaneously, the parallel computing logic is simple and can be implemented through the hardware pipeline of ASIC / FPGA chips, adapting to the high-speed decoding requirements of scenarios such as fiber optic communication and high-speed storage, thereby improving the overall system transmission efficiency. The core decoding code (five modules) of this invention is 100% reusable. The decoding logic for different RS codes only needs to be adjusted through header file parameters, resulting in extremely low code redundancy (below 5%). Compared to traditional solutions (code redundancy exceeding 60%), this significantly improves code utilization. Simultaneously, the parallel architecture offers high resource reuse, reducing chip resource consumption by more than 50% compared to traditional multiple serial decoders. This significantly reduces chip design costs and hardware overhead, making it highly valuable for engineering implementation.

[0092] The decoding logic of this invention is implemented based on a general header file and parallel computing, eliminating the need for complex dedicated logic design. Core operations are performed by calling functions and arrays in the header file, resulting in a concise and easy-to-understand logic that facilitates later maintenance and upgrades. Furthermore, it is implemented using the Verilog hardware description language, allowing direct adaptation to various chip platforms such as ASICs and FPGAs without extensive modifications. This strong adaptability makes it widely applicable to various digital communication and storage systems requiring error control, improving the reliability of system data transmission.

[0093] This invention utilizes optimization techniques such as segmented storage of the Galois domain arithmetic table, multiplication result caching, and dynamic clock adjustment, and introduces a dynamic power consumption control module to achieve flexible control of decoding power consumption. Compared with existing traditional RS decoders, power consumption is reduced by more than 40%, making it suitable for both low-power scenarios (such as IoT terminals) and high-speed scenarios (such as fiber optic communication).

[0094] This invention designs a comprehensive exception handling mechanism, with corresponding handling schemes for four typical exceptions: data loss, arithmetic table reading errors, module failures, and parameter configuration errors. Through backup modules, parameter verification, and data retransmission, it ensures that the decoder operates stably in complex chip operating environments, avoids decoding interruptions, and improves the reliability and stability of the system.

[0095] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions, and variations can be made to these embodiments, or they can be used directly or indirectly, without departing from the principles and spirit of the invention. In other related technical fields, the scope of the invention is defined by the appended claims and their equivalents, and they are similarly included within the scope of patent protection of the invention.

Claims

1. A method for implementing a high-efficiency, general-purpose Reed-Solomon decoder on a chip, applicable to ASIC chips or FPGA chips, characterized in that, Based on the Galois field operation principle, a parallel decoding architecture is constructed. Multi-RS code adaptation is achieved through a predefined general header file. Decoding of different RS codes can be completed without modifying the core decoding code; only the header file parameters need to be adjusted. Specifically, the following steps are included: S1. Initialization: Start the RS decoder on the chip, import the predefined general header file, configure the core macro definition parameters in the header file, initialize the Galois field operation table and general functions according to the target RS code specification, and enable the parallel decoding function; the general header file contains macro definitions, Galois field operation table and general functions, which are used to uniformly manage the core parameters and operation logic of different RS codes; S2, Data Input: Input the erroneous RS-encoded data according to the preset parallelism. The data is input to the decoder in parallel, and the length of each data stream matches the size of the Galois field element. S3. Parallel computation of the adjoint polynomial: The adjoint polynomial computation module calls the parameters and functions in the general header file to generate general multiplication coefficients, calculates the adjoint polynomial coefficients through parallel multiplication operations, and transmits the results to the key equation solving module. S4. Parallel solution of key equations: The key equation solution module adopts the parallel RIBM algorithm, calls the operation functions in the general header file, and obtains the characteristic roots in parallel based on the coefficients of the adjoint polynomial. The characteristic roots are then transmitted to the Qian search module and the Forney transformation module respectively. S5. Parallel search for error locations: The search module calls the parameters and functions in the general header file to generate general multiplication coefficients, searches for error locations through parallel multiplication operations, and transmits the results to the error calculation module. S6. Parallel error value calculation: The Forney Transform module calls the parameters and functions in the general header file to generate general multiplication coefficients, calculates the error value through parallel multiplication operations, and transmits the result to the error calculation module; S7. Error Correction and Data Output: The error calculation module calls the Galois field inverse element table in the general header file to generate an error matrix. It then corrects the input error data through parallel XOR operations and outputs the correct original data. S8. Repeated execution or specification switching: Repeat steps S2-S7 for subsequent input RS-encoded data; if it is necessary to switch RS code specifications, only the macro definition parameters in the general header file need to be modified, and the core decoding code does not need to be modified to complete the decoding of the new specification RS code.

2. The method for implementing a high-efficiency, universal Reed-Solomon decoder on a chip according to claim 1, characterized in that: The macro definition parameters in the general header file include: Macro The size of the Galois field containing the original polynomial, corresponding to the Galois field. ; Macro The error-correcting code length of the RS code, i.e., the parity bit length, is calculated using the following formula: t is the maximum number of errors to be corrected in the RS code; Macro Parallelism, or the number of data streams processed in a single parallel operation, can be flexibly configured according to chip hardware resources. Macro _ The total length of the RS code, including the length of the original data and the length of the error correction code; Macro The total number of elements in the Galois field is calculated using the following formula: ; The Galois field operation table in the general header file includes: array Size is Storage Galois Domain All elements are used for quick querying of element values ​​within the Galois domain; array _inf: size is Storage Galois Domain The inverse of each element in the set is used to quickly solve the inverse operation.

3. The method for implementing a high-efficiency, universal Reed-Solomon decoder on a chip according to claim 1, characterized in that: The generic functions in the generic header file include: function : A function for descending order of elements in a Galois field, used to sort elements greater than or equal to... Elements of -1 in descending order to the Galois field are represented by the following formula: ； function The Galois field multiplication function is used to perform multiplication of two elements within the Galois field. The formula is: ； Where α is the Galois domain The fundamental element, Let be the logarithm of element a in the Galois field; The accompanying polynomial calculation module, key equation solving module, Qian search module, Furniture transformation module, and error calculation module all adopt... The language is implemented in parallel, with each module working synchronously and in parallel, and data is transmitted in a pipeline manner.

4. The method for implementing a high-efficiency, universal Reed-Solomon decoder on a chip according to claim 1, characterized in that: The multiplication coefficients of the adjoint polynomial calculation module and the Qian search module are obtained through... The nested for loop generates statements, combined with those in the general header file. arrays and Function generation enables universal adaptation to different RS codes; It also includes an error rate detection module, which is used to collect error data from the error calculation module in real time and calculate the current data error rate. And dynamically adjust the parallelism based on the error rate. This achieves a balance between decoding efficiency and chip resource usage.

5. The method for implementing a high-efficiency, general-purpose Reed-Solomon decoder on a chip according to claim 1, characterized in that: It also includes an error feedback module, which feeds back the error correction results of the error calculation module to the accompanying polynomial calculation module and the key equation solving module. If the error correction fails, the operation parameters are adjusted and the decoding is performed again to improve the error correction success rate. The RS code specifications include, but are not limited to, RS(255,239), RS(528,514), RS(544,514), RS(450,406), RS(192,186), and RS(360,326); The parallelism It can be configured to any of 2, 4, 8, or 16, and can be flexibly adjusted according to chip hardware resources and decoding rate requirements.

6. The method for implementing a high-efficiency, general-purpose Reed-Solomon decoder on a chip according to claim 1, characterized in that: The Galois domain arithmetic table adopts a segmented storage + dynamic wake-up mechanism, which only wakes up the arithmetic table segments required by the current RS code specification, and the unused segments enter a low-power sleep state to reduce the static power consumption of the chip. The rs_mul multiplication function introduces a result caching mechanism to cache frequently used multiplication results in a high-speed register, reducing operation table lookup and dynamic power consumption. It also includes a dynamic power consumption control module, which dynamically adjusts the clock frequency of the computing module according to the current decoding rate to achieve a balance between decoding efficiency and power consumption.

7. The method for implementing a high-efficiency, universal Reed-Solomon decoder on a chip according to claim 1, characterized in that: It also includes an exception handling mechanism to handle four typical exceptions: data loss, operation table reading error, module failure, and parameter configuration error, to ensure stable operation of the decoder; The Galois domain operation table adopts a storage unit reuse design, with the gf_table and gf_table_inf arrays reusing the same storage unit and distinguished by read and write control signals to reduce storage resource consumption; In low parallelism scenarios ( (≤4), the operation logic of the Qian search module and the Furni transformation module is time-division multiplexed to reduce the occupation of logic units.

8. The method for implementing a high-efficiency, universal Reed-Solomon decoder on a chip according to claim 1, characterized in that: By using shift registers to store the intermediate results of parallel operations, the number of registers occupied is reduced, and dynamic power consumption is lowered. The decoder is compatible with TSMC ASIC chips using 28nm and 14nm process nodes, as well as Xilinx Kintex-7 and Altera Cyclone V series FPGA chips, without requiring additional dedicated hardware resources.

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