A high-speed serial deserializing receiver based on a double MLSD architecture

Abstract

The application discloses a high-speed serial deserializing receiver based on a dual-MLSD architecture, on the basis of feedforward equalization, in order to cope with the different requirements of the number of MLSD states in the two scenarios that the correlation coefficient is less than or greater than the mode threshold, a dual-MLSD (Dual-MLSD) architecture containing an RS-MLSD with power consumption mode and an FS-MLSD with limit performance mode is designed, the high-speed serial state, the branch decoding process and the independent decoupling are designed into a 2-state 4-branch decoding module, and an Arburg estimation module is constructed to calculate the correlation coefficient value of the high-speed serial signal, that is, the value, the switching of the two modes is completed in cooperation with the low-state and post-filtering module and the high-state decoding module, the optimal area design is achieved, and the optimal power consumption is achieved in each scenario, and the MLSD decoder approximating the limit performance is achieved.

Description

Technical Field

[0001] This invention belongs to the field of high-speed data communication technology. More specifically, it relates to a high-speed serial deserialization (SerDes) receiver based on a dual MLSD (Dual Maximum Likelihood Sequence Detection) architecture, which can be used for serial deserialization of high-speed data at rates of 200G / lane and above to solve the problems of high-intensity inter-symbol interference and noise. Background Technology

[0002] With the explosive growth in bandwidth demands from data centers, high-performance computing, and artificial intelligence networks, SerDes' per-channel transmission rates are advancing from 100G to 200G, 400G, and even higher. The higher the symbol rate, the more severe the system band-limiting of the signal, leading to severe ISI (Inter-Symbol Interference), causing the pulse energy of a single symbol to spread and interfere with multiple or even dozens of adjacent symbols.

[0003] SerDes has transitioned from an analog architecture to a DSP-based architecture. DSPs can leverage algorithms such as FFE (Feed Forward Equalization), DFE (Decision Feedback Equalization), and MLSD to significantly improve transmission capacity. Traditional linear equalizers, such as FFE and DFE, are approaching their performance limits when handling signals of 200G / channel and above. MLSD, on the other hand, is a maximum likelihood sequence detector, theoretically the optimal detection algorithm, based on the Viterbi algorithm to find the sequence with the highest probability among all possible transmission sequences. The design of MLSD plays a crucial role in high-speed SerDes.

[0004] However, the power consumption of MLSDs increases exponentially with memory length and signal status. For large data centers, the computing power interconnect of SerDes and similar systems may use thousands, tens of thousands, or even hundreds of thousands of channels. The increase in power consumption per channel, when considered over the entire data center, becomes hundreds of thousands of times amplified, which is unacceptable. Sometimes, due to the increased interconnect power consumption, a single rack cannot dissipate heat, causing the computing power that could be achieved in a single rack to be distributed across multiple racks, which further increases costs. Therefore, it is necessary to pursue the ultimate power consumption of MLSD architectures.

[0005] In addition, the area of ​​the chip is also a very important factor. In chip designs such as GPUs, if the area of ​​the transmission unit is too large, it will squeeze the area of ​​computing power. Therefore, there are often very high requirements for the area of ​​the transmission unit.

[0006] However, with the gradual increase in transmission speed, traditional MLSD architectures face severe challenges in power consumption and area:

[0007] In relatively low-speed transmission systems, such as 100G SerDes, the maximum bandwidth limit is 40dB. Considering the noise in the link, the effective alpha value of the system generally does not exceed 0.6. In this case, the MLSD algorithm can simplify the design to reduce power consumption. However, as the speed increases to 200G / lane or even higher, the noise and bandwidth limit of the transmission system increase dramatically, and the effective alpha value also increases further. At this point, the simplified MLSD design will no longer meet the requirements, and power consumption and area will increase significantly.

[0008] Therefore, there is an urgent need for a new receiver architecture that can achieve excellent power consumption and area in high-speed interconnects.

[0009] Figure 1 This is the architecture diagram of the existing MLSD algorithm (see: YUKUI YU, YI CHE, TIANWAI BO, DAEHOKIM, ANDHOONKIM*, “Reduced-state MLSE for an IM / DD system using PAMmodulation”, Vol. 28, No. 26 / 21 December 2020 / Optics Express 38505). For example... Figure 1 As shown, (a) is the traditional MLSD algorithm architecture, and the corresponding Viterbi is shown in (b). There are 4 states, corresponding to the four levels of the PAM4 signal, and 16 transitions. We call it Full-State MLSD, or FS-MLSD for short. Figure 1 (c) is the Reduced-state MLSD, also known as RS-MLSD algorithm architecture. It uses FFE to provide decision conditions, reducing the dimension from the original 4 states to 2 states, thereby realizing the computation and transmission of 4 branches, as shown in (d).

[0010] from Figure 1 As we can see, due to the 75% reduction in transmission, the power consumption of the RS-MLSD architecture is only about 30% of that of the full-MLSD architecture.

[0011] However, the use of the RS-MLSD architecture has limitations:

[0012] like Figure 2As shown (see reference: 7.3: A 224Gb / s 3pJ / b 40dB Insertion LossTransceiver in 3nm FinFET CMOS, © 2024 IEEE International Solid-State Circuits Conference)

[0013] RS-MLSD is only applicable to correlation coefficients. The scenario, and the correlation coefficient Once the value exceeds 0.75, the performance of RS-MLSD will decrease, and FS-MLSD is needed to approach the performance limit.

[0014] The correlation coefficient has been defined in the standard definition of 200G SerDes. The maximum value reaches 0.85, meaning that RS-MLSD cannot be used in a considerable number of scenarios.

[0015] How can this challenge be solved in MLSD chip design? One approach, prioritizing power, is to place both RS-MLSD and FS-MLSD within the high-speed serial-to-deserial receiver chip. This allows different MLSDs to be activated for different scenarios, achieving optimal power consumption for each. However, two algorithms mean two separate circuits, requiring two separate chip areas, resulting in wasted space. Alternatively, we could place only one FS-MLSD and use it for all scenarios. While this saves space, the power consumption for each scenario is not optimal. Summary of the Invention

[0016] The purpose of this invention is to overcome the shortcomings of the prior art and provide a high-speed serial deserializer based on a dual MLSD architecture, which enables the high-speed serial deserializer to achieve transmission performance close to the Shannon limit, while achieving optimal power consumption in two scenarios with optimal area: correlation coefficient less than or greater than the mode threshold.

[0017] To achieve the above-mentioned objectives, this invention provides a high-speed serial-to-deserial receiver based on a dual MLSD architecture, comprising an ADC and a feedforward equalizer. The ADC processes the received signal... Perform analog-to-digital conversion to obtain a high-speed serial signal. The signal is then fed into a feedforward equalizer for pre-emphasis processing to compensate for high-frequency attenuation, resulting in a compensated high-speed serial signal. ;

[0018] Its features include:

[0019] Arburg estimation module is used to calculate high-speed serial signals. The correlation coefficient value is value;

[0020] Dual MLSD mode module, by It consists of a 2-state 4-branch decoding module. Equal to high-speed serial signal The number of states;

[0021] Elevation state decoding module;

[0022] The downstate and post-filtering modules, according to Values ​​are used for judgment:

[0023] if The value is less than the set mode threshold. Then, the down-state and post-filtering modules, based on the coarse decision from the feedforward equalizer output, reduce the high-speed serial signal... After the state decreases to two states, it is sent to the dual MLSD mode module, which then... The value is less than the set mode threshold. Initiate the downstate MLSD mode, i.e., RS-MLSD mode. One of the two-state four-branch decoding modules performs the decoding, while the other two-state four-branch decoding modules are in the off state. The decoded information is output to the rising state decoding module, which outputs the decoded symbol based on the decoded information to complete the MLSD decoding.

[0024] if The value is greater than or equal to the set mode threshold. Then, the down-state and post-filtering modules, based on the coarse decision from the feedforward equalizer output, reduce the high-speed serial signal... The state is divided into The status is sent to the dual MLSD mode coupling module, which then determines the status based on the given information. The value is greater than or equal to the set mode threshold. To activate the downgraded MLSD mode, i.e., FS-MLSD mode, Each of the 2-state 4-branch decoding modules respectively... Each state is decoded simultaneously, and the decoded information is sent to the rising state decoding module. The rising state decoding module then... The decoded information from each 2-state 4-branch decoding module, i.e., the comprehensive metric value, selects the optimal probability, outputs the decoded symbol, and completes MLSD decoding.

[0025] The objective of this invention is achieved as follows:

[0026] This invention provides a high-speed serial-to-deserial receiver based on a dual MLSD architecture. Building upon feedforward equalization, to address the different MLSD state requirements in scenarios where the correlation coefficient is less than or greater than the mode threshold, a dual-MLSD architecture is designed, incorporating both RS-MLSD (state-decreasing MLSD, low-power mode) and FS-MLSD (full-state transition MLSD, extreme performance mode). This architecture integrates high-speed serial... One state, The decoding process of the branches is designed with independent decoupling. A 2-state 4-branch decoding module is constructed, and an Arburg estimation module is built for calculating high-speed serial signals. The correlation coefficient value is The value, combined with the down-state and post-filtering modules and the up-state decoding module, completes the switching between the two modes, achieving optimal area design and optimal power consumption in various scenarios, approaching the limit performance of the MLSD decoder. This invention employs a 2-state, 4-branch decoding module to achieve full-state... Branch calculation, broken down into Each partition In each 2-state 4-branch decoding module, each partition performs only 2-state 4-branch decoding calculations, thus realizing independent design and independent switching of each branch. This achieves maximum compatibility of RS-MLSD and FS-MLSD design resources and ensures independent and complete decoupling of power consumption. Attached Figure Description

[0027] Figure 1 The following are existing MLSD architecture diagrams: (a) is the MLSD architecture diagram based on the traditional MLSE (Maximum LikelihoodSequence Equalizer); (b) is the Trellis Diagram of the four states and sixteen transitions of the MLSD based on the traditional MLSE; (c) is the MLSD architecture diagram based on the reduced-state MLSE; and (d) is the Trellis Diagram of the two states and four branches of the MLSD algorithm based on the reduced-state MLSE.

[0028] Figure 2 Bit Error Rate (BER) and Correlation Coefficient Relationship diagram;

[0029] Figure 3 This is a principle block diagram of a specific embodiment of the high-speed serial-to-deserial receiver based on a dual MLSD architecture of the present invention;

[0030] Figure 4 yes Figure 3The diagram shows the working principle of a high-speed serial-to-deserial receiver based on a dual MLSD architecture.

[0031] Figure 5 yes Figure 3 The diagram shows the specific structure of the dual MLSD mode module.

[0032] Figure 6 These are comparison diagrams of mesh diagrams, where (a) is the Trellis Diagram of MLSD with four states and sixteen transitions based on traditional MLSE, and (b) is the partitioned mesh diagram of the present invention. Detailed Implementation

[0033] The specific embodiments of the present invention will now be described with reference to the accompanying drawings to enable those skilled in the art to better understand the invention. It should be particularly noted that in the following description, detailed descriptions of known functions and designs that might obscure the main content of the invention will be omitted here.

[0034] Figure 3 This is a principle block diagram of a specific implementation of the high-speed serial-to-deserial receiver based on a dual MLSD architecture.

[0035] In this embodiment, as Figure 1 As shown, the high-speed serial-to-deserial receiver based on the dual MLSD architecture of this invention includes an ADC 1, a feedforward equalizer (FFE) 2, a timing error detector (TED) 3, and a digital phase-locked loop (DPLL) 4. The ADC 1 processes the received signal... Perform analog-to-digital conversion to obtain a high-speed serial signal. The signal is then fed into feedforward equalizer 2 for pre-emphasis processing to compensate for high-frequency attenuation, resulting in a compensated high-speed serial signal. Simultaneously, timing error detector 3 detects the compensated high-speed serial signal. Perform timing error estimation to obtain the timing error. The signal is then input to digital phase-locked loop 4, which controls the sampling clock of ADC 1 to ensure the compensated high-speed serial signal... With received signal synchronous.

[0036] Based on this, to address the different requirements for the number of MLSD states in scenarios where the correlation coefficient is less than or greater than the mode threshold, a dual-MLSD architecture, namely the dual-MLSD mode module 7, was designed, which includes both RS-MLSD and FS-MLSD modes. An Arburg estimation module 5, a down-state and post-filtering module 6, and a rising-state decoding module 8 were also constructed. Specifically, as follows... Figure 4 As shown:

[0037] Arburg estimation module 5 is used to calculate high-speed serial signals. The correlation coefficient value is The value is the equivalent alpha value of the system.

[0038] like Figure 5 As shown, the dual MLSD mode module 7 consists of It consists of a 2-state 4-branch decoding module. Equal to high-speed serial signal The number of states. In this embodiment, the received signal is received using the PAM4 modulation format commonly used by SerDes receivers. Taking the PAM4 modulation format as an example, at this time, Other higher-priced modulation formats of serial signals are also applicable, but will not be described in detail here.

[0039] like Figure 4 As shown, the down-state and post-filtering module 6 is based on Values ​​are used for judgment:

[0040] if The value is less than the set mode threshold. Then, the down-state and post-filtering module 6, based on the coarse decision output by the feedforward equalizer 2, reduces the high-speed serial signal... After the state is reduced to two states, it is sent to the dual MLSD mode module 7. In this embodiment, the reduced state is one of four states: [-3,-1], [-1,1], [1,3], or [3,-3]. The mode threshold is... Dual MLSD mode module 7 according to The value is less than the set mode threshold. That is, 0.75, to activate the downstate MLSD, i.e., RS-MLSD mode. One of the 2-state 4-branch decoding modules performs the decoding, while the other 2-state 4-branch decoding modules are in the off state. The decoded information is output to the rising state decoding module, which outputs the decoded symbol based on the decoded information, thus completing the MLSD decoding.

[0041] if The value is greater than or equal to the set mode threshold. Then, the down-state and post-filtering module 6, based on the coarse decision output by the feedforward equalizer 2, reduces the high-speed serial signal... The state is divided into The states are sent to the dual MLSD mode coupling module 7. In this embodiment, there are 4 states: [-3,-1], [-1,1], [1,3] and [3,-3].

[0042] Dual MLSD mode coupling module 7 according to The value is greater than or equal to the set mode threshold. To activate the downgraded MLSD mode, i.e., FS-MLSD mode, Each of the 2-state 4-branch decoding modules respectively... Each state is decoded simultaneously, and the decoded information is sent to the rising state decoding module 8. The rising state decoding module 8 then... The decoded information from each 2-state 4-branch decoding module, i.e., the comprehensive metric value, selects the optimal probability, outputs the decoded symbol, and completes MLSD decoding.

[0043] In this embodiment, as Figure 5 As shown, the present invention adopts A 2-state 4-branch decoding module, such as Figure 6 As shown, the full state That is, branching calculation, breaking it down into Each partition In each 2-state 4-branch decoding module, each partition performs only 2-state 4-branch decoding calculations. This enables independent design and independent switching of each branch, thereby maximizing the compatibility of RS-MLSD and FS-MLSD design resources and ensuring independent and complete decoupling of power consumption.

[0044] This invention adaptively selects between RS-MLSD and FS-MLSD modes based on the equivalent alpha value in a scene, maximizing scene performance. In RS-MLSD mode, the computational resources are in a 2-state, 4-branch configuration, exhibiting extremely low power consumption. In FS-MLSD mode, the computational resources are... It has 2 states and 4 branches, for a total of 16 branches, and is capable of extreme performance under extreme conditions.

[0045] The two modes of this invention are passed The 2-state, 4-branch decoding modules for each independent partition can be freely combined. In RS-MLSD mode, only one partition needs to be enabled, while in FS-MLSD mode, all four partitions need to be enabled. The partition decoding modules are connected before and after the 2-state de-splitting and de-splitting modules to achieve signal segmentation and combination for different modes. Ultimately, this helps to achieve optimal performance and power consumption for MLSD in various scenarios, while maintaining a highly efficient application environment.

[0046] Although the illustrative specific embodiments of the present invention have been described above to enable those skilled in the art to understand the invention, it should be understood that the invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of the present invention are protected.

Claims

1. A high-speed serial-to-deserial receiver based on a dual MLSD architecture, comprising an ADC and a feedforward equalizer, wherein the ADC performs equalization on the received signal. Analog-to-digital conversion is performed to obtain a high-speed serial signal. The signal is then fed into a feedforward equalizer for pre-emphasis processing to compensate for high-frequency attenuation, resulting in a compensated high-speed serial signal. ; Its features are, include: Arburg estimation module is used to calculate high-speed serial signals. The correlation coefficient value is value; Dual MLSD mode module, by It consists of a 2-state 4-branch decoding module. Equal to high-speed serial signal The number of states; Elevation state decoding module; The downstate and post-filtering modules, according to Values ​​are used for judgment: if The value is less than the set mode threshold. Then, the down-state and post-filtering modules, based on the coarse decision from the feedforward equalizer output, reduce the high-speed serial signal... After the state decreases to two states, it is sent to the dual MLSD mode module, which then... The value is less than the set mode threshold. Initiate the downstate MLSD mode, i.e., RS-MLSD mode. One of the two-state four-branch decoding modules performs the decoding, while the other two-state four-branch decoding modules are in the off state. The decoded information is output to the rising state decoding module, which outputs the decoded symbol based on the decoded information to complete the MLSD decoding. if The value is greater than or equal to the set mode threshold. Then, the down-state and post-filtering modules, based on the coarse decision from the feedforward equalizer output, reduce the high-speed serial signal... The state is divided into The status is sent to the dual MLSD mode coupling module, which then determines the status based on the given information. The value is greater than or equal to the set mode threshold. To activate the downgraded MLSD mode, i.e., FS-MLSD mode, Each of the 2-state 4-branch decoding modules respectively... Each state is decoded simultaneously, and the decoded information is sent to the rising state decoding module. The rising state decoding module then... The decoded information from each 2-state 4-branch decoding module, i.e., the comprehensive metric value, selects the optimal probability, outputs the decoded symbol, and completes MLSD decoding.

2. The high-speed serial-to-deserial receiver based on a dual MLSD architecture according to claim 1, characterized in that, Received signal It is a PAM4 modulation format. The decreasing states are [-3, -1], [-1, 1], [1, 3], and [3, -3], which are the mode thresholds. .

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