Low-voltage high-frequency HEMT device based on arrayed buried gate modulation and preparation method thereof

Abstract

The application discloses a low-voltage high-frequency HEMT device based on arrayed buried gate modulation and a preparation method, and relates to the technical field of semiconductor devices.The device comprises a substrate, a buffer layer, a potential barrier layer, a source electrode, a drain electrode, a passivation layer and a gate electrode.The gate electrode is composed of a plurality of discrete gate columns arranged at intervals along the gate width direction, penetrating through the potential barrier layer and extending into the buffer layer, and a suspended gate cap connected to the top of each gate column.The structure divides the wide channel into a plurality of parallel nanochannels, efficiently modulates the carriers by using the depletion region formed by the sidewall of the gate column, significantly enhances the gate control ability, and effectively suppresses the short channel effect.Meanwhile, the electric field concentration effect in the nanochannel makes the carriers reach the speed saturation at a lower drain voltage, thereby greatly reducing the knee voltage and realizing low-voltage, high-frequency and high-efficiency operation.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a low-voltage, high-frequency HEMT (High Electron Mobility Transistor) device based on arrayed buried gate modulation and its fabrication method. Background Technology

[0002] The field of semiconductor device technology is continuously evolving towards higher frequencies, higher efficiency, and lower power consumption. Third-generation semiconductor materials, represented by gallium nitride (GaN), have become ideal choices for fabricating high-performance power devices due to their superior characteristics such as high electron saturation velocity and high critical breakdown electric field. However, with the increasing integration of chips and the continuous miniaturization of device dimensions, the channel effect is becoming increasingly prominent, leading to a decline in gate control capability and posing a serious challenge to device reliability. In low-power applications such as mobile communications and RF front-ends, reducing device operating voltage and improving efficiency have become urgent industry needs.

[0003] To improve device performance, existing technologies have proposed various structural optimization schemes. For example, a back barrier structure can suppress the short-channel effect, but this leads to a decrease in the two-dimensional electron gas surface density and enhanced interface scattering. A three-dimensional gate-controlled Fin structure, while enhancing gate control capability, increases gate capacitance, affecting frequency characteristics. Furthermore, divergent sidewall structures reduce knee voltage through asymmetric gate design, but electric field spikes limit breakdown voltage, causing reliability issues. Other technologies use ion implantation to separate channels to reduce parasitic resistance and lower knee voltage, but this sacrifices effective channel width, limiting saturation current capability.

[0004] While the aforementioned methods improve specific performance to some extent, none of them simultaneously achieve a balance between strong gate control capability and low-power, high-frequency operation. Existing structures often introduce new problems when improving a certain performance, such as frequency reduction due to gate control enhancement or low-voltage implementation at the expense of current capability. Therefore, how to achieve low-voltage, high-frequency, and high-efficiency operation while suppressing short-channel effects remains a key technical challenge that urgently needs to be solved in the field of semiconductor devices. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a low-voltage, high-frequency HEMT device based on arrayed buried gate modulation and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a low-voltage, high-frequency HEMT device based on arrayed buried gate modulation, comprising: Substrate; A buffer layer and a barrier layer are sequentially formed on the substrate; The source and drain are disposed on the buffer layer; A passivation layer covering the barrier layer, wherein a gate trench region is provided in the passivation layer between the source and the drain; and the gate disposed in the gate trench region; The gate includes a plurality of discrete gate pillars spaced apart along the gate width direction, penetrating the barrier layer and extending into the buffer layer, and a gate cap connecting the top of the discrete gate pillars; The barrier layer in the gate slot region is not covered by the passivation layer, and the gate cap is suspended and supported by the discrete gate posts.

[0006] In one embodiment of the present invention, along the gate width direction, the discrete gate pillars separate the conductive channels in the barrier layer and buffer layer into multiple independent nanochannels.

[0007] In one embodiment of the present invention, the discrete gate pillars have a cross-sectional shape that is rectangular, circular, or triangular when parallel to the surface of the substrate.

[0008] In one embodiment of the present invention, the width of the discrete gate pillar is 50-200 nm, and the spacing between adjacent discrete gate pillars is equal to the width of the discrete gate pillar.

[0009] In one embodiment of the present invention, the discrete gate pillars penetrate the buffer layer to a depth of 20-50 nm.

[0010] In one embodiment of the present invention, when the HEMT device is an N-polar HEMT device, the barrier layer includes a back barrier layer, a spacer layer and an N-polar channel layer stacked from bottom to top.

[0011] In one embodiment of the present invention, the low-voltage high-frequency HEMT device based on arrayed buried gate modulation further includes a metal interconnect layer connected to the source and the drain.

[0012] In one embodiment of the present invention, the passivation layer is one or more of SiN, SiO2 or Al2O3.

[0013] This invention provides a method for fabricating a low-voltage, high-frequency HEMT device based on arrayed buried gate modulation, applicable to the low-voltage, high-frequency HEMT device based on arrayed buried gate modulation described in any of the above embodiments, comprising the following steps: Step 1: Provide an epitaxial substrate, wherein the epitaxial substrate comprises a substrate, a buffer layer and a barrier layer disposed sequentially from bottom to top; Step 2: Form the source and drain on the buffer layer; Step 3: Deposit a passivation layer on the substrate having the source and drain electrodes; Step 4: Form a gate trench opening region on the passivation layer between the source and the drain to expose the underlying barrier layer; Step 5: Within the gate slot opening area, a plurality of grooves arranged at intervals are etched along the gate width direction to form a groove array that penetrates the barrier layer and extends into the buffer layer; Step 6: Fill the groove array with metal to form multiple discrete grid pillars; Step 7: Form a grid cap at the top of the discrete grid post to connect the discrete grid post, and the grid cap is suspended in the air.

[0014] In one embodiment of the present invention, in step 5, an electron beam lithography is used to define a pattern, and an inductively coupled plasma etching process is used to form the groove array.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The low-voltage high-frequency HEMT device based on arrayed buried gate modulation of the present invention, compared with the previous planar HEMT device, completely abandons the control capability of the top gate cap on the channel carriers, and directly controls the channel by using the gate foot sidewalls that are deep in the buffer layer, which greatly suppresses the subthreshold characteristic degradation caused by the short-channel effect, and realizes short gate control of a thick barrier layer device.

[0016] 2. The low-voltage, high-frequency HEMT device based on arrayed buried gate modulation of this invention fundamentally reduces the operating voltage requirement of the device. The electric field concentration and carrier saturation acceleration effect achieved through the nanochannel structure significantly reduce the knee voltage compared to conventional HEMT devices. This means that the device with this structure has lower static power consumption, requires a lower drain bias voltage to achieve the same output current, and thus reduces DC power consumption; higher power-added efficiency and lower Vknee effectively improve power-added efficiency, thereby overcoming the key bottleneck of multi-channel HEMTs in low-power, high-efficiency RF applications. This makes the device more compatible with low-supply-voltage RF front-end modules and mobile terminals, providing a crucial device-level solution for next-generation high-efficiency energy-saving systems.

[0017] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0018] Figure 1 A three-dimensional structural schematic diagram of a low-voltage high-frequency HEMT device based on arrayed buried gate electric field modulation provided in an embodiment of the present invention; Figure 2A schematic diagram illustrating the working principle of a junction field-effect transistor (n-channel JFET) provided in an embodiment of the present invention; Figure 3 The switching principle of the junction field-effect transistor in HEMT devices provided in the embodiments of the present invention; Figure 4 This is a schematic diagram of the depletion region and electron distribution in the longitudinal section of a low-voltage, high-frequency HEMT device based on arrayed buried gate electric field modulation, within a single cycle in the gate width direction, as the bias voltage increases. Figure 5 A schematic diagram showing the comparison curves of subthreshold characteristics of two different gate type devices provided in an embodiment of the present invention; Figure 6 A schematic diagram showing the comparison of capacitance-voltage (CV) characteristics of two different gate-type devices provided in an embodiment of the present invention; Figure 7 A schematic diagram of the electric field distribution in a top view (without passivation) of a low-voltage high-frequency HEMT device based on arrayed buried gate electric field modulation, provided for an embodiment of the present invention; Figure 8 This is a schematic diagram comparing the output characteristics of two different gate-type devices provided in an embodiment of the present invention; Figure 9 A schematic diagram illustrating the fabrication method of a low-voltage, high-frequency HEMT device based on arrayed buried gate electric field modulation provided in an embodiment of the present invention; Figure 10 A process flow diagram for fabricating a low-voltage, high-frequency HEMT device based on arrayed buried gate electric field modulation, provided for an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of an N-polar HEMT device based on arrayed buried gate electric field modulation according to an embodiment of the present invention. Detailed Implementation

[0019] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail, with reference to the accompanying drawings and specific embodiments, a low-voltage high-frequency HEMT device based on arrayed buried gate modulation and its fabrication method proposed according to the present invention.

[0020] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0021] In a first aspect, embodiments of the present invention provide a low-voltage, high-frequency HEMT device based on arrayed buried gate modulation.

[0022] Example 1 Please see Figure 1 , Figure 1 This is a three-dimensional structural diagram of a low-voltage, high-frequency HEMT device based on arrayed buried gate electric field modulation, provided in an embodiment of the present invention.

[0023] like Figure 1 As shown, the low-voltage high-frequency HEMT device based on arrayed buried gate modulation in this embodiment includes a substrate 101, a buffer layer 102, a barrier layer 103, a source 104, a drain 105, a passivation layer 106, a gate, and a metal interconnect layer 109.

[0024] Specifically, the substrate 101 is made of sapphire, SiC, or Si. A buffer layer 102 is formed on the substrate 101, and its material is intrinsic or weakly doped GaN. A barrier layer 103 is formed on the buffer layer 102, and its material is AlGaN, InAlN, or AlN, etc.

[0025] Source 104 and drain 105 are fabricated at both ends of the barrier layer 103 / buffer layer 102 structure, located on the buffer layer 102. Their material is an ohmic contact metal stack, for example, Ti / Al / Ni / Au from bottom to top. Passivation layer 106 covers the source 104, drain 105, and part of the barrier layer 103. Its material is one or more of SiN, SiO2, or Al2O3, and the thickness of passivation layer 106 is, for example, 20-120 nm. The passivation layer 106 is etched away in the region between the source 104 and drain 105 to form a gate trench region.

[0026] The gate is disposed in the gate trench region and includes multiple discrete gate pillars 107 spaced apart along the gate width direction (i.e., perpendicular to the source-drain direction), and a gate cap 108 connecting the tops of all discrete gate pillars 107. Each discrete gate pillar 107 penetrates the barrier layer 103 and extends downward into the buffer layer 102 to a certain depth, for example, 20-50 nm. The width (dimension in the gate width direction) of the discrete gate pillars 107 is 50-200 nm, and the spacing between adjacent discrete gate pillars 107 is the same as its width.

[0027] Optionally, the discrete gate post 107 has a cross-sectional shape that is rectangular, circular, or triangular when parallel to the surface of the substrate 101.

[0028] In this embodiment, the top of the barrier layer 103 in the gate trench region is completely exposed and not covered by the passivation layer 106. The gate cap 108 is suspended, and its bottom has no contact with the surface of the passivation layer 106 or the barrier layer 103. It is only physically supported and electrically connected by the discrete gate pillars 107 below. Along the gate width direction, the discrete gate pillars 107 separate the conductive channels in the barrier layer 103 and the buffer layer 102 into multiple independent nanochannels.

[0029] In this embodiment, the metal interconnect layer 109 is fabricated on top of the passivation layer 106 and is connected to the source 104 and drain 105 through etched contact holes to achieve external circuit connection. Optionally, the metal interconnect layer 109 is a Ti and Au stacked metal layer from bottom to top.

[0030] The low-voltage, high-frequency HEMT device based on arrayed buried gate modulation in this embodiment draws on the working principle of a junction field-effect transistor (n-channel JFET). Please refer to [link to relevant documentation]. Figure 2 , Figure 2 This is a schematic diagram illustrating the working principle of a junction field-effect transistor (n-channel JFET) provided in an embodiment of the present invention.

[0031] like Figure 2 As shown, the applied voltage V GS and V DS Both can change the thickness of the depletion layer in the pn junction, thereby changing the length and width of the channel. The gates on both sides control the depletion region along the direction perpendicular to the channel. The source-drain electrode difference makes the depletion layer trapezoidal along the channel direction. For an n-channel JFET device, its pinch-off voltage V P Less than 0, when V GS =0V, the channel is fully open, and the conductivity is at its maximum. When V P <V GS At <0V, the channel width varies with gate voltage. As the drain voltage increases, the depletion region near the drain becomes wider, and the channel becomes narrower. DS When a certain threshold is reached, the channel near the drain is almost pinched off, and the current is in constant saturation. GS ≤V P The depletion regions on both sides are connected, and the channel is clamped off. Utilizing the above-mentioned depletion-type JFET device working principle, the discontinuous gate pins divide the device into several nanochannels similar to junction field-effect transistors. Each discrete gate pillar 107 forms a Schottky contact or pn-like junction with the semiconductors on both sides (barrier layer 103 and buffer layer 102), and its sidewalls are equivalent to the gate of the JFET.

[0032] Please see Figure 3 , Figure 3 The switching principle of the junction field-effect transistor in HEMT devices provided in the embodiments of the present invention; such as Figure 3 As shown, the core of the device structure in this embodiment of the invention lies in relying on the gate pin sidewalls to generate a depletion region in the channel. An external bias voltage controls the thickness and extension direction of the depletion layer. As the gate voltage gradually increases, the depletion region formed by the sidewalls gradually widens, and the number of charge carriers per unit cross-section of the channel gradually decreases. For details, please refer to [link to relevant documentation]. Figure 4 , Figure 4This is a schematic diagram showing the depletion region and electron distribution within a longitudinal section of the gate width direction of a low-voltage, high-frequency HEMT device based on arrayed buried gate electric field modulation, as the bias voltage increases. Figure 4 As shown, the channel is almost clamped off when the leakage voltage reaches a certain value, and the current is in a constant current state.

[0033] In this embodiment, the device is pinched off by the depletion region generated by the side gates on both sides of the channel, such as Figure 1 As shown, in the longitudinal cross-section along the gate width direction of the device, there is no passivation layer above the channel. Since the lateral spacing of a single sub-channel is much greater than the longitudinal thickness of the channel, and the growth rates of the sidewall and top depletion layer are similar, the passivation layer above the channel is etched away to prevent the channel from being preferentially pinched off by the longitudinally extending depletion layer. Compared with planar devices, the device structure proposed in this invention abandons the control capability of the top gate cap over the channel, and instead uses the side gate that extends into the buffer layer to indirectly regulate the channel carriers. This structure has stronger gate control capability and fundamentally avoids the negative impact of the short-channel effect.

[0034] Please see Figure 5 and Figure 6 , Figure 5 A schematic diagram showing the comparison curves of subthreshold characteristics of two different gate type devices provided in an embodiment of the present invention; Figure 6 This is a schematic diagram comparing the capacitance-voltage (CV) characteristics of two different gate-type devices provided in an embodiment of the present invention. Figure 5 As shown, arrayed buried gate devices exhibit smaller subthreshold swings, enabling control of thicker barrier layers with shorter gate lengths. Furthermore, due to the gradual channel pinch-off process, compared to conventional devices, arrayed buried gate devices show a more gradual step when the capacitance depletes during turn-on, specifically as follows: Figure 6 As shown, this reduces the impact of electrical stress on reliability and can extend the device's lifespan.

[0035] By using discrete gate pillars 107 deeply embedded within the buffer layer 102, the channel is divided into several independently distributed nano-conductive channels along the gate width direction. The total width of these conductive channels is smaller than the width of the source and drain terminals of the device, making the electric field lines within the channels more concentrated. Under the same bias voltage, the electric field strength within the channels is higher, and the carrier acceleration is increased. Specifically, as shown... Figure 8 As shown, Figure 8 This is a schematic diagram comparing the output characteristics of two different gate-type devices provided in an embodiment of the present invention. As can be seen from the diagram, compared to the traditional structure, the drain current of the arrayed buried gate device of the present invention can quickly reach saturation at a lower gate voltage, resulting in a lower knee voltage and ultimately achieving low-voltage applications. Furthermore, according to the formula... and It can be seen that the lower the knee voltage, the higher the output power and the higher the power-added efficiency. For output power, Maximum drain current, This is the breakdown voltage. Knee voltage, Add efficiency to power. For input power, The total power supplied to the DC power source.

[0036] Based on the above theory, different masks can be fabricated using electron beam lithography to etch grooves with different cross-sectional shapes, thus accommodating devices with varying performance requirements. Please see [link to relevant documentation]. Figure 7 , Figure 7 This is a schematic diagram of the electric field distribution in a top view (without passivation) of a low-voltage, high-frequency HEMT device based on arrayed buried gate electric field modulation, provided as an embodiment of the present invention. Figure 7 As shown, conventional rectangular grid pillars are mainly used in low-voltage applications. For circular grid pillars, the number of electric field lines concentrated in a single channel increases, the electric field strength near the channel increases, and the uneven junction temperature at the sharp edge of the pattern is avoided. This can achieve low voltage while mitigating the efficiency degradation caused by self-heating. For triangular grid pillars, the position of electric field line concentration can be changed by changing the orientation of the apex of the pattern, and the position of the electric field peak can be controlled to avoid premature breakdown.

[0037] Example 2 This invention also provides an N-polar HEMT device; please refer to [link to relevant documentation]. Figure 11 , Figure 11 This is a schematic diagram of the structure of an N-polarity HEMT device based on arrayed buried gate electric field modulation, according to an embodiment of the present invention. Figure 11 As shown, the N-polar HEMT device based on arrayed buried gate electric field modulation in this embodiment includes, from bottom to top: a substrate 201, an unintentionally doped GaN buffer layer 202, an AlGaN back barrier layer 203a, an AlN spacer layer 203b, and an N-polar GaN channel layer 203c. The source 204 and drain 205 are fabricated on the GaN buffer layer 202 and form ohmic contacts. A passivation layer 206 covers the device surface and has a gate trench region.

[0038] Understandably, the material of the back barrier layer 203 can also be InAlN or AlN.

[0039] The gate also includes periodically arranged discrete gate pillars 207 and a floating gate cap 208. The discrete gate pillars 207 penetrate the N-polar GaN channel layer 203c and extend into the underlying GaN buffer layer 202. Other features of the device, such as gate pillar size, shape, and floating gate cap, are similar to those in Embodiment 1 and will not be described in detail here.

[0040] In this embodiment, the N-polar material system inherently possesses a back barrier (provided by the AlGaN back barrier layer 203a), which better confines charge carriers within the channel layer. Combined with the strongly gate-controlled arrayed buried gate structure provided by this invention, stronger and more complete control over the channel can be achieved in a small size, further suppressing the short-channel effect. At the same time, the thicker barrier layer structure makes the buried discrete gate pillars 207 more stable.

[0041] The low-voltage, high-frequency HEMT device based on arrayed buried gate electric field modulation of the present invention has a wide range of structural compatibility. In addition to conventional rectangular gate pillars, circular gate pillars can realize ultra-low voltage applications, and triangular gate pillars can improve breakdown characteristics by adjusting the position of electric field peaks. Therefore, by changing the shape of the discrete gate pin cross-section, low voltage and strong gate control can be achieved while taking into account other performance requirements. It can also be applied to N-polar HEMT devices. A thicker barrier layer can make the buried gate pillar more stable, and thanks to the confinement of the natural back barrier, N-polar GaN HEMTs are more likely to form high-frequency devices that simultaneously meet the requirements of small size and strong gate control.

[0042] Secondly, embodiments of the present invention provide a method for fabricating a low-voltage, high-frequency HEMT device based on arrayed buried gate electric field modulation. This method is applicable to the low-voltage, high-frequency HEMT device based on arrayed buried gate modulation provided in the first aspect.

[0043] Please see Figure 9 , Figure 9 This is a schematic diagram illustrating the fabrication method of a low-voltage, high-frequency HEMT device based on arrayed buried gate electric field modulation, as provided in an embodiment of the present invention. Figure 9 As shown, the fabrication method of the low-voltage high-frequency HEMT device based on arrayed buried gate modulation according to an embodiment of the present invention may include the following steps: Step 1: Provide an epitaxial substrate, which includes a substrate, a buffer layer and a barrier layer disposed sequentially from bottom to top; Step 2: Form the source and drain on the buffer layer; Step 3: Deposit passivation layers on the substrate to form the active and drain electrodes; Step 4: Form a gate trench opening region on the passivation layer between the source and drain to expose the underlying barrier layer; Step 5: In the gate trench opening area, a multiple trench array with spacing is formed by etching along the gate width direction, penetrating the barrier layer and extending into the buffer layer; wherein, electron beam lithography is used to define the pattern, and inductively coupled plasma etching process is used to form the trench array. Step 6: Fill the groove array with metal to form multiple discrete grid pillars; Step 7: Form a grid cap at the top of the discrete grid post to connect the discrete grid post, with the grid cap suspended in the air.

[0044] Example 3 Taking the low-voltage, high-frequency HEMT device based on arrayed buried gate electric field modulation shown in Example 1 as an example, combined with Figure 10 The preparation method and process flow are described in detail. Figure 10 A process flow diagram for fabricating a low-voltage, high-frequency HEMT device based on arrayed buried gate electric field modulation, provided for embodiments of the present invention.

[0045] The specific process steps are as follows: Step 1: Preparation of source-drain ohmic contacts.

[0046] 1a) Provide a commercial or self-developed epitaxial substrate, which, from bottom to top, comprises a SiC substrate, a GaN buffer layer, and an AlGaN barrier layer. Spin-coat photoresist on the surface of the epitaxial substrate, and define the source and drain electrode pattern regions by photolithography.

[0047] 1b) Evaporation by electron beam under a vacuum level better than 2×10 -6 Under Torr conditions, Ti / Al / Ni / Au metal stacks are deposited sequentially.

[0048] 1c) Remove the metal outside the pattern by stripping, and then perform rapid thermal annealing for 30 seconds in a N2 atmosphere at a temperature of 830°C to form the source and drain electrodes.

[0049] Step 2, create countertop partition.

[0050] 2a) Define the active region using photolithography.

[0051] 2b) Inductively coupled plasma (ICP) dry etching technology is used to sequentially etch the AlGaN barrier layer and GaN buffer layer in the electrically isolated region to achieve mesa isolation of the active region. The total etching depth is 100 nm.

[0052] Step 3: Deposit a SiN passivation layer.

[0053] Using plasma-enhanced chemical vapor deposition (PECVD) technology, a SiN thin film with a thickness of about 60 nm was grown on the entire device surface at 250 °C with SiH4 and NH3 as the reaction gas source, as a surface passivation layer.

[0054] Step 4: Deeply etch the gate opening and the nanogroove array.

[0055] 4a) Gate trench opening: A gate strip pattern is photolithographically etched on the passivation layer, and the SiN passivation layer in the gate trench area is removed using ICP etching until the surface of the underlying AlGaN barrier layer is exposed, forming a gate trench.

[0056] 4b) Deep trench array etching: In the gate trench region, periodic gate pillar patterns are defined using electron beam lithography. Deep etching is performed using ICP with an etching formula for nitrides to completely etch through the AlGaN barrier layer within the gate pillar pattern. Subsequently, the underlying GaN buffer layer is etched, with the etching depth of the buffer layer controlled at 20-50 nm, ultimately forming a periodic rectangular trench array that penetrates the heterojunction and is deeply embedded inside the buffer layer.

[0057] Step 5, gate fabrication.

[0058] 5a) Gate pillar metal evaporation: In the gate trench area, periodic gate pillar patterns are defined using electron beam lithography. Through evaporation and stripping processes, Ni / Au / Ni multilayer metal is filled in the trench array to form discrete gate pillars that match the shape of the trench.

[0059] 5b) Metal Deposition to Form an Unsupported Gate Cap: Photolithography is performed again to evaporate a thicker layer of gate metal on top of the discrete gate pillars. After peeling, a suspended gate cap connecting the discrete gate pillars is formed. This structure ensures that the gate electrode is coupled to the channel only through the gate pillars, avoiding interference from the top passivation layer. Finally, the gate metal is annealed at 860°C for 60 seconds to complete the gate fabrication.

[0060] Step 6: Fabricate the metal interconnect layer.

[0061] 6a) Photolithography and etching of the passivation layer to remove the 60nm thick SiN passivation layer in the interconnect opening area; 6b) Evaporate interconnect metal on the electrodes and SiN passivation layer in the metal interconnect region and on the photoresist outside the metal interconnect region to form a metal interconnect layer. The metal interconnect layer is a metal stack structure consisting of two layers, Ti and Au, arranged from bottom to top, to bring out the electrodes and complete the device fabrication.

[0062] Understandably, the process variations when fabricating gate pillars with different cross-sectional shapes (e.g., circular or triangular) primarily differ from step 4b in Example 3. For circular gate pillars, the pattern defined using electron beam lithography is a periodic circular aperture array (e.g., 100 nm in diameter, 200 nm in center-to-center spacing). Deep etching with ICP forms a circular groove array. Metal is then filled into the circular grooves to form cylindrical gate pillars. This shape facilitates uniform electric field and heat distribution, mitigating self-heating effects. For triangular gate pillars, the pattern defined using electron beam lithography is a periodic triangular aperture array (e.g., isosceles triangles with apex pointing towards the drain). Deep etching with ICP forms a triangular groove array. Metal is then filled to form triangular prism gate pillars. By designing the orientation of the triangular apex, the position of the electric field peaks in the channel can be actively controlled, thereby optimizing the device's breakdown characteristics.

[0063] This invention relates to a low-voltage, high-frequency HEMT device and its fabrication method based on arrayed buried gate modulation. By utilizing the sidewalls of discrete gate pillars deeply embedded in the channel for depletion modulation, it achieves stronger and more direct three-dimensional control of channel carriers, fundamentally alleviating the short-channel effect caused by gate length shortening. The nanochannel structure generates an electric field concentration effect, accelerating carrier saturation and increasing the knee voltage (V). knee The power consumption is significantly reduced, which not only lowers static power consumption but also enables the device to achieve higher output power and power-added efficiency at low supply voltages, making it particularly suitable for low-power applications such as 5G RF front-ends. The cross-sectional shape of the discrete gate pillars (rectangular, circular, triangular) can serve as a degree of design freedom to specifically optimize the electrical, thermal, or reliability performance of the device (e.g., circular shapes improve heat dissipation, triangular shapes control breakdown), enabling customized performance. Its fabrication process is compatible with existing semiconductor micro / nano fabrication technologies, making it suitable not only for mainstream Ga-polar HEMTs but also for successful integration into N-polar HEMTs with inherent advantages, demonstrating broad application prospects.

[0064] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0065] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0066] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A low-voltage, high-frequency HEMT device based on arrayed buried gate modulation, characterized in that, include: Substrate; A buffer layer and a barrier layer are sequentially formed on the substrate; The source and drain are disposed on the buffer layer; A passivation layer covering the barrier layer, wherein a gate trench region is provided in the passivation layer between the source and the drain; and the gate disposed in the gate trench region; The gate includes a plurality of discrete gate pillars spaced apart along the gate width direction, penetrating the barrier layer and extending into the buffer layer, and a gate cap connecting the top of the discrete gate pillars; The barrier layer in the gate slot region is not covered by the passivation layer, and the gate cap is suspended and supported by the discrete gate posts.

2. The low-voltage high-frequency HEMT device based on arrayed buried gate modulation according to claim 1, characterized in that, Along the gate width direction, the discrete gate pillars separate the conductive channels within the barrier layer and buffer layer into multiple independent nanochannels.

3. The low-voltage high-frequency HEMT device based on arrayed buried gate modulation according to claim 1, characterized in that, The discrete grid pillars have a cross-sectional shape that is rectangular, circular, or triangular, parallel to the surface of the substrate.

4. The low-voltage high-frequency HEMT device based on arrayed buried gate modulation according to claim 1, characterized in that, The width of the discrete gate pillar is 50-200nm, and the spacing between adjacent discrete gate pillars is equal to the width of the discrete gate pillar.

5. The low-voltage high-frequency HEMT device based on arrayed buried gate modulation according to claim 1, characterized in that, The discrete gate pillars penetrate the buffer layer to a depth of 20-50 nm.

6. The low-voltage high-frequency HEMT device based on arrayed buried gate modulation according to claim 1, characterized in that, When the HEMT device is an N-polar HEMT device, the barrier layer includes a back barrier layer, a spacer layer, and an N-polar channel layer stacked from bottom to top.

7. The low-voltage high-frequency HEMT device based on arrayed buried gate modulation according to claim 1, characterized in that, It also includes a metal interconnect layer connected to the source and the drain.

8. The low-voltage high-frequency HEMT device based on arrayed buried gate modulation according to claim 1, characterized in that, The passivation layer is one or more of SiN, SiO2, or Al2O3.

9. A method for fabricating a low-voltage, high-frequency HEMT device based on arrayed buried gate modulation, characterized in that, The low-voltage, high-frequency HEMT device based on arrayed buried gate modulation as described in any one of claims 1-8 includes the following steps: Step 1: Provide an epitaxial substrate, wherein the epitaxial substrate comprises a substrate, a buffer layer and a barrier layer disposed sequentially from bottom to top; Step 2: Form the source and drain on the buffer layer; Step 3: Deposit a passivation layer on the substrate having the source and drain electrodes; Step 4: Form a gate trench opening region on the passivation layer between the source and the drain to expose the underlying barrier layer; Step 5: Within the gate slot opening area, a plurality of grooves arranged at intervals are etched along the gate width direction to form a groove array that penetrates the barrier layer and extends into the buffer layer; Step 6: Fill the groove array with metal to form multiple discrete grid pillars; Step 7: Form a grid cap at the top of the discrete grid post to connect the discrete grid post, and the grid cap is suspended in the air.

10. The method for fabricating a low-voltage, high-frequency HEMT device based on arrayed buried gate modulation according to claim 9, characterized in that, In step 5, an electron beam lithography pattern is defined, and the groove array is formed by inductively coupled plasma etching.

Images