A high on-off ratio structure design and preparation method of a bipolar two-dimensional transistor

Abstract

The application discloses a high on-off ratio structure design and preparation method of a bipolar two-dimensional transistor, and has the characteristics that the device comprises a bottom dielectric layer arranged on a back gate, a bottom two-dimensional material channel covered on the bottom dielectric layer, a low dielectric constant isolation layer covered on the bottom two-dimensional material channel, a top two-dimensional material channel covered on the low dielectric constant isolation layer, a top dielectric layer covered on the top two-dimensional material channel, and a device top gate covered on the top dielectric layer; the bottom two-dimensional material channel is in contact with an N-type metal at both ends, and the top two-dimensional material channel is in contact with a P-type metal at both ends. Compared with the prior art, the application has the advantages that the device transfer characteristic is adjusted through the upper and lower double-gate double-two-dimensional channel structure of different work functions, a high on-off ratio greater than 10 10 is realized, the application is especially suitable for application in the field of high-density large-scale digital logic integrated circuits, further expands the development of the bipolar field effect transistor in a logic circuit, and has a good application prospect.

Description

Technical Field

[0001] This invention relates to the field of field-effect transistor technology, specifically to a high on / off ratio structure design and fabrication method for a bipolar two-dimensional transistor. Background Technology

[0002] As complementary metal-oxide-semiconductor (CMOS) technology approaches its physical and thermodynamic scaling limits, integrated circuits face unprecedented challenges in terms of power density, short-channel effects, and interconnect delays. With Moore's Law slowing down, academia and industry are turning their attention to novel electronic devices with entirely new physical transport mechanisms to overcome the computing power and energy efficiency bottlenecks of the von Neumann architecture. Among these, field-effect transistors (FETs) with ambipolar transport characteristics exhibit extremely high logic expression capabilities and system reconfiguration potential due to their ability to simultaneously realize electron (n-type) and hole (p-type) transport in a single device. The typical transfer characteristic curves of bipolar devices exhibit a significant "U"-shaped or "V"-shaped feature. This characteristic not only reveals the physics of carrier injection in the band structure but also provides new degrees of freedom for novel logic circuits and radio frequency (RF) applications.

[0003] However, early research on bipolar devices largely focused on intrinsically bipolar materials, such as graphene, black phosphorus, and two-dimensional transition metal chalcogenides (WSe2). While these materials exhibited the potential for bidirectional conductivity, they were often limited by low on / off ratios, asymmetric carrier mobility, and unipolarity due to Fermi level pinning. To overcome these intrinsic limitations, recent research has fundamentally shifted its focus, moving towards bipolar devices that artificially shape "U"- or "V"-shaped transfer curves through heterojunction engineering, bandgap engineering, and complex multi-gate structure design.

[0004] In summary, existing field-effect transistors have low current on / off ratios and bidirectional conductivity, exhibit asymmetric carrier mobility, and suffer from unipolarity due to Fermi level pinning. Summary of the Invention

[0005] The purpose of this invention is to provide a high on / off ratio structure design for a bipolar two-dimensional transistor, addressing the shortcomings of existing technologies. It employs metals with different work functions as the bottom and back gates. During the gate voltage scan from negative to positive, the transfer curves of the N-type and P-type channels are adjusted separately. By using a dual-gate, dual-two-dimensional channel structure with different work functions at the top and bottom, the device's transfer characteristics are adjusted, achieving a ratio greater than 10. 10This high-switching-ratio bipolar device significantly improves the switching ratio of the bipolar curve, further expanding the application of bipolar field-effect transistors in logic circuits. It has promising application prospects and commercial development value.

[0006] The specific technical solution for achieving the objective of this invention is as follows: a high on / off ratio structure design for a bipolar two-dimensional transistor, characterized in that the high on / off ratio structure of the bipolar two-dimensional transistor includes: a device back gate, a bottom dielectric layer covering the device back gate, a bottom two-dimensional material channel covering the bottom dielectric layer, a low dielectric constant isolation layer covering the bottom two-dimensional material channel, a top two-dimensional material channel covering the low dielectric constant isolation layer, a top dielectric layer covering the top two-dimensional material channel, and a device top gate covering the top dielectric layer; the two ends of the bottom two-dimensional material channel are in contact with N-type metal, and the two ends of the top two-dimensional material channel are in contact with P-type metal; the two parts of the N-type metal and the two parts of the P-type metal are respectively connected to VDD and GND; the device back gate and the device top gate are connected to a common gate voltage VG; a low dielectric constant isolation layer with a dielectric constant of 2.7 is used to isolate the bottom two-dimensional material channel and the top two-dimensional material channel.

[0007] A method for fabricating a high on / off ratio structure of a bipolar two-dimensional transistor, characterized by the following fabrication method... Specifically, it includes: 1) Deposit the bottom gate and source / drain of the device The substrate bottom gate Al electrode and the two metal electrodes of the bottom N-type metal Ti source and drain ports are prepared by sputtering or evaporation processes. 2) Deposition of the bottom dielectric layer A bottom dielectric layer, such as HfO2, ZrO2, or Al2O3, is deposited on top of the bottom gate Al electrode using an ALD process as the first gate dielectric layer. 3) Transfer of WSe2 thin film in dielectric layer After the first dielectric layer is prepared, the first monolayer WSe2 film obtained by mechanical peeling process is precisely transferred and attached to the surface of the bottom dielectric layer by wet transfer technology. 4) Deposit and etch the isolation layer A low dielectric constant material is deposited using the ALD process, and an isolation layer is formed using an etching process to construct a separate channel structure; then, the areas that need to be stacked again are exposed. 5) Transfer of WSe2 thin film in the isolation layer The second monolayer WSe2 film obtained by mechanical peeling process was transferred again using wet transfer to the pre-prepared low dielectric constant isolation layer. 6) Deposit the top dielectric layer The top dielectric layer is deposited using the ALD process as the top gate dielectric. 7) Deposit the top gate and source / drain of the device The entire device is fabricated by sputtering or evaporation processes to prepare the top metal gate and two metal electrodes at the top P-type Pt source / drain ports.

[0008] Compared with the prior art, the present invention has the following beneficial technical advancements and significant technical effects: 1) By controlling the bottom two-dimensional material channel and the top two-dimensional material channel respectively by gates with different metal work functions, and isolating the bottom two-dimensional material channel and the top two-dimensional material channel with a low dielectric constant material, the mutual influence between the channels is reduced, and the voltage drop of the top gate voltage of the device is avoided from acting on the bottom two-dimensional material channel and the voltage drop of the back gate voltage of the device is avoided from acting on the top two-dimensional material channel. This achieves a bipolar "U" curve with an extremely high current switching ratio, improves the performance of bipolar devices, and expands the application of bipolar devices in logic circuits. 2) This device improves the current switching ratio of bipolar devices, enabling its application in high-density large-scale digital logic integrated circuits and promoting the further development of advanced technology nodes; 3) This device can achieve greater than 10 10 The improved current switching ratio further expands the application of bipolar field-effect transistors in logic circuits. Attached Figure Description

[0009] Figure 1 A schematic diagram of the high on / off ratio structure of the bipolar two-dimensional transistor designed for Example 1; Figure 2 for Figure 1 The left view; Figure 3 This is a flowchart of the preparation method for Example 1; Figure 4 The transfer curve of the high switching ratio structure designed for Example 1. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings and examples. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] Example 1 See Figures 1-2This embodiment of a high on / off ratio structure design for a bipolar two-dimensional transistor includes: a device back gate 101, a bottom dielectric layer 102 covering the device back gate 101, a bottom two-dimensional material channel 103 covering the bottom dielectric layer 102, a low dielectric constant isolation layer 104 covering the bottom two-dimensional material channel 103, a top two-dimensional material channel 105 covering the low dielectric constant isolation layer 104, a top dielectric layer 106 covering the top two-dimensional material channel 105, and a device top gate 107 covering the top dielectric layer 106; the two ends of the bottom two-dimensional material channel 103 are in contact with N-type metal 108, and the two ends of the top two-dimensional material channel 105 are in contact with P-type metal 109. The two parts of the N-type metal 108 are connected to VDD and GND respectively, and the two parts of the P-type metal 109 are also connected to VDD and GND respectively. That is, the N-type source and the P-type source are connected to GND together, and the N-type drain and the P-type drain are connected to VDD together. The back gate 101 and the top gate 107 of the device are connected to the common gate voltage VG.

[0012] The back gate 101 of the device is preferably made of Au, and the top gate 107 is preferably made of Al. Other materials with metallic properties can also be selected according to the work function. The bottom dielectric layer 102 and the top dielectric layer 106 are made of HfO2. Other materials with insulating properties can also be selected. The bottom two-dimensional material channel 103 and the top two-dimensional material channel 105 are made of WSe2 with a thickness of 0.7 nm. A single-layer two-dimensional transition metal sulfide or other two-dimensional materials with semiconductor properties can also be selected. The low dielectric constant isolation layer is made of SiOC with a dielectric constant of 2.7. In this embodiment, the smaller the dielectric constant, the better the isolation effect. The N-type metal 108 is made of Ti, and the P-type metal 109 is made of Pt. Other suitable metal materials can also be selected according to the work function.

[0013] When the gate voltage VG scans from negative to positive, holes from the drain of the P-type metal 109 are first injected into the top two-dimensional material channel 105 and then collected at the source. At this time, under the action of the negative gate voltage VG, the top two-dimensional material channel is turned on and the bottom two-dimensional material channel is turned off, forming the P-type branch of the "U"-shaped curve. When the gate voltage VG is equal to zero, both the top and bottom two-dimensional material channels are turned off, and the device is in a completely off state. When the gate voltage VG is greater than zero, the bottom two-dimensional material channel 103 gradually turns on, and electrons from the source of the N-type metal 108 enter the bottom two-dimensional material channel 103 and are collected by the drain. At this time, under the action of the positive gate voltage VG, the bottom two-dimensional material channel turns on and the top two-dimensional material channel is turned off, forming the N-type branch of the "U"-shaped curve.

[0014] See Figure 3 The fabrication of the high on / off ratio structure of the bipolar two-dimensional transistor involves a seven-step process to obtain the final device prototype, specifically including: 1) Deposit the bottom gate and source / drain of the device The substrate bottom gate Al electrode and the two metal electrodes of the bottom N-type metal Ti source and drain ports are prepared by sputtering or evaporation processes. 2) Deposition of the bottom dielectric layer A bottom dielectric layer, such as HfO2, ZrO2, or Al2O3, is deposited on top of the bottom gate Al electrode using an ALD process as the first gate dielectric layer. 3) Transfer of WSe2 thin film in dielectric layer After the first dielectric layer is prepared, the first monolayer WSe2 film obtained by mechanical peeling process is precisely transferred and attached to the surface of the bottom dielectric layer by wet transfer technology. 4) Deposit and etch the isolation layer A low dielectric constant material is deposited using the ALD process, and an isolation layer is formed using an etching process to construct a separate channel structure; then, the areas that need to be stacked again are exposed. 5) Transfer of WSe2 thin film in the isolation layer The second monolayer WSe2 film obtained by mechanical peeling process was transferred again using wet transfer to the pre-prepared low dielectric constant isolation layer. 6) Deposit the top dielectric layer The top dielectric layer is deposited using the ALD process as the top gate dielectric. 7) Deposit the top gate and source / drain of the device The entire device is fabricated by sputtering or evaporation processes to prepare the top metal gate and two metal electrodes at the top P-type Pt source / drain ports.

[0015] The current switching ratio simulation test was performed on the device designed in Example 1. Its transfer curve describes the relationship between the drain current of the field-effect transistor and the applied gate voltage.

[0016] See Figure 4 As can be seen from the figure, the high switching ratio structure designed in Example 1 has a current switching ratio greater than 10. 10 It also has a bipolar "U"-shaped curve formed by both N-type and P-type branches.

[0017] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high on / off ratio structure design for a bipolar two-dimensional transistor, characterized in that, The bipolar two-dimensional transistor consists of a device back gate, a bottom dielectric layer covering the device back gate, a bottom two-dimensional material channel covering the bottom dielectric layer, a low dielectric constant isolation layer covering the bottom two-dimensional material channel, a top two-dimensional material channel covering the low dielectric constant isolation layer, a top dielectric layer covering the top two-dimensional material channel, and a device top gate covering the top dielectric layer; the two ends of the bottom two-dimensional material channel are in contact with N-type metal, and the two ends of the top two-dimensional material channel are in contact with P-type metal.

2. The high on / off ratio structure design of a bipolar two-dimensional transistor according to claim 1, characterized in that, The N-type metal is disposed at both ends of the bottom two-dimensional material channel and is connected to VDD and GND respectively.

3. The high on / off ratio structure design of a bipolar two-dimensional transistor according to claim 1, characterized in that, The P-type metal is disposed at both ends of the top two-dimensional material channel and is connected to VDD and GND respectively.

4. The high on / off ratio structure design of a bipolar two-dimensional transistor according to claim 1, characterized in that, The back gate and top gate of the device are connected to the gate voltage VG.

5. The high on / off ratio structure design of a bipolar two-dimensional transistor according to claim 1, characterized in that, The bottom and top two-dimensional material channels are made of two-dimensional materials with semiconductor properties and have a thickness of 6 nm.

6. A high on / off ratio structure design for a bipolar two-dimensional transistor according to claim 1 or claim 5, characterized in that, The bottom two-dimensional material channel (103) and the top two-dimensional material channel (105) are made of a single-layer two-dimensional transition metal sulfide.

7. The high on / off ratio structure design of a bipolar two-dimensional transistor according to claim 1, characterized in that, The low dielectric constant isolation layer is made of SiOC with a dielectric constant of 2.7 and a thickness of 6 nm.

8. A method for fabricating the high on / off ratio structure of the bipolar two-dimensional transistor according to claim 1, Its features are, The preparation method specifically includes: 1) Deposition of the bottom gate and source / drain electrodes of the device The substrate bottom gate Al electrode and the two metal electrodes at the bottom N-type metal Ti source / drain ports were fabricated using sputtering or evaporation processes. 2) Deposition of the bottom dielectric layer A bottom dielectric layer is deposited on top of the bottom gate Al electrode using an ALD process as the first gate dielectric layer, and the material is HfO2, ZrO2 or Al2O3. 3) Transfer of WSe2 thin film in dielectric layer The first monolayer WSe2 film obtained by mechanical peeling process is wet-transfer bonded to the surface of the bottom dielectric layer. 4) Deposition and etching of the isolation layer A layer of low dielectric constant material is deposited using the ALD process, and an isolation layer is formed by etching to construct a separate channel structure and expose the area that needs to be stacked again. The low dielectric constant material is SiOC with a dielectric constant of 2.

7. 5) Transfer of WSe2 thin film in the isolation layer The second monolayer WSe2 film obtained by mechanical peeling process is transferred onto the isolation layer by wet method. 6) Deposition of the top dielectric layer A top dielectric layer is deposited using the ALD process as the top gate dielectric. 7) Deposition of the top gate and source / drain electrodes of the device The top metal gate and the two metal electrodes of the top P-type metal Pt source / drain ports are fabricated using sputtering or evaporation processes to complete the fabrication of the entire device.

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