A semiconductor device and a manufacturing method thereof
By employing a stacked silicon-doped and non-silicon-doped design in gallium oxide epitaxial layers, the doping efficiency and crystal quality issues of gallium oxide epitaxial layers are solved, achieving high performance and stability of gallium oxide-based power devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WUXI CHINA RESOURCES MICROELECTRONICS
- Filing Date
- 2024-12-03
- Publication Date
- 2026-06-05
AI Technical Summary
In the existing technology, gallium oxide epitaxial layers suffer from low doping efficiency and poor crystal quality, which affects the performance of gallium oxide-based power devices.
A gallium oxide epitaxial layer design with multiple stacked structures is adopted. Each stacked structure includes stacked silicon-doped gallium oxide layers and non-silicon-doped gallium oxide layers, with gallium oxide bulk layers formed before and after the epitaxial layers. The doping efficiency and crystal quality are improved by controlling the growth conditions and doping methods.
It significantly improves the electron mobility and crystal quality of gallium oxide epitaxial layers, thereby enhancing the electrical performance and stability of gallium oxide-based power devices.
Smart Images
Figure CN122161146A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] As a novel ultrawide semiconductor material, gallium oxide (Ga2O3) has a bandgap of 4.9 eV and a critical electric field of 8 MV·cm. -1 At room temperature, its electron mobility is two to three times higher than that of other semiconductor materials such as gallium nitride (GaN) and silicon carbide (SiC), with an electron mobility of 200 cm⁻¹. 2 Ga2O3-based power devices exhibit a voltage rating of / (Vs) and a Baliga figure of 3444. These properties enable Ga2O3-based power devices to achieve both higher voltage withstand capability and lower power consumption, significantly improving energy conversion efficiency and making them promising for applications in the fabrication of high-power devices.
[0003] Among them, monoclinic gallium oxide (β-Ga2O3) is the most stable thermodynamic crystal structure and is a necessary condition for realizing the excellent characteristics of Ga2O3-based power devices. However, gallium oxide epitaxial layers in related technologies suffer from low doping efficiency and poor crystal quality.
[0004] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention
[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0006] To address the existing problems, this application provides a semiconductor device comprising: a substrate; a first gallium oxide bulk layer on the substrate; a gallium oxide epitaxial layer on the first gallium oxide bulk layer, the gallium oxide epitaxial layer comprising a plurality of stacked structures, each of the stacked structures comprising stacked silicon-doped gallium oxide layers and non-silicon-doped gallium oxide layers; and a second gallium oxide bulk layer on the gallium oxide epitaxial layer.
[0007] For example, each of the stacked structures includes a silicon-doped gallium oxide layer and a non-silicon-doped gallium oxide layer stacked sequentially from bottom to top; or, each of the stacked structures includes a non-silicon-doped gallium oxide layer and a silicon-doped gallium oxide layer stacked sequentially from bottom to top.
[0008] For example, the number of stacked structures is 380-510.
[0009] For example, the first gallium oxide body layer and the second gallium oxide body layer include an undoped β-Ga2O3 body layer, the thickness of the first gallium oxide body layer is 20nm-100nm, and the thickness of the second gallium oxide body layer is 40nm-120nm.
[0010] For example, the substrate includes an iron-doped gallium oxide substrate or a tin-doped gallium oxide substrate.
[0011] Another aspect of this application provides a method for manufacturing a semiconductor device, comprising: providing a substrate, forming a first gallium oxide body layer on the substrate; forming a gallium oxide epitaxial layer on the first gallium oxide body layer, the gallium oxide epitaxial layer comprising a plurality of stacked structures, each of the stacked structures comprising stacked silicon-doped gallium oxide layers and non-silicon-doped gallium oxide layers; and forming a second gallium oxide body layer on the gallium oxide epitaxial layer.
[0012] For example, the growth temperature for forming the gallium oxide epitaxial layer is 820℃-1000℃, the growth pressure is 15mbar-60mbar, the carrier gas is nitrogen, the oxygen source is high-purity oxygen, and the VI / III ratio is 180-400.
[0013] For example, when forming the silicon-doped gallium oxide layer, the gallium source is trimethylgallium or triethylgallium, and the flow rate of the gallium source is 500 sccm-1000 sccm; the silicon doping source is tetraethoxysilane, and the flow rate of the silicon doping source is 2 sccm-8 sccm; when forming the non-silicon-doped gallium oxide layer, the silicon doping source is turned off.
[0014] For example, the thickness of the silicon-doped gallium oxide layer is 4nm-6nm, and the thickness of the non-silicon-doped gallium oxide layer is 1nm-3nm.
[0015] For example, the growth temperature for forming the first gallium oxide bulk layer and the second gallium oxide bulk layer is 800℃-900℃, the growth pressure is 15mbar-70mbar, the carrier gas is nitrogen, the oxygen source is high-purity oxygen, the gallium source is trimethylgallium or triethylgallium, the flow rate of the gallium source is 400sccm-900sccm, and the VI / III ratio is 280-520.
[0016] The semiconductor device and its manufacturing method provided in this application include a gallium oxide epitaxial layer comprising multiple stacked structures. Each stacked structure includes stacked silicon-doped gallium oxide layers and non-silicon-doped gallium oxide layers, with gallium oxide bulk layers formed before and after the gallium oxide epitaxial layer. This effectively improves the electron mobility of the gallium oxide epitaxial layer, thereby enhancing the doping efficiency and improving the crystal quality of the gallium oxide epitaxial layer. It is widely used in the field of power devices. Attached Figure Description
[0017] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments of this application in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain this application and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.
[0018] In the attached image:
[0019] Figure 1 A schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of this application is shown;
[0020] Figure 2 A schematic cross-sectional view of a semiconductor device according to another exemplary embodiment of this application is shown;
[0021] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of this application is shown. Detailed Implementation
[0022] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.
[0023] It should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.
[0024] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0025] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0027] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be construed as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as interpreted in an ideal or overly formal sense, unless expressly defined herein.
[0028] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.
[0029] In related technologies, metal-organic chemical vapor deposition (MOCVD) has shown significant advantages in controlling growth dynamic parameters and maintaining film integrity in semiconductor device processes, making it one of the main methods for epitaxial growth of β-Ga2O3 epitaxial layers. To improve the electron mobility of β-Ga2O3 epitaxial layers and achieve conductivity, N-type doping is performed. Common N-type doping elements are silicon (Si), tin (Sn), and germanium (Ge). However, Sn and Ge doping often introduce deeper donor levels. Furthermore, under high temperature and high concentration doping conditions, Sn doping often leads to parasitic reactions resulting in the formation of a second phase, and Sn doping tends to saturate. Ge doping, on the other hand, may cause donor deactivation, all of which severely reduce doping efficiency. Simultaneously, the introduction of Sn and Ge also leads to lattice distortion, generating more defects and causing a decrease in the crystal quality of the epitaxial layer. Si, as a commonly used N-type doping source, has been widely applied in wide-bandgap semiconductor materials. However, for ultra-wide-bandgap β-Ga2O3 epitaxial materials, a lower background carrier concentration is required for doping. But the Si doping concentration in related technologies is often greater than 6E16 / cm. 3 This affects conductivity and reduces electron mobility. At the same time, under conditions such as high temperature, dopant elements can diffuse to the substrate or escape from the surface of the epitaxial layer, affecting the electrical performance of subsequent power devices.
[0030] Therefore, in view of the aforementioned technical problems, this application proposes a semiconductor device, comprising:
[0031] Substrate;
[0032] The first gallium oxide bulk layer is located on the substrate;
[0033] A gallium oxide epitaxial layer is located on a first gallium oxide bulk layer. The gallium oxide epitaxial layer includes multiple stacked structures, each stacked structure including stacked silicon-doped gallium oxide layers and non-silicon-doped gallium oxide layers.
[0034] The second gallium oxide bulk layer is located on the gallium oxide epitaxial layer.
[0035] The semiconductor device provided in this application includes a gallium oxide epitaxial layer comprising multiple stacked structures. Each stacked structure includes stacked silicon-doped gallium oxide layers and non-silicon-doped gallium oxide layers, with gallium oxide bulk layers formed before and after the gallium oxide epitaxial layer. This effectively improves the electron mobility of the gallium oxide epitaxial layer, thereby enhancing the doping efficiency and improving the crystal quality of the gallium oxide epitaxial layer. It is widely used in the field of power devices.
[0036] Example 1
[0037] Below, for reference Figure 1 and Figure 2 The semiconductor devices in the embodiments of this application are described, wherein, Figure 1 A schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of this application is shown. Figure 2 A cross-sectional schematic diagram of a semiconductor device according to another exemplary embodiment of this application is shown. The semiconductor device includes: a substrate 100; a first gallium oxide bulk layer 110 located on the substrate 100; a gallium oxide epitaxial layer 120 located on the first gallium oxide bulk layer 110, the gallium oxide epitaxial layer 120 including a plurality of stacked structures 121, each stacked structure 121 including stacked silicon-doped gallium oxide layers 1211 and non-silicon-doped gallium oxide layers 1212; and a second gallium oxide bulk layer 130 located on the gallium oxide epitaxial layer 120.
[0038] In one example, substrate 100 includes an iron-doped gallium oxide substrate or a tin-doped gallium oxide substrate. Specifically, substrate 100 can be an iron-doped gallium oxide substrate with crystal orientations such as (100), (010), or (001), or substrate 100 can be a tin-doped gallium oxide substrate with crystal orientations such as (100), (010), or (001). In this embodiment, substrate 100 is an iron-doped (010) gallium oxide substrate.
[0039] In one example, a first gallium oxide bulk layer 110 is formed on the substrate 100, wherein the first gallium oxide bulk layer 110 includes, but is not limited to, undoped β-Ga₂O₃. Exemplarily, the thickness of the first gallium oxide bulk layer 110 can be 20nm-100nm, such as 20nm, 30nm, 40nm, 50nm, 55nm, 60nm, 70nm, 80nm, 90nm, or 100nm. The formed first gallium oxide bulk layer 110 can prevent the diffusion of doped silicon atoms from the subsequently formed gallium oxide epitaxial layer 120 into the substrate 100, thereby ensuring the stability and uniformity of the doping in the gallium oxide epitaxial layer 120.
[0040] In one example, such as Figure 1 and Figure 2 As shown, a gallium oxide epitaxial layer 120 is formed on the first gallium oxide bulk layer 110. The gallium oxide epitaxial layer 120 includes a plurality of stacked structures 121, each stacked structure 121 including stacked silicon-doped gallium oxide layers 1211 and non-silicon-doped gallium oxide layers 1212. Exemplarily, the gallium oxide epitaxial layer 120 includes, but is not limited to, β-Ga2O3. In this application, the β-Ga2O3 epitaxial layer is an HT-Ga2O3 (High Temperature-Ga2O3) epitaxial layer.
[0041] In one example, such as Figure 1 and Figure 2 As shown, each stacked structure 121 includes a silicon-doped gallium oxide layer 1211 and a non-silicon-doped gallium oxide layer 1212 stacked sequentially from bottom to top; or, each stacked structure 121 includes a non-silicon-doped gallium oxide layer 1212 and a silicon-doped gallium oxide layer 1211 stacked sequentially from bottom to top. Exemplarily, trimethylgallium (TMGa) or triethylgallium (TEGa) can be used as the gallium source (Ga) during the growth of the silicon-doped gallium oxide layer 1211 and the non-silicon-doped gallium oxide layer 1212, and tetraethoxysilane (TEOS) can be used as the silicon doping source during the growth of the silicon-doped gallium oxide layer 1211. When forming the non-silicon-doped gallium oxide layer 1212, the silicon doping source (i.e., TEOS) can be turned off. Silicon doping is performed in a pulsed manner to form alternating silicon-doped gallium oxide layers 1211 and non-silicon-doped gallium oxide layers 1212. Silicon doping introduces shallower donor levels, improving doping efficiency and electron mobility, and significantly enhancing the electrical characteristics of gallium oxide-based power devices. The pulsed doping method provides sufficient diffusion time for silicon atoms, resulting in substitutional doping, which greatly reduces crystal structure distortion, improves crystal quality, and allows the silicon doping concentration to reach 5E16 / cm³. 3 The following describes how high-crystal-quality β-Ga2O3 epitaxial layers exhibit N-type conductivity.
[0042] In one example, the thickness of the silicon-doped gallium oxide layer 1211 can be 4nm-6nm, such as 4nm, 4.5nm, 4.8nm, 5nm, 5.5nm, 5.7nm, or 6nm. The thickness of the non-silicon-doped gallium oxide layer 1212 can be 1nm-3nm, such as 1nm, 1.5nm, 1.8nm, 2nm, 2.5nm, 2.7nm, or 3nm.
[0043] In one example, the number of stacked structures 121 can be 380-510 to obtain a β-Ga2O3 epitaxial structure with a certain thickness.
[0044] In one example, a second gallium oxide bulk layer 130 is formed on the gallium oxide epitaxial layer 120, wherein the second gallium oxide bulk layer 130 includes, but is not limited to, undoped β-Ga₂O₃. Exemplarily, the thickness of the second gallium oxide bulk layer 130 can be 40nm-120nm, such as 40nm, 50nm, 55nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, or 120nm. The second gallium oxide bulk layer 130 ensures that silicon atoms will not diffuse out of the gallium oxide epitaxial layer 120 during subsequent device fabrication processes, even under conditions such as high temperatures, thus preventing a decrease in silicon doping efficiency. It also ensures that subsequent steps such as mask deposition will not be interfered with by doped silicon atoms, guaranteeing the stability and good electrical characteristics of the gallium oxide-based power device.
[0045] In summary, the semiconductor device provided in this application includes a gallium oxide epitaxial layer comprising multiple stacked structures, each stacked structure comprising stacked silicon-doped gallium oxide layers and non-silicon-doped gallium oxide layers, with gallium oxide bulk layers formed before and after the gallium oxide epitaxial layer, which can effectively improve the electron mobility of the gallium oxide epitaxial layer, thereby improving the doping efficiency, and at the same time improving the crystal quality of the gallium oxide epitaxial layer, and is widely used in the field of power devices.
[0046] Example 2
[0047] This application also provides a method for manufacturing a semiconductor device, the method being used to manufacture the semiconductor device described in Embodiment 1. For example... Figure 3 As shown, it mainly includes the following steps:
[0048] In step S1, a substrate is provided, and a first gallium oxide bulk layer is formed on the substrate;
[0049] In step S2, a gallium oxide epitaxial layer is formed in the first gallium oxide bulk layer. The gallium oxide epitaxial layer includes multiple stacked structures, each stacked structure including stacked silicon-doped gallium oxide layers and non-silicon-doped gallium oxide layers.
[0050] In step S3, a second gallium oxide bulk layer is formed on the gallium oxide epitaxial layer.
[0051] The semiconductor device manufacturing method of this application embodiment forms a gallium oxide epitaxial layer including multiple stacked structures. Each stacked structure includes stacked silicon-doped gallium oxide layers and non-silicon-doped gallium oxide layers, and gallium oxide bulk layers are formed before and after the gallium oxide epitaxial layer. This method can effectively improve the electron mobility of the gallium oxide epitaxial layer, thereby improving the doping efficiency and enhancing the crystal quality of the gallium oxide epitaxial layer. It is widely used in the field of power devices.
[0052] Below, for reference Figure 1 , Figure 2 and Figure 3 The method for manufacturing the semiconductor device of this application is described in detail, wherein, Figure 1 A schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of this application is shown. Figure 2 A schematic cross-sectional view of a semiconductor device according to another exemplary embodiment of this application is shown. Figure 3 A flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of this application is shown.
[0053] For example, the method for manufacturing the semiconductor device of this application includes the following steps:
[0054] First, step S1 is performed to provide a substrate and form a first gallium oxide bulk layer on the substrate.
[0055] In one example, such as Figure 1 and Figure 2 As shown, substrate 100 includes an iron-doped gallium oxide substrate or a tin-doped gallium oxide substrate. Specifically, substrate 100 can be an iron-doped gallium oxide substrate with crystal orientations such as (100), (010), or (001), or substrate 100 can be a tin-doped gallium oxide substrate with crystal orientations such as (100), (010), or (001). In this embodiment, substrate 100 is an iron-doped (010) gallium oxide substrate.
[0056] For example, before forming the first gallium oxide bulk layer 110, the substrate 100 needs to be pretreated. Specifically, the pretreatment of the substrate 100 is performed by placing the substrate 100 in a reaction chamber. In this embodiment, the reaction chamber is a metal-organic chemical vapor deposition (MOCVD) reaction chamber. At this time, the temperature of the MOCVD reaction chamber is 800℃-1000℃, the pressure is 100mbar-200mbar, and the substrate 100 is subjected to high-temperature in-situ annealing pretreatment in an oxygen atmosphere for 5min-20min. The purpose of the pretreatment is to remove organic contaminants from the surface of the substrate 100, which is beneficial to the subsequent epitaxial growth of the gallium oxide thin film.
[0057] In one example, such as Figure 1 and Figure 2As shown, a first gallium oxide bulk layer 110 is formed on substrate 100. Exemplarily, the first gallium oxide bulk layer 110 includes, but is not limited to, undoped β-Ga₂O₃. Exemplarily, the first gallium oxide bulk layer 110 is grown in an MOCVD reaction chamber at a growth temperature (i.e., the temperature of the MOCVD reaction chamber) of 800°C-900°C, a growth pressure of 15 mbar-70 mbar, using nitrogen as the carrier gas, and employing trimethylgallium (TMGa) or triethylgallium (TEGa) as the Ga source at a flow rate of 400 sccm-900 sccm. High-purity oxygen (O₂) is used as the oxygen source, with a VI / III ratio of 280-520. The thickness of the grown first gallium oxide bulk layer 110 can be 20 nm-100 nm, for example, 20 nm, 30 nm, 40 nm, 50 nm, 55 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm. Wherein, the VI / III ratio is the molar ratio of group VI sources and group III sources introduced into the MOCVD reaction chamber; in this embodiment, the VI / III ratio is the molar ratio of O2 to TMGa introduced into the MOCVD reaction chamber. Exemplarily, as a combined embodiment, when growing the first gallium oxide bulk layer 110, the growth temperature, growth pressure, VI / III ratio, and thickness of the first gallium oxide bulk layer 110 are 850°C, 50 mbar, 400 nm, and 50 nm, respectively. The formed first gallium oxide bulk layer 110 can prevent the diffusion of doped silicon atoms in the subsequently formed gallium oxide epitaxial layer 120 into the substrate 100, thereby ensuring the stability and uniformity of the doping in the gallium oxide epitaxial layer 120.
[0058] Next, step S2 is performed to form a gallium oxide epitaxial layer in the first gallium oxide bulk layer. The gallium oxide epitaxial layer includes multiple stacked structures, each stacked structure including stacked silicon-doped gallium oxide layers and non-silicon-doped gallium oxide layers.
[0059] In one example, a gallium oxide epitaxial layer 120 is grown on the first gallium oxide bulk layer 110. Exemplarily, the gallium oxide epitaxial layer 120 includes, but is not limited to, β-Ga₂O₃. Specifically, when growing each silicon-doped gallium oxide layer 1211 in the MOCVD reaction chamber, the growth temperature (i.e., the temperature of the MOCVD reaction chamber) is 820℃-1000℃, the growth pressure is 15mbar-60mbar, the carrier gas is nitrogen, high-purity O₂ is used as the oxygen source, the Ga source is TMGa or TEGa, the Ga source flow rate is 500sccm-1000sccm, the silicon doping source is tetraethoxysilane (TEOS), and the silicon doping source flow rate is 2sccm-8sccm. The thickness of the grown silicon-doped gallium oxide layer 1211 can be 4nm-6nm, for example, 4nm, 4.5nm, 4.8nm, 5nm, 5.5nm, 5.7nm, or 6nm. When growing each undoped gallium oxide layer 1212 in the MOCVD reaction chamber, the silicon doping source can be turned off, while the growth conditions of the rest of the MOCVD reaction chamber remain unchanged. The thickness of the grown undoped gallium oxide layer 1212 can be 1nm-3nm, such as 1nm, 1.5nm, 1.8nm, 2nm, 2.5nm, 2.7nm, or 3nm. The VI / III ratio is the molar ratio of group VI sources and group III sources introduced into the MOCVD reaction chamber; in this embodiment, the VI / III ratio is the molar ratio of O2 to TMGa introduced into the MOCVD reaction chamber. Exemplarily, as a combined embodiment, when growing the gallium oxide epitaxial layer 120, the growth temperature, growth pressure, VI / III ratio, Si doping source flow rate, and alternating growth cycle (i.e., the number of stacked structures 121) are 895°C, 40mbar, 220°C, 6ccm, and 430°C, respectively. By pulsed doping of silicon, multiple alternating silicon-doped gallium oxide layers 1211 and non-silicon-doped gallium oxide layers 1212 (i.e., a stacked structure 121) are formed. Silicon doping introduces shallower donor levels, improving doping efficiency, stimulating donor level activity, increasing electron mobility, and significantly enhancing the electrical characteristics of gallium oxide-based power devices. Simultaneously, the pulsed silicon doping provides sufficient diffusion time for silicon atoms, resulting in substitutional doping, which greatly reduces crystal structure distortion and improves crystal quality. This allows the silicon doping concentration to reach 5E16 / cm³. 3 The following describes how high-crystal-quality β-Ga2O3 epitaxial layers exhibit N-type conductivity.
[0060] In one example, a silicon-doped gallium oxide layer 1211 and a non-silicon-doped gallium oxide layer 1212 constitute a stacked structure 121. Exemplarily, as... Figure 1 As shown, each stacked structure 121 includes, from bottom to top, a silicon-doped gallium oxide layer 1211 and a non-silicon-doped gallium oxide layer 1212 stacked sequentially; or as shown... Figure 2 As shown, each stacked structure 121 includes a non-silicon-doped gallium oxide layer 1212 and a silicon-doped gallium oxide layer 1211 stacked sequentially from bottom to top. Exemplarily, the number of stacked structures 121 can be 380-510.
[0061] Finally, step S3 is performed to form a second gallium oxide bulk layer on the gallium oxide epitaxial layer.
[0062] In one example, a second gallium oxide bulk layer 130 is grown on a gallium oxide epitaxial layer 120. Exemplarily, the second gallium oxide bulk layer 130 includes, but is not limited to, undoped β-Ga₂O₃. Exemplarily, the second gallium oxide bulk layer 130 is grown in an MOCVD reaction chamber at a growth temperature (i.e., the temperature of the MOCVD reaction chamber) of 800°C-900°C and a growth pressure of 15 mbar-70 mbar. Nitrogen is used as the carrier gas, and trimethylgallium (TMGa) or triethylgallium (TEGa) is used as the Ga source at a flow rate of 400 sccm-900 sccm. High-purity oxygen (O₂) is used as the oxygen source, with a VI / III ratio of 280-520. The thickness of the grown second gallium oxide bulk layer 130 can be 40 nm-120 nm, for example, 40 nm, 50 nm, 55 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, or 120 nm. Wherein, the VI / III ratio is the molar ratio of group VI sources and group III sources introduced into the MOCVD reaction chamber; in this embodiment, the VI / III ratio is the molar ratio of O2 to TMGa introduced into the MOCVD reaction chamber. Exemplarily, as a combined embodiment, when growing the second gallium oxide bulk layer 130, the growth temperature, growth pressure, VI / III ratio, and thickness of the second gallium oxide bulk layer 130 are 850°C, 50 mbar, 400 nm, and 65 nm, respectively. The formed second gallium oxide bulk layer 130 ensures that the gallium oxide epitaxial layer 120 will not experience silicon atom diffusion and escape under high-temperature conditions during subsequent device fabrication processes, thus preventing a decrease in silicon doping efficiency. It also ensures that subsequent steps such as mask deposition will not be interfered with by doped silicon atoms, guaranteeing the stability and good electrical characteristics of the gallium oxide-based power device.
[0063] In one example, after forming the second gallium oxide bulk layer 130, a cooling process is included: the carrier gas is oxygen or oxygen plus nitrogen; the MOCVD reaction chamber temperature is controlled at 800℃-1000℃, the pressure is controlled at 20mbar-80mbar, and the duration is 3min-10min; then, the MOCVD reaction chamber temperature is reduced to below 150℃ to end the entire epitaxial growth process. This cooling process alleviates the thermal stress and lattice mismatch problems caused by rapid cooling in the β-Ga2O3 epitaxial structure.
[0064] It is worth mentioning that the above steps are only examples, and the order of the steps can be adjusted without conflict.
[0065] Thus, the process steps of the semiconductor device manufacturing method according to an embodiment of this application are completed. It is understood that the semiconductor device manufacturing method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included in the scope of the manufacturing method of this embodiment.
[0066] In summary, the semiconductor device manufacturing method of this application forms a gallium oxide epitaxial layer comprising multiple stacked structures, each stacked structure comprising stacked silicon-doped gallium oxide layers and non-silicon-doped gallium oxide layers, with gallium oxide bulk layers formed before and after the gallium oxide epitaxial layer, which can effectively improve the electron mobility of the gallium oxide epitaxial layer, thereby improving the doping efficiency, and at the same time improve the crystal quality of the gallium oxide epitaxial layer, and is widely used in the field of power devices.
[0067] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.
Claims
1. A semiconductor device, characterized in that, include: Substrate; A first gallium oxide bulk layer is located on the substrate; A gallium oxide epitaxial layer is located on the first gallium oxide bulk layer. The gallium oxide epitaxial layer includes multiple stacked structures, each of which includes stacked silicon-doped gallium oxide layers and non-silicon-doped gallium oxide layers. The second gallium oxide bulk layer is located on the gallium oxide epitaxial layer.
2. The semiconductor device as claimed in claim 1, characterized in that, Each of the stacked structures includes, from bottom to top, the silicon-doped gallium oxide layer and the non-silicon-doped gallium oxide layer; or, Each of the stacked structures includes, from bottom to top, the undoped gallium oxide layer and the silicon-doped gallium oxide layer.
3. The semiconductor device as described in claim 1, characterized in that, The number of stacked structures is 380-510.
4. The semiconductor device as claimed in claim 1, characterized in that, The first gallium oxide body layer and the second gallium oxide body layer comprise undoped β-Ga2O3, the thickness of the first gallium oxide body layer is 20nm-100nm, and the thickness of the second gallium oxide body layer is 40nm-120nm.
5. The semiconductor device as claimed in claim 1, characterized in that, The substrate includes an iron-doped gallium oxide substrate or a tin-doped gallium oxide substrate.
6. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, on which a first gallium oxide bulk layer is formed; A gallium oxide epitaxial layer is formed in the first gallium oxide bulk layer. The gallium oxide epitaxial layer includes multiple stacked structures, each of which includes stacked silicon-doped gallium oxide layers and non-silicon-doped gallium oxide layers. A second gallium oxide bulk layer is formed on the gallium oxide epitaxial layer.
7. The manufacturing method as described in claim 6, characterized in that, The growth temperature for forming the gallium oxide epitaxial layer is 820℃-1000℃, the growth pressure is 15mbar-60mbar, the carrier gas is nitrogen, the oxygen source is high-purity oxygen, and the VI / III ratio is 180-400.
8. The manufacturing method as described in claim 7, characterized in that, When forming the silicon-doped gallium oxide layer, the gallium source is trimethylgallium or triethylgallium, and the flow rate of the gallium source is 500 sccm-1000 sccm. The silicon doping source is tetraethoxysilane, and the flow rate of the silicon doping source is 2 sccm-8 sccm. When forming the undoped gallium oxide layer, the silicon doping source is turned off.
9. The manufacturing method as described in claim 6, characterized in that, The growth temperature for forming the first gallium oxide bulk layer and the second gallium oxide bulk layer is 800℃-900℃, the growth pressure is 15mbar-70mbar, the carrier gas is nitrogen, the oxygen source is high-purity oxygen, the gallium source is trimethylgallium or triethylgallium, the flow rate of the gallium source is 400sccm-900sccm, and the VI / III ratio is 280-520.
10. The manufacturing method according to any one of claims 6 to 9, characterized in that, The thickness of the silicon-doped gallium oxide layer is 4nm-6nm, and the thickness of the non-silicon-doped gallium oxide layer is 1nm-3nm.