Switching array, dc-dc switching converter circuit, and switching array manufacturing method

Abstract

Embodiments of the present application provide a switch array and a manufacturing method thereof, and a DC-DC switching conversion circuit using the switch array. The switch array comprises, for example, a substrate, an insulating layer and a plurality of semiconductor switching devices, the plurality of semiconductor switching devices are arranged side by side on the substrate, and the insulating layer is arranged between the substrate and the plurality of semiconductor switching devices and separates the plurality of semiconductor switching devices from each other. Each of the semiconductor switching devices comprises a barrier layer, a channel layer, a first electrode, a second electrode and a gate structure; the first electrode metal layer of the first electrode and the second electrode metal layer of the second electrode are respectively separated from the substrate by the insulating layer, so that the back gate effect problem caused by the substrate voltage bias in the related art can be overcome, and the switching performance of the device can be improved.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a switch array, a DC-DC switch conversion circuit, and a method for manufacturing a switch array. Background Technology

[0002] DC-DC switching converters have extremely wide applications in military, industrial, and daily life. With the continuous advancement of power electronics technology, high-frequency, miniaturized, high-efficiency, and high-power-density DC-DC switching converters have become a sought-after goal. While traditional Buck / Boost circuits can stably provide the required voltage output, their inductors and capacitors are large, and the inductor is difficult to integrate around the switching transistor. Therefore, this type of topology is rarely used in ultra-miniature DC-DC switching converters, such as on-chip power management systems and LCD drivers. In the increasingly miniaturized and high-density DC-DC switching converter topologies, the DC-DC switched-capacitor power converter has always been a highly anticipated structure. This topology eliminates the need for inductors, integrating capacitors and multiple semiconductor switching devices onto a single chip, reducing parasitic parameters, and enabling multi-stage voltage and current conversion with a single chip, significantly reducing system size. However, in related technologies, multiple switching devices integrated on the same chip have their sources connected to the same substrate, which leads to a back-gate effect caused by substrate voltage bias, thus affecting the normal switching of the device. The back-gate effect, also known as the body effect or substrate bias effect, is a phenomenon in transistors such as MOSFETs. It describes the effect on the threshold voltage of a MOSFET device when there is a voltage difference between the source and the substrate.

[0003] Therefore, how to improve the switching performance of DC-DC switching converter circuits, such as DC-DC switched capacitor converters, is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a switch array, a DC-DC switch conversion circuit, and a method for manufacturing a switch array, in order to improve the switching performance of the circuit.

[0005] Specifically, an embodiment of the present invention provides a switch array, for example, including a substrate, an insulating layer, and a plurality of semiconductor switching devices. The plurality of semiconductor switching devices are arranged side by side on the substrate, and the insulating layer is disposed between the substrate and the plurality of semiconductor switching devices, spacing the plurality of semiconductor switching devices apart from each other. Each semiconductor switching device includes a barrier layer, a channel layer, a first electrode, a second electrode, and a gate structure; the barrier layer is disposed on the substrate, and the barrier layer and the substrate are spaced apart by the insulating layer; the channel layer is disposed on the side of the barrier layer opposite to the substrate; the first electrode includes a first electrode metal layer and a first connection metal layer, the first electrode metal layer is located on the side of the barrier layer facing the substrate, and the first electrode metal layer and the substrate are spaced apart by the insulating layer, the first connection metal layer connects to the first electrode metal layer and is partially exposed on the side of the channel layer opposite to the substrate; the second electrode includes A second electrode metal layer and a second connection metal layer are provided. The second electrode metal layer is located on the side of the barrier layer facing the substrate and is separated from the substrate by the insulating layer. The second connection metal layer is connected to the second electrode metal layer and is partially exposed on the side of the channel layer away from the substrate. The gate structure includes a gate semiconductor layer and a gate metal layer. The gate semiconductor layer is located on the side of the barrier layer facing the substrate and is separated from the substrate by the insulating layer. The gate metal layer is connected to the gate semiconductor layer and is partially exposed on the side of the insulating layer away from the substrate.

[0006] Furthermore, an embodiment of the present invention provides a DC-DC switching converter circuit, which includes, for example, a first power input terminal, a second power input terminal, an input capacitor, the aforementioned switch array, a load capacitor, and an output capacitor; the input capacitor is connected between the first power input terminal and the second power input terminal; the plurality of semiconductor switching devices in the switch array include a first semiconductor switching device, a second semiconductor switching device, a third semiconductor switching device, and a fourth semiconductor switching device; the first electrode of the first semiconductor switching device is connected to the first power input terminal; the first electrode of the second semiconductor switching device is connected to the second electrode of the first semiconductor switching device; the first electrode of the third semiconductor switching device is connected to the second electrode of the second semiconductor switching device; the first electrode of the fourth semiconductor switching device is connected to the second electrode of the third semiconductor switching device; and the second electrode of the fourth semiconductor switching device is connected to the second power input terminal; the load capacitor is connected between the node between the first electrode of the second semiconductor switching device and the second electrode of the first semiconductor switching device, and between the node between the first electrode of the fourth semiconductor switching device and the second electrode of the third semiconductor switching device; and the output capacitor is connected between the node between the first electrode of the third semiconductor switching device and the second electrode of the second semiconductor switching device, and the second power input terminal.

[0007] In addition, an embodiment of the present invention provides a method for fabricating a switch array, which includes, for example, the following steps:

[0008] An initial switch array is provided, the initial switch array comprising: a substrate, a plurality of initial semiconductor switching devices and an insulating layer, the plurality of initial semiconductor switching devices being disposed side by side on the substrate, each of the initial semiconductor switching devices comprising a channel layer, a barrier layer, a first electrode metal layer, a second electrode metal layer and a gate semiconductor layer, the channel layer being located between the substrate and the barrier layer, the first electrode metal layer, the second electrode metal layer and the gate semiconductor layer being located on the side of the barrier layer opposite to the substrate, and the insulating layer being located on the substrate and covering the plurality of initial semiconductor switching devices and spacing the plurality of initial semiconductor switching devices apart from each other;

[0009] The initial switch array is flip-bonded to the substrate, and then the substrate is removed; and

[0010] After removing the substrate, a first interconnect metal layer, a second interconnect metal layer, and a gate metal layer are formed to obtain a switch array having a plurality of semiconductor switching devices, wherein each of the semiconductor switching devices includes: a barrier layer, a channel layer, a first electrode, a second electrode, and a gate structure. The barrier layer is disposed on the substrate and is spaced apart from the substrate by the insulating layer. The channel layer is disposed on the side of the barrier layer facing away from the substrate. The first electrode includes a first electrode metal layer and a first interconnect metal layer. The first electrode metal layer is located on the side of the barrier layer facing the substrate and is spaced apart from the substrate by the insulating layer. The first interconnect metal layer connects to the first electrode metal layer and... The second electrode includes a second electrode metal layer and a second connection metal layer. The second electrode metal layer is located on the side of the barrier layer facing the substrate, and the second electrode metal layer is separated from the substrate by the insulating layer. The second connection metal layer is connected to the second electrode metal layer and is partially exposed on the side of the channel layer facing away from the substrate. The gate structure includes a gate semiconductor layer and a gate metal layer. The gate semiconductor layer is located on the side of the barrier layer facing the substrate, and the gate semiconductor layer is separated from the substrate by the insulating layer. The gate metal layer is connected to the gate semiconductor layer and is partially exposed on the side of the insulating layer facing away from the substrate.

[0011] The above embodiments of the present invention can have the following beneficial effects: In the switch array of the embodiments of the present invention, the first electrode and the second electrode of each semiconductor switching device are separated from the substrate by the insulating layer, and the first electrode, the second electrode and the gate structure are structurally designed accordingly. Taking the first electrode or the second electrode as the source of the semiconductor switching device as an example, in practical applications, each semiconductor switching device can achieve independent source voltage application, thereby avoiding the back gate effect problem caused by substrate voltage bias that occurs when the sources of each switching device are electrically connected to the same substrate in related technologies. In this way, the switching performance of the switch array can be improved. Furthermore, the DC-DC switching converter circuit, due to the use of the switch array, can have better circuit switching performance. In addition, the switch array fabrication method, by using flip-chip bonding technology to remove the substrate and replace it with the substrate, can improve heat dissipation performance, and the resulting switch array also has better switching performance. Attached Figure Description

[0012] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0013] Figure 1This is a cross-sectional view of a switch array provided in an embodiment of the present invention.

[0014] Figure 2 for Figure 1 A magnified three-dimensional schematic diagram of a single semiconductor switching device in the switch array shown.

[0015] Figure 3 for Figure 2 Top view of the structure shown.

[0016] Figure 4 In order to be in Figure 2 Top view of the structure after the passivation layer has been formed.

[0017] Figures 5A to 5C This is a schematic diagram of the process structure of a switch array fabrication method provided in an embodiment of the present invention.

[0018] Figure 6 This is a schematic diagram of the connection relationship of a DC-DC switching converter circuit provided in an embodiment of the present invention.

[0019] [Explanation of Key Figure Markings]

[0020] 10. Switch array; 11. Substrate; 13. Insulating layer; 15. S1-S4. Semiconductor switching device; 151. Barrier layer; 153. Channel layer; 155. First electrode; 1551. First electrode metal layer; 1553. First connection metal layer; 1553a. First horizontal portion; 1553b. First vertical portion; 157. Second electrode; 1571. Second electrode metal layer; 1573. Second connection metal layer; 1573a. Second horizontal portion; 1573b. Second vertical portion; 1591. Gate 1593, Gate metal layer; 159, Gate structure; 155S, 157SA, 157SB, 159S, End face; 155P, First electrode pad; 157P, Second electrode pad; 159P, Gate pad; 20, Substrate; 150, Initial semiconductor switching device; 1510, Channel material layer; 1530, Barrier material layer; 1590, Gate semiconductor material layer; 17, Passivation layer; INPUT0, First power input terminal; INPUT1, Second power input terminal; C IN Input capacitor; C L , load capacitance; C OUT Output capacitor. Detailed Implementation

[0021] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] It should also be noted that the division of multiple embodiments in this invention is only for the convenience of description and should not constitute a special limitation. Features in various embodiments can be combined and referenced in each other without contradiction.

[0025] See Figure 1 , Figure 2 and Figure 3 An embodiment of the present invention provides a switch array 10, which includes, for example, a substrate 11, an insulating layer 13, and a plurality of semiconductor switching devices 15. The plurality of semiconductor switching devices 15 are arranged side by side on the substrate 11, and the insulating layer 13 is disposed between the substrate 11 and the plurality of semiconductor switching devices 15 and spaces the plurality of semiconductor switching devices 15 apart from each other. Figure 1 The illustration shows four semiconductor switching devices 15 as an example, but the embodiments of the present invention are not limited thereto. For example, the number of semiconductor switching devices 15 in the switch array 10 may be two, three or more.

[0026] As described above, the semiconductor switching device 15 includes, for example, a barrier layer 151, a channel layer 153, a first electrode 155, a second electrode 157, and a gate structure 159.

[0027] The barrier layer 151 is disposed on the substrate 11, and the barrier layer 151 and the substrate 11 are separated by the insulating layer 13.

[0028] The channel layer 153 is disposed on the side of the barrier layer 151 opposite to the substrate 11.

[0029] The first electrode 155 includes a first electrode metal layer 1551 and a first connection metal layer 1553. The first electrode metal layer 1551 is located on the side of the barrier layer 151 facing the substrate 11, and the first electrode metal layer 1551 and the substrate 11 are separated by the insulating layer 13. The first connection metal layer 1553 is connected to the first electrode metal layer 1551 and is partially exposed on the side of the channel layer 153 facing away from the substrate 11.

[0030] The second electrode 157 includes a second electrode metal layer 1571 and a second connecting metal layer 1573. The second electrode metal layer 1571 is located on the side of the barrier layer 151 facing the substrate 11, and the second electrode metal layer 1571 and the substrate 11 are separated by the insulating layer 13. The second connecting metal layer 1573 connects to the second electrode metal layer 1571 and is partially exposed on the side of the channel layer 153 facing away from the substrate 11.

[0031] The gate structure 159 includes a gate semiconductor layer 1591 and a gate metal layer 1593. The gate semiconductor layer 1591 is located on the side of the barrier layer 151 facing the substrate 11, and the gate semiconductor layer 1591 and the substrate 11 are separated by the insulating layer 13. The gate metal layer 1593 is connected to the gate semiconductor layer 1591 and is partially exposed on the side of the insulating layer 13 away from the substrate 11.

[0032] As can be seen from the above, in the switch array 10 of the present invention, the first electrode 155 and the second electrode 157 of each semiconductor switch device 15 are separated from the substrate 11 by an insulating layer 13, and the first electrode 155, the second electrode 157 and the gate structure 159 are designed accordingly. Taking the first electrode 155 as the source of the semiconductor switch device 15 and the second electrode 157 as the drain of the semiconductor switch device 15 as an example, in practical applications, each semiconductor switch device 15 can achieve independent voltage application to its source, thereby avoiding the back gate effect problem caused by substrate voltage bias that occurs when the source of each switch device is connected to the same substrate in related technologies. In this way, the switching performance of the switch array 10 can be improved.

[0033] In some embodiments, see Figure 1 and Figure 2 The substrate 11 is made of a material that is resistant to high temperatures and dissipates heat quickly, such as diamond or silicon carbide, which gives the switch array 10 advantages such as high temperature resistance and improved heat dissipation performance.

[0034] In some embodiments, see Figure 1 and Figure 2 The barrier layer 151 and the channel layer 153, for example, are made of third-generation wide-bandgap semiconductor materials, which have the characteristics of large bandgap, high critical breakdown electric field strength, high saturated electron drift velocity, and strong radiation resistance. The semiconductor switching device 15 fabricated with these materials has a faster switching rate and lower switching power consumption, and has considerable application prospects in small-scale high-frequency switching circuits such as DC-DC switched capacitor converters. For example, the barrier layer 151 is an aluminum gallium nitride (AlGaN) layer, the channel layer 153 is a gallium nitride (GaN) layer, and the corresponding gate semiconductor layer 1591 can be a P-type GaN layer, but the embodiments of the present invention are not limited thereto.

[0035] In some embodiments, see Figure 1 , Figure 2 and Figure 3 The first connecting metal layer 1553 includes a first horizontal portion 1553a and a first vertical portion 1553b. The first horizontal portion 1553a is located on the side of the channel layer 153 facing away from the substrate 11. The first vertical portion 1553b penetrates the channel layer 153 and the barrier layer 151, and its opposite ends are respectively connected to the first horizontal portion 1553a and the first electrode metal layer 1551. Furthermore, the first horizontal portion 1553a and the first vertical portion 1553b are, for example, an integral structure and are, for example, generally L-shaped.

[0036] As described above, the second connecting metal layer 1573 includes a second horizontal portion 1573a and a second vertical portion 1573b. The second vertical portion 1573b penetrates the channel layer 153 and the barrier layer 151 to connect to the second electrode metal layer 1571. The second horizontal portion 1573a is connected to the side of the second vertical portion 1573b opposite to the second electrode metal layer 1571 and is spaced apart from the channel layer 153 and the barrier layer 151, and is exposed on the side of the insulating layer 13 opposite to the substrate 11. Furthermore, the second vertical portion 1573b is, for example, generally L-shaped, and the second horizontal portion 1573a is generally straight. During fabrication, the L-shaped second vertical portion 1573b can be sputtered first, and then the second horizontal portion 1573a can be sputtered.

[0037] Furthermore, one end of the gate metal layer 1593 is exposed on the side of the insulating layer 13 opposite to the substrate 11, and the other end extends into the insulating layer 13 in a direction close to the substrate 11 to connect to the gate semiconductor layer 1591. The gate semiconductor layer 1591 is, for example, generally L-shaped.

[0038] In this way, the embodiments of the present invention employ short-range vertical interconnects to lead the first electrode metal layer 1551, the second electrode metal layer 1571 and the gate semiconductor layer 1591 to the side of the channel layer 153 away from the substrate 11. The interconnect metal is short, thus reducing RC delay and improving the signal transmission speed of the device compared to the long-range metal interconnects in related technologies.

[0039] In some embodiments, see Figure 2 The end face 155S of the first horizontal portion 1553a of the first connecting metal layer 1553 facing away from the substrate 11, the end face 157SA of the second horizontal portion 1573a of the second connecting metal layer 1573 facing away from the substrate 11, and the end face 159S of the gate metal layer 1593 facing away from the substrate 11 are flush. The end face 157SA of the second horizontal portion 1573a of the second connecting metal layer 1573 facing away from the substrate 11 is higher than the end face 157SB of the second vertical portion 1573b of the second connecting metal layer 1573 facing away from the substrate 11. In this way, a passivation layer 17 is subsequently formed on the side of the channel layer 153 and the insulating layer 13 facing away from the substrate 11 (see...). Figure 4 When the passivation layer 17 is applied, it can completely cover the top surfaces (including end face 157SB) except for end face 155S, end face 157SA, and end face 159S, thereby achieving the desired effect. Figure 4 As shown, the positions of the first electrode pad 155P, the second electrode pad 157P, and the gate pad 159P are staggered to facilitate subsequent wire bonding.

[0040] In some embodiments, see Figure 2 , Figure 3 and Figure 4 The passivation layer 17 covers the side of the insulating layer 13 and the channel layer 153 facing away from the substrate 11, and exposes part or all of the end face 155S of the first horizontal portion 1553a of the first connecting metal layer 1553 facing away from the substrate 11 as the first electrode pad 155P, part or all of the end face 157SA of the second horizontal portion 1573a of the second connecting metal layer 1573 facing away from the substrate 11 as the second electrode pad 157P, and part or all of the end face 159S of the gate metal layer 1593 facing away from the substrate 11 as the gate pad 159P. It should be noted that... Figure 3 The dashed line in the figure represents the boundary line between the insulating layer 13 and the channel layer 153 on the side opposite to the substrate 11.

[0041] See Figures 5A to 5C as well as Figure 1 and Figure 2This invention provides a method for manufacturing a switch array, which can be used to manufacture... Figure 1 The switch array 10 shown. Specifically, the method for manufacturing the switch array in this embodiment includes, for example, the following steps (i) to (iii).

[0042] In step (i), see Figure 5B An initial switch array is provided. This initial switch array includes, for example, a substrate 20, a plurality of initial semiconductor switching devices 150, and an insulating layer 13. The plurality of initial semiconductor switching devices 150 are arranged side-by-side on the substrate 20. Each initial semiconductor switching device 150 includes a channel layer 153, a barrier layer 151, a first electrode metal layer 1551, a second electrode metal layer 1571, and a gate semiconductor layer 1591. The channel layer 153 is located between the substrate 20 and the barrier layer 151. The first electrode metal layer 1551, the second electrode metal layer 1571, and the gate semiconductor layer 1591 are all located on the side of the barrier layer 151 facing away from the substrate 20. The insulating layer 13 is located on the substrate 20, covers the plurality of initial semiconductor switching devices 150, and spaces the plurality of initial semiconductor switching devices 150 apart from each other.

[0043] More specifically, in some embodiments, in order to obtain Figure 5B The initial switch array shown can first provide, as Figure 5A The layer structure shown includes a substrate 20 and a channel material layer 1510, a barrier material layer 1530, and a gate semiconductor material layer 1590 sequentially stacked on the substrate 20. Next, the gate semiconductor material layer 1590 is patterned to obtain multiple gate semiconductor layers 1591, and multiple first electrode metal layers 1551 and multiple second electrode metal layers 1553 are formed using sputtering technology. Then, multiple active regions are isolated using Mesa etching to obtain the multiple initial semiconductor switching devices 150. Next, an insulating material layer 13 can be obtained by depositing an insulating material layer using plasma-enhanced chemical vapor deposition (PECVD) and then depositing the insulating material layer using chemical mechanical polishing (CMP). Thus, the desired semiconductor switching device 13 can be fabricated. Figure 5B The initial switch array is shown. The insulating layer 13 is, for example, made of insulating materials such as silicon oxide, silicon nitride, aluminum oxide, or aluminum nitride.

[0044] In step (ii), the initial switch array is flip-bonded to substrate 11 (see...). Figure 5CThe substrate 20 is then removed, for example, by wet etching or laser lift-off. The substrate 20 is made of materials such as silicon or sapphire, while the substrate 11 is made of a different material than the substrate 20, such as a high-temperature resistant and fast-dissipating material like diamond or silicon carbide. In this way, by employing flip-chip bonding technology, the heat dissipation performance is improved by removing the heat-sensitive substrate 20 and replacing it with the high-temperature resistant and fast-dissipating substrate 11.

[0045] In step (iii), after removing the substrate 20, a first interconnect metal layer 1553, a second interconnect metal layer 1573, and a gate metal layer 1593 are formed to obtain a switch array 10 having a plurality of semiconductor switching devices 15 (see [link]). Figure 1 More specifically, dry etching can be used to create openings to expose a portion of the surface of the first electrode metal layer 1551, a portion of the surface of the second electrode metal layer 1571, and a portion of the surface of the gate semiconductor layer 1591; then metal deposition is performed to form the first interconnect metal layer 1553, the second interconnect metal layer 1573, and the gate metal layer 1593, achieving short-range metal interconnections between each of them and the first electrode metal layer 1551, the second electrode metal layer 1571, and the gate semiconductor layer 1591. For example, the metal deposited here may be a material such as AlCu.

[0046] In some embodiments, for Figure 1 The switch array 10 shown can further form a passivation layer 17 (see [reference]). Figure 4 The first electrode pad 155P is exposed at least a portion of the end face 155S of the first horizontal portion 1553a of the first connecting metal layer 1553 facing away from the substrate 11, the second electrode pad 157P is exposed at least a portion of the end face 157SA of the second horizontal portion 1573a of the second connecting metal layer 1573 facing away from the substrate 11, and the gate pad 159P is exposed at least a portion of the end face 159S of the gate metal layer 1593 facing away from the substrate 11.

[0047] See Figure 6 The present invention provides a DC-DC switching converter circuit, which includes, for example, a first power input terminal INPUT0, a second power input terminal INPUT1, and an input capacitor C. IN Switch array, load capacitor C L and output capacitor C OUTHere, the first power input terminal INPUT0 is, for example, the drain power input terminal, and the second power input terminal INPUT1 is, for example, the ground terminal.

[0048] The input capacitor C IN It is connected between the first power input terminal INPUT0 and the second power input terminal INPUT1.

[0049] The switch array, for example, employs... Figure 1 The switch array 10 shown contains a plurality of semiconductor switching devices 15 (see [reference]). Figure 1 For example, it includes a first semiconductor switch S1, a second semiconductor switch S2, a third semiconductor switch S3, and a fourth semiconductor switch S4. The first electrode (e.g., drain) of the first semiconductor switch S1 is connected to the first power input terminal INPUT0. The first electrode (e.g., drain) of the second semiconductor switch S2 is connected to the second electrode (e.g., source) of the first semiconductor switch S1. The first electrode (e.g., drain) of the third semiconductor switch S3 is connected to the second electrode (e.g., source) of the second semiconductor switch S2. The first electrode (e.g., drain) of the fourth semiconductor switch S4 is connected to the second electrode (e.g., source) of the third semiconductor switch S3. The second electrode (e.g., source) of the fourth semiconductor switch S4 is connected to the second power input terminal INPUT1.

[0050] The load capacitor C L Between node N1, which is connected between the first electrode of the second semiconductor switch S2 and the second electrode of the first semiconductor switch S1, and node N3, which is connected between the first electrode of the fourth semiconductor switch S4 and the second electrode of the third semiconductor switch S3.

[0051] The output capacitor C OUT Between node N2, which is connected between the first electrode of the third semiconductor switching device S3 and the second electrode of the second semiconductor switching device S2, and the second power input terminal INPUT1.

[0052] The DC-DC switching converter circuit of this invention employs... Figure 1The switch array 10 shown can have excellent switching performance, and even advantages such as low RC delay, fast signal transmission speed, and high temperature resistance. Furthermore, when the first to fourth semiconductor switching devices S1-S4 use third-generation wide-bandgap semiconductor devices (such as GaN devices), the resulting switching devices have faster switching rates and lower switching losses due to the large bandgap, high critical breakdown electric field strength, high saturated electron drift velocity, and strong radiation resistance of third-generation wide-bandgap semiconductor materials. This makes them promising for small-scale, high-frequency applications. In contrast, current silicon-based devices, due to their inherent characteristics, have low switching frequencies, high losses, and consequently require large capacitor sizes and have relatively low overall efficiency.

[0053] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A switch array, characterized in that, include: A substrate, an insulating layer, and a plurality of semiconductor switching devices are arranged side by side on the substrate, and the insulating layer is disposed between the substrate and the plurality of semiconductor switching devices and spaced apart from each other. Each of the semiconductor switching devices includes: A barrier layer is disposed on the substrate, and the barrier layer and the substrate are separated by the insulating layer; A channel layer is disposed on the side of the barrier layer opposite to the substrate; The first electrode includes a first electrode metal layer and a first connecting metal layer. The first electrode metal layer is located on the side of the barrier layer facing the substrate, and the first electrode metal layer is separated from the substrate by the insulating layer. The first connecting metal layer is connected to the first electrode metal layer and is partially exposed on the side of the channel layer away from the substrate. The second electrode includes a second electrode metal layer and a second connecting metal layer. The second electrode metal layer is located on the side of the barrier layer facing the substrate, and the second electrode metal layer is spaced from the substrate by the insulating layer. The second connecting metal layer connects to the second electrode metal layer and is partially exposed on the side of the channel layer facing away from the substrate. A gate structure includes a gate semiconductor layer and a gate metal layer, wherein the gate semiconductor layer is located on the side of the barrier layer facing the substrate and the gate semiconductor layer is separated from the substrate by the insulating layer, and the gate metal layer is connected to the gate semiconductor layer and partially exposed on the side of the insulating layer away from the substrate.

2. The switch array according to claim 1, characterized in that, The substrate material includes diamond or silicon carbide; and / or, The gate semiconductor layer includes a P-type gallium nitride layer.

3. The switch array according to claim 1, characterized in that, The first connecting metal layer includes a first horizontal portion and a first vertical portion. The first horizontal portion is located on the side of the channel layer away from the substrate. The first vertical portion penetrates the channel layer and the barrier layer, and its opposite ends are respectively connected to the first horizontal portion and the first electrode metal layer. The second connecting metal layer includes a second horizontal portion and a second vertical portion. The second vertical portion penetrates the channel layer and the barrier layer to connect the second electrode metal layer. The second horizontal portion is connected to the side of the second vertical portion away from the second electrode metal layer and is spaced apart from the channel layer and the barrier layer, and is exposed on the side of the insulating layer away from the substrate. as well as One end of the gate metal layer is exposed on the side of the insulating layer away from the substrate, and the other end extends into the insulating layer in a direction close to the substrate to connect to the gate semiconductor layer.

4. The switch array according to claim 3, characterized in that, The end face of the first horizontal portion of the first connecting metal layer facing away from the substrate, the end face of the second horizontal portion of the second connecting metal layer facing away from the substrate, and the end face of the gate metal layer facing away from the substrate are flush. The end face of the second horizontal portion of the second connecting metal layer facing away from the substrate is higher than the end face of the second vertical portion of the second connecting metal layer facing away from the substrate.

5. The switch array according to claim 4, characterized in that, The switch array further includes a passivation layer covering the side of the insulating layer and the channel layer away from the substrate, and exposing at least a portion of the end face of the first horizontal portion of the first connection metal layer away from the substrate as a first electrode pad, at least a portion of the end face of the second horizontal portion of the second connection metal layer away from the substrate as a second electrode pad, and at least a portion of the end face of the gate metal layer away from the substrate as a gate pad.

6. A DC-DC switching converter circuit, characterized in that, include: First power input terminal; Second power input terminal; An input capacitor is connected between the first power input terminal and the second power input terminal; The switch array as described in any one of claims 1 to 5, wherein the plurality of semiconductor switching devices includes a first semiconductor switching device, a second semiconductor switching device, a third semiconductor switching device, and a fourth semiconductor switching device, wherein the first electrode of the first semiconductor switching device is connected to the first power input terminal, the first electrode of the second semiconductor switching device is connected to the second electrode of the first semiconductor switching device, the first electrode of the third semiconductor switching device is connected to the second electrode of the second semiconductor switching device, the first electrode of the fourth semiconductor switching device is connected to the second electrode of the third semiconductor switching device, and the second electrode of the fourth semiconductor switching device is connected to the second power input terminal; A load capacitor is connected between the node between the first electrode of the second semiconductor switch and the second electrode of the first semiconductor switch, and between the node between the first electrode of the fourth semiconductor switch and the second electrode of the third semiconductor switch. as well as The output capacitor is connected between the node between the first electrode of the third semiconductor switching device and the second electrode of the second semiconductor switching device and the second power input terminal.

7. A method for manufacturing a switch array, characterized in that, include: An initial switch array is provided, the initial switch array comprising: a substrate, a plurality of initial semiconductor switching devices and an insulating layer, the plurality of initial semiconductor switching devices being disposed side by side on the substrate, each of the initial semiconductor switching devices comprising a channel layer, a barrier layer, a first electrode metal layer, a second electrode metal layer and a gate semiconductor layer, the channel layer being located between the substrate and the barrier layer, the first electrode metal layer, the second electrode metal layer and the gate semiconductor layer being located on the side of the barrier layer opposite to the substrate, and the insulating layer being located on the substrate and covering the plurality of initial semiconductor switching devices and spacing the plurality of initial semiconductor switching devices apart from each other; The initial switch array is flip-bonded to the substrate, and then the substrate is removed; and After removing the substrate, a first interconnect metal layer, a second interconnect metal layer, and a gate metal layer are formed to obtain a switch array having a plurality of semiconductor switching devices, wherein each of the semiconductor switching devices includes: The barrier layer is disposed on the substrate, and the barrier layer and the substrate are separated by the insulating layer; The channel layer is disposed on the side of the barrier layer opposite to the substrate; The first electrode includes a first electrode metal layer and a first connection metal layer. The first electrode metal layer is located on the side of the barrier layer facing the substrate, and the first electrode metal layer is separated from the substrate by the insulating layer. The first connection metal layer is connected to the first electrode metal layer and is partially exposed on the side of the channel layer away from the substrate. The second electrode includes a second electrode metal layer and a second connection metal layer. The second electrode metal layer is located on the side of the barrier layer facing the substrate, and the second electrode metal layer is spaced from the substrate by the insulating layer. The second connection metal layer connects to the second electrode metal layer and is partially exposed on the side of the channel layer opposite to the substrate. A gate structure includes a gate semiconductor layer and a gate metal layer, wherein the gate semiconductor layer is located on the side of the barrier layer facing the substrate and the gate semiconductor layer is separated from the substrate by the insulating layer, and the gate metal layer is connected to the gate semiconductor layer and partially exposed on the side of the insulating layer away from the substrate.

8. The method for manufacturing a switch array according to claim 7, characterized in that, The substrate is made of silicon or sapphire, and the base material is different from the substrate material and includes diamond or silicon carbide.

9. The method for manufacturing a switch array according to claim 7, characterized in that, The provision of the initial switch array includes: forming the insulating layer using plasma-enhanced chemical vapor deposition and chemical mechanical polishing; and / or The formation of the first interconnect metal layer, the second interconnect metal layer, and the gate metal layer includes: creating openings using dry etching to expose a portion of the surface of the first electrode metal layer, a portion of the surface of the second electrode metal layer, and a portion of the surface of the gate semiconductor layer; and / or The removal of the substrate includes: removing the substrate by wet etching or laser stripping.

10. The method for manufacturing a switch array according to any one of claims 7 to 9, characterized in that, The first connecting metal layer includes a first horizontal portion and a first vertical portion. The first horizontal portion is located on the side of the channel layer away from the substrate. The first vertical portion penetrates the channel layer and the barrier layer, and its opposite ends are respectively connected to the first horizontal portion and the first electrode metal layer. The second connecting metal layer includes a second horizontal portion and a second vertical portion. The second vertical portion penetrates the channel layer and the barrier layer to connect the second electrode metal layer. The second horizontal portion is connected to the side of the second vertical portion away from the second electrode metal layer and is spaced apart from the channel layer and the barrier layer, and is exposed on the side of the insulating layer away from the substrate. One end of the gate metal layer is exposed on the side of the insulating layer away from the substrate, and the other end extends into the insulating layer in a direction close to the substrate to connect to the gate semiconductor layer. as well as The end face of the first horizontal portion of the first connecting metal layer facing away from the substrate, the end face of the second horizontal portion of the second connecting metal layer facing away from the substrate, and the end face of the gate metal layer facing away from the substrate are flush.

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