A solar cell intermediate, a solar cell, and a preparation method and application thereof

Abstract

The application discloses a solar cell intermediate, a solar cell and a preparation method and application thereof. When the doped polysilicon and the tunneling oxide layer in the non-metallized area are selectively removed, the continuous removal is replaced by the intermittent removal in the left-right direction interval. The structure design unexpectedly reduces the lateral transmission distance and the lateral transmission resistance. Meanwhile, the structure can obviously compensate the partial carrier convergence failure caused by the failure of the doped polysilicon in the partial metal fine grid and the corresponding orthographic projection range, and has strong risk resistance. In addition, the structure can directly make the partial metal fine grid into the intermittent design, so that the partial metal fine grid is locally disconnected. The structure not only does not reduce the core indicators of the solar cell, but also has the characteristics of reducing the required silver paste amount and metal composite, and is favorable to improving the short-circuit current, the fill factor and the conversion efficiency and other core indicators of the solar cell.

Description

Technical Field

[0001] This invention relates to the field of solar cells, specifically to a solar cell intermediate, a solar cell, its preparation method, and its applications. Background Technology

[0002] The emergence of TOPCon tunneling oxide passivated contact solar cells has attracted significant attention to high-efficiency crystalline silicon solar cell technology. TOPCon cells use N-type silicon as the substrate material and consist of an ultrathin silicon oxide layer and a doped polycrystalline silicon layer forming the passivation contact structure. This structure reduces carrier recombination between the metal electrode and silicon, and facilitates full-area passivation, thereby improving the efficiency of TOPCon solar cells. However, the presence of doped polycrystalline silicon in TOPCon cells also causes severe parasitic absorption, leading to a decrease in the photocurrent and resulting in efficiency loss. Therefore, currently, this tunneling silicon oxide and doped polycrystalline silicon layer structure is only used on the back surface of TOPCon cells. Meanwhile, in the solar spectrum, photons with wavelengths greater than 950 nm will be transmitted to the back surface of the silicon wafer. The doped polycrystalline silicon layer will also exhibit parasitic absorption of these infrared photons, resulting in efficiency loss. In order to reduce the efficiency loss caused by parasitic absorption of doped polycrystalline silicon, selective polycrystalline silicon passivation contact technology is currently used. This technology removes some of the polycrystalline silicon in the non-metallized region while retaining the polycrystalline silicon structure in the metallized region. This reduces the area ratio of doped polycrystalline silicon on the back surface of the cell, reduces parasitic absorption of infrared photons, and improves the efficiency of solar cells.

[0003] However, in the current selective polysilicon passivation contact structure, the doped polysilicon layer between two adjacent metal gates is continuously removed (except at the metal main gate location). Although this significantly reduces the parasitic loss of the doped polysilicon layer, it also increases the lateral transport resistance of the back carriers, resulting in a low fill factor FF of the cell and limiting the extent of efficiency improvement.

[0004] Meanwhile, when some of the metal grids and the corresponding doped polycrystalline silicon within their orthographic projection range fail, making it difficult or even impossible to transport electrons, the entire metal grid in the current structural design is prone to directly losing its function of collecting charge carriers. This will cause some charge carriers generated on the silicon substrate to have to travel a long distance before they can be collected. As a result, it will be very easy to cause the intensification of charge carrier recombination, increase the series resistance, and ultimately lead to a significant deterioration of the battery's core indicators such as short-circuit current, fill factor, and conversion efficiency. In other words, the current structural design is not resilient enough.

[0005] Although Chinese invention patent CN119486360 B shortens the transmission distance in the longitudinal direction by separating the laser ablation area, it does not fundamentally improve the above-mentioned problems.

[0006] It should be noted that the information disclosed in the background section above is only for understanding the background of this application. Therefore, the background section of this invention may include background information about the problems or environment of this invention, and is not necessarily a description of the prior art. Thus, the content included in the background section does not constitute an admission of the prior art by the applicant. Summary of the Invention

[0007] The purpose of this invention is to overcome one or more shortcomings in the prior art and provide an improved solar cell intermediate and a solar cell containing the intermediate. The improved structure of this invention can help shorten the lateral transport distance of charge carriers on the back side and reduce the total lateral resistance. At the same time, it has excellent risk resistance when local charge carrier transport path fails. In addition, the structure of this invention can reduce the amount of paste used in the metal electrode while ensuring good charge carrier transport effect, which greatly saves costs.

[0008] The present invention also provides the above-mentioned solar cell intermediate, solar cell, method for preparing them, and application in solar photovoltaic power generation system.

[0009] To achieve the above objectives, the present invention employs the following technical solution: A solar cell intermediate includes a silicon wafer with a back surface and a plurality of back metal grids and a plurality of back metal main grids respectively disposed on the back surface. The back surface includes a plurality of unit regions, and each unit region includes n first sub-regions and second sub-regions, where n is greater than or equal to 2. The n first sub-regions are arranged sequentially at intervals along the left-right direction, and the intervals extend along the up-down direction; the second sub-region surrounds the n first sub-regions, and the intervals are part of the second sub-regions; In the first sub-region, a silicon wafer and a first back passivation layer are sequentially disposed along a direction perpendicular to the first sub-region; in the second sub-region, a silicon wafer, a tunneling oxide layer, a polysilicon layer, and a second back passivation layer are sequentially disposed along a direction perpendicular to the second sub-region. The back metal fine gate and the back metal main gate are both located in the second sub-region. The back metal fine gate passes through the second back passivation layer and is connected to the polysilicon layer. The back metal main gate is connected to the back metal fine gate. At least one of the back metal grids corresponding to each of the unit regions is partially broken, and the length of the partially broken part is less than 20% of the length of the corresponding back metal grid.

[0010] In some embodiments of the present invention, the distance between two adjacent first sub-regions in the n first sub-regions is 50-200 μm.

[0011] According to some specific aspects of the present invention, the distance between two adjacent first sub-regions in the n first sub-regions includes, but is not limited to, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm, 105μm, 110μm, 115μm, 120μm, 125μm, 130μm, 135μm, 140μm, 145μm, 150μm, 155μm, 160μm, 165μm, 170μm, 175μm, 180μm, 185μm, 190μm, 195μm, 200μm, etc.

[0012] In some embodiments of the present invention, the total area of ​​the n first sub-regions accounts for 40%-96% of the area of ​​the unit region. Further, the total area of ​​the n first sub-regions accounts for 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, etc., of the area of ​​the unit region.

[0013] In some embodiments of the present invention, the length of the partial break is 0.1-2 mm. Further, the length of the partial break includes, but is not limited to, 0.1 mm, 0.15 mm, 0.20 mm, 0.25 mm, 0.30 mm, 0.35 mm, 0.4 mm, 0.45 mm, 0.5 mm, 0.55 mm, 0.60 mm, 0.65 mm, 0.70 mm, 0.75 mm, 0.8 mm, 0.85 mm, 0.90 mm, 0.95 mm, 1.0 mm, 1.1 mm, 1.2 mm, 1.3 mm, 1.4 mm, 1.5 mm, 1.6 mm, 1.7 mm, 1.8 mm, 1.9 mm, 2.0 mm, etc.

[0014] In some embodiments of the invention, each of the back metal grids has multiple partial breaks.

[0015] Furthermore, the total length of the plurality of said partial breaks accounts for 1%-20% of the length of the corresponding back metal grid, for example, including but not limited to 1%, 1.5%, 2.0%, 2.5%, 3.0%, 3.5%, 4.0%, 4.5%, 5.0%, 5.5%, 6.0%, 6.5%, 7.0%, 7.5%, 8.0%, 8.5%, 9.0%, 9.5%, 10.0%, 10.5%, 11.0%, 11.5%, 12.0%, 12.5%, 13.0%, 13.5%, 14.0%, 14.5%, 15.0%, 15.5%, 16.0%, 16.5%, 17.0%, 17.5%, 18.0%, 18.5%, 19.0%, 19.5%, etc.

[0016] In some embodiments of the invention, the lengths of the respective partial breaks on each of the back metal grids remain the same or different.

[0017] In some embodiments of the present invention, the position and length of the partial breaks on any two of the back metal grids remain the same or different.

[0018] In some embodiments of the present invention, the n first sub-regions are arranged at intervals along the length direction of the back metal grid.

[0019] In some embodiments of the invention, the spacing region extends along the width direction of the back metal grid.

[0020] In some embodiments of the present invention, the spacing regions of each of the unit regions located between two adjacent back metal main grids are distributed on the same extension line or on multiple parallel extension lines.

[0021] In some embodiments of the present invention, the polysilicon layer in the second sub-region forms a multidimensional carrier transport path. A "multidimensional carrier transport path" means that the carrier transport path is not singular, and carrier transport can be achieved in multiple directions.

[0022] In some embodiments of the present invention, a continuous carrier transport path is formed between any two points in the polysilicon layer corresponding to the second sub-region.

[0023] In some embodiments of the present invention, the polysilicon layer corresponding to the interval region and the polysilicon layer corresponding to the partial disconnection are directly connected.

[0024] In some embodiments of the present invention, the polysilicon in the polysilicon layer is phosphorus-doped polysilicon.

[0025] In some embodiments of the present invention, the first back passivation layer and the second back passivation layer are integrally formed.

[0026] In some embodiments of the present invention, the first back passivation layer and the second back passivation layer independently include a passivation film and a selective antireflection film.

[0027] Another technical solution provided by the present invention: a method for preparing the above-mentioned solar cell intermediate, the preparation method comprising: Provide a silicon wafer; A tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are prepared on the back surface of the silicon wafer; Remove the tunneling oxide layer and the phosphorus-doped polysilicon layer within the n first sub-regions; A passivation layer is formed over the entire area of ​​the back surface, and then a back metal fine gate and a back metal main gate are fabricated, with at least one of them being partially disconnected during the fabrication of the back metal fine gate.

[0028] Another technical solution provided by the present invention: a solar cell, wherein the solar cell comprises the solar cell intermediate described above.

[0029] Another technical solution provided by the present invention: a method for preparing a solar cell, the method comprising: An N-type silicon wafer is provided, and the N-type silicon wafer is subjected to boron diffusion treatment to form emitters on the front and back surfaces of the N-type silicon wafer, respectively. The emitter on the back surface of the N-type silicon wafer is removed, and a tunneling oxide layer and a polycrystalline silicon layer are sequentially prepared on the back surface. Then, phosphorus diffusion is performed to form a phosphorus-doped polycrystalline silicon layer, and a phosphorus-silicon glass layer is formed on the phosphorus-doped polycrystalline silicon layer. The back surface includes multiple unit regions, each of which includes n first sub-regions and second sub-regions, where n is greater than or equal to 2; the n first sub-regions are arranged sequentially at intervals along the left-right direction, and the intervals extend along the up-down direction; the second sub-regions surround the n first sub-regions, and the intervals are part of the second sub-regions; The patterned film is created on the phosphosilicate glass layer using laser film-forming, and the phosphosilicate glass layer in each of the first sub-regions is removed after film-forming. Wet chemical etching is performed to remove the tunneling oxide layer and phosphorus-doped polysilicon layer corresponding to each of the first sub-regions from the open film region, and then the phosphorus-silicon glass layer in the second sub-region is removed. Passivation layers are deposited on the front and back surfaces, and metal fine gates and metal main gates are fabricated separately. When fabricating the back metal fine gate, at least one of them is partially broken, and the length of the partially broken part is controlled to be less than 20% of the length of the corresponding back metal fine gate.

[0030] In some embodiments of the present invention, the sheet resistance of the phosphorus-doped polycrystalline silicon layer is 40~80 Ω / sq, and the phosphorus atom doping concentration is 4.0×10⁻⁶. 20 ~8.0×10 20 cm -3 .

[0031] Another technical solution provided by the present invention: a solar cell manufactured by the above-described method for preparing a solar cell, wherein in the first sub-region, a silicon wafer and a first back passivation layer are sequentially disposed along a direction perpendicular to the first sub-region; and in the second sub-region, a silicon wafer, a tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer, and a second back passivation layer are sequentially disposed along a direction perpendicular to the second sub-region. The back metal fine gate and the back metal main gate are both located in the second sub-region. The back metal fine gate passes through the second back passivation layer and is connected to the polysilicon layer. The back metal main gate is connected to the back metal fine gate. At least one of the back metal grids corresponding to each of the unit regions is partially disconnected.

[0032] Another technical solution provided by the present invention is a solar photovoltaic power generation system, wherein the solar photovoltaic power generation system includes the solar cells described above.

[0033] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art: Based on the problems of high lateral transport distance, high lateral resistance, and insufficient risk resistance of the current selective polysilicon passivation contact structure, the inventors of this invention discovered during extensive experimental research that by replacing the continuous removal method with intermittent removal in the left-right direction when selectively removing the doped polysilicon and tunnel oxide layer in the non-metallized region, this structural design achieved an unexpected reduction in lateral transport distance and lateral transport resistance. In particular, this structural design has a significant compensatory effect on the failure of partial carrier aggregation function caused by the failure of some metal grids and the doped polysilicon within their corresponding orthogonal projection range, reducing carrier recombination, avoiding the increase of series resistance, and thus ensuring that the battery has good core indicators such as short-circuit current, fill factor, and conversion efficiency. In particular, according to the structural design of this invention, some of the metal grids can also be made into an intermittent design, making them partially disconnected. This not only does not reduce the core performance of the battery, but also has the following advantages: 1) The reduction in printing area helps to reduce the amount of silver paste required for printing; 2) The reduction in printing area helps to reduce the metal composite of the battery and improve the open-circuit voltage of the battery; 3) The metal grid lines on the back of the battery reduce the obstruction of incident light, optimize the utilization rate of light on the back of the battery, and combined with the special selective passivation battery structure of this invention, further improve the bifacial utilization rate of the solar cell. Attached Figure Description

[0034] Figure 1 This is one of the top views of the back surface of a solar cell in an embodiment of the present invention; Figure 2 This is a second top view of the back surface of the solar cell in an embodiment of the present invention; Figure 3 This is the third top view of the back surface of the solar cell in an embodiment of the present invention; Figure 4 This is the fourth top view of the back surface of the solar cell in an embodiment of the present invention; Figure 5 This is one of the schematic diagrams of carrier transport on the back surface of a solar cell in an embodiment of the present invention; Figure 6 This is a second schematic diagram of carrier transport on the back surface of a solar cell in an embodiment of the present invention (in the case of partial failure). Figure 7 This is a schematic diagram of carrier transport on the back surface of a solar cell under local failure conditions in the prior art; Figure 8 This is the third schematic diagram of carrier transport on the back surface of a solar cell in an embodiment of the present invention (in the case of partial failure). Figure 9 This is a top view of the back surface of the solar cell in Comparative Example 1. Figure 10 This is a top view of the back surface of the solar cell in Comparative Example 2; Figure 11 This is a top view of the back surface of the solar cell in Comparative Example 3; Figure 12 This is a top view of the back surface of the solar cell in Comparative Example 4; In the attached figures, the following are the reference numerals: 1, unit area; 11, back metal grid; 111, partially broken portion; 12, back metal main grid; 13, first sub-region; 14, second sub-region; 141, interval area; 15, continuous open film area. Detailed Implementation

[0035] The main concept of this invention is as follows: On the one hand, this invention does not adopt the current selective polycrystalline silicon passivation contact structure design. Instead, it divides the original transversely complete polycrystalline silicon opening region between two fine gates into two or more opening regions spaced apart in the left-right direction. That is, the doped polycrystalline silicon layer between two adjacent fine gates is not continuously removed in the left-right direction. A portion of doped polycrystalline silicon extending in the up-down direction is retained between two adjacent opening regions. The transport of charge carriers in doped polycrystalline silicon is similar to that in metal materials. The structural design in this invention allows charge carriers to be transported through polycrystalline silicon channels that are closer together after generation. In particular, the transport distance in the left-right direction is greatly shortened. Furthermore, since the resistance of doped polycrystalline silicon is significantly lower than that of silicon wafers, i.e. silicon substrates, the shortening of the transport distance in the left-right direction is beneficial to improving the charge carrier transport efficiency and improving indicators such as the fill factor (FF) of solar cells. On the other hand, the back metallized fine grating pattern structure design in this invention does not adopt the traditional pattern scheme, but breaks up the through fine grating pattern; The reason why the traditional back-side full-surface polysilicon passivation contact structure cannot adopt the solution of this invention is that, in the traditional back-side full-surface polysilicon structure, in order to ensure that the parasitic absorption loss of the polysilicon layer is not too high, the doping concentration or the thickness of the polysilicon is limited, such as: doping concentration N≤4.0E+20 cm. -3 With a thickness ≤120 nm, the sheet resistance of the doped polycrystalline silicon layer is as high as 100~150 Ω / sq, resulting in high sheet resistance for lateral transmission. Although the disconnected grid structure of this invention can save silver paste, the excessively high resistance of the disconnected portion leads to a decrease in the efficiency of the solar cell. As mentioned above, in the traditional full-surface polycrystalline silicon structure on the back side, if the solution of this invention is adopted, while avoiding the high sheet resistance problem caused by the disconnected portion, it is necessary to increase the doping concentration or the thickness of the polycrystalline silicon to reduce the surface sheet resistance of the disconnected area and avoid efficiency loss in the disconnected fine grid area. However, the two solutions mentioned above for reducing surface sheet resistance will aggravate the parasitic absorption of polycrystalline silicon, resulting in greater efficiency loss. Therefore, this novel metallization structure design is not applicable to the traditional polycrystalline silicon passivation structure. However, this structure can be matched with the novel selective polycrystalline silicon passivation contact structure proposed in this invention for the following reasons: 1) In the selective passivation structure, a large area of ​​polycrystalline silicon is removed, leaving only a small portion of the polycrystalline silicon layer between the fine grid lines. In particular, the discontinuous design structure along the left and right directions is adopted during removal. The two schemes mentioned above for reducing the sheet resistance of the polycrystalline layer surface—increasing the doping concentration or increasing the thickness of the doped polycrystalline silicon layer—can be applied to the structure of this invention, and the influence of polycrystalline silicon parasitic absorption can be greatly reduced, without a sharp increase in parasitic absorption; 2) At the same time, a small portion of the polycrystalline silicon layer between the fine grid lines is retained. This portion of the polycrystalline silicon layer connects two adjacent fine grid lines, which is beneficial for carriers to select a shorter transmission distance, further reducing resistance loss and improving the fill factor FF of the cell; In particular, metallization is an important step in the manufacturing process of solar cells, and achieving cost reduction and efficiency improvement is the eternal goal of the metallization process of solar cells. Silver paste is an important auxiliary material in the metallization process. With the rise in silver prices, the price of silver paste has exceeded 10,000 yuan / kg, accounting for more than 80% of the non-silicon cost of solar cells (excluding the cost of silicon wafers). The design of partial disconnection of the metal grid in this invention can reduce the cost of silver paste. Furthermore, it is precisely because of the special selective passivation contact structure design of this invention that the overall battery performance is basically not negatively affected after the active disconnection of the local fine grid. This effect means that when the battery structure of this invention faces sudden situations, such as the failure of some metal fine grids and the corresponding doped polycrystalline silicon within the projected range, the structure of this invention has a significant compensatory effect on the loss of partial carrier aggregation function that may be caused by the aforementioned failure, reducing carrier recombination, avoiding the increase of series resistance, and thus ensuring that the battery has good core indicators such as short-circuit current, fill factor and conversion efficiency. This effect is surprising.

[0036] Based on this, the present invention provides a solar cell intermediate, which includes a silicon wafer having a back surface and a plurality of back metal fine grids and a plurality of back metal main grids respectively disposed on the back surface. The back surface includes a plurality of unit regions, and each unit region includes n first sub-regions and second sub-regions, where n is greater than or equal to 2. The n first sub-regions are arranged sequentially at intervals along the left-right direction, and the intervals extend along the up-down direction; the second sub-region surrounds the n first sub-regions, and the intervals are part of the second sub-regions; In the first sub-region, a silicon wafer and a first back passivation layer are sequentially disposed along a direction perpendicular to the first sub-region; in the second sub-region, a silicon wafer, a tunneling oxide layer, a polysilicon layer, and a second back passivation layer are sequentially disposed along a direction perpendicular to the second sub-region. The back metal fine gate and the back metal main gate are both located in the second sub-region. The back metal fine gate passes through the second back passivation layer and is connected to the polysilicon layer. The back metal main gate is connected to the back metal fine gate. At least one of the back metal grids corresponding to each of the unit regions is partially broken, and the length of the partially broken part is less than 20% of the length of the corresponding back metal grid.

[0037] The following is combined with Figures 1 to 4 The selective passivation contact structure of the present invention is further described, wherein the selective passivation contact structure is disposed on a solar cell intermediate; the left-right and up-down directions in the present invention are all... Figure 1 From the perspective of the image, the direction of the arrangement of each back metal main grid is left and right, that is, multiple back metal main grids are arranged in the left and right direction, and the direction of the arrangement of each back metal fine grid is up and down, that is, multiple back metal fine grids are arranged in the up and down direction.

[0038] See Figure 1 As shown, within each unit region 1, two spaced first sub-regions 13 are sequentially arranged along the left-right direction of the back metal grid 11, specifically along the length direction of the back metal grid 11. The shape of the first sub-region 13 is rectangular, and each first sub-region 13 is surrounded by a second sub-region 14. Each back metal grid 11 is provided with a partial break portion 111 that avoids contact with the back metal main grid 12, and the spaced regions 141 and the partial break portions 111 in all unit regions 1 between every two adjacent back metal main grids 12 extend along the same path.

[0039] See Figure 2 As shown, within each unit region 1, two spaced first sub-regions 13 are sequentially arranged along the left-right direction of the back metal grid 11, specifically along the length direction of the back metal grid 11. The shape of the first sub-region 13 is trapezoidal, with the shorter side of the two parallel sides of the trapezoid close to the back metal main grid 12 and the longer side close to the spaced area 141. Each first sub-region 13 is surrounded by a second sub-region 14. Each back metal grid 11 is provided with a partial break portion 111 that avoids contact with the back metal main grid 12. The spaced area 141 and the partial break portion 111 in all unit regions 1 between every two adjacent back metal main grids 12 extend along the same path.

[0040] See Figure 3As shown, within each unit region 1, three spaced first sub-regions 13 are arranged sequentially along the left-right direction of the back metal grid 11, specifically along the length direction of the back metal grid 11. The shape of the first sub-region 13 is rectangular, and each first sub-region 13 is surrounded by a second sub-region 14. Each back metal grid 11 is provided with a partially broken portion 111 that avoids contact with the back metal main grid 12. In this example, the three first sub-regions 13 within each unit region 1 form two spaced regions 141, which are arranged on the left and right sides of the partially broken portion 111. The two grid segments formed by the broken back metal grid 11 within each unit region 1 are of approximately the same length.

[0041] See Figure 4 As shown, within each unit region 1, three spaced first sub-regions 13 are arranged sequentially along the left-right direction of the back metal grid 11, specifically along the length direction of the back metal grid 11. The shape of the first sub-region 13 is rectangular, and each first sub-region 13 is surrounded by a second sub-region 14. Each back metal grid 11 has a partially broken portion 111 that avoids contact with the back metal main grid 12. In this example, the three first sub-regions 13 in each unit region 1 form two spaced regions 141. One spaced region 141 is located below the partially broken portion 111, and the other is far away from the partially broken portion 111. The two grid segments formed by the broken back metal grid 11 in each unit region 1 have different lengths.

[0042] The following is combined with Figures 5 to 8 The special selective passivation contact structure of the present invention can maintain a short carrier transport distance under both normal and special conditions as explained below: In actual battery design, the length of each cell area is much greater than its width, generally more than 10 times. The figure in this invention uses 10 times as an example for illustration. See Figure 5 As shown, the present invention extends the spacing region 141 in the vertical direction. That is, within each unit region, multiple spaced first sub-regions are sequentially arranged along the length direction of the back metal grid 11. In this case, taking the charge carriers generated at the center as an example, the distance they travel to the nearest side in the length direction decreases from 5d to 2.5d. Since the absolute amount of decrease in the length direction is much greater than the order of magnitude of the transmission distance in the width direction, overall, the design of the selective passivation contact structure of the present invention is beneficial to reducing the carrier transmission distance. In particular, the more spaced first sub-regions are arranged, the greater the decrease in the distance they travel to the nearest side in the length direction will be. For example... Figure 5The lower schematic diagram shows that when there are 10 interval regions 141, the first sub-region has 11 corresponding regions, and the distance transmitted to the nearest side in the length direction is shortened to 5d / 11.

[0043] Further, see Figure 6 As shown, the method of sequentially arranging multiple spaced first sub-regions along the length of the back metal grid 11 in this invention actually forms a longitudinal anti-breakage grid design. If the back metal grid 11 and the corresponding doped polysilicon experience an unexpected carrier transport failure, this longitudinal anti-breakage grid design, relying on the spaced regions 141 extending vertically (the spaced regions themselves are polysilicon layers, such as phosphorus-doped polysilicon, whose conductivity is close to that of metal; therefore, although their carrier transport capability is not as good as metal, it still possesses good carrier transport capability), can transfer some of the carriers gathered on the metal grid to the adjacent back metal grid to complete the carrier aggregation. This avoids the complete failure of the back metal grid itself when there is a partial failure, ultimately ensuring that the overall carrier transport capability of the battery is maintained under special circumstances. However, if the design in CN119486360 B is adopted, it cannot possess the ability of this invention to reduce the lateral transport distance (e.g., ...). Figure 7 As shown, its structure consists of multiple spaced first sub-regions arranged sequentially along the width direction of the back metal grid 11. Moreover, in the case of such a sudden event, it is difficult to guarantee a short carrier transmission distance, and its carrier transmission distance becomes longer. Specifically, see Figure 8 As shown, even if the longitudinal anti-breakage grid design of the present invention, i.e. the interval region 141 extending in the vertical direction, experiences local failure, the charge carriers can still be converged through other back metal grids adjacent to it, and the lateral transport distance of the charge carriers does not increase. This structure makes the advantages of the longitudinal anti-breakage grid design of the present invention more obvious, and has a significant positive effect on ensuring that the battery has good short-circuit current, fill factor and conversion efficiency and other core indicators, and has outstanding risk resistance.

[0044] Based on the above research and findings, this invention proposes a partial disconnection design for the back metal grid, which not only does not reduce the core performance indicators of the battery, but also has the following advantages: 1) The reduction in printing area helps to reduce the amount of silver paste required for printing; 2) The reduction in printing area helps to reduce metal recombination in the battery and improve the open-circuit voltage of the battery; 3) The reduction in the obstruction of incident light by the metal grid lines on the back of the battery optimizes the utilization rate of light on the back of the battery. Combined with the special selective passivation battery structure of this invention, it further improves the bifacial utilization rate of the solar cell.

[0045] The solar cell intermediate and solar cell of the present invention will be further described below in conjunction with the preparation method.

[0046] In some embodiments, the method for preparing the solar cell of the present invention includes: 1) Take an N-type monocrystalline silicon wafer and perform wet cleaning to remove the damaged layer on the wafer surface, clean surface metal impurities and oil, and create a textured surface. At a reaction temperature of 70±10℃, use a 10% (v / v) sodium hydroxide aqueous solution to etch the damaged layer on the wafer surface caused by wire cutting. The etched thickness on both sides is approximately 10µm. Then, a random pyramidal surface texture is generated using a wet chemical process with an alkaline solution and texturing additives. Standard RCA wet cleaning is then performed, resulting in random pyramids with a height of approximately 0.5–2µm. This achieves a pyramidal textured surface structure on both sides of the N-type monocrystalline silicon wafer.

[0047] 2) A double-sided boron diffusion process is performed on the texturized silicon wafer to form surface emitters. The boron source used in the boron diffusion process is boron tribromide (BBr3) or boron trichloride (BCl3), and the peak diffusion temperature is 1000–1100℃. After the boron diffusion process, the sheet resistance of the boron emitter is measured to be 300Ω / sq–400Ω / sq using a four-probe testing method. That is, boron-doped emitters are formed on both the front and back surfaces of the N-type single-crystal silicon wafer.

[0048] 3) Wet polishing of the battery back surface. The BSG layer on the back and edges of the boron-doped silicon wafer is removed using a 3%–10% HF aqueous solution. Then, the back surface of the silicon wafer is polished using a wet additive + KOH / NaOH + water solution (ratio 1:5:90) at a reaction temperature of 60±10℃. This ensures that only the boron-doped emitter on the front side is retained on the N-type single-crystal silicon wafer.

[0049] 4) A tunneling oxide layer and an intrinsic amorphous silicon layer are grown on the back surface of the battery. Low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) are used to deposit an ultrathin tunneling oxide layer and an intrinsic amorphous silicon layer on the back surface of the silicon wafer under low-pressure conditions using oxygen and silane. The structural material of the ultrathin tunneling oxide layer is SiO2, the deposition reaction temperature is 580–630℃, and the thickness is selected to be 1.0–2.5 nm. The deposition reaction temperature of the intrinsic amorphous silicon is 580–650℃, and the thickness is selected to be 60–200 nm. 5) Phosphorus diffusion, forming a phosphorus-doped polycrystalline silicon structure. The phosphorus diffusion process is as follows: Under oxygen conditions, phosphorus oxychloride decomposes at high temperature (approximately 790°C) to generate phosphorus pentachloride and phosphorus pentoxide. The generated phosphorus pentoxide reacts with silicon at the diffusion temperature (approximately 875°C) to generate silicon dioxide and phosphorus atoms. The phosphorus atoms enter the intrinsic amorphous silicon layer, forming a phosphorus-doped polycrystalline silicon layer. Phosphorus silicate glass (PSG) is formed on the surface of the doped polycrystalline silicon layer. The sheet resistance of the phosphorus-doped polycrystalline silicon layer is 40~80 Ω / sq, and the phosphorus atom doping concentration is 4.0E+20~8.0E+20 cm⁻¹. -3 The thickness of PSG is 25~35 nm.

[0050] 6) Laser-assisted patterning is performed on the back PSG layer to remove the doped polysilicon in the non-metallized area on the back surface of the battery. (i.e., patterning is performed at the location corresponding to the first sub-region. The multiple first sub-regions of this invention are spaced apart, and the corresponding patterning areas are also spaced apart.) This removes the PSG protective layer on the surface of the doped polysilicon layer and completes the patterning. The wavelength of the laser used for patterning is a picosecond laser of 300–600 nm, preferably a 355 nm ultraviolet laser or a 532 nm green laser. The laser spot length is 100–800 µm, the width is 50–400 µm, the laser frequency is 100–1000 kHz, the laser scanning speed is 25–75 m / s, and the laser energy of a single spot is 40–150 µJ. In a single cell (corresponding to the cell region mentioned above) formed by the intersection of two adjacent metal main grid lines and two adjacent metal fine grid lines (or the extensions of two adjacent metal fine grid lines), the area of ​​laser-etched film accounts for 40% to 96% of the area of ​​the single cell. The pattern of laser-etched film can be a rectangle, trapezoid, triangle, or other shapes.

[0051] 7) Wet chemical etching to form a selective polysilicon layer. First, the silicon wafer is passed through a chain-machine HF aqueous solution to remove excess doped polysilicon layers on the front and edges. Then, the wafer undergoes an RCA process using a mixed solution of wet additives + KOH / NaOH + water (ratio 1:5:90) to etch away the doped polysilicon layer at the back trench area and the tunneling oxide layer on the back. The doped polysilicon layer in areas not laser-etched is protected by PSG and remains unetched in the solution. The reaction temperature is 60±10℃, the reaction time is 5~8 min, and the etching depth is 3~5 μm. Finally, the remaining PSG layer on the back of the wafer is completely removed using an HF aqueous solution.

[0052] 8) Deposition of passivation / antireflection film on the front and back surfaces of the battery. The passivation / antireflection film on the front and back surfaces adopts a stacked film design, which is a combination of two materials such as alumina, silicon dioxide, and silicon oxynitride. Preferably, an alumina + silicon nitride passivation / antireflection film stacked design is adopted, wherein the preferred thickness of alumina is 3-8 nm and the preferred thickness of silicon nitride is 60-100 nm.

[0053] 9) Metal electrode printing and sintering on the front and back surfaces. Metallized patterns are formed on the front and back surfaces. The metal grid lines can be made of silver paste, silver-aluminum paste, or other metal materials (aluminum, copper, titanium, nickel, etc.). The width of the fine metal grid lines on the front and back surfaces is 5–30 µm, the height is 2–15 µm, the spacing between adjacent fine metal grids is 0.4–1.2 mm, and the number is 150–400. The width of the main metal grid lines is 40–80 µm, the height is 1–10 µm, the spacing between adjacent main metal grids is 9–18 mm, and the number is 12–20. The back surface has local breaks in the fine metal grid lines. The position and length of the break between two adjacent fine metal grid lines can be the same or different. That is, the length of the fine grid lines leading from the main grids on both sides can be consistent or inconsistent, with a break width of 0.1 mm–2 mm, accounting for approximately 1%–20% of the length of a single cell's fine grid line. The metal grid lines can be prepared using the industry-standard screen printing method, which will not be detailed here. After the metal grid lines are formed, they are solidified by sintering or annealing. The sintering temperature is 650-800℃, and the annealing temperature is 200-450℃. Laser-assisted sintering process can be superimposed to enhance the contact between the metal grid lines and silicon and reduce the contact resistivity.

[0054] The above-mentioned solution will be further described below with reference to specific embodiments; it should be understood that these embodiments are used to illustrate the basic principles, main features and advantages of the present invention, and the present invention is not limited to the scope of the following embodiments; the implementation conditions used in the embodiments can be further adjusted according to specific requirements, and the implementation conditions not specified are usually the conditions in conventional experiments.

[0055] Unless otherwise specified in the following examples, all raw materials are commercially available or prepared by conventional methods in the art.

[0056] Example 1: This example provides a method for preparing a solar cell containing a solar cell intermediate and the solar cell made therefrom.

[0057] The aforementioned specific preparation method is adopted, wherein: Figure 1The structure shown has two rectangular sub-regions spaced 200 μm apart. The total area of ​​the two sub-regions accounts for 80% of the area of ​​the unit region. The two sides of the partially broken back metal grid are of equal length, with a spacing of 1.5 mm between the breaks and a corresponding back grid line length of 10 mm.

[0058] Example 2: This example provides a method for preparing a solar cell containing a solar cell intermediate and the solar cell made therefrom.

[0059] The aforementioned specific preparation method is adopted, wherein: Figure 2 The structure shown has a trapezoidal first sub-region, which consists of two regions spaced 200 μm apart. The total area of ​​the two first sub-regions accounts for 84% of the area of ​​the unit region. The two sides of the partially broken back metal grid have equal lengths, and the spacing between the breaks is 1.5 mm. The corresponding length of the back grid line is 10 mm.

[0060] Example 3: This example provides a method for preparing a solar cell containing a solar cell intermediate and the solar cell made therefrom.

[0061] The aforementioned specific preparation method is adopted, wherein: Figure 3 The structure shown has a rectangular shape for the first sub-region, with three sub-regions spaced 150 μm apart. The total area of ​​the three sub-regions accounts for 80% of the area of ​​the unit region. The lengths of the back metal grids on both sides of the partial break are equal, and the spacing between the partial breaks is 2.0 mm. The length of the corresponding back grid lines is 10 mm.

[0062] Example 4: This example provides a method for preparing a solar cell containing a solar cell intermediate and the solar cell made therefrom.

[0063] The aforementioned specific preparation method is adopted, wherein: Figure 4 The structure shown has a rectangular shape for the first sub-region, with three sub-regions spaced 150 μm apart. The total area of ​​the three sub-regions accounts for 80% of the area of ​​the unit region. The lengths of the back metal grids on both sides of the partial break are unequal, with a spacing of 1.5 mm between the breaks and a corresponding back grid line length of 10 mm.

[0064] Comparative Example 1: It adopts a traditional TOPCon solar cell structure, the structure of which can be found in [reference needed]. Figure 9 As shown, the tunnel oxide layer and polysilicon layer were not removed within the cell region 1 formed by the back metal fine gate 11 and the back metal main gate 12.

[0065] Comparative Example 2: It adopts a conventional selective TOPCon solar cell structure, the structure of which is shown in [reference needed]. Figure 10 As shown, the unit region 1 formed by the back metal fine gate 11 and the back metal main gate 12 has undergone continuous removal of the tunnel oxide layer and polysilicon layer, that is, a continuous open film region 15 is provided.

[0066] Comparative Example 3: Employing a conventional selective TOPCon solar cell structure, the unit region 1 formed by the back metal grid 11 and the back metal main grid 12 undergoes continuous removal of the tunneling oxide layer and polycrystalline silicon layer, i.e., a continuous open film region 15 is provided. Furthermore, the design of the partially disconnected back metal grid region 111 of this invention is adopted, the structure of which is described in [reference needed]. Figure 11 As shown.

[0067] Comparative Example 4: The selective TOPCon solar cell structure described in CN119486360 B is adopted. Within unit region 1, two first sub-regions 13 and one second sub-region are spaced apart along the vertical direction (i.e., along the width direction of the back metal grid). A spacing region 141 extending along the horizontal direction (i.e., the length direction of the back metal grid) is formed between the two first sub-regions 13. The design incorporates a partially broken back metal grid region 111, as described in the present invention. (See attached diagram). Figure 12 As shown.

[0068] Performance testing: The batteries obtained in Examples 1-4 and Comparative Examples 1-4 were subjected to the following performance tests: The test method was to use an IV tester to test the photoelectric conversion efficiency and related electrical performance parameters of the batteries under standard illumination power under simulated solar light. The specific test results are shown in Table 1 (Eta: conversion efficiency, Voc: open-circuit voltage, Jsc: short-circuit current density, FF: fill factor).

[0069] Table 1 As shown in Table 1, the conversion efficiency of the battery of the present invention has been significantly improved. Compared with Comparative Example 1, the conversion efficiency of Example 1 has increased by 0.17%. For crystalline silicon solar cells, a change of 0.1% is usually a huge improvement. It can be seen that the improved battery structure of the present invention can optimize short-circuit current density, open-circuit voltage and fill factor, and promotes a significant improvement in battery efficiency through synergistic effect. Moreover, it can reduce the amount of paste used in the back metal grid electrode, which greatly reduces the cost.

[0070] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

[0071] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein.

Claims

1. A solar cell intermediate, the solar cell intermediate comprising a silicon wafer having a back surface and a plurality of back metal grids and a plurality of back metal main grids respectively disposed on the back surface, characterized in that: The back surface includes multiple unit regions, and each unit region includes n first sub-regions and second sub-regions, where n is greater than or equal to 2. The n first sub-regions are arranged sequentially at intervals along the left-right direction, and the intervals extend along the up-down direction; the second sub-region surrounds the n first sub-regions, and the intervals are part of the second sub-regions; In the first sub-region, a silicon wafer and a first back passivation layer are sequentially disposed along a direction perpendicular to the first sub-region; in the second sub-region, a silicon wafer, a tunneling oxide layer, a polysilicon layer, and a second back passivation layer are sequentially disposed along a direction perpendicular to the second sub-region. The back metal fine gate and the back metal main gate are both located in the second sub-region. The back metal fine gate passes through the second back passivation layer and is connected to the polysilicon layer. The back metal main gate is connected to the back metal fine gate. At least one of the back metal grids corresponding to each of the unit regions is partially broken, and the length of the partially broken part is less than 20% of the length of the corresponding back metal grid.

2. The solar cell intermediate according to claim 1, characterized in that: In the n first sub-regions, the distance between any two adjacent first sub-regions is 50-200 μm.

3. The solar cell intermediate according to claim 1, characterized in that: The total area of ​​the n first sub-regions accounts for 40%-96% of the area of ​​the unit region.

4. The solar cell intermediate according to claim 1, characterized in that: The length of the partial break is 0.1-2 mm.

5. The solar cell intermediate according to claim 1, characterized in that: Each of the aforementioned back metal grids has multiple local breaks.

6. The solar cell intermediate according to claim 5, characterized in that: The total length of the plurality of said partial breaks accounts for 1%-20% of the length of the corresponding back metal grid; and / or, the lengths of the respective partial breaks on each of the back metal grids remain the same or different.

7. The solar cell intermediate according to claim 1, characterized in that: The position and length of the partial breaks on any two of the back metal grids remain the same or different.

8. The solar cell intermediate according to claim 1, characterized in that: The n first sub-regions are arranged sequentially at intervals along the length direction of the back metal grid; and / or, the interval regions extend along the width direction of the back metal grid.

9. The solar cell intermediate according to claim 1, characterized in that: The spacing regions of each of the cell regions located between two adjacent back metal main gates are distributed on the same extension line or on multiple parallel extension lines; and / or, the polysilicon layer in the second sub-region forms a multidimensional carrier transport path.

10. The solar cell intermediate according to claim 1, characterized in that: A continuous carrier transport path is formed between any two points in the polysilicon layer corresponding to the second sub-region; and / or, the polysilicon layer corresponding to the interval region and the polysilicon layer corresponding to the partial disconnection are directly connected.

11. The solar cell intermediate according to claim 1, characterized in that: The polycrystalline silicon in the polycrystalline silicon layer is phosphorus-doped polycrystalline silicon; and / or, the first back passivation layer and the second back passivation layer are integrally formed; and / or, the first back passivation layer and the second back passivation layer independently include a passivation film and a selective antireflection film.

12. A method for preparing a solar cell intermediate according to any one of claims 1-11, characterized in that, The preparation method includes: Provide a silicon wafer; A tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are prepared on the back surface of the silicon wafer; Remove the tunneling oxide layer and the phosphorus-doped polysilicon layer within the n first sub-regions; A passivation layer is formed over the entire area of ​​the back surface, and then a back metal fine gate and a back metal main gate are fabricated, with at least one of them being partially disconnected during the fabrication of the back metal fine gate.

13. A solar cell, characterized in that, The solar cell comprises the solar cell intermediate as described in any one of claims 1-11.

14. A method for preparing a solar cell, characterized in that, The method for preparing the solar cell includes: An N-type silicon wafer is provided, and the N-type silicon wafer is subjected to boron diffusion treatment to form emitters on the front and back surfaces of the N-type silicon wafer, respectively. The emitter on the back surface of the N-type silicon wafer is removed, and a tunneling oxide layer and a polycrystalline silicon layer are sequentially prepared on the back surface. Then, phosphorus diffusion is performed to form a phosphorus-doped polycrystalline silicon layer, and a phosphorus-silicon glass layer is formed on the phosphorus-doped polycrystalline silicon layer. The back surface includes multiple unit regions, each of which includes n first sub-regions and second sub-regions, where n is greater than or equal to 2; the n first sub-regions are arranged sequentially at intervals along the left-right direction, and the intervals extend along the up-down direction; the second sub-regions surround the n first sub-regions, and the intervals are part of the second sub-regions; The patterned film is created on the phosphosilicate glass layer using laser film-forming, and the phosphosilicate glass layer in each of the first sub-regions is removed after film-forming. Wet chemical etching is performed to remove the tunneling oxide layer and phosphorus-doped polysilicon layer corresponding to each of the first sub-regions from the open film region, and then the phosphorus-silicon glass layer in the second sub-region is removed. Passivation layers are deposited on the front and back surfaces, and metal fine gates and metal main gates are fabricated separately. When fabricating the back metal fine gate, at least one of them is partially broken, and the length of the partially broken part is controlled to be less than 20% of the length of the corresponding back metal fine gate.

15. The method for preparing a solar cell according to claim 14, characterized in that, The sheet resistance of the phosphorus-doped polycrystalline silicon layer is 40~80 Ω / sq, and the phosphorus atom doping concentration is 4.0×10⁻⁶. 20 ~8.0×10 20 cm -3 .

16. A solar cell manufactured by the method of preparing a solar cell according to claim 14 or 15, characterized in that, In the first sub-region, a silicon wafer and a first back passivation layer are sequentially disposed along a direction perpendicular to the first sub-region; in the second sub-region, a silicon wafer, a tunneling oxide layer, a phosphorus-doped polysilicon layer, and a second back passivation layer are sequentially disposed along a direction perpendicular to the second sub-region. The back metal fine gate and the back metal main gate are both located in the second sub-region. The back metal fine gate passes through the second back passivation layer and is connected to the polysilicon layer. The back metal main gate is connected to the back metal fine gate. At least one of the back metal grids corresponding to each of the unit regions is partially disconnected.

17. A solar photovoltaic power generation system, characterized in that, The solar photovoltaic power generation system includes the solar cell as described in claim 13 or 16.

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