Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided. The display device includes a plurality of lower insulating layers on a substrate, a light emitting element on the plurality of lower insulating layers, an encapsulation layer on the light emitting element and including a plurality of insulating encapsulation layers, a base insulating layer on the encapsulation layer, a conductive pattern on the base insulating layer, and an upper insulating layer on the conductive pattern. The upper insulating layer can be spaced apart from an edge of the substrate. At least one insulating layer among the plurality of lower insulating layers, the encapsulation layer, and the base insulating layer extends to the edge of the substrate. A first surface roughness of a first upper surface of the at least one insulating layer not covered by the upper insulating layer can be greater than a second surface roughness of a second upper surface of the at least one insulating layer covered by the upper insulating layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0177858, filed on December 3, 2024, and Korean Patent Application No. 10-2025-0005569, filed on January 14, 2025, the entire contents of each of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments of this disclosure relate to a display device and an electronic device including the display device. Background Technology

[0004] Electronic devices that typically provide images to users, such as smartphones, digital cameras, laptops, navigation systems, and smart TVs, may include display devices for displaying images. The display device generates images and provides the generated images to the user via a screen. The display device typically includes a display panel configured to display images and input sensing units disposed on the display panel and configured to sense external input.

[0005] However, display devices can be vulnerable to external impacts. For example, when a display device is dropped onto the floor, the impact may be applied to the sides of the device, causing damage to those sides. For instance, the sides of some components of the input sensing unit may delaminate against each other. Therefore, it is necessary and / or desirable to develop technologies to prevent or reduce damage to the sides of display devices. Summary of the Invention

[0006] One or more aspects of embodiments of this disclosure relate to display devices configured to prevent or reduce damage to the sides of a display device and electronic devices including display devices. Additional aspects will be set forth in part in the description which follows and will be apparent in part from the description, or may be learned by practice of the embodiments presented.

[0007] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a plurality of lower insulating layers disposed on (e.g., on) the substrate; a light-emitting element disposed on (e.g., on) the plurality of lower insulating layers; an encapsulation layer disposed on (e.g., on) the light-emitting element and including a plurality of insulating encapsulation layers; a base insulating layer disposed on (e.g., on) the encapsulation layer; a conductive pattern disposed on (e.g., on) the base insulating layer; and an upper insulating layer disposed on (e.g., on) the conductive pattern, wherein the upper insulating layer may be spaced apart from and / or separated from the edge of the substrate (e.g., spaced apart or separated), at least one insulating layer selected from the plurality of lower insulating layers, the plurality of insulating encapsulation layers and the base insulating layer may extend to the edge of the substrate, and a first surface roughness of a first upper surface of the at least one insulating layer exposed upward by the upper insulating layer but not covered by the upper insulating layer may be greater than a second surface roughness of a second upper surface of the at least one insulating layer covered by the upper insulating layer.

[0008] In one or more embodiments of this disclosure, the display device includes: a substrate; a plurality of lower insulating layers disposed on (e.g., on) the substrate; a light-emitting element disposed on (e.g., on) the plurality of lower insulating layers; an encapsulation layer disposed on (e.g., on) the light-emitting element and including a plurality of insulating encapsulation layers; a base insulating layer disposed on (e.g., on) the encapsulation layer; a conductive pattern disposed on (e.g., on) the base insulating layer; and an upper insulating layer disposed on (e.g., on) the conductive pattern, wherein: the upper insulating layer, the plurality of lower insulating layers, the plurality of insulating encapsulation layers, and the base insulating layer may be spaced apart and / or separated from the edges of the substrate (e.g., spaced apart or separated); the edges of the upper insulating layer, the plurality of lower insulating layers, the plurality of insulating encapsulation layers, and the base insulating layer may overlap each other; and a first surface roughness of a first upper surface of the substrate exposed upward by the upper insulating layer but not covered by the upper insulating layer may be greater than a second surface roughness of a second upper surface of the substrate covered by the upper insulating layer.

[0009] In one or more embodiments of this disclosure, an electronic device includes: a display device for providing an image to a user; and a processor for processing image signals and providing the processed image signals to the display device, wherein the display device includes: a substrate; a plurality of lower insulating layers disposed on (e.g., on) the substrate; a light-emitting element disposed on (e.g., on) the plurality of lower insulating layers; an encapsulation layer disposed on (e.g., on) the light-emitting element and including a plurality of insulating encapsulation layers; a base insulating layer disposed on (e.g., on) the encapsulation layer; a conductive pattern disposed on (e.g., on) the base insulating layer; and an upper insulating layer disposed on (e.g., on) the conductive pattern, wherein: the upper insulating layer may be spaced apart from and / or separated from the edge of the substrate (e.g., spaced apart or separated); at least one insulating layer selected from the plurality of lower insulating layers, the plurality of insulating encapsulation layers, and the base insulating layer may extend to the edge of the substrate; and a first surface roughness of a first upper surface of the at least one insulating layer exposed upward by the upper insulating layer but not covered by the upper insulating layer may be greater than a second surface roughness of a second upper surface of the at least one insulating layer covered by the upper insulating layer. Attached Figure Description

[0010] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this disclosure. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. The above and / or other aspects of this disclosure will become apparent and understandable from the following description of the embodiments taken in conjunction with the accompanying drawings. In the drawings:

[0011] Figure 1 This is a block diagram of an electronic device according to one or more embodiments of the present disclosure;

[0012] Figure 2 A schematic diagram of an electronic device according to one or more suitable embodiments of the present disclosure is shown;

[0013] Figure 3 This is a perspective view of an electronic device according to one or more embodiments of the present disclosure;

[0014] Figure 4 It is based on one or more embodiments of this disclosure Figure 3 An exploded perspective view of the electronic device shown in the image;

[0015] Figure 5 One or more embodiments according to this disclosure are shown. Figure 4 The cross-section of the display device shown in the figure;

[0016] Figure 6 One or more embodiments according to this disclosure are shown. Figure 5 The image shows a cross-section of the display panel;

[0017] Figure 7 It is based on one or more embodiments of this disclosure Figure 5 The plan view of the display device shown in the figure;

[0018] Figure 8 One or more embodiments of the present disclosure are shown. Figure 7 The cross-section of the display panel and input sensing unit corresponding to any pixel shown in the figure;

[0019] Figure 9 It is based on one or more embodiments of this disclosure Figure 5 A plan view of the input sensing unit is shown in the figure;

[0020] Figure 10 It is based on one or more embodiments of this disclosure Figure 9 An enlarged view of two adjacent first sensing units and two adjacent second sensing units is shown in the figure;

[0021] Figure 11 It is according to one or more embodiments of this disclosure along Figure 10 The cross-sectional view taken by line A-A' is shown in the figure;

[0022] Figure 12 It is according to one or more embodiments of this disclosure along Figure 7 The cross-sectional view taken by line I-I' is shown in the figure;

[0023] Figure 13 It is according to one or more embodiments of this disclosure along Figure 7 The cross-sectional view taken by line II-II' shown in the figure;

[0024] Figure 14 The cross-sectional configuration of the comparison display device is shown;

[0025] Figure 15 The illustration schematically depicts one or more embodiments according to this disclosure. Figure 12 The cross-sectional configuration of the display device is shown in the figure;

[0026] Figure 16 It shows Figure 14 The comparison display device shown herein and one or more embodiments according to this disclosure. Figure 15 The external impact test results of the display device are shown in the figure;

[0027] Figure 17 The illustration shows one or more embodiments according to this disclosure, including... Figure 7 The planar configuration of the mother panel of the display panel is shown in the figure;

[0028] Figure 18It is based on one or more embodiments of this disclosure Figure 17 An enlarged view of any of the unit panels shown;

[0029] Figures 19A to 19D It is along Figure 18 The cross-sectional view taken by line III-III' is shown in the figure, and a method for manufacturing a display device according to one or more embodiments of the present disclosure is explained.

[0030] Figure 20 Test results regarding the adhesive strength between the third insulating encapsulation layer and the cover layer according to one or more embodiments of the present disclosure are shown;

[0031] Figures 21 to 25 A portion of an insulating layer, each having a first upper surface formed thereon, is shown according to one or more embodiments of the present disclosure;

[0032] Figure 26 The configuration on a unit panel according to one or more embodiments of the present disclosure is shown;

[0033] Figure 27A It is according to one or more embodiments of this disclosure along Figure 26 The cross-sectional view taken by line IV-IV' is shown in the figure;

[0034] Figure 27B One or more embodiments of the present disclosure are shown by means of... Figure 26 The unit panel is formed by cutting along the cutting lines shown in the figure;

[0035] Figure 28 The configuration on a unit panel according to one or more embodiments of the present disclosure is shown;

[0036] Figure 29A It is according to one or more embodiments of this disclosure along Figure 28 The cross-sectional view taken by line V-V' is shown in the figure;

[0037] Figure 29B One or more embodiments of the present disclosure are shown by means of... Figure 28 The unit panel is formed by cutting along the cutting lines shown in the figure; and

[0038] Figure 30 The configuration on a unit panel according to one or more embodiments of the present disclosure is shown. Detailed Implementation

[0039] The embodiments of this disclosure can be modified and practiced in many alternative forms, and therefore exemplary embodiments will be illustrated in the accompanying drawings and described in more detail in the specification. However, it should be understood that this disclosure is not intended to be limited to the specific forms disclosed, but rather to cover all modifications, equivalents, and substitutions falling within the spirit and scope of this disclosure.

[0040] In this disclosure, it will be understood that if an element (or region, layer, and / or portion, etc.) is referred to as being "on" another element, "connected to," or "attached to" another element (e.g., when an element (or region, layer, and / or portion, etc.) is referred to as being "on" another element, "connected to," or "attached to" another element), then the element may be directly on, directly connected to, or attached to the other element, or one or more intervening elements may exist between them. Conversely, "directly on" may mean that there is no additional intervening element or layer between the element or layer and the other element or layer. Additionally, if a layer, membrane, region, and / or plate, etc., is referred to as being "below" or "under" another component (e.g., when a layer, membrane, region, and / or plate, etc., is referred to as being "below" or "under" another component), then the layer, membrane, region, and / or plate, etc., may be "directly below" the other component, or one or more intervening layers may exist between them. Furthermore, if an element is referred to as being arranged "on" another element (e.g., when an element is referred to as being arranged "on" another element), then that element may be arranged below that other element.

[0041] Throughout this disclosure, the same reference numerals refer to the same elements, and for the sake of brevity, repetitive descriptions may be omitted. Additionally, in the drawings, the thickness, scale, and dimensions of elements may be exaggerated for the sake of effective description of the technical content. As used herein, the terms "and / or" or "or" can include any and all combinations that the associated configuration may define.

[0042] Although the terms “first” and / or “second”, etc., may be used herein to describe one or more suitable components, such components should not be limited by these terms. These terms are used only to distinguish one component, assembly, region, layer, or portion from another component, assembly, region, layer, or portion. For example, a first component, first assembly, first region, first layer, or first portion may be referred to as a second component, second assembly, second region, second layer, or second portion, and similarly, a second component, second assembly, second region, second layer, or second portion may also be referred to as a first component, first assembly, first region, first layer, or first portion, without departing from the scope and teachings of this disclosure. Singular expressions include plural expressions unless the context clearly indicates otherwise. For example, the singular forms “a” and “the (described)” are intended to also include the plural forms unless the context clearly indicates otherwise. Furthermore, when describing embodiments of this disclosure, the use of “may” means “one or more embodiments of this disclosure.”

[0043] Additionally, for ease of description, terms such as "below," "under," "above," and / or "upper" are used herein to describe the relationship between one element and another(s) as shown in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0044] It will be understood that, if used in this disclosure (e.g., as used in this disclosure), the terms “comprising” and / or “including” and / or “having” indicate the presence of the stated features, quantities, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, and / or groups thereof. Furthermore, the terms “comprising,” “including,” “having,” or other similar terms include or support the terms “consisting of” and “substantially consisting of”, indicating the presence of the stated features, quantities, steps, operations, components, and / or components, while other features, quantities, steps, operations, components, components, and / or groups thereof are absent or substantially absent.

[0045] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having meanings consistent with their meanings in the context of the relevant art, and unless expressly defined herein, these terms shall not be interpreted in an idealized or overly formal sense.

[0046] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0047] Figure 1 This is a block diagram of an electronic device according to one or more embodiments of the present disclosure.

[0048] refer to Figure 1 An electronic device ED according to one or more embodiments of the present disclosure may include a display device DD for providing images to a user, and may further include modules or devices with additional functions in addition to the display device DD. An electronic device ED according to one or more embodiments of the present disclosure may include a display device DD, a processor PRS, a memory MEM, and a power module PSM, and the display device DD may include a display module DM.

[0049] The processor PRS may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. The processor PRS can process image signals and provide the processed image signals to the display device DD, and the display device DD can generate an image corresponding to the processed image signals.

[0050] In one or more embodiments of this disclosure, from a functional or structural perspective, the processor PRS can be provided by being divided into two or more parts. For example, in one or more embodiments, the processor PRS may include a main processor in the form of a first driver chip containing a central processing unit and an auxiliary processor in the form of a second driver chip containing a controller configured to receive image signals from the main processor and process the image signals to match the interface specifications of the display module DM.

[0051] The memory MEM can store the data information required for the operation of the processor PRS or the display module DM. When the processor PRS executes the application program stored in the memory MEM, image data signals and / or input control signals can be transmitted to the display module DM, and the display module DM can process the received signals and output image information through the display screen.

[0052] The power supply module (PSM) may include a power supply module such as a power adapter and / or battery device, and a power conversion module configured to convert the power supplied by the power supply module to generate the power required for the operation of the electronic device (ED). The power supply module (PSM) can supply power to the display module (DM) and the processor (PRS).

[0053] According to the embodiments of this disclosure, at least one of the components of the electronic device ED (e.g., at least one selected from the components of the electronic device ED) may be included in the display device DD. In one or more embodiments, some modules of functionally independent modules included in a module may be included in the display device DD, while other modules may be provided independently of the display device DD. For example, in one or more embodiments, the display device DD may include a display module DM, while the processor PRS, memory MEM, and power supply module PSM may be provided as other devices within the electronic device ED independent of the display device DD.

[0054] Figure 2 A schematic diagram of an electronic device according to one or more suitable embodiments of the present disclosure is shown.

[0055] refer to Figure 2 The display device DD according to one or more embodiments of the present disclosure can be applied to one or more suitable electronic devices. For example, one or more suitable electronic devices to which the display device DD according to one or more embodiments of the present disclosure is applied may include electronic devices for displaying images, such as a smartphone 10_1a, a tablet PC 10_1b, a laptop computer 10_1c, a TV 10_1d, or a desktop monitor 10_1e.

[0056] Additionally, one or more suitable electronic devices for the display device DD according to one or more embodiments of the present disclosure may include wearable electronic devices such as smart glasses 10_2a, head-mounted displays 10_2b, or smartwatches 10_2c. Furthermore, one or more suitable electronic devices for the display device DD according to one or more embodiments of the present disclosure may include vehicle electronics 10_3 such as a car dashboard, center console, central information display (CID) arranged on the dashboard, or rearview mirror display.

[0057] Figure 3 This is a perspective view of an electronic device according to one or more embodiments of the present disclosure.

[0058] refer to Figure 3 An electronic device ED according to one or more embodiments of the present disclosure may have a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. In one or more embodiments, the corners of the electronic device ED may have an arcuate shape. The shape of the electronic device ED may be defined as a quadrilateral shape with arcuate corners. For example, Figure 3 The electronic device ED shown in the figure can be Figure 2 The smartphone 10_1a shown in the figure.

[0059] In the following text, the direction substantially orthogonal (e.g., perpendicular) to the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3. Furthermore, in this disclosure, "when viewed in a plane" or "in a plan view" is defined as the state viewed from the third direction DR3.

[0060] The upper surface of the electronic device ED can be defined as a display surface DS, and has a plane defined by a first direction DR1 and a second direction DR2. An image IM generated by the electronic device ED can be provided to the user through the display surface DS. The electronic device ED can sense the touch of the user's hand US_F.

[0061] The display surface DS may include a display area DA and a non-display area NDA surrounding (e.g., around) the display area DA. The display area DA may display an image, and the non-display area NDA may not display an image. The non-display area NDA may surround (e.g., around) the display area DA and may define an edge of the electronic device ED that can be printed in a set or predetermined color.

[0062] The electronic device ED may include multiple sensors SN and at least one camera CM. The sensor SNs and camera CM may be adjacent to the edge of the electronic device ED. In one or more embodiments, the sensor SNs and camera CM may be arranged in a display area DA adjacent to a non-display area NDA. For example, in one or more embodiments, the sensor SNs may be proximity sensors, but the type (variety) of the sensor SNs is not limited thereto. The camera CM may capture external images.

[0063] Figure 4 It is based on one or more embodiments of this disclosure Figure 3 An exploded perspective view of the electronic device shown in the image.

[0064] refer to Figure 4 Electronic devices (EDs) may include display devices (DDs), cameras (CMs), sensors (SNs), electronic modules (EMs), power modules (PSMs), and housings (CASs).

[0065] The display device DD may have a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. The display device DD may have a quadrilateral shape with rounded corners to correspond to the shape of the electronic device ED.

[0066] The display device DD may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image, and the non-display area NDA may not display an image. The display area DA and the non-display area NDA of the display device DD may be respectively connected to... Figure 3 The electronic device ED shown in the figure corresponds to the display area DA and the non-display area NDA.

[0067] The display device DD may include a display module DM and a window WIN disposed on the display module DM. The display module DM can generate images. The window WIN can protect the display module DM from external scratches and impacts. The image generated in the display module DM can be transmitted through the window WIN and can be provided to the user.

[0068] Each of the display module DM and the window WIN may include a display area DA for displaying images and a non-display area NDA surrounding the display area DA that does not display images. The display area DA and the non-display area NDA of each of the display module DM and the window WIN may correspond respectively to the display area DA and the non-display area NDA of the display device DD.

[0069] The first and second hole regions can be defined in the display device DD. Although not shown, a hole can be defined in each of the first and second hole regions. The hole can be defined in the display module DM. The camera CM can be arranged in the hole defined in the first hole region, and the sensor SN can be arranged in the hole defined in the second hole region.

[0070] The electronic module EM and the power supply module PSM can be arranged below the display device DD. In one or more embodiments, the electronic module EM and the power supply module PSM can be connected to each other via separate flexible circuit boards. The electronic module EM can control the operation of the display device DD. The electronic module EM may include the aforementioned processor PRS. The power supply module PSM can supply power to the electronic module EM and the display module DM.

[0071] The housing CAS can accommodate the display device DD, camera CM, sensor SN, electronic module EM, and power module PSM. The housing CAS can protect the display device DD, camera CM, sensor SN, electronic module EM, and power module PSM. The electronic module EM and power module PSM can be respectively arranged in the recessed portion RES defined in the bottom portion BTP of the housing CAS.

[0072] Figure 5 One or more embodiments according to this disclosure are shown. Figure 4 The cross-section of the display device is shown in the figure.

[0073] As an example, Figure 5 A cross-section of the display device DD as viewed from the first direction DR1 is shown.

[0074] refer to Figure 5The display device DD may include a display panel DP, an input sensing unit ISP, an anti-reflective layer RPL, a window WIN, a panel protective film PPF, and a first adhesive layer AL1, a second adhesive layer AL2, and a third adhesive layer AL3. The display module DM may include a display panel DP, an input sensing unit ISP, an anti-reflective layer RPL, and a panel protective film PPF.

[0075] The display panel DP according to one or more embodiments of this disclosure may be a light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include organic light-emitting materials. The light-emitting layer of an inorganic light-emitting display panel may include quantum dots and / or quantum rods, etc. Hereinafter, by way of example, the display panel DP will be described as an organic light-emitting display panel.

[0076] The input sensing unit ISP can be disposed on the display panel DP. In one or more embodiments, the input sensing unit ISP may include a plurality of sensing units for sensing external input by capacitive methods. When manufacturing the display device DD, the input sensing unit ISP may be directly manufactured on the display panel DP. However, it is not limited thereto; the input sensing unit ISP may be manufactured as a panel separate from the display panel DP and then attached to the display panel DP by an adhesive layer.

[0077] An anti-reflective layer (RPL) can be disposed on the input sensing unit (ISP). The RPL can be defined as an anti-reflective film against external light. The RPL reduces the reflectivity of external light incident from above the display device (DD) toward the display panel (DP). Due to the RPL, external light can be invisible to the user.

[0078] When external light traveling toward the display panel DP is reflected back to the user by the display panel DP like a mirror, the user can visually perceive the external light. To prevent or reduce this phenomenon, in one or more embodiments, the anti-reflective layer RPL may include multiple color filters that display the same color as the light emitted from the pixels of the display panel DP.

[0079] A color filter can filter external light to the same color as the light emitted by a pixel. As a result, the external light may be invisible to the user. However, it is not limited to this; the anti-reflective layer RPL may include a retarder and / or a polarizer to reduce the reflectivity of external light.

[0080] The window (WIN) can be placed on the anti-reflective layer (RPL). The window (WIN) can protect the display panel (DP), input sensing unit (ISP), and anti-reflective layer (RPL) from external scratches and impacts.

[0081] A panel protective film (PPF) can be placed beneath the display panel (DP). The PPF protects the lower portion of the display panel (DP). The PPF can comprise flexible plastic materials such as polyethylene terephthalate (PET).

[0082] A first adhesive layer AL1 is disposed between the display panel DP and the panel protective film PPF, and the display panel DP and the panel protective film PPF can be bonded to each other through the first adhesive layer AL1. A second adhesive layer AL2 is disposed between the input sensing unit ISP and the anti-reflective layer RPL, and the input sensing unit ISP and the anti-reflective layer RPL can be bonded to each other through the second adhesive layer AL2. A third adhesive layer AL3 is disposed between the window WIN and the anti-reflective layer RPL, and the window WIN and the anti-reflective layer RPL can be bonded to each other through the third adhesive layer AL3.

[0083] Figure 6 One or more embodiments according to this disclosure are shown. Figure 5 The image shows a cross-section of the display panel.

[0084] As an example, Figure 6 A cross-section of the display panel DP as viewed from the first direction DR1 is shown.

[0085] refer to Figure 6 The display panel DP may include a substrate SUB, a circuit element layer DP-CL disposed on the substrate SUB, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and an encapsulation layer TFE disposed on the display element layer DP-OLED.

[0086] The substrate SUB may include a display area DA and a non-display area NDA surrounding (e.g., around) the display area DA. The substrate SUB may include a flexible plastic (e.g., polymer) material such as polyimide (PI). The display element layer DP-OLED may be disposed on the display area DA.

[0087] Multiple pixels can be arranged in the circuit element layer DP-CL and the display element layer DP-OLED. Each pixel may include a transistor arranged in the circuit element layer DP-CL and a light-emitting element arranged in the display element layer DP-OLED and connected to the transistor.

[0088] The encapsulation layer TFE can be placed on the circuit element layer DP-CL to cover the display element layer DP-OLED. The encapsulation layer TFE can protect the pixels from moisture, oxygen and external foreign matter.

[0089] Figure 7 It is based on one or more embodiments of this disclosure Figure 5The diagram shows a plan view of the display device.

[0090] refer to Figure 7 The display device DD may include a display panel DP, a scan driver SDV, a data driver DDV, a light-emitting driver EDV, and a plurality of first pads PD1.

[0091] The display panel DP may have a quadrilateral shape containing a long side extending in a first direction DR1 and a short side extending in a second direction DR2. The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA.

[0092] The display panel DP may include multiple pixels PX, multiple scan lines SL1 to SLm, multiple data lines DL1 to DLn, multiple light emission lines EL1 to ELm, a first control line CSL1 and a second control line CSL2, a power line PL, and multiple connection lines CNL, where m and n are each natural numbers greater than zero.

[0093] Pixels PX can be arranged in the display area DA. Scan driver SDV and light-emitting driver EDV can be separately arranged in a non-display area NDA adjacent to one of the long sides of the display panel DP. Data driver DDV can be arranged in any of the non-display areas NDA adjacent to the short sides of the display panel DP. When viewed in a plane (e.g., in a plan view), in one or more embodiments, the data driver DDV can be adjacent to the lower end of the display panel DP.

[0094] Scan lines SL1 to SLm can extend in the second direction DR2 to connect to the corresponding pixel PX and scan driver SDV. Data lines DL1 to DLn can extend in the first direction DR1 to connect to the corresponding pixel PX and data driver DDV. Light emission lines EL1 to ELm can extend in the second direction DR2 to connect to the corresponding pixel PX and light emission driver EDV.

[0095] The power line PL can extend along the first direction DR1 to be disposed in the non-display area NDA. In one or more embodiments, the power line PL can be disposed between the display area DA and the light-emitting driver EDV, but embodiments of this disclosure are not limited thereto, and the power line PL can be disposed between the display area DA and the scan driver SDV.

[0096] The connecting line CNL can extend along the second direction DR2 and can be arranged along the first direction DR1 to connect to the power line PL and the pixel PX. A driving voltage can be applied to the pixel PX through the power line PL and the connecting line CNL connected to each other.

[0097] The first control line CSL1 can be connected to the scan driver SDV and can extend towards the bottom of the display panel DP. The second control line CSL2 can be connected to the light-emitting driver EDV and can also extend towards the bottom of the display panel DP. The data driver DDV can be arranged between the first control line CSL1 and the second control line CSL2.

[0098] The first pad PD1 can be located in the non-display area NDA adjacent to the lower end of the display panel DP, and can be closer to the lower end of the display panel DP than the data driver DDV. The data driver DDV, power line PL, first control line CSL1, and second control line CSL2 can be connected to the first pad PD1. Data lines DL1 to DLn can be connected to the data driver DDV, and the data driver DDV can be connected to the first pad PD1 corresponding to the data lines DL1 to DLn.

[0099] In one or more embodiments, the display device DD may further include a timing controller for controlling the operation of the scan driver SDV, the data driver DDV, and the light-emitting driver EDV. The timing controller may be mounted on a printed circuit board and may be connected to the first pad PD1 via the printed circuit board.

[0100] The scan driver SDV can generate multiple scan signals, and these scan signals can be applied to pixel PX through scan lines SL1 to SLm. The data driver DDV can generate multiple data voltages, and these data voltages can be applied to pixel PX through data lines DL1 to DLn. The light emission driver EDV can generate multiple light emission signals, and these light emission signals can be applied to pixel PX through light emission lines EL1 to ELm.

[0101] A pixel (PX) can receive a data voltage in response to a scan signal. A pixel (PX) can display an image by emitting light with a brightness corresponding to the data voltage in response to a light emission signal.

[0102] The display device DD may include an upper insulating layer U-INS and a dummy insulating layer D-INS disposed above (e.g., above) the display panel DP. For example, the upper insulating layer U-INS and the dummy insulating layer D-INS are located in... Figure 7 It is shown in gray. In one or more embodiments, the insulating tape may be arranged on the data drive DDV.

[0103] When viewed in a plane (e.g., in a plan view), the edges of the display panel DP may include a first side S1, a second side S2, a third side S3, and a fourth side S4. The first side S1 and the second side S2 may define the shorter sides of the quadrilateral shape of the display panel DP and may extend in a second direction DR2. The third side S3 and the fourth side S4 may define the longer sides of the quadrilateral shape of the display panel DP and may extend in a first direction DR1.

[0104] The first side S1 can be defined as the top edge of the display panel DP, and the second side S2 can be defined as the bottom edge of the display panel DP. The third side S3 can be defined as the left edge of the display panel DP, and the fourth side S4 can be defined as the right edge of the display panel DP.

[0105] When viewed in a plane (e.g., in a plan view), the upper insulating layer U-INS may have a quadrilateral shape containing a long side extending in the first direction DR1 and a short side extending in the second direction DR2. The upper insulating layer U-INS may have an area larger than the area of ​​the display area DA. The upper insulating layer U-INS may be disposed inward beyond the edge of the display panel DP. The edge of the upper insulating layer U-INS may be spaced apart from and / or separated from the edge of the display panel DP (e.g., spaced apart or separated), and may be disposed inward beyond the edge of the display panel DP.

[0106] The edges of the upper insulating layer U-INS may include a first side S1', a second side S2', a third side S3', and a fourth side S4'. The first side S1' and the second side S2' may define the short sides of the quadrilateral shape of the upper insulating layer U-INS and may extend in the second direction DR2. The third side S3' and the fourth side S4' may define the long sides of the quadrilateral shape of the upper insulating layer U-INS and may extend in the first direction DR1.

[0107] The first side S1' can be defined as the upper side of the upper insulating layer U-INS, and the second side S2' can be defined as the lower side of the upper insulating layer U-INS. The third side S3' can be defined as the left side of the upper insulating layer U-INS, and the fourth side S4' can be defined as the right side of the upper insulating layer U-INS.

[0108] The first side S1, the second side S2, the third side S3, and the fourth side S4 can be separated from and / or separated from the first side S1', the second side S2', the third side S3', and the fourth side S4', respectively (e.g., spaced apart or separated). The distance between the second side S2 and the second side S2' can be greater than the distance between the first side S1 and the first side S1', the distance between the third side S3 and the third side S3', and the distance between the fourth side S4 and the fourth side S4'.

[0109] When viewed in a planar plane (e.g., in a plan view), the stepped portion STP can be defined by the first side S1, the third side S3, and the fourth side S4 of the display panel DP and the first side S1', the third side S3', and the fourth side S4' of the upper insulating layer U-INS. The cross-sectional shape of the stepped portion STP will be... Figure 12 As shown in the image.

[0110] When viewed in a planar plane (e.g., in a plan view), the dummy insulating layer D-INS can be disposed between the upper insulating layer U-INS and the second side S2 of the display panel DP. The second side S2 of the display panel DP can be defined as the lower side of the substrate SUB. Therefore, the dummy insulating layer D-INS can be disposed between the upper insulating layer U-INS and the lower side of the substrate SUB. The dummy insulating layer D-INS can be spaced apart from and / or separated from the second side S2 (e.g., spaced apart or separated), and can be disposed between the data driver DDV and the second side S2' of the upper insulating layer U-INS.

[0111] The groove GV can be defined between the dummy insulating layer D-INS and the upper insulating layer U-INS. The groove GV can extend in the second direction DR2. The cross-sectional shape of the groove GV will be... Figure 13 As shown in the figure. The stepped portion STP and the groove GV can be continuously defined to have a quadrilateral closed loop shape and can be around the display area DA (e.g., around the display area DA).

[0112] Figure 8 One or more embodiments of the present disclosure are shown. Figure 7 The cross-section of the display panel and input sensing unit corresponding to any pixel shown in the figure.

[0113] refer to Figure 8 The pixel PX can be arranged above the substrate SUB (e.g., on top). The pixel PX may include a transistor TR and a light-emitting element OLED. The light-emitting element OLED may include a first electrode AE ​​(or anode), a second electrode CE (or cathode), a hole control layer HCL, an electron control layer ECL, and a light-emitting layer EML.

[0114] The transistor TR and the light-emitting element OLED can each be arranged on the substrate SUB. Although a single transistor TR is shown as an example, generally, a pixel PX can include multiple transistors for driving the light-emitting element OLED and at least one capacitor.

[0115] The display area DA may include a light-emitting area LA corresponding to each of the pixels PX and a non-light-emitting area NLA surrounding (e.g., around) the light-emitting area LA. The light-emitting element OLED may be arranged in the light-emitting area LA.

[0116] A buffer layer (BFL) can be disposed on a substrate (SUB), and the buffer layer (BFL) may include an inorganic insulating layer. Semiconductor patterns can be disposed on the buffer layer (BFL). The semiconductor patterns may include polycrystalline silicon, amorphous silicon, or metal oxide.

[0117] Semiconductor patterns can be doped with N-type or P-type dopants. Semiconductor patterns can include heavily doped regions and lightly doped regions. The conductivity (e.g., electrical conductivity) of the heavily doped regions can be greater than that of the lightly doped regions, and the heavily doped regions can essentially serve as the source (S) and drain (D) of a transistor TR. The lightly doped regions can essentially correspond to the active portion (A) (or channel) of the transistor TR.

[0118] The source (S), active portion (A), and drain (D) of transistor TR can be formed from a semiconductor pattern. A first insulating layer (INS1) can be disposed on the semiconductor pattern and a buffer layer (BFL). The gate (G) of transistor TR can be disposed on the first insulating layer (INS1). A second insulating layer (INS2) can be disposed on the gate (G) and the first insulating layer (INS1). A third insulating layer (INS3) can be disposed on the second insulating layer (INS2).

[0119] The connection electrode CNE may include a first connection electrode CNE1 and a second connection electrode CNE2 for connecting the transistor TR and the light-emitting element OLED to each other. The first connection electrode CNE1 may be disposed on the third insulating layer INS3 and may be connected to the drain electrode D through a first contact hole CH1 defined in the first insulating layer INS1 to the third insulating layer INS3.

[0120] A fourth insulating layer INS4 can be disposed on the first connecting electrode CNE1 and the third insulating layer INS3. A second connecting electrode CNE2 can be disposed on the fourth insulating layer INS4. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 through a second contact hole CH2 defined in the fourth insulating layer INS4.

[0121] The fifth insulating layer INS5 can be disposed on the second connecting electrode CNE2 and the fourth insulating layer INS4. The layer from the buffer layer BFL to the fifth insulating layer INS5 can be defined as the circuit element layer DP-CL. The first insulating layer INS1 to the third insulating layer INS3 can include inorganic insulating layers, and the fourth insulating layer INS4 and the fifth insulating layer INS5 can include organic insulating layers.

[0122] The first electrode AE ​​can be disposed on the fifth insulating layer INS5. The first electrode AE ​​can be connected to the second connecting electrode CNE2 through the third contact hole CH3 defined in the fifth insulating layer INS5. A pixel defining film PDL, which defines an opening PX_OP for exposing a set or predetermined portion of the first electrode AE, can be disposed on the first electrode AE ​​and the fifth insulating layer INS5.

[0123] The hole control layer (HCL) can be disposed on the first electrode (AE) and the pixel defining film (PDL). The hole control layer (HCL) may include a hole transport layer and a hole injection layer.

[0124] The luminescent layer (EML) can be disposed on the hole control layer (HCL). The EML can be disposed in the region corresponding to the opening (PX_OP). The EML can comprise organic and / or inorganic materials. The EML can generate any of the following light types: red, green, and blue.

[0125] An electron control layer (ECL) can be disposed on the light-emitting layer (EML) and the hole control layer (HCL). The ECL may include an electron transport layer and an electron injection layer. In one or more embodiments, the hole control layer (HCL) and the ECL may be commonly disposed in the light-emitting region (LA) and the non-light-emitting region (NLA).

[0126] The second electrode CE can be disposed on the electronic control layer ECL. The second electrode CE can be disposed in each pixel PX. The layers constituting the light-emitting element OLED can be defined as the display element layer DP-OLED.

[0127] A buffer layer BFL disposed above (e.g., on top) the substrate SUB, along with first insulating layers INS1, second insulating layers INS2, and third insulating layers INS3, can be defined as lower insulating layers L-INS. Transistors TR can be disposed between the lower insulating layers L-INS, and light-emitting elements OLEDs can be disposed above (e.g., on top) the lower insulating layers L-INS and can be connected to the transistors TR. Fourth insulating layers INS4 and fifth insulating layers INS5 can be defined as via insulating layers V-INS.

[0128] The encapsulation layer TFE can be disposed on the light-emitting element OLED. The encapsulation layer TFE can be disposed on the second electrode CE and can cover the pixel PX. The encapsulation layer TFE can be defined as a thin-film encapsulation layer.

[0129] The encapsulation layer TFE may include multiple insulating encapsulation layers EN1, EN2 and EN3. The insulating encapsulation layers EN1, EN2 and EN3 may include a first insulating encapsulation layer EN1 disposed on the second electrode CE, a second insulating encapsulation layer EN2 disposed on the first insulating encapsulation layer EN1 and a third insulating encapsulation layer EN3 disposed on the second insulating encapsulation layer EN2.

[0130] The first insulating encapsulation layer EN1 and the third insulating encapsulation layer EN3 may each include an inorganic insulating layer and can protect the pixel PX from moisture / oxygen. The second insulating encapsulation layer EN2 may include an organic insulating layer and can protect the pixel PX from foreign matter such as dust particles.

[0131] A first voltage can be applied to the first electrode AE ​​via transistor TR, and a second voltage having a lower level than the first voltage can be applied to the second electrode CE. Holes and electrons injected into the light-emitting layer EML can recombine to form excitons, and the light-emitting element OLED can emit light when the excitons transition and decay to the ground state.

[0132] The input sensing unit (ISP) can be disposed on the TFE (Transformer Embedded Surface) layer. The ISP can also be disposed directly on the upper surface of the TFE layer. The ISP may include a substrate insulating layer (BSL), a conductive pattern (CTL), a touch insulating layer (T-INS), an upper insulating layer (U-INS), and a cover layer (COV).

[0133] The base insulating layer (BSL) can be disposed on the third insulating encapsulation layer (EN3). The base insulating layer (BSL) may include an inorganic insulating layer. One or more inorganic insulating layers may be provided on the encapsulation layer (TFE) as the base insulating layer (BSL).

[0134] The conductive pattern CTL can be disposed on the substrate insulating layer BSL. The conductive pattern CTL may include a first conductive pattern CTL1 and a second conductive pattern CTL2 disposed on the first conductive pattern CTL1.

[0135] A first conductive pattern CTL1 may be disposed on a substrate insulating layer BSL. A touch insulating layer T-INS may be disposed on the first conductive pattern CTL1 and the substrate insulating layer BSL. The touch insulating layer T-INS may be disposed on the substrate insulating layer BSL to cover the first conductive pattern CTL1. The touch insulating layer T-INS may include an inorganic insulating layer.

[0136] A second conductive pattern CTL2 can be disposed on a touch insulating layer T-INS. An upper insulating layer U-INS can be disposed on the second conductive pattern CTL2 and the touch insulating layer T-INS. The upper insulating layer U-INS can be disposed on the touch insulating layer T-INS to cover the second conductive pattern CTL2. The upper insulating layer U-INS may include an organic insulating layer. A cover layer COV can be disposed on the upper insulating layer U-INS. The cover layer COV may include an organic insulating layer.

[0137] The first conductive pattern CTL1 and the second conductive pattern CTL2 may overlap with the non-light-emitting region NLA. In one or more embodiments, the first conductive pattern CTL1 and the second conductive pattern CTL2 may be arranged in the non-light-emitting region NLA and may each have a grid shape.

[0138] The first conductive pattern CTL1 and the second conductive pattern CTL2 can form the sensor of the aforementioned input sensing unit ISP. For example, in one or more embodiments, the first conductive pattern CTL1 and the second conductive pattern CTL2, each having a grid shape, can be separated from each other in a defined or predetermined area to form the sensor. A portion of the second conductive pattern CTL2 can be connected to the first conductive pattern CTL1. Figures 9 to 11 The configuration of the sensor formed by the first conductive pattern CTL1 and the second conductive pattern CTL2 is described in more detail.

[0139] Figure 9 It is based on one or more embodiments of this disclosure Figure 5 The diagram shows a plan view of the input sensing unit.

[0140] refer to Figure 9 The input sensing unit (ISP) may include multiple sensing electrodes SE1 and SE2, multiple lines TX1 to TXh and RX1 to RXk, multiple second pads PD2, and multiple third pads PD3, where h and k are each natural numbers greater than zero. The sensing electrodes SE1 and SE2, lines TX1 to TXh and RX1 to RXk, and second and third pads PD2 and PD3 may be arranged on the TFE (Transformer Embedded Surface) layer.

[0141] The planar region of the input sensing unit (ISP) may include an active region AA and an inactive region NAA surrounding the active region AA. The active region AA may overlap with the display region DA, and the inactive region NAA may overlap with the non-display region NDA.

[0142] Sensing electrodes SE1 and SE2 can be arranged in the active region AA, and second pad PD2 and third pad PD3 can be arranged in the inactive region NAA. When viewed in a plane (e.g., in a plan view), second pad PD2 and third pad PD3 can be adjacent to the lower end of the input sensing unit ISP. When viewed in a plane (e.g., in a plan view), first pad PD1 can be arranged between second pad PD2 and third pad PD3. A description of first pad PD1 can be found in [reference needed]. Figure 7 The description.

[0143] Lines TX1 to TXh and RX1 to RXk can each be connected to one end of the sensing electrodes SE1 and SE2, and can extend to the inactive region NAA to connect to the second pad PD2 and the third pad PD3. In one or more embodiments, although in Figure 9 Although not shown in the diagram, the sensing control unit of the control input sensing unit ISP can be connected to the second pad PD2 and the third pad PD3 via a printed circuit board.

[0144] The sensing electrodes SE1 and SE2 may include a plurality of first sensing electrodes SE1 extending in a first direction DR1 and arranged in a second direction DR2, and a plurality of second sensing electrodes SE2 extending in the second direction DR2 and arranged in the first direction DR1. The second sensing electrodes SE2 may extend to be insulated from and intersect the first sensing electrodes SE1.

[0145] Lines TX1 to TXh and RX1 to RXk may include multiple first lines TX1 to TXh connected to the first sensing electrode SE1 and multiple second lines RX1 to RXk connected to the second sensing electrode SE2. The first lines TX1 to TXh may extend to the inactive region NAA to connect to the second pad PD2. The second lines RX1 to RXk may extend to the inactive region NAA to connect to the third pad PD3.

[0146] For example, when viewed in a plane (e.g., in a plan view), the first lines TX1 to TXh can be arranged in the inactive region NAA adjacent to the lower side of the active region AA. When viewed in a plane (e.g., in a plan view), the second lines RX1 to RXk can be arranged in the inactive region NAA adjacent to the right side of the active region AA. The first lines TX1 to TXh can be defined as transmission lines, and the second lines RX1 to RXk can be defined as sensing lines.

[0147] Each of the first sensing electrodes SE1 may include a plurality of first sensing units SP1 arranged on a first direction DR1 and a plurality of connection patterns CP connecting the first sensing units SP1 to each other. Each of the connection patterns CP may be arranged between two adjacent first sensing units SP1 on the first direction DR1 to connect the two first sensing units SP1 to each other.

[0148] Each of the second sensing electrodes SE2 may include a plurality of second sensing units SP2 arranged on the second direction DR2 and a plurality of extension patterns EP extending from the second sensing units SP2. Each of the extension patterns EP may be arranged between two adjacent second sensing units SP2 on the second direction DR2 and may extend from the two second sensing units SP2.

[0149] The first sensing unit SP1 and the second sensing unit SP2 may be spaced apart and / or separated (e.g., spaced apart or separated) without overlapping each other, and may be arranged alternately. A capacitor may be formed by the first sensing unit SP1 and the second sensing unit SP2. The extension pattern EP may not overlap with the connecting pattern CP.

[0150] Figure 10 It is based on one or more embodiments of this disclosure Figure 9 The image shows an enlarged view of two adjacent first sensing units and two adjacent second sensing units.

[0151] refer to Figure 10 The first sensing unit SP1 and the second sensing unit SP2 may each have a grid shape. In order to have a grid shape, each of the first sensing unit SP1 and the second sensing unit SP2 may include a plurality of first branch portions BP1 extending in the first diagonal direction DDR1 and a plurality of second branch portions BP2 extending in the second diagonal direction DDR2.

[0152] The first oblique direction DDR1 can be defined as a direction that intersects the first direction DR1 and the second direction DR2 in a plane defined by the first direction DR1 and the second direction DR2. The second oblique direction DDR2 can be defined as a direction that intersects the first oblique direction DDR1 in a plane defined by the first direction DR1 and the second direction DR2. For example, the first direction DR1 and the second direction DR2 can intersect each other orthogonally (e.g., perpendicularly), and the first oblique direction DDR1 and the second oblique direction DDR2 can intersect each other orthogonally (e.g., perpendicularly).

[0153] The first branch portion BP1 and the second branch portion BP2 of each of the first sensing unit SP1 and the second sensing unit SP2 can intersect and be integrally formed. The touch opening TOP with a diamond shape can be defined by the first branch portion BP1 and the second branch portion BP2.

[0154] When viewed in a flat surface (e.g., in a planar diagram), the light-emitting region LA can be arranged accordingly within the touch opening TOP. The light-emitting element OLED can be arranged accordingly within the light-emitting region LA. Each of the light-emitting regions LA can be... Figure 8 The light-emitting region LA is shown in the diagram. The first sensing unit SP1 and the second sensing unit SP2 can be arranged in the non-light-emitting region NLA. Because the first sensing unit SP1 and the second sensing unit SP2 are arranged in the non-light-emitting region NLA, the light generated in the light-emitting region LA can be emitted normally without being affected by the first sensing unit SP1 and the second sensing unit SP2.

[0155] The connecting pattern CP can be extended to avoid overlapping with the extended pattern EP, and can connect the first sensing units SP1 to each other. The connecting pattern CP can be connected to the first sensing unit SP1 through multiple contact holes TC-CH. Figure 11 The structure of the contact hole TC-CH is shown. The connection pattern CP can extend toward the first sensing unit SP1 through the area overlapping with the second sensing unit SP2.

[0156] An extended pattern EP can be arranged between the first sensing units SP1 and can extend from the second sensing unit SP2. The second sensing unit SP2 and the extended pattern EP can be integrally formed. The extended pattern EP can have a grid shape.

[0157] The extended pattern EP, the first sensing unit SP1, and the second sensing unit SP2 can be arranged on the same layer and can be formed by concurrently (e.g., simultaneously) patterning using the same material. The connecting pattern CP can be arranged on a different layer from the extended pattern EP, the first sensing unit SP1, and the second sensing unit SP2.

[0158] The connecting pattern CP may include a first connecting pattern CP1 and a second connecting pattern CP2 having shapes that are symmetrical to each other in a first direction DR1. An extension pattern EP may be arranged between the first connecting pattern CP1 and the second connecting pattern CP2. In one or more embodiments, the first connecting pattern CP1 and the second connecting pattern CP2 may each have a bent shape.

[0159] The first connection pattern CP1 may extend toward the first sensing unit SP1 via one of the two second sensing units SP2. The second connection pattern CP2 may extend toward the first sensing unit SP1 via the other of the two second sensing units SP2.

[0160] The contact hole TC-CH can be positioned adjacent to both ends (e.g., both ends) of the first connection pattern CP1 and the second connection pattern CP2. When viewed in a plane (e.g., in a planar view), the contact hole TC-CH can overlap with the first sensing unit SP1. The first connection pattern CP1 and the second connection pattern CP2 can be connected to the first sensing unit SP1 through the contact hole TC-CH.

[0161] The bent portions of the first connecting pattern CP1 and the second connecting pattern CP2 can overlap with the second sensing unit SP2, respectively. A single touch opening TOP can be defined at each of the bent portions of the first connecting pattern CP1 and the second connecting pattern CP2. Each of the first connecting pattern CP1 and the second connecting pattern CP2 may include two grid lines extending toward the first sensing unit SP1.

[0162] Figure 11 It is according to one or more embodiments of this disclosure along Figure 10 The cross-sectional view taken by line A-A' is shown in the figure.

[0163] refer to Figure 10 and Figure 11 The substrate insulating layer BSL can be disposed on the encapsulation layer TFE. The connection pattern CP can be disposed on the substrate insulating layer BSL. The touch insulating layer T-INS can be disposed on the connection pattern CP and the substrate insulating layer BSL. The touch insulating layer T-INS can be disposed on the substrate insulating layer BSL to cover the connection pattern CP. The connection pattern CP can be defined as the first conductive pattern CTL1 described above.

[0164] The first sensing unit SP1 and the second sensing unit SP2 can be arranged on the touch insulating layer T-INS. An extended pattern EP integrally formed with the second sensing unit SP2 can also be arranged on the touch insulating layer T-INS. A connection pattern CP can be connected to the first sensing unit SP1 through multiple contact holes TC-CH defined in the touch insulating layer T-INS.

[0165] The extended pattern EP, the first sensing unit SP1, and the second sensing unit SP2 can be arranged on the same layer of the touch insulating layer T-INS. The extended pattern EP, the first sensing unit SP1, and the second sensing unit SP2 can be defined as the aforementioned second conductive pattern CTL2. The connecting pattern CP can be arranged below the extended pattern EP, the first sensing unit SP1, and the second sensing unit SP2.

[0166] The upper insulating layer U-INS can be arranged on the extended pattern EP, the first sensing unit SP1 and the second sensing unit SP2 and the touch insulating layer T-INS, and the cover layer COV can be arranged on the upper insulating layer U-INS.

[0167] Figure 12 It is according to one or more embodiments of this disclosure along Figure 7 The cross-sectional view taken by line I-I' is shown in the figure.

[0168] refer to Figure 12 The buffer layer BFL, defined as the lower insulating layer L-INS, and the first insulating layers INS1 to the third insulating layers INS3 can extend toward the non-display area NDA. The lower insulating layer L-INS can extend to the edge of the substrate SUB. The edge of the lower insulating layer L-INS can overlap with the edge of the substrate SUB. The fourth insulating layer INS4, the fifth insulating layer INS5, and the pixel defining film PDL can extend to the portion of the non-display area NDA adjacent to the display area DA.

[0169] The display panel DP may include a first dam DM1, a second dam DM2, and a third dam DM3 that are sequentially separated from and / or isolated from the display area DA (e.g., spaced apart or separated). In the non-display area NDA, the first dam DM1, the second dam DM2, and the third dam DM3 may each be arranged on a third insulating layer INS3.

[0170] The first dam DM1 can be disposed between the second dam DM2 and the display area DA. In the non-display area NDA, the first dam DM1 can be disposed between the second dam DM2 and the sides of the fourth insulating layer INS4 and the fifth insulating layer INS5. The second dam DM2 can be disposed between the first dam DM1 and the third dam DM3. The third dam DM3 can be disposed between the second dam DM2 and the edge of the substrate SUB.

[0171] The second dam DM2 may be higher than the first dam DM1. The third dam DM3 may be lower than the first dam DM1. For example, in one or more embodiments, the first dam DM1 may be formed by three layers stacked on top of each other, the second dam DM2 may be formed by four layers stacked on top of each other, and the third dam DM3 may be formed by one layer.

[0172] The first dam DM1 may include a layer formed of the same material as the fourth insulating layer INS4, the fifth insulating layer INS5, and the pixel defining film PDL. The second dam DM2 may include a layer formed of the same material as the fourth insulating layer INS4, the fifth insulating layer INS5, and the pixel defining film PDL. Additionally, the second dam DM2 may further include a layer (e.g., an organic layer) disposed higher than the pixel defining film PDL. The third dam DM3 may be formed of the same material as the fourth insulating layer INS4.

[0173] The lower insulation layer L-INS can be separated below the third dam DM3. The lower insulation layer L-INS can be separated to define the groove GV'. The third dam DM3 can fill the groove GV'.

[0174] If a crack occurs at the edge of the lower insulating layer L-INS that overlaps with the edge of the substrate SUB (e.g., when a crack occurs at the edge of the lower insulating layer L-INS that overlaps with the edge of the substrate SUB), then the crack may extend into the display panel DP. The groove GV' can prevent or reduce such crack extension into the display area DA of the display panel DP.

[0175] The hole control layer HCL, the electron control layer ECL, and the second electrode CE can extend to the non-display area NDA adjacent to the display area DA, and can be arranged on the fifth insulating layer INS5.

[0176] The first insulating encapsulation layer EN1 can extend into the non-display area NDA. In the non-display area NDA, the first insulating encapsulation layer EN1 can be disposed on the third insulating layer INS3 to cover the first dam DM1, the second dam DM2, and the third dam DM3.

[0177] The second insulating encapsulation layer EN2 may extend into the non-display area NDA. The second insulating encapsulation layer EN2 may be arranged up to the first dam DM1. During the manufacture of the display device DD, a fluid organic material may be solidified to form the second insulating encapsulation layer EN2. The fluid organic material may flow into the non-display area NDA, but it can be blocked by the first dam DM1. In one or more embodiments, organic material overflowing the first dam DM1 may be further blocked by the second dam DM2.

[0178] The third insulating encapsulation layer EN3 can extend to the non-display area NDA. The third insulating encapsulation layer EN3 can be disposed on the first insulating encapsulation layer EN1 and the second insulating encapsulation layer EN2 in the non-display area NDA.

[0179] In one or more embodiments, the encapsulation layer TFE may extend to the edge of the substrate SUB. For example, the first insulating encapsulation layer EN1 and the third insulating encapsulation layer EN3 may extend to the edge of the substrate SUB. The edges of the first insulating encapsulation layer EN1 and the third insulating encapsulation layer EN3 may overlap with the edge of the substrate SUB.

[0180] The substrate insulating layer BSL may extend to the non-display area NDA and may be disposed on the third insulating encapsulation layer EN3. The touch insulating layer T-INS may extend to the non-display area NDA and may be disposed on the substrate insulating layer BSL. The substrate insulating layer BSL and the touch insulating layer T-INS may be spaced apart from the edges of the substrate SUB (e.g., spaced apart or separated). For example, the edges of each of the substrate insulating layer BSL and the touch insulating layer T-INS may be spaced apart from the edges of the substrate SUB.

[0181] The upper insulating layer U-INS may extend to the non-display area NDA and may be disposed on the touch insulating layer T-INS. The edge of the upper insulating layer U-INS may be spaced apart from and / or separated from the edge of the substrate SUB (e.g., spaced apart or separated). The distance DT between the edge of the upper insulating layer U-INS and the edge of the substrate SUB may be from approximately 20 micrometers (μm) to approximately 200 μm (e.g., from approximately 40 μm to approximately 120 μm). The thickness of the upper insulating layer U-INS may be from approximately 0.1 μm to approximately 10 μm (e.g., from approximately 2 μm to approximately 4 μm).

[0182] When viewed in a plane (e.g., in a plan view), the base insulating layer BSL may overlap with the upper insulating layer U-INS, and the edge of the base insulating layer BSL may overlap with the edge of the upper insulating layer U-INS. When viewed in a plane (e.g., in a plan view), the touch insulating layer T-INS may overlap with the upper insulating layer U-INS, and the edge of the touch insulating layer T-INS may overlap with the edge of the upper insulating layer U-INS.

[0183] The cover layer COV can extend to the non-display area NDA and can be disposed on the upper insulating layer U-INS. The cover layer COV can extend to the edge of the substrate SUB and can be disposed on the third insulating encapsulation layer EN3 to cover the upper insulating layer U-INS. The edge of the cover layer COV can overlap with the edge of the substrate SUB.

[0184] The second adhesive layer AL2 can be disposed on the cover layer COV. The anti-reflective layer RPL can be disposed on the second adhesive layer AL2, and the anti-reflective layer RPL can be attached to the cover layer COV through the second adhesive layer AL2. The second adhesive layer AL2 can extend to the edge of the substrate SUB, and the edge of the second adhesive layer AL2 can overlap with the edge of the substrate SUB.

[0185] The stepped portion STP can be defined by the edge of the display panel DP and the edge of the upper insulating layer U-INS. The edge of the display panel DP can be defined by the edge of the substrate SUB, the edge of the lower insulating layer L-INS, the edge of the first insulating encapsulation layer EN1, and the edge of the third insulating encapsulation layer EN3.

[0186] Because the edge of the display panel DP (e.g., the third side S3) and the edge of the upper insulating layer U-INS (e.g., the third side S3', see...) Figure 7 The steps (STP) are positioned at different heights, thus defining the stepped portion of the display panel (DP). Essentially, the edge of the defined stepped portion (STP) of the display panel (DP) can be as described above. Figure 7 The first side S1, the third side S3, and the fourth side S4 are shown in the diagram. Additionally, the edge of the defined step portion STP of the upper insulating layer U-INS can be as described above. Figure 7 The first side S1', the third side S3', and the fourth side S4' are shown in the figure.

[0187] In one or more embodiments of this disclosure, at least one insulating layer selected from lower insulating layers BFL and INS1 to INS3, insulating encapsulation layers EN1 and EN3, and substrate insulating layer BSL may extend to the edge of the substrate SUB. Additionally, the first surface roughness of the first upper surface of the at least one insulating layer exposed upwards by the upper insulating layer U-INS may be greater than the second surface roughness of the second upper surface of the at least one insulating layer covered by the upper insulating layer U-INS.

[0188] Figure 12 This is an example embodiment of the present disclosure, and the at least one insulating layer selected from the aforementioned insulating layers may be... Figure 12 The third insulating encapsulation layer EN3. For example, the upper surface of the third insulating encapsulation layer EN3 may include a first upper surface US1 that is exposed upwards but not covered by the upper insulating layer U-INS and a second upper surface US2 that is covered by the upper insulating layer U-INS. In other words, the uppermost insulating layer among the insulating encapsulation layers EN1, EN2 and EN3 (e.g., the third insulating encapsulation layer EN3) may include the first upper surface US1 and the second upper surface US2.

[0189] The first surface roughness of the first upper surface US1 can be greater than the second surface roughness of the second upper surface US2. The first upper surface US1 can be surface-treated to have a high surface roughness using a dry etching process. In areas not overlapping with the upper insulating layer U-INS, the touch insulating layer T-INS and the base insulating layer BSL can be removed using a dry etching process, and this dry etching process can be performed on the first upper surface US1 of the third insulating encapsulation layer EN3. (Refer to...) Figures 19A to 19DThe dry etching process for the first upper surface US1 is described in more detail.

[0190] The cover layer COV can contact the first upper surface US1 of the third insulating encapsulation layer EN3. As the surface roughness increases, the adhesive force between the cover layer COV and the first upper surface US1 can be improved (e.g., increased). In one or more embodiments of this disclosure, the adhesive force between the cover layer COV and the first upper surface US1 can be improved and increased due to the increased surface roughness of the first upper surface US1, which is exposed but not covered by the upper insulating layer U-INS. Because the cover layer COV adheres more firmly to the third insulating encapsulation layer EN3, the cover layer COV and the third insulating encapsulation layer EN3 can remain in contact without separating from each other due to external impact.

[0191] In one or more embodiments of this disclosure, the difference between the first surface roughness of the first upper surface US1 and the second surface roughness of the second upper surface US2 can be from about 10 nm to about 70 nm. The first surface roughness can be from about 30 nm to about 70 nm, and the second surface roughness can be from about 1 nm to about 20 nm. For example, in one or more embodiments, the first surface roughness can be about 66.1 nm, and the second surface roughness can be about 1.3 nm. In this disclosure, the term "surface roughness" refers to the average distance between the highest peak and the lowest valley in each sample length of the surface profile of the surface of the layer.

[0192] exist Figure 12 In this disclosure, at least one insulating layer is described as a third insulating encapsulation layer EN3; however, embodiments of this disclosure are not limited thereto. In one or more embodiments, the at least one insulating layer may be a base insulating layer BSL. In one or more embodiments, the at least one insulating layer may be a first insulating encapsulation layer EN1. In one or more embodiments, the at least one insulating layer may be any of the following insulating layers L-INS. (Refer to...) Figures 21 to 24 These embodiments will be described in more detail.

[0193] The sum of the thicknesses of the lower insulating layer L-INS, the first insulating encapsulation layer EN1, and the third insulating encapsulation layer EN3 in the region not overlapping with the upper insulating layer U-INS can be approximately 0 angstroms. up to approximately (for example, approximately) up to approximately ).

[0194] In the region not overlapping with the upper insulating layer U-INS, as the number of insulating layers removed from the lower insulating layer L-INS and the first insulating encapsulation layer EN1 and the third insulating encapsulation layer EN3 increases, the sum of the thicknesses of the insulating layers can decrease. If all of the lower insulating layer L-INS and the first insulating encapsulation layer EN1 and the third insulating encapsulation layer EN3 are removed in the region not overlapping with the upper insulating layer U-INS (e.g., when all of the lower insulating layer L-INS and the first insulating encapsulation layer EN1 and the third insulating encapsulation layer EN3 are removed in the region not overlapping with the upper insulating layer U-INS), then the sum of the thicknesses of the insulating layers can be zero, and its structure can be substantially as follows: Figure 25 As shown in the image.

[0195] Figure 13 It is according to one or more embodiments of this disclosure along Figure 7 The cross-sectional view taken by line II-II' is shown in the figure.

[0196] refer to Figure 13 The upper insulating layer U-INS and the dummy insulating layer D-INS can be arranged on the same layer. For example, the upper insulating layer U-INS and the dummy insulating layer D-INS can be arranged on the touch insulating layer T-INS. In essence, the upper insulating layer U-INS and the dummy insulating layer D-INS can be formed concurrently (e.g., simultaneously) from the same material. The groove GV can be defined between the upper insulating layer U-INS and the dummy insulating layer D-INS.

[0197] The base insulating layer BSL and the touch insulating layer T-INS may overlap with the upper insulating layer U-INS and the dummy insulating layer D-INS. The base insulating layer BSL and the touch insulating layer T-INS may not be arranged in the groove GV. The third surface roughness of the third upper surface US3 of the third insulating encapsulation layer EN3 (at least one of the above insulating layers) exposed by the groove GV may be substantially the same as the first surface roughness and may be greater than the second surface roughness.

[0198] The cover layer COV can be disposed on the upper insulating layer U-INS and the dummy insulating layer D-INS, and can fill the groove GV. The cover layer COV can contact the third upper surface US3 in the groove GV. The cover layer COV can adhere more firmly to the third upper surface US3, which has a high surface roughness. The cover layer COV can be disposed on a portion of the dummy insulating layer D-INS. The second adhesive layer AL2 and the anti-reflective layer RPL can be disposed on the flat surface of the cover layer COV.

[0199] Figure 14 The cross-sectional configuration of the comparison display device DD' is shown.

[0200] For ease of explanation, Figure 14In this paper, the detailed configuration of the display panel DP is omitted. The display panel DP is shown as a single layer, and the conductive pattern CTL, the substrate insulating layer BSL, and the touch insulating layer T-INS are also omitted.

[0201] refer to Figure 14 The side cover layer S-COV can be disposed at the edges of the upper insulating layer U-INS' and the cover layer COV'. The edges of the upper insulating layer U-INS' and the cover layer COV' of the comparison display device DD' can overlap with the edges of the display panel DP. If the side cover layer S-COV is not disposed (e.g., when the side cover layer S-COV is not disposed), then the edges of the upper insulating layer U-INS' and the cover layer COV' can be exposed to the outside.

[0202] External shocks may be applied to the side cover layer S-COV. The side cover layer S-COV can absorb external shocks, but if the external shock is large (e.g., when the external shock is large), the amount of shock transmitted to the edge of the upper insulation layer U-INS' and the edge of the cover layer COV' may increase.

[0203] When the impact transmitted to the edges of the upper insulating layer U-INS' and the cover layer COV' is large enough to damage them, the edges of the upper insulating layer U-INS' and the cover layer COV' may peel off. Consequently, the side of the comparison display device DD' may be damaged.

[0204] Figure 15 The illustration schematically depicts one or more embodiments according to this disclosure. Figure 12 The cross-sectional configuration of the display device DD is shown in the figure.

[0205] For example, Figure 15 Shown as with Figure 14 The corresponding cross-sectional view. Therefore, in Figure 15 In, with Figure 14 Similarly, the detailed configuration of the display panel DP is omitted, and the display panel DP is shown as a single layer. In addition, the conductive pattern CTL, the substrate insulating layer BSL, and the touch insulating layer T-INS are omitted.

[0206] refer to Figure 15The side cover layer S-COV can be disposed at the edges of the upper insulating layer U-INS and the cover layer COV. The edge of the upper insulating layer U-INS can be spaced apart from and / or separated from the edge of the display panel DP (e.g., spaced apart or separated), and the cover layer COV can be disposed on the display panel DP to cover the edge of the upper insulating layer U-INS. The edge of the cover layer COV and the edge of the second adhesive layer AL2 can overlap with the edge of the display panel DP. Because external impacts can be absorbed by the side cover layer S-COV and the cover layer COV, the amount of impact transmitted to the upper insulating layer U-INS can be reduced.

[0207] In this case, Figure 15 The display device DD shown in the figure may not include it. Figure 14 The image shows the phenomenon of peeling at the edges of the upper insulating layer U-INS' and the cover layer COV'.

[0208] Figure 16 It shows Figure 14 The comparison display device shown herein and one or more embodiments according to this disclosure. Figure 15 The results of the external impact test of the display device are shown in the figure.

[0209] exist Figure 16 In this diagram, the vertical axis represents stress, and stress can be measured in megapascals (MPa). Stress can be broadly correlated with the amount of impact transmitted to the upper insulating layer U-INS or U-INS'. Additionally, in... Figure 16 In the figure, the values ​​shown for the display device DD (i.e., 40μm and 115μm) can represent the distance between the edge of the substrate SUB and the edge of the upper insulating layer U-INS.

[0210] refer to Figure 16 The amount of impact transmitted to the upper insulating layer U-INS in the display device DD can be reduced compared to the amount of impact transmitted to the upper insulating layer U-INS in the comparison display device DD'. Furthermore, in Figure 16 In this process, as the distance between the edge of the substrate SUB and the edge of the upper insulating layer U-INS increases, that is, as the edge of the upper insulating layer U-INS is further away from the edge of the substrate SUB, the amount of impact transmitted to the upper insulating layer U-INS can be reduced.

[0211] Figure 17 The illustration shows one or more embodiments according to this disclosure, including... Figure 7 The planar configuration of the mother panel of the display panel is shown in the figure. Figure 18 It is based on one or more embodiments of this disclosure Figure 17 An enlarged view of any of the unit panels shown.

[0212] refer to Figure 17 The mother panel M-PN may include multiple unit panels U-PN arranged on the first direction DR1 and the second direction DR2. Each of the unit panels U-PN may be Figure 7 The display panel DP is shown in the image. For example, in... Figure 17 In the diagram, the display area DA and the data driver DDV are each shown with dashed lines.

[0213] Cutting lines CL and unit cutting lines U-CL can be defined within the mother panel M-PN. For example, cutting lines CL and unit cutting lines U-CL are shown as dashed lines. The edge of each unit panel U-PN can be defined as the unit cutting line U-CL.

[0214] The area defined by the cutting line CL can be larger than the area defined by the unit cutting line U-CL. The cutting line CL can be defined outward from the unit cutting line U-CL, and can divide the mother panel M-PN into sub-panels S-PN corresponding to the unit panel U-PN. The area of ​​the sub-panel S-PN can be larger than the area of ​​the unit panel U-PN.

[0215] Along the cutting line CL, the mother panel M-PN can be cut first, dividing it into multiple sub-panels S-PN. Subsequently, along the unit cutting line U-CL, a portion of the sub-panels S-PN can be cut to form the unit panel U-PN. The unit cutting line U-CL corresponds to the first side S1 to the fourth side S4 of the aforementioned display panel DP.

[0216] After the aforementioned input sensing unit ISP and anti-reflective layer RPL are arranged on the unit panel U-PN, the unit panel U-PN can be separated from the mother panel M-PN. When the unit panel U-PN is separated, the input sensing units ISP can also be separated from each other, and the anti-reflective layers RPL can also be separated from each other.

[0217] The aforementioned upper insulating layer U-INS and dummy insulating layer D-INS can be arranged on each of the unit panels U-PN. The groove GV can be defined between the upper insulating layer U-INS and the dummy insulating layer D-INS.

[0218] refer to Figure 18 The groove GV can be defined on the unit panel U-PN, and the groove GV can be... Figure 7 , Figure 12 and Figure 13 The stepped portion STP and the groove GV shown correspond to each other. A portion of the upper insulating layer U-INS (e.g., the second side S2') is defined with... Figure 18 The groove GV between the dummy insulating layers D-INS shown can be retained on the display panel DP, allowing for the definition of... Figure 7The groove GV is shown in the figure.

[0219] therefore, Figure 17 and Figure 18 The groove GV shown in the figure is used with Figure 7 The groove GV shown in the figure is indicated by the same reference numerals. For example, to illustrate and explain more clearly... Figure 18 The shape of the groove GV in the middle, Figure 18 The groove GV in the middle is shown as relatively larger than Figure 7 The groove GV is shown in the figure.

[0220] The dummy insulating layer D-INS can be arranged around the upper insulating layer U-INS to surround it. The groove GV can be defined between the upper insulating layer U-INS and the dummy insulating layer D-INS. The groove GV can be defined as a quadrilateral closed-loop shape corresponding to the shape of the upper insulating layer U-INS.

[0221] The groove GV can overlap with a portion of the cell cutting line U-CL. For example, the groove GV can overlap with each of the adjacent cell cutting lines U-CL in the first side S1', the third side S3', and the fourth side S4'.

[0222] The groove GV that overlaps with the cell cut line U-CL adjacent to the first side S1' can extend in the second direction DR2. The groove GV that overlaps with each of the cell cut lines U-CL adjacent to the third side S3' and the fourth side S4' can extend in the first direction DR1. The groove GV that is spaced apart from and / or separated from the second side S2 (e.g., spaced apart or separated) and defined between the second side S2' and the dummy insulating layer D-INS can extend in the second direction DR2.

[0223] The width of the groove GV overlapping each of the adjacent unit cutting lines U-CL of the first side S1', the third side S3', and the fourth side S4' can be greater than the width of the groove GV defined between the second side S2' and the dummy insulating layer D-INS. In this disclosure, the term "width" can be defined as a value measured in a direction intersecting the extension direction of the component.

[0224] When the unit panel U-PN is cut and separated along the unit cutting line U-CL, the aforementioned stepped portion STP can be formed at the portion cut along the unit cutting line U-CL adjacent to the first side S1', the third side S3', and the fourth side S4'. When the unit panel U-PN is cut and separated along the unit cutting line U-CL, the groove GV defined between the second side S2' and the dummy insulating layer D-INS can be retained on the unit panel U-PN.

[0225] The opening D-OP can be defined within the dummy insulating layer D-INS. The opening D-OP can be defined to expose the data driver DDV. The opening D-OP can expose the portion of the unit panel U-PN adjacent to the data driver DDV. The recess GV can be defined between the opening D-OP and the display area DA.

[0226] Figures 19A to 19D It is along Figure 18 The diagram shows a cross-sectional view taken by line III-III' and explains a method for manufacturing a display device according to one or more embodiments of the present disclosure.

[0227] For example, in Figures 19A to 19D In the figure, the insulating layers BFL, INS1 to INS3, EN1, EN3, BSL, T-INS and U-INS arranged in the non-displayed area are shown, and the dams DM1, DM2 and DM3 are omitted to avoid confusion with the figure.

[0228] refer to Figure 19A The lower insulating layer L-INS, the first insulating encapsulation layer EN1 and the third insulating encapsulation layer EN3, the substrate insulating layer BSL, and the touch insulating layer T-INS can be provided above the substrate SUB (e.g., on top). The lower insulating layer L-INS, the first insulating encapsulation layer EN1 and the third insulating encapsulation layer EN3, the substrate insulating layer BSL, and the touch insulating layer T-INS can extend to the cell cut line U-CL defining the edge of the substrate SUB.

[0229] Figure 12 The first conductive pattern CTL1 and the second conductive pattern CTL2 shown can be arranged on the cell panel U-PN, and the upper insulating layer U-INS can be arranged on the second conductive pattern CTL2. The portion of the upper insulating layer U-INS that overlaps with the cell cut line U-CL can be removed to define the groove GV. The portion of the touch insulating layer T-INS that overlaps with the cell cut line U-CL can be exposed upward by the groove GV.

[0230] refer to Figure 19A and Figure 19B Dry etching can be performed on the mother panel M-PN using the upper insulating layer U-INS and the dummy insulating layer D-INS as masks. For example, in one or more embodiments, ions generated from plasma can be accelerated by an electric field and collide with the material to be etched, thereby performing a dry etching process.

[0231] Using a dry etching process, the portions of the touch insulating layer T-INS and the substrate insulating layer BSL exposed by the groove GV can be removed. Because these portions of the touch insulating layer T-INS and the substrate insulating layer BSL are removed, the portion of the third insulating encapsulation layer EN3 that overlaps with the groove GV can be exposed upwards. Through the dry etching process, the upper surface of the portion of the third insulating encapsulation layer EN3 that overlaps with the groove GV can have a high surface roughness.

[0232] During a dry etching process, ions generated from plasma are accelerated by an electric field and collide with the material to be etched, thus etching the material. After the aforementioned portions of the contact insulating layer T-INS and the substrate insulating layer BSL are removed, ions can collide with the upper surface of the portion of the third insulating encapsulation layer EN3 that overlaps with the groove GV. The dry etching process can be performed such that the portion of the third insulating encapsulation layer EN3 overlapping with the groove GV is not completely removed.

[0233] In this respect, since the upper surface of the third insulating encapsulation layer EN3 overlapping the groove GV is etched, the surface of the upper surface of the third insulating encapsulation layer EN3 overlapping the groove GV can become rough. According to the above process, the third insulating encapsulation layer EN3 may include a first upper surface US1 exposed by the groove GV and having a first surface roughness, and a second upper surface US2 covered by the upper insulating layer U-INS and having a second surface roughness. For example, the first upper surface US1 can be surface treated to have a high surface roughness by a dry etching process.

[0234] refer to Figure 19C In one or more embodiments, a flowable organic ink may be provided on the upper insulating layer U-INS, and the organic ink may be cured to form a cover layer COV. The cover layer COV may fill the groove GV. A second adhesive layer AL2 may be disposed on the cover layer COV, and an antireflective layer RPL may be disposed on the second adhesive layer AL2.

[0235] Because the cover layer COV fills the groove GV, it can contact the first upper surface US1. Due to the dry etching process, the surface roughness of the first upper surface US1 is increased, which improves and strengthens the adhesion between the cover layer COV and the first upper surface US1. Consequently, because the cover layer COV adheres more firmly to the third insulating encapsulation layer EN3, the cover layer COV and the third insulating encapsulation layer EN3 can remain together without separating due to external impact.

[0236] refer to Figure 19DAfter cutting, the unit panel U-PN can be separated through the unit cutting line U-CL to form the display panel DP. In addition, the stepped portion STP can be defined.

[0237] Figure 20 Test results regarding the adhesive strength between the third insulating encapsulation layer and the cover layer according to one or more embodiments of the present disclosure are shown.

[0238] refer to Figure 20 Tests were performed on five samples (N=5), and the distribution of adhesive force among the five samples is shown in a bar graph. The test results on the left show the adhesive force between the cover layer COV and the third insulating encapsulation layer EN3, to which no dry etching process was performed. The test results on the right show the adhesive force between the cover layer COV and the third insulating encapsulation layer EN3, to which a dry etching process was performed.

[0239] The adhesion between the cover layer COV and the third insulating encapsulation layer EN3 to which a dry etching process has been performed can be greater than the adhesion between the cover layer COV and the third insulating encapsulation layer EN3 to which a dry etching process has not been performed. Accordingly, for samples with a third insulating encapsulation layer EN3 after dry etching, the cover layer COV can adhere more firmly to the first upper surface US1 of the third insulating encapsulation layer EN3 as described above.

[0240] Figures 21 to 25 A portion of an insulating layer having a first upper surface formed thereon is shown according to one or more embodiments of the present disclosure.

[0241] Figures 21 to 25 The example shown is based on one or more embodiments of this disclosure. Figure 12 The corresponding cross-sectional view, and Figures 21 to 25 The components shown will be described in more detail, with a focus on those related to... Figure 12 The components shown are different components.

[0242] refer to Figures 21 to 24 As described above, the first surface roughness of the first upper surface of at least one insulating layer exposed upwards by the upper insulating layer U-INS but not covered by it can be greater than the second surface roughness of the second upper surface of the at least one insulating layer covered by the upper insulating layer U-INS.

[0243] refer to Figure 21 For reference Figure 19A The lower insulating layer L-INS, the first insulating encapsulation layer EN1 and the third insulating encapsulation layer EN3, the base insulating layer BSL, and the touch insulating layer T-INS can extend to the cell cut line U-CL. Thereafter, by reference... Figure 19BThe dry etching process described involves removing the portion of the touch insulating layer T-INS exposed by the groove GV, and then the upper surface of the substrate insulating layer BSL exposed by the groove GV can be surface treated to have a high surface roughness by the dry etching process.

[0244] In the display device DD-1, the substrate insulating layer BSL, the first insulating encapsulation layer EN1, the third insulating encapsulation layer EN3, and the lower insulating layer L-INS can extend to the edge of the substrate SUB. Additionally, the substrate insulating layer BSL may include a first upper surface US1 that is not covered by the upper insulating layer U-INS and has a first surface roughness, and a second upper surface US2 that is covered by the upper insulating layer U-INS and has a second surface roughness. The first surface roughness is greater than the second surface roughness. The cover layer COV can contact the first upper surface US1 of the substrate insulating layer BSL.

[0245] The touch insulating layer T-INS may be spaced apart from and / or separated from the edge of the substrate SUB (e.g., spaced apart or separated), and may overlap with the upper insulating layer U-INS. The edge of the touch insulating layer T-INS may overlap with the edge of the upper insulating layer U-INS.

[0246] refer to Figure 22 For reference Figure 19A The lower insulating layer L-INS, the first insulating encapsulation layer EN1 and the third insulating encapsulation layer EN3, the base insulating layer BSL, and the touch insulating layer T-INS can extend to the cell cut line U-CL. Thereafter, by reference... Figure 19B The dry etching process described involves removing the portion of the touch insulating layer T-INS exposed by the groove GV, the portion of the base insulating layer BSL exposed by the groove GV, and the portion of the third insulating encapsulation layer EN3 exposed by the groove GV. Then, the upper surface of the first insulating encapsulation layer EN1 exposed by the groove GV can be surface treated to have a high surface roughness by the dry etching process.

[0247] In the display device DD-2, the first insulating encapsulation layer EN1 and the lower insulating layer L-INS can extend to the edge of the substrate SUB. Furthermore, the first insulating encapsulation layer EN1 may include a first upper surface US1 that is not covered by the upper insulating layer U-INS and has a first surface roughness, and a second upper surface US2 that is covered by the upper insulating layer U-INS and has a second surface roughness. The first surface roughness is greater than the second surface roughness. The cover layer COV can contact the first upper surface US1 of the first insulating encapsulation layer EN1.

[0248] The third insulating encapsulation layer EN3, the base insulating layer BSL, and the touch insulating layer T-INS may be spaced apart from and / or separated from the edge of the substrate SUB (e.g., spaced apart or separated), and may overlap with the upper insulating layer U-INS. The edges of the third insulating encapsulation layer EN3, the base insulating layer BSL, and the touch insulating layer T-INS may overlap with the edges of the upper insulating layer U-INS.

[0249] refer to Figure 23 For reference Figure 19A The lower insulating layer L-INS, the first insulating encapsulation layer EN1 and the third insulating encapsulation layer EN3, the base insulating layer BSL, and the touch insulating layer T-INS can extend to the cell cut line U-CL. Thereafter, by reference... Figure 19B The dry etching process described involves removing the portions of the touch insulating layer T-INS exposed by the groove GV, the portions of the base insulating layer BSL exposed by the groove GV, the portions of the first insulating encapsulation layer EN1 exposed by the groove GV, and the portions of the third insulating encapsulation layer EN3 exposed by the groove GV. Then, the upper surface of the third insulating layer INS3 exposed by the groove GV can be surface treated to have a high surface roughness by the dry etching process.

[0250] The third insulating layer INS3, the first insulating layer INS1, the second insulating layer INS2, and the buffer layer BFL of the display device DD-3 can extend to the edge of the substrate SUB. Additionally, the third insulating layer INS3 may include a first upper surface US1 that is not covered by the upper insulating layer U-INS and has a first surface roughness, and a second upper surface US2 that is covered by the upper insulating layer U-INS and has a second surface roughness. The first surface roughness is greater than the second surface roughness. The cover layer COV can contact the first upper surface US1 of the third insulating layer INS3.

[0251] The insulating layers EN1, EN3, BSL, and T-INS disposed above the third insulating layer INS3 may be spaced apart from and / or separated from the edge of the substrate SUB (e.g., spaced apart or separated), and may overlap with the upper insulating layer U-INS. The edges of the insulating layers EN1, EN3, BSL, and T-INS may overlap with the edges of the upper insulating layer U-INS.

[0252] refer to Figure 24 For reference Figure 19A The lower insulating layer L-INS, the first insulating encapsulation layer EN1 and the third insulating encapsulation layer EN3, the base insulating layer BSL, and the touch insulating layer T-INS can extend to the cell cut line U-CL. Thereafter, by reference... Figure 19BThe dry etching process described involves removing the portions of the touch insulating layer T-INS exposed by the groove GV, the portions of the base insulating layer BSL exposed by the groove GV, the portions of the first insulating encapsulation layer EN1 exposed by the groove GV, the portions of the third insulating encapsulation layer EN3 exposed by the groove GV, and the portions of the third insulating layer INS3 exposed by the groove GV. Then, the upper surface of the second insulating layer INS2 exposed by the groove GV can be surface treated with a dry etching process to have a high surface roughness.

[0253] The second insulating layer INS2, the first insulating layer INS1, and the buffer layer BFL of the display device DD-4 can extend to the edge of the substrate SUB. Additionally, the second insulating layer INS2 may include a first upper surface US1 that is not covered by the upper insulating layer U-INS and has a first surface roughness, and a second upper surface US2 that is covered by the upper insulating layer U-INS and has a second surface roughness. The first surface roughness is greater than the second surface roughness. The cover layer COV can contact the first upper surface US1 of the second insulating layer INS2.

[0254] The insulating layers INS3, EN1, EN3, BSL, and T-INS disposed above the second insulating layer INS2 may be spaced apart from and / or separated from the edge of the substrate SUB (e.g., spaced apart or separated), and may overlap with the upper insulating layer U-INS. The edges of the insulating layers INS3, EN1, EN3, BSL, and T-INS may overlap with the edges of the upper insulating layer U-INS.

[0255] As an example, Figure 23 and Figure 24 The diagrams illustrate structures in which the third insulating layer INS3 includes a first upper surface US1 and a second upper surface US2, and structures in which the second insulating layer INS2 includes a first upper surface US1 and a second upper surface US2. However, embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, the first insulating layer INS1 may include a first upper surface US1 and a second upper surface US2, or the buffer layer BFL may include a first upper surface US1 and a second upper surface US2.

[0256] If the first insulating layer INS1 includes a first upper surface US1 and a second upper surface US2 (e.g., when the first insulating layer INS1 includes a first upper surface US1 and a second upper surface US2), then the first insulating layer INS1 and the buffer layer BFL can extend to the edge of the substrate SUB. Additionally, the insulating layers INS2, INS3, EN1, EN3, BSL, and T-INS disposed on the first insulating layer INS1 can be spaced apart and / or separated from the edge of the substrate SUB (e.g., spaced apart or separated) and can overlap with the upper insulating layer U-INS, and the edges of the insulating layers INS2, INS3, EN1, EN3, BSL, and T-INS can overlap with the edges of the upper insulating layer U-INS. The cover layer COV can contact the first upper surface US1 of the first insulating layer INS1.

[0257] If the buffer layer BFL includes a first upper surface US1 and a second upper surface US2 (e.g., when the buffer layer BFL includes a first upper surface US1 and a second upper surface US2), then the buffer layer BFL can extend to the edge of the substrate SUB. Additionally, the insulating layers INS1 to INS3, EN1, EN3, BSL, and T-INS disposed on the buffer layer BFL can be spaced apart and / or separated from the edge of the substrate SUB (e.g., spaced apart or separated) and can overlap with the upper insulating layer U-INS, and the edges of the insulating layers INS1 to INS3, EN1, EN3, BSL, and T-INS can overlap with the edges of the upper insulating layer U-INS. The cover layer COV can contact the first upper surface US1 of the buffer layer BFL.

[0258] Based on the aforementioned lower insulating layer L-INS, according to one or more embodiments of this disclosure, one of the lower insulating layers BFL and INS1 to INS3 (e.g., selected from lower insulating layers BFL and INS1 to INS3) may extend to the edge of the substrate SUB and may include a first upper surface US1 and a second upper surface US2. In these embodiments, the insulating layers, insulating encapsulation layers EN1 and EN3, substrate insulating layer BSL, and touch insulating layer T-INS disposed on the lower insulating layer L-INS may be spaced apart and / or separated (e.g., spaced apart or separated) from the edge of the substrate SUB and may overlap with the upper insulating layer U-INS, and the edge of the aforementioned insulating layer disposed on the lower insulating layer L-INS may overlap with the edge of the upper insulating layer U-INS.

[0259] refer to Figure 25 For reference Figure 19A The lower insulating layer L-INS, the first insulating encapsulation layer EN1 and the third insulating encapsulation layer EN3, the base insulating layer BSL, and the touch insulating layer T-INS can extend to the cell cut line U-CL. Thereafter, by reference... Figure 19B The dry etching process described removes the portions of the touch insulating layer T-INS exposed by the groove GV, the portions of the base insulating layer BSL exposed by the groove GV, the portions of the first insulating encapsulation layer EN1 exposed by the groove GV, the portions of the third insulating encapsulation layer EN3 exposed by the groove GV, and the portions of the lower insulating layer L-INS exposed by the groove GV. Then, the upper surface of the substrate SUB exposed by the groove GV can be surface treated to have a high surface roughness by the dry etching process.

[0260] The substrate SUB may include a first upper surface US1 that is not covered by the upper insulating layer U-INS and has a first surface roughness, and a second upper surface US2 that is covered by the upper insulating layer U-INS and has a second surface roughness. The first surface roughness is greater than the second surface roughness. The cover layer COV may contact the first upper surface US1 of the substrate SUB.

[0261] The lower insulating layer L-INS, insulating encapsulation layers EN1 and EN3, base insulating layer BSL, and touch insulating layer T-INS of the display device DD-5 may be spaced apart and / or separated from the edge of the substrate SUB (e.g., spaced apart or separated), and may overlap with the upper insulating layer U-INS. The edges of the lower insulating layer L-INS, insulating encapsulation layers EN1 and EN3, base insulating layer BSL, and touch insulating layer T-INS may overlap with the edges of the upper insulating layer U-INS.

[0262] Figure 26 The configuration on a unit panel according to one or more embodiments of the present disclosure is shown. Figure 27A It is according to one or more embodiments of this disclosure along Figure 26 The cross-sectional view shown is taken from line IV-IV'. Figure 27B One or more embodiments of the present disclosure are shown by means of... Figure 26 The unit panel is formed by cutting along the cutting lines shown in the figure.

[0263] As an example, Figure 26 Shown as with Figure 18 The corresponding floor plan, and Figure 27A and Figure 27B Shown as respectively with Figure 19C and Figure 19D The corresponding cross-sectional view. This will be described below. Figure 26 , Figure 27A and Figure 27B The components shown in the image, with particular attention to those related to... Figure 18 , Figure 19C and Figure 19D The components shown are different components.

[0264] refer to Figure 26 The first dam layer DML1 can be arranged on the unit panel U-PN. When viewed in a plane (e.g., in a plan view), the first dam layer DML1 can be around (e.g., surrounding) the upper insulating layer U-INS. When viewed in a plane (e.g., in a plan view), the first dam layer DML1 can be around (e.g., surrounding) the display area DA. When viewed in a plane (e.g., in a plan view), the dummy insulating layer D-INS can be around (e.g., surrounding) the first dam layer DML1.

[0265] The groove GV can be defined between the dummy insulating layer D-INS and the first dam layer DML1. The groove GV can be defined around the first dam layer DML1 (e.g., around the first dam layer DML1). The first dummy groove DGV1 can be defined between the first dam layer DML1 and the upper insulating layer U-INS.

[0266] refer to Figure 27A The first dam layer DML1 can be arranged on the same layer as the upper insulation layer U-INS. The first dam layer DML1 and the upper insulation layer U-INS can be formed concurrently (e.g., simultaneously) from the same material.

[0267] By reference Figure 19B In the described dry etching process, the first upper surface US1 of the third insulating encapsulation layer EN3, exposed by the groove GV and the first dummy groove DGV1, can have a first surface roughness. The second upper surface US2 of the third insulating encapsulation layer EN3, covered by the first dam layer DML1 and the upper insulating layer U-INS, can have a second surface roughness. The first surface roughness is greater than the second surface roughness.

[0268] refer to Figure 27B After cutting, the unit panel U-PN can be separated through the unit cutting line U-CL to form the display panel DP. The first dam layer DML1 can be disposed on the display panel DP, and the first dam layer DML1 can be spaced apart and / or separated from the edge of the display panel DP (e.g., spaced apart or separated). The first dam layer DML1 can be disposed between the edge of the display panel DP and the upper insulating layer U-INS.

[0269] Figure 28 The configuration on a unit panel according to one or more embodiments of the present disclosure is shown. Figure 29A It is according to one or more embodiments of this disclosure along Figure 28 The cross-sectional view taken by line V-V' is shown in the figure. Figure 29B One or more embodiments of the present disclosure are shown by means of... Figure 28 The unit panel is formed by cutting along the cutting lines shown in the figure.

[0270] As an example, Figure 28 Shown as with Figure 18 The corresponding floor plan, and Figure 29A and Figure 29B The diagram is shown as being respectively with Figure 19C and Figure 19D The corresponding cross-sectional view. This will be described below. Figure 28 , Figure 29A and Figure 29B The components shown in the image, with particular attention to those related to... Figure 18 , Figure 19C and Figure 19D The components shown are different components.

[0271] refer to Figure 28 The first dam layer DML1 and the second dam layer DML2 can be arranged on the unit panel U-PN. When viewed in a plane (e.g., in a plan view), the first dam layer DML1 can be around (e.g., surrounding) the second dam layer DML2. When viewed in a plane (e.g., in a plan view), the second dam layer DML2 can be around (e.g., surrounding) the upper insulation layer U-INS. When viewed in a plane (e.g., in a plan view), the second dam layer DML2 can be around (e.g., surrounding) the display area DA. When viewed in a plane (e.g., in a plan view), the dummy insulation layer D-INS can be around (e.g., surrounding) the first dam layer DML1.

[0272] The groove GV can be defined between the dummy insulation layer D-INS and the first dam layer DML1. The first dummy groove DGV1 can be defined between the first dam layer DML1 and the second dam layer DML2. The second dummy groove DGV2 can be defined between the second dam layer DML2 and the upper insulation layer U-INS.

[0273] refer to Figure 29A The first dam layer DML1 and the second dam layer DML2 can be arranged on the same layer as the upper insulation layer U-INS. The first dam layer DML1, the second dam layer DML2 and the upper insulation layer U-INS can be formed concurrently (e.g., simultaneously) from the same material.

[0274] By reference Figure 19B In the described dry etching process, the first upper surface US1 of the third insulating encapsulation layer EN3, exposed by the groove GV, the first dummy groove DGV1, and the second dummy groove DGV2, can have a first surface roughness. The second upper surface US2 of the third insulating encapsulation layer EN3, covered by the first dam layer DML1, the second dam layer DML2, and the upper insulating layer U-INS, can have a second surface roughness. The first surface roughness is greater than the second surface roughness.

[0275] refer to Figure 29B After cutting, the unit panel U-PN can be separated through the unit cutting line U-CL to form the display panel DP. A first dam layer DML1 and a second dam layer DML2 can be disposed on the display panel DP, and the first dam layer DML1 and the second dam layer DML2 can be spaced apart and / or separated from the edge of the display panel DP (e.g., spaced apart or separated). The first dam layer DML1 and the second dam layer DML2 can be disposed between the edge of the display panel DP and the upper insulating layer U-INS. The second dam layer DML2 can be disposed between the first dam layer DML1 and the upper insulating layer U-INS.

[0276] Figure 30 The configuration on a unit panel according to one or more embodiments of the present disclosure is shown.

[0277] As an example, Figure 30 Shown as with Figure 28 The corresponding floor plan. This will be described below. Figure 30 The components shown in the image, with particular attention to those related to... Figure 28 The components shown are different components.

[0278] refer to Figure 30 The second dam layer DML2' can be arranged adjacent to the first side S1', third side S3', and fourth side S4' of the upper insulation layer U-INS. Multiple dummy dam layers DDML can be arranged between the second side S2' of the upper insulation layer U-INS and the first dam layer DML1. The dummy dam layers DDML can be arranged on the second direction DR2.

[0279] According to one or more embodiments of this disclosure, the side surface of the upper insulating layer of the input sensing unit may be spaced apart and / or separated from the edge of the display panel (e.g., spaced apart or separated), and a cover layer may be disposed on the display panel to cover the side surface of the upper insulating layer. Because the cover layer absorbs external impacts, the external impacts applied to the upper insulating layer can be reduced.

[0280] For example, the side surface of the upper insulating layer of the input sensing unit can be separated from the edge of the display panel, and a cover layer can be disposed on the display panel to cover the side surface of the upper insulating layer. Because the cover layer absorbs external impacts, the impact applied to the upper insulating layer can be reduced.

[0281] Furthermore, the insulating layer disposed beneath the upper insulating layer can extend to the edge of the substrate, and the surface roughness of the first upper surface of the insulating layer not covered by the upper insulating layer can be improved via a dry etching process. When the cover layer contacts the first upper surface with the improved surface roughness, the adhesion between the cover layer and the first upper surface can be improved. Accordingly, because the cover layer is more firmly attached to the insulating layer, the cover layer and the insulating layer can be prevented from separating from each other due to external impacts.

[0282] Furthermore, the arrangement of the aforementioned insulating and cover layers ensures that the display device can more effectively withstand external impacts. By separating the upper insulating layer from the edge of the substrate and increasing the surface roughness of the exposed insulating layer, the adhesion between the cover layer and the insulating layer is enhanced. This configuration prevents or reduces layer delamination and separation, thereby improving the durability and reliability of the display device.

[0283] In this disclosure, expressions such as “at least one of,” “one of,” and “selected from…” modify the entire list of elements but not individual elements in the list, whether before or after the list of elements. For example, “at least one of a, b, and c,” “selected from at least one of a, b, and c,” “selected from at least one of a to c,” etc., can mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0284] As used herein, the terms “substantially,” “approximately,” “roughly,” or similar terms are used as approximate terms and not as terms of degree, and are intended to take into account the inherent biases of measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” or “roughly” as used herein includes the value and means within an acceptable range of deviation for that particular value as determined by one of ordinary skill in the art. For example, “approximately” or “roughly” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, or ±5% of the value.

[0285] Those skilled in the art will understand that, in view of the whole of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole and may be technically linked and operated in a variety of suitable ways, and each embodiment may be implemented independently or in combination with each other in any suitable way, unless otherwise stated or implied.

[0286] The light-emitting elements, display panels, display devices, electronic devices / apparatus, device manufacturing equipment, or any other related devices / apparatus or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of the device can be formed on an integrated circuit (IC) chip or on a discrete IC chip. Furthermore, various components of the device can be implemented on a flexible printed circuit film, a tape-on-a-chip (TCP), a printed circuit board (PCB), or can be formed on a substrate. Additionally, various components of the device can be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components to perform the various functions described herein. The computer program instructions can be stored in a memory that can be implemented in a computing device using standard memory devices (e.g., random access memory (RAM)). The computer program instructions can also be stored in other non-transitory computer-readable media (e.g., CD-ROMs or flash drives). Furthermore, those skilled in the art will recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices without departing from the scope of the embodiments of this disclosure.

[0287] Although the foregoing has been described with reference to exemplary embodiments of the present disclosure, those skilled in the art or of ordinary skill in the art will understand that one or more suitable modifications and changes may be made to the present disclosure without departing from the spirit and technical scope of the present disclosure as described in the claims.

[0288] Accordingly, the technical scope of this disclosure should not be limited to the content described in the detailed description of this disclosure, but should be determined by the claims and their equivalents.

Claims

1. A display device, comprising: substrate; Multiple lower insulating layers are present on the substrate; Light-emitting elements are located on the plurality of lower insulating layers; An encapsulation layer is provided on the light-emitting element, the encapsulation layer comprising a plurality of insulating encapsulation layers; A substrate insulating layer is present on the encapsulation layer; A conductive pattern is formed on the substrate insulating layer; as well as Upper insulating layer, on the conductive pattern, in: The upper insulating layer is spaced apart from the edge of the substrate; At least one insulating layer selected from the plurality of lower insulating layers, the plurality of insulating encapsulation layers, and the substrate insulating layer extends to the edge of the substrate; and The first surface roughness of the first upper surface of the at least one insulating layer that is exposed upward by the upper insulating layer but not covered by the upper insulating layer is greater than the second surface roughness of the second upper surface of the at least one insulating layer that is covered by the upper insulating layer.

2. The display device according to claim 1, further comprising: Covering layer, on the upper insulating layer, The cover layer extends to the edge of the substrate.

3. The display device according to claim 2, wherein, The covering layer is in contact with the first upper surface.

4. The display device according to claim 2, wherein, Each of the upper insulating layer and the cover layer includes an organic insulating layer.

5. The display device according to claim 1, wherein, The difference between the first surface roughness and the second surface roughness is 10 nm to 70 nm.

6. The display device according to claim 5, wherein, The first surface roughness is 30 nm to 70 nm, and the second surface roughness is 1 nm to 20 nm.

7. The display device according to claim 1, further comprising: A transistor is located between the plurality of lower insulating layers and connected to the light-emitting element.

8. The display device according to claim 1, wherein: The plurality of lower insulating layers and the encapsulation layer extend to the edge of the substrate; The base insulating layer is spaced apart from the edge of the substrate and overlaps with the upper insulating layer; and The edge of the base insulating layer overlaps with the edge of the upper insulating layer.

9. The display device according to claim 8, further comprising: Touch the insulating layer, on the substrate insulating layer, The conductive pattern includes: First conductive pattern; and The second conductive pattern is on top of the first conductive pattern, and in: The touch insulating layer is on the first conductive pattern; The second conductive pattern is on the touch insulating layer; The upper insulating layer is on the second conductive pattern; The touch insulating layer is spaced apart from the edge of the substrate and overlaps with the upper insulating layer; and The edge of the touch insulating layer overlaps with the edge of the upper insulating layer.

10. The display device according to claim 8, wherein, The uppermost insulating encapsulation layer among the plurality of insulating encapsulation layers includes the first upper surface and the second upper surface.

11. The display device according to claim 8, wherein, The plurality of insulating encapsulation layers include: First insulating encapsulation layer; A second insulating encapsulation layer is disposed on the first insulating encapsulation layer; and A third insulating encapsulation layer is formed on top of the second insulating encapsulation layer, and The second insulating encapsulation layer includes an organic insulating layer, and the first insulating encapsulation layer and the third insulating encapsulation layer each include an inorganic insulating layer.

12. The display device according to claim 11, wherein: The first insulating encapsulation layer and the third insulating encapsulation layer extend to the edge of the substrate; and The third insulating encapsulation layer includes the first upper surface and the second upper surface.

13. The display device according to claim 11, wherein: The first insulating encapsulation layer extends to the edge of the substrate; The first insulating encapsulation layer includes the first upper surface and the second upper surface; The third insulating encapsulation layer is spaced apart from the edge of the substrate and overlaps with the upper insulating layer; and The edge of the third insulating encapsulation layer overlaps with the edge of the upper insulating layer.

14. The display device according to claim 8, wherein, Each of the plurality of lower insulating layers and the base insulating layer includes an inorganic insulating layer.

15. The display device according to claim 1, wherein, The distance between the edge of the substrate and the edge of the upper insulating layer is 40 μm to 120 μm.

16. The display device according to claim 1, wherein, The substrate insulating layer extends to the edge of the substrate and includes the first upper surface and the second upper surface.

17. The display device according to claim 1, wherein: A lower insulating layer selected from one of the plurality of lower insulating layers extends to the edge of the substrate and includes the first upper surface and the second upper surface; The insulating layer disposed on one of the plurality of lower insulating layers, the plurality of insulating encapsulation layers and the base insulating layer are spaced apart from the edge of the substrate and overlap with the upper insulating layer; and The edge of the insulating layer disposed on the lower insulating layer overlaps with the edge of the upper insulating layer.

18. The display device according to claim 1, further comprising: A dummy insulating layer is provided, located between the upper insulating layer and the lower side of the substrate in the plan view. in: The dummy insulating layer and the upper insulating layer are arranged on the same layer; The groove is defined between the dummy insulating layer and the upper insulating layer; and The third surface roughness of the third upper surface of the at least one insulating layer exposed by the groove is equal to the first surface roughness and greater than the second surface roughness.

19. The display device according to claim 1, further comprising: At least one dam layer is located between the edge of the substrate and the upper insulating layer. Wherein, the at least one dam layer is on the same layer as the upper insulating layer; The dummy groove is defined between the at least one dam layer and the upper insulating layer; and The upper surface of the at least one insulating layer exposed by the dummy groove has the first surface roughness.

20. The display device according to claim 1, wherein, The first upper surface is surface treated by a dry etching process.

21. A display device, comprising: substrate; Multiple lower insulating layers are present on the substrate; Light-emitting elements are located on the plurality of lower insulating layers; An encapsulation layer is provided on the light-emitting element and includes multiple insulating encapsulation layers; A substrate insulating layer is present on the encapsulation layer; A conductive pattern is formed on the substrate insulating layer; as well as Upper insulating layer, on the conductive pattern, in: The upper insulating layer, the plurality of lower insulating layers, the plurality of insulating encapsulation layers, and the base insulating layer are spaced apart from the edge of the substrate; The edges of the upper insulating layer, the plurality of lower insulating layers, the plurality of insulating encapsulation layers, and the base insulating layer overlap with each other; and The first surface roughness of the first upper surface of the substrate that is exposed upward by the upper insulating layer but not covered by the upper insulating layer is greater than the second surface roughness of the second upper surface of the substrate that is covered by the upper insulating layer.

22. The display device according to claim 21, further comprising: Covering layer, on the upper insulating layer, The cover layer extends to the edge of the substrate and contacts the first upper surface.

23. An electronic device comprising: The display device according to any one of claims 1 to 22; as well as A processor for processing image signals and providing the processed image signals to the display device.

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