Method for forming photoresist layer and semiconductor structure

Abstract

The application provides a photoresist layer forming method. A bottom photoresist sacrificial layer and a planarization layer are formed on a substrate. A first trimming process is performed to remove a first width of the planarization layer. A second trimming process is performed to remove a second width of the planarization layer. The first width and the second width are summed to be a target width. An exposure processing process is performed to remove the exposed bottom photoresist sacrificial layer. A third trimming process is performed to remove the residual planarization layer within the target width. A target photoresist layer is formed. The application has an unexpected effect. The bottom photoresist sacrificial layer and the multi-step trimming process can effectively improve the trimming defects of the planarization layer material, effectively improve the process stability, effectively improve the etching stability, reduce the risk of machine contamination, prolong the service life of the machine, effectively reduce the edge defects, and have important significance for improving the process yield.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a method for forming a photoresist layer and a semiconductor structure. Background Technology

[0002] In the photolithography process, edge removal of the photoresist is a crucial step, primarily aimed at removing excess photoresist from the wafer edges. Currently, this is mainly achieved through two methods: EBR (edge ​​bead removal) and WEE (wafer edge exposure). Edge removal of the photoresist offers several advantages: 1) It prevents the peeling off of accumulated photoresist at the edges, forming particles that contaminate the pattern and cause defects; 2) Removing the accumulated photoresist at the edges improves the difference between the wafer center (W / C) and the wafer edge (W / E) during etching, enhancing etching stability; 3) It avoids contaminating the equipment structure with accumulated photoresist at the edges, increasing equipment lifespan and reducing maintenance costs.

[0003] With the evolution of process technology, in addition to photoresist, materials used in photolithography, such as SOC (Spin-On Carbon), SOG (Spin-On Glass), and BARC (Bottom Anti-Reflective Coating), all require edge trimming. These materials cannot produce photosensitive reactions and therefore require EBR (Electrical Brush Removal) etching. However, for some thicker materials, the instability and incompleteness of the chemical reaction often lead to defects such as edge marks and burrs. This not only increases the risk of residue falling off but also causes etching instability. Currently, extending the trimming time and adjusting the rotation speed are mainly used to improve these situations, but this has little effect on very thick (usually referring to thicknesses greater than 2000 angstroms) spin-coated carbon materials. Summary of the Invention

[0004] The purpose of this invention is to provide a method for forming a photoresist layer and a semiconductor structure to reduce defects such as edge marks and burrs in the EBR chemical etching process of extra-thick spin-coated carbon materials.

[0005] To solve the above-mentioned technical problems, the present invention provides a method for forming a photoresist layer, comprising:

[0006] A substrate is provided on which a bottom photoresist sacrificial layer is formed;

[0007] A planarization layer is formed, which covers the bottom photoresist sacrificial layer;

[0008] Perform the first edge washing process to remove the planarization layer of the first width;

[0009] Perform a second edge washing process to remove the planarization layer of the second width, where the sum of the first width and the second width is the target width;

[0010] Perform an edge exposure process to remove the exposed bottom photoresist sacrificial layer;

[0011] A third edge washing process is performed to remove the planarization layer remaining within the target width from the edge of the substrate;

[0012] A target photoresist layer is formed, which covers the top surface of the substrate, the sidewalls of the bottom photoresist sacrificial layer, and the top surface and sidewalls of the planarization layer.

[0013] Optionally, the material of the bottom photoresist sacrificial layer is photosensitive adhesive.

[0014] Optionally, the material of the bottom photoresist sacrificial layer is at least one of I-line, krF, and ArF.

[0015] Optionally, the solutions used in the first, second, and third edge washing processes are photoresist diluents.

[0016] Optionally, the first width is 40% to 70% of the target width, and the second width is 30% to 60% of the target width.

[0017] Optionally, the material of the planarization layer is a spin-coated carbon layer.

[0018] Optionally, the thickness of the bottom photoresist sacrificial layer is 5% to 20% of the thickness of the planarization layer.

[0019] Optionally, the step of forming the target photoresist layer includes:

[0020] A spin-coated photoresist layer is provided, which covers the exposed top surface of the substrate, the sidewalls of the bottom photoresist sacrificial layer, and the top surface and sidewalls of the planarization layer.

[0021] An edge exposure process is performed to remove the photoresist layer material layer on the substrate at a distance of the width from the edge of the substrate, and the remaining photoresist layer material layer constitutes the target photoresist layer.

[0022] Optionally, removing the bottom photoresist sacrificial layer at the target width from the edge of the substrate includes:

[0023] An exposure process is performed to expose the bottom photoresist sacrificial layer at a target width from the edge of the substrate;

[0024] A developing process is performed in which the bottom photoresist sacrificial layer, at a distance of the target width from the edge of the substrate, is dissolved by a developing solution to remove the bottom photoresist sacrificial layer at a distance of the target width from the edge of the substrate.

[0025] Based on the same inventive concept, the present invention also provides a semiconductor structure, prepared by the method for forming a photoresist layer as described in any one of the above claims, comprising:

[0026] Substrate;

[0027] A bottom photoresist sacrificial layer, wherein the bottom photoresist sacrificial layer is located on the substrate and covers the top surface of the substrate;

[0028] A planarization layer, which covers the bottom photoresist sacrificial layer, has the same width as the bottom photoresist sacrificial layer;

[0029] A target photoresist layer, which covers the top surface of the substrate, the sidewalls of the bottom photoresist sacrificial layer, and the top surface and sidewalls of the planarization layer.

[0030] In the photoresist layer formation method provided by this invention, a first edge washing process is performed to remove a planarization layer of a first width, a second edge washing process is performed to remove a planarization layer of a second width, the sum of the first width and the second width is the target width, then an edge exposure process is performed to remove the exposed bottom photoresist sacrificial layer, and then a third edge washing process is performed to remove the planarization layer remaining within the target width from the edge of the substrate, and finally the target photoresist layer is formed. An unexpected effect of this invention is that by constructing a bottom photoresist sacrificial layer and using a multi-step edge washing process, edge washing defects in the planarization layer material are effectively improved, effectively enhancing process stability; furthermore, reducing edge washing defects can effectively improve etching stability and reduce the risk of equipment contamination, extending equipment lifespan; and effectively reducing edge removal defects is of great significance for improving process yield. Attached Figure Description

[0031] Figure 1 This is a flowchart of the method for forming a photoresist layer according to an embodiment of the present invention.

[0032] Figure 2 This is a schematic diagram of the semiconductor structure after the bottom photoresist sacrificial layer is formed according to an embodiment of the present invention.

[0033] Figure 3 This is a schematic diagram of the semiconductor structure after the planarization layer is formed according to an embodiment of the present invention.

[0034] Figure 4 This is a schematic diagram of the semiconductor structure after the first edge washing process in an embodiment of the present invention.

[0035] Figure 5 This is a schematic diagram of the semiconductor structure after the second edge washing process in an embodiment of the present invention.

[0036] Figure 6 This is a schematic diagram of the semiconductor structure in the edge exposure process of this invention.

[0037] Figure 7 This is a schematic diagram of the semiconductor structure after the edge exposure process is performed according to an embodiment of the present invention.

[0038] Figure 8 This is a schematic diagram of the semiconductor structure after the third edge washing process in an embodiment of the present invention.

[0039] Figure 9 This is a schematic diagram of the semiconductor structure after the formation of the photoresist layer material layer according to an embodiment of the present invention.

[0040] Figure 10 This is a schematic diagram of the semiconductor structure after the formation of the target photoresist layer according to an embodiment of the present invention.

[0041] Figure 11 This is a test diagram of the semiconductor structure according to an embodiment of the present invention.

[0042] In the figure: 10-substrate; 11-bottom photoresist sacrificial layer; 12-planarization layer; 12a-residual planarization layer; 13-target photoresist layer; 13a-photoresist material layer. Detailed Implementation

[0043] The method for forming the photoresist layer and the semiconductor structure proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, used only to facilitate and clarify the illustration of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different proportions may be used in different drawings to illustrate different aspects.

[0044] Figure 1 This is a flowchart of a method for forming a photoresist layer according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for forming a photoresist layer, including:

[0045] Step S10: Provide a substrate on which a bottom photoresist sacrificial layer is formed;

[0046] Step S20: A planarization layer is formed, which covers the bottom photoresist sacrificial layer;

[0047] Step S30: Perform the first edge washing process to remove the planarization layer of the first width;

[0048] Step S40: Perform a second edge washing process to remove the planarization layer of the second width. The sum of the first width and the second width is the target width.

[0049] Step S50: Perform an edge exposure process to remove the exposed bottom photoresist sacrificial layer;

[0050] Step S60: Perform a third edge washing process to remove the planarization layer remaining within the target width of the substrate edge;

[0051] Step S70: Form a target photoresist layer, which covers the top surface of the substrate, the sidewalls of the bottom photoresist sacrificial layer, and the top surface and sidewalls of the planarization layer.

[0052] Figures 2 to 10 This is a schematic diagram of the structural steps corresponding to the formation method of a photoresist layer according to an embodiment of the present invention. To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the following description is provided in conjunction with the appendix to the specification. Figures 2 to 10 Specific embodiments of the present invention will be described in detail below.

[0053] Figure 2 This is a schematic diagram of the semiconductor structure after forming the bottom photoresist sacrificial layer according to an embodiment of the present invention. The following is in conjunction with... Figure 2 Step S10 will be described in detail. For example... Figure 2 As shown, in step S10, a substrate 10 is provided, and a bottom photoresist sacrificial layer 11 is formed on the substrate 10. The material of the bottom photoresist sacrificial layer 11 is, for example, photosensitive adhesive. The material of the bottom photoresist sacrificial layer 11 can be at least one of I-line, krF, and ArF. Preferably, the bottom photoresist sacrificial layer 11 has different photosensitive wavelengths. In this embodiment, the thickness of the bottom photoresist sacrificial layer is 5% to 20% of the thickness of the subsequently formed planarization layer. The photosensitive wavelength of the bottom photoresist sacrificial layer 11 is 193nm to 365nm.

[0054] Figure 3 This is a schematic diagram of the semiconductor structure after the planarization layer is formed, according to an embodiment of the present invention. The following is combined with... Figure 3 Step S20 will be described in detail. For example... Figure 3As shown, in step S20, a planarization layer 12 is formed, which covers the bottom photoresist sacrificial layer 11. The material of the planarization layer 12 is, for example, a spin-on carbon (SOC) layer. The planarization layer 12 is a thick film, with a thickness of, for example, 1500 angstroms to 6000 angstroms. The spin-on carbon layer not only planarizes the surface but also assists in anti-reflection. For example, when the bottom photoresist sacrificial layer 11 has topological undulations due to the underlying circuit structure, the planarization layer 12 fills the depressions through its fluidity and filling properties, forming a flat surface and reducing focal length differences after photoresist coating. This is crucial for patterning high aspect ratio structures. Furthermore, the light absorption properties of the planarization layer 12 can reduce reflected light from the underlying layer, helping to suppress standing wave effects and improve exposure uniformity.

[0055] Figure 4 This is a schematic diagram of the semiconductor structure after the first edge-washing process according to an embodiment of the present invention. The following is in conjunction with... Figure 4 Step S30 will be described in detail. For example... Figure 4 As shown, in step S30, a first edge-washing process is performed to remove the planarization layer 12 at a distance of a first width W1 from the edge of the substrate 10. The solution for the first edge-washing process is preferably a photoresist diluent. For example, the photoresist diluent for the first edge-washing process is OK-73 solvent. OK-73 solvent, as referred to herein, is an organic solvent mixture specifically designed for high-precision cleaning, whose main components include, for example, propylene glycol monomethyl ether and propylene glycol methyl ether acetate, with a volume ratio of, for example, 7:3. The first width W1 is 40% to 70% of the target width. After the first edge-washing process, a residual planarization layer 12a remains within the range of the first width W1 from the edge of the substrate 10.

[0056] Figure 5 This is a schematic diagram of the semiconductor structure after the second edge-washing process according to an embodiment of the present invention. The following is in conjunction with... Figure 5 Step S40 will be described in detail. For example... Figure 5 As shown, in step S40, a second edge-washing process is performed to remove the planarization layer 12 of the second width W2. The sum of the first width W1 and the second width W2 is the target width W. The solution for the second edge-washing process is, for example, a photoresist diluent. The photoresist diluent for the second edge-washing process is, for example, OK-73 solvent. The second width W2 is 30% to 60% of the target width W. After the second edge-washing process, a residual planarization layer 12a remains within the range of the second width W2.

[0057] Figure 6 This is a schematic diagram of the semiconductor structure in the edge exposure process of this invention. Figure 7This is a schematic diagram of the semiconductor structure after the edge exposure process is performed according to an embodiment of the present invention. The following is in conjunction with... Figure 6 and Figure 7 Step S50 will be described in detail. For example... Figure 6 and Figure 7 As shown, in step S50, an edge exposure process is performed to remove the bottom photoresist sacrificial layer 11 at a distance of the target edge width W from the substrate 10. In a specific embodiment, the step of removing the bottom photoresist sacrificial layer 11 at a distance of the target edge width W from the substrate 10 includes: firstly, as... Figure 6 As shown, an exposure process is performed to expose the bottom photoresist sacrificial layer 11 at a target width W from the edge of the substrate 10; then, as... Figure 7 As shown, during the development process, the portion of the bottom photoresist sacrificial layer 11 that is exposed at a distance of the target width W from the edge of the substrate 10 is dissolved by the developing solution, thereby removing this portion of the bottom photoresist sacrificial layer 11, that is, removing the bottom photoresist sacrificial layer 11 at a distance of the target width W from the edge of the substrate 10.

[0058] Figure 8 This is a schematic diagram of the semiconductor structure after the third edge-washing process according to an embodiment of the present invention. The following is in conjunction with... Figure 7 and Figure 8 Step S60 will be described in detail. For example... Figure 7 and Figure 8 As shown, in step S60, a third edge washing process is performed to remove the planarization layer 12a remaining within the target width W of the edge from the substrate 10. The solution for the third edge washing process is, for example, a photoresist diluent. The photoresist diluent for the third edge washing process is, for example, OK-73 solvent. The washing width for the third edge washing process is the target width W.

[0059] It is understood that the multiple edge washing process of this application can effectively improve the edge washing defects of thick film SOC materials and effectively improve the process stability; the reduction of edge washing defects effectively improves etching stability and reduces the risk of machine contamination, extending the service life of the machine; and effectively reduces edge removal defects, which is of great significance to improving process yield.

[0060] Figure 9 This is a schematic diagram of the semiconductor structure after the formation of the photoresist layer material layer according to an embodiment of the present invention. Figure 10 This is a schematic diagram of the semiconductor structure after the formation of the target photoresist layer according to an embodiment of the present invention. (Combined with...) Figure 9 and Figure 10 Step S70 will be described in detail. For example... Figure 9 and Figure 10As shown, in step S70, a target photoresist layer 13 is formed, which covers the top surface of the substrate, the sidewalls of the bottom photoresist sacrificial layer 11, and the top surface and sidewalls of the planarization layer 12. The steps for forming the target photoresist layer include: Figure 9 As shown, a spin-coated photoresist layer 13a is applied, which covers the top surface of the exposed substrate 10, the sidewalls of the bottom photoresist sacrificial layer 11, and the top surface and sidewalls of the planarization layer 12. Figure 10 As shown, an edge exposure process is performed to remove the photoresist material layer 13a on the substrate 10 from the edge portion of the substrate 10, and the remaining photoresist material layer 13a constitutes the target photoresist layer 13.

[0061] Please continue to refer to this. Figure 10 The present invention also provides a semiconductor structure comprising:

[0062] Substrate 10;

[0063] A bottom photoresist sacrificial layer 11 is located on the substrate 10 and covers the top surface of the substrate 10;

[0064] A planarization layer 12 is located on the bottom photoresist sacrificial layer 11. The width of the planarization layer 12 is the same as the width of the bottom photoresist sacrificial layer 11. In other words, the width of the planarization layer 12 from the edge of the substrate is the same as the width of the bottom photoresist sacrificial layer 11 from the edge of the substrate.

[0065] The target photoresist layer 13 covers the top surface of the substrate, the sidewalls of the bottom photoresist sacrificial layer 11, and the top surface and sidewalls of the planarization layer 12.

[0066] The applicant used the photoresist layer formation method provided in this embodiment to prepare a semiconductor structure. The thickness of the planarization layer was, for example, 2000 angstroms, and the edge width design value was, for example, 2.0 mm. The semiconductor structure was measured, and the measurement results are shown in Table 1.

[0067] Table 1 Actual measured values ​​of trimmed width

[0068]

[0069] As shown in Table 1, the actual measured values ​​of the edge removal width meet the design values ​​for process error and measurement error. Figure 11 This is a test diagram of the semiconductor structure according to an embodiment of the present invention. Figure 11 As shown, the experiment in this embodiment obtained the edge washing state in which the edge defects of the substrate 10 disappeared (free).

[0070] In summary, in the photoresist layer formation method provided in this embodiment of the invention, a first edge washing process is performed to remove a planarization layer of a first width, a second edge washing process is performed to remove a planarization layer of a second width, the sum of the first width and the second width is the target width, then an edge exposure process is performed to remove the exposed bottom photoresist sacrificial layer, and then a third edge washing process is performed to remove the planarization layer remaining within the target width from the edge of the substrate, and finally the target photoresist layer is formed. The unexpected effect of this invention is that by constructing a bottom photoresist sacrificial layer and using a multi-step edge washing process, edge washing defects in the planarization layer material are effectively improved, effectively enhancing process stability; furthermore, reducing edge washing defects can effectively improve etching stability and reduce the risk of equipment contamination, extending equipment lifespan; and effectively reducing edge removal defects is of great significance for improving process yield.

[0071] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0072] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for forming a photoresist layer, characterized in that, include: A substrate is provided on which a bottom photoresist sacrificial layer is formed; A planarization layer is formed, which covers the bottom photoresist sacrificial layer; Perform the first edge washing process to remove the planarization layer of the first width; Perform a second edge washing process to remove the planarization layer of the second width, where the sum of the first width and the second width is the target width; Perform an edge exposure process to remove the exposed bottom photoresist sacrificial layer; A third edge washing process is performed to remove the planarization layer remaining within the target width from the edge of the substrate; A target photoresist layer is formed, which covers the top surface of the substrate, the sidewalls of the bottom photoresist sacrificial layer, and the top surface and sidewalls of the planarization layer.

2. The method for forming a photoresist layer as described in claim 1, characterized in that, The material of the bottom photoresist sacrificial layer is photosensitive emulsion.

3. The method for forming a photoresist layer as described in claim 2, characterized in that, The material of the bottom photoresist sacrificial layer is at least one of I-line, krF, and ArF.

4. The method for forming a photoresist layer as described in claim 1, characterized in that, The solutions used in the first, second, and third edge washing processes are photoresist diluents.

5. The method for forming a photoresist layer as described in claim 1, characterized in that, The first width is 40% to 70% of the target width, and the second width is 30% to 60% of the target width.

6. The method for forming a photoresist layer as described in claim 1, characterized in that, The material of the planarization layer is a spin-coated carbon layer.

7. The method for forming a photoresist layer as described in claim 1, characterized in that, The thickness of the bottom photoresist sacrificial layer is 5% to 20% of the thickness of the planarization layer.

8. The method for forming a photoresist layer as described in claim 1, characterized in that, The steps for forming the target photoresist layer include: A spin-coated photoresist layer is provided, which covers the exposed top surface of the substrate, the sidewalls of the bottom photoresist sacrificial layer, and the top surface and sidewalls of the planarization layer. An edge exposure process is performed to remove the photoresist layer material layer on the substrate at a distance of the width from the edge of the substrate, and the remaining photoresist layer material layer constitutes the target photoresist layer.

9. The method for forming a photoresist layer as described in claim 1, characterized in that, Removing the bottom photoresist sacrificial layer from the target width at the edge of the substrate includes: An exposure process is performed to expose the bottom photoresist sacrificial layer at a target width from the edge of the substrate; A developing process is performed in which the bottom photoresist sacrificial layer, at a distance of the target width from the edge of the substrate, is dissolved by a developing solution to remove the bottom photoresist sacrificial layer at a distance of the target width from the edge of the substrate.

10. A semiconductor structure, characterized in that, It is prepared by the method for forming a photoresist layer as described in any one of claims 1 to 9, including Substrate; A bottom photoresist sacrificial layer, wherein the bottom photoresist sacrificial layer is located on the substrate and covers the top surface of the substrate; A planarization layer, which covers the bottom photoresist sacrificial layer, has the same width as the bottom photoresist sacrificial layer; A target photoresist layer, which covers the top surface of the substrate, the sidewalls of the bottom photoresist sacrificial layer, and the top surface and sidewalls of the planarization layer.

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