Semiconductor package and method of forming the same

Abstract

In one embodiment, a method includes forming an interconnect structure including a plurality of die regions separated by scribe lines, at least one of the plurality of die regions including a semiconductor substrate and a wiring structure on the semiconductor substrate, the wiring structure including an alignment mark adjacent to the scribe line. The method includes forming a passivation layer over the wiring structure. The method includes removing a portion of the passivation layer to expose the alignment mark. The method includes performing a singulation process to separate the interconnect structure into individual dies. Embodiments of the present application also disclose a semiconductor package and a method of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to a semiconductor package and a method for forming the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, this increase in integration density stems from iterative reductions in the minimum feature size, allowing more components to be integrated into a given area. As the demand for miniaturized electronics grows, so too does the need for smaller and more innovative semiconductor die-packaging technologies. Summary of the Invention

[0003] One aspect of this application provides a method for forming a semiconductor package, comprising: forming an interconnect structure including a plurality of die regions separated by scribe lines, at least one of the plurality of die regions including a semiconductor substrate and a wiring structure located on the semiconductor substrate, the wiring structure including alignment marks adjacent to the scribe lines; forming a passivation layer over the wiring structure; removing a portion of the passivation layer to expose the alignment marks; and performing a unitization process to separate the interconnect structure into individual dies.

[0004] Another aspect of this application provides a method for forming a semiconductor package, comprising: forming a passivation layer over a wiring structure of a die, the wiring structure being located on a semiconductor substrate, the wiring structure including a plurality of conductive layers and a plurality of dielectric layers, alignment marks, and a sealing ring structure; removing a portion of the passivation layer to form an opening exposing the alignment marks in a plan view; after exposing the alignment marks, forming a sealant that laterally seals the die and extends over the alignment marks; and forming a redistribution structure over the sealant, the redistribution structure being electrically connected to the wiring structure, the redistribution structure including conductors and conductive vias, wherein the conductors and the conductive vias include a copper-containing conductive layer, and wherein the conductors serve as signal lines, power lines, or ground lines.

[0005] Another aspect of this application provides a semiconductor package, the semiconductor package comprising:

[0006] An interconnect die, the interconnect die comprising: a semiconductor substrate having a first side and a second side opposite to the first side; a wiring structure located on the first side of the semiconductor substrate, the wiring structure including a plurality of metallization layers disposed among a plurality of dielectric layers, at least one of the metallization layers including a barrier layer adjoining one of the dielectric layers, and a fill metal spaced apart from the one of the dielectric layers by the barrier layer, wherein the conductivity of the barrier layer is lower than the conductivity of the fill metal, the wiring structure including a die region, a sealing ring structure, and alignment marks, the sealing ring structure including a wall-like metal member surrounding the die region of the wiring structure, the sealing ring structure including a material comprising a copper atomic percentage greater than 80%; a die connector located on the die region of the wiring structure; and a passivation layer laterally surrounding the die connector, the alignment marks being laterally spaced apart from the passivation layer; and

[0007] The semiconductor package also includes a sealant extending along the sidewall of the interconnect die, wherein, in a plan view, the area occupied by the sealant is larger than the area occupied by the interconnect die. Attached Figure Description

[0008] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0009] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 2C , Figure 3A , Figure 3B , Figure 4 , Figure 5A , Figure 5B ,and Figure 5C These are cross-sectional views and perspectives of intermediate stages in the fabrication of interconnect structures according to some embodiments;

[0010] Figures 6-7 , Figure 8A , Figure 8B ,and Figures 9-15 This is a cross-sectional view of an intermediate stage in the manufacturing of a semiconductor package according to some embodiments;

[0011] Figure 16A , Figure 16B ,and Figure 17 This is a cross-sectional view of an intermediate stage in the manufacturing of a semiconductor package according to some embodiments;

[0012] Figure 18A , Figure 18B ,and Figure 19 This is a cross-sectional view of an intermediate stage in the manufacturing of a semiconductor package according to some embodiments. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0015] The semiconductor industry continuously strives to improve the performance, reliability, and cost-effectiveness of integrated circuit packages. A crucial aspect of semiconductor packaging is the alignment of components during the assembly process. Accurate alignment is essential for ensuring proper electrical connections and overall package functionality. However, as semiconductor devices become smaller and more complex, achieving precise alignment becomes increasingly challenging.

[0016] A particular problem arises in the singletization of dies such as interconnect dies (also known as local silicon interconnect (LSI) dies). During the singletization process, where individual dies are separated from the wafer, the passivation layer at the die's dicing edge may be damaged or deformed. This damage affects the clarity of the alignment marks used to position the die during subsequent packaging steps. As a result, the alignment process becomes less reliable, leading to increased failure rates and reduced manufacturing yields.

[0017] This invention addresses this challenge by introducing a method for protecting and preserving alignment marks on a die. In some embodiments, the alignment marks are not covered by a passivation layer that typically protects the die surface. Instead, the alignment marks can be exposed through openings in the passivation layer. This exposure prevents the alignment marks from being affected during the individualization process due to any deformation or damage to the passivation layer.

[0018] To further protect the exposed alignment marks, some embodiments include an insulating layer formed over the alignment marks. This insulating layer can be composed of a material different from the passivation layer, such as benzocyclobutene (BCB), polyimide (PI), or polybenzoxazole (PBO). The use of different materials allows for specialized protection of the alignment marks while maintaining their visibility for alignment purposes.

[0019] The disclosed method offers several advantages in semiconductor packaging. By maintaining the clarity and integrity of alignment marks, the accuracy of die placement during the packaging process is significantly improved. This enhanced alignment accuracy enables better electrical connections, reduces failure rates, and improves overall package reliability. Furthermore, the improved alignment process allows for tighter manufacturing tolerances, potentially enabling further miniaturization of semiconductor packages.

[0020] Furthermore, the disclosed method is compatible with existing semiconductor manufacturing processes and can be easily integrated into current production lines. This compatibility ensures that the benefits of improved alignment can be achieved without requiring significant changes to established manufacturing workflows or equipment.

[0021] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 2C , Figure 3A , Figure 3B , Figure 4 , Figure 5A , Figure 5B ,and Figure 5C Cross-sectional and plan views of intermediate stages in the fabrication of interconnect structures according to some embodiments are shown. Figure 1A , Figure 2A ,and Figure 5A A cross-sectional view is shown at an intermediate stage in the fabrication of the interconnect structure. Figure 1B , Figure 2C , Figure 3B ,and Figure 5C A plan view showing an intermediate stage in the fabrication of the interconnect structure is shown. Figure 2B , Figure 3A , Figure 4 ,and Figure 5BA detailed cross-sectional view of an intermediate stage in the fabrication of the interconnect structure is shown.

[0022] exist Figure 1A and Figure 1B The diagram illustrates an interconnect structure 50 at an intermediate stage of processing. The interconnect structure 50 includes a semiconductor substrate 52 having a front side 52F and a back side 52B. A wiring structure 54 is formed on the front side 52F of the semiconductor substrate 52. The wiring structure 54 may include various interconnect patterns distributed on the interconnect structure 50. The interconnect structure 50 may be a wafer. It can be obtained or formed as shown in the diagram. Figure 1A and Figure 1B The interconnect structure 50 shown is shown.

[0023] The interconnect structure 50 is divided into multiple die regions 56, such as Figure 1B As shown in the diagram, each die region 56 can be surrounded by a sealing ring structure 58. The sealing ring structure 58 is a wall-like structure that surrounds the die region 56 of the wiring structure 54. The sealing ring structure 58 can provide protection for individual die regions 56 against moisture ingress and mechanical stress. Scribbles 60 can be formed between adjacent die regions 56. These scribbles 60 can define the boundaries where the interconnect structure 50 will separate into individual dies during subsequent processing steps.

[0024] A sealing ring structure 58 is disposed within the dielectric structure of the interconnect structure 50. It includes a plurality of conductors and conductive vias arranged to form a continuous barrier around the periphery of each die region 56. This arrangement helps prevent moisture and contaminants from penetrating into the active areas of the die. The conductors and vias of the sealing ring structure 58 can be formed during the same processing steps used to create the interconnect layer within the die region 56, thereby allowing for efficient integration into the manufacturing process.

[0025] In some embodiments, at least one conductive via in the sealing ring structure 58 is formed of a material comprising more than 80% copper. This high copper content helps ensure the integrity of the sealing ring structure. In some embodiments, the copper content may be even higher, with at least one conductive via formed of a material comprising more than 90% copper. This increased copper concentration can further improve the performance and reliability of the sealing ring structure.

[0026] Scribing line 60 is the area between adjacent die regions 56, designed to be cut or break during the separation of individual dies. The width of scribing line 60 can be determined based on factors such as the cutting method to be used, the required final die size, and the need to accommodate any potential damage during the individualization process.

[0027] In some cases, scribing 60 may be included in test structures used during manufacturing and packaging processes. These features aid in quality control; however, these structures are often damaged during the individualization process.

[0028] In some embodiments, the interconnect structure 50 may be an interposer and may not include active devices therein, although in some cases the interposer may include passive devices. In some embodiments, the interconnect structure 50 may include active devices (e.g., transistors or memory devices) formed in and / or on the front side of the semiconductor substrate 52 (e.g., the surface of the front side 52F of the semiconductor substrate 52). In some embodiments, the semiconductor substrate 52 may be a bulk semiconductor substrate, a semiconductor-on-insulator (SO1) substrate, a multilayer semiconductor substrate, etc. The semiconductor substrate 52 may include semiconductor materials, such as: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof in some cases. In some embodiments, other substrates, such as multilayer substrates or gradient substrates, may also be used.

[0029] Alignment mark 62 is located in sealing ring structure 58 and near scribe line 60, as shown. Figure 1A and Figure 1B As shown in both examples, alignment marks 62 can be formed at multiple locations along the periphery of the die region 56, with each alignment mark 62 located between adjacent sealing ring structures 58. In some cases, the alignment marks 62 can be hollow patterns, which can enhance their visibility during the alignment process. In some embodiments, the alignment marks are hollow square patterns (e.g., see...). Figure 1B However, other alignment mark designs, such as crosshair patterns, box-in-box patterns, etc., are also within the scope of this disclosure.

[0030] The wiring structure 54 disposed on the front side 52F of the semiconductor substrate 52 may include multilayer interconnect patterns. These interconnect patterns can facilitate electrical connections between various components within each die region 56 and can also provide connections to external devices.

[0031] Wiring structure 54 includes multilayer interconnect patterns (which may be referred to as interconnect layers) that facilitate electrical connections within the device. These interconnect patterns include metallization patterns 53 and dielectric layers 55. Metallization patterns 53 may be formed of a conductive material such as a metal that may be copper, cobalt, aluminum, gold, or combinations thereof, and are used to carry electrical signals throughout the device. Dielectric layers 55 electrically isolate the metallization patterns 53 from each other and may include materials such as oxides, nitrides, carbides, or combinations thereof. For example, dielectric materials may include silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or combinations thereof. In some embodiments, dielectric layer 55 may include a material that may be a polymer such as polybenzoxazole (PBO), polyimide, or benzocyclobutene (BCB)-based polymers. Metallization patterns 53 may include conductive vias and / or wires for interconnecting components. In some embodiments, wiring structure 54 may be formed by damascene processes, such as single damascene processes, dual damascene processes, or combinations thereof. In some embodiments, each metallization pattern 53 includes a metal line disposed in a dielectric layer 55, and at least one metal line includes a barrier layer (not shown separately) adjoining the dielectric layer 55, and a filler metal spaced apart from the dielectric layer 55 by the barrier layer. In some embodiments, the conductivity of the barrier layer is less than the conductivity of the filler metal of the metallization pattern 53. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc., while the filler metal may include copper, cobalt, aluminum, gold, etc.

[0032] The alignment marks 62 formed in the wiring structure 54 can be used in subsequent manufacturing processes. These alignment marks 62 can be used for positioning during die individualization, packaging, and integration with other components.

[0033] exist Figure 2A , Figure 2B ,and Figure 2C In this configuration, conductive components 66 and a passivation layer 68 are formed above the wiring structure 54. These conductive components 66 may include bonding pads, redistribution layers, or other structures that facilitate electrical connections to external devices or package assemblies. The conductive components 66 may be composed of a material similar to that used in the metallization pattern 53. In some embodiments, the conductive components 66 may be conductive pillars, conductive pads, or similar structures. The conductive components 66 may be formed using metals such as copper, aluminum, alloys thereof, or other suitable conductive materials. In some cases, the conductive components 66 may be formed by plating or other deposition techniques. In some embodiments, the conductive components 66 may be copper pillars.

[0034] A passivation layer 68 may be formed over the wiring structure 54 and cover the conductive component 66. The passivation layer 68 can be used to protect the underlying structure from environmental factors such as moisture and contaminants. In some cases, the passivation layer 68 may be a polymeric material, such as polyimide, PBO, BCB, combinations thereof, etc., and may be formed by CVD, coating, or any suitable technique. Alternatively, the passivation layer 68 may be a molding compound, which may include an epoxy resin with or without particulate fillers, and may be formed by compression molding, transfer molding, etc.

[0035] Figure 2B A more detailed cross-sectional view of a portion of the interconnect structure 50 is provided. (See figure.) Figure 2B As shown, a pad layer 64 is formed on top of the wiring structure 54. Conductive components 66 may be formed on the pad layer 64. Another portion of the pad layer 64 may be in the region of the sealing ring structure 58. In some embodiments, the pad layer 64 may be composed of a material such as aluminum, copper, or an alloy thereof.

[0036] Figure 2C A plan view showing the layout of multiple die regions 56 is shown. Each die region 56 is surrounded by a sealing ring structure 58, which provides mechanical strength and acts as a barrier against moisture and contaminants. Scribbles 60 are visible between the die regions 56, defining the areas where the wafer will be diced to separate individual dies.

[0037] Alignment marks 62 are located at the intersection of scribe lines 60. These alignment marks 62 help ensure accurate positioning during subsequent manufacturing processes such as die individualization and packaging. At this point in the process, passivation layer 68 extends beyond the alignment marks 62, but can then be patterned to expose certain areas, such as portions of the alignment marks 62 or conductive parts 66.

[0038] exist Figure 3A and Figure 3B In this process, the passivation layer is patterned to form an opening 72 to expose the alignment mark 62. This patterning process creates the opening 72 directly above the alignment mark 62 within the passivation layer 68. Alternatively, the opening 72 may also be positioned directly above the scribing line 60. In some embodiments, a photolithography process can be used to remove a portion of the passivation layer 68. In some cases, this process may involve applying a photoresist layer over the passivation layer 68, exposing the photoresist through a mask pattern, developing the photoresist to create an opening corresponding to the desired removal area, and then etching the exposed portion of the passivation layer 68.

[0039] Figure 3BA plan view of the interconnect structure 50 after exposing alignment marks 62 and optional scribe lines 60 is shown. An opening 72 in the passivation layer 68 allows direct access to the alignment marks 62. The exposed alignment marks 62 are located at the intersection of scribe lines 60 between the corners of adjacent die regions 56. In some embodiments, the opening 72 has an octagonal shape in the plan view, and the corners of the adjacent passivation layer 68 of the opening 72 are angled in the plan view. In embodiments where the scribe lines 60 are exposed, the opening 72 may have an octagonal shape provided by a geometric octagon that merges with the cross-shaped shape of the intersecting scribe lines 60.

[0040] The alignment mark 62 exposed through the opening 72 in the passivation layer 68 offers several benefits for subsequent manufacturing processes. The exposed alignment mark 62 provides improved visibility and contrast for alignment equipment, resulting in more accurate positioning during die individualization and packaging steps. Furthermore, by removing the passivation layer 68 over the alignment mark 62, any potential deformation or damage to the passivation layer 68 during individualization will not affect the clarity of the alignment mark 62.

[0041] In some cases, the exposed alignment marks 62 can allow for more precise alignment during subsequent packaging processes, such as when placing a single die on a carrier substrate, or when aligning multiple dies in a package-on-package configuration. Improved alignment accuracy can contribute to better electrical connectivity and overall package reliability. Additionally, in embodiments where the scribe line 60 is also exposed, subsequent individualization processes are not applied to the passivation layer 68. As a result, defects (e.g., deformation) in the passivation layer caused by the individualization process can be avoided.

[0042] Figure 4 A single-die separation process 78 is illustrated, separating individual interconnect dies 50A from interconnect structure 50. The single-die separation process 78 can be implemented using a combination of laser grooving and blade sawing. In some cases, laser grooving can be used to create an initial groove along scribing line 60. This initial groove can help guide subsequent blade sawing processes, potentially improving the accuracy of die separation.

[0043] The individual interconnect dies can then be separated using a blade sawing process. During this process, the sawing blade cuts along the scribing line 60, effectively separating the interconnect dies from each other.

[0044] By exposing the alignment mark 62 through the opening 72 in the passivation layer 68, the alignment mark 62 remains clearly visible even if the passivation layer 68 near the cut edge is damaged or deformed during the individualization process 78. In embodiments where the scribing 60 is also exposed through the opening 72, the individualization process 78 is not applied to the passivation layer 68, thus avoiding damage (e.g., deformation) to the passivation layer 68 and further improving the clarity of the alignment mark 62. This approach helps maintain the accuracy of subsequent alignment steps in the packaging process.

[0045] In some cases, the combination of laser grooving and blade sawing in the individualization process 78 can help minimize damage to the passivation layer 68 and other structures near the cut edge. This can further help maintain the integrity and visibility of the alignment marks 62, potentially improving overall alignment accuracy in subsequent manufacturing steps.

[0046] Figure 5A , Figure 5B ,and Figure 5C A single interconnect die 50A is shown. For example... Figure 5B As clearly shown, the sidewalls of the individualized interconnect die 50A (including the sidewalls of the semiconductor substrate 52 and the wiring structure 54) exhibit a non-planar and non-perpendicular profile relative to the main top (or main bottom) surface of the interconnect die 50A. This non-planar sidewall configuration is a feature caused by the individualization process, particularly by the combination of laser grooving and blade sawing described previously.

[0047] After individualization, the distance D1 from the sidewall of passivation layer 68 to the top of the sidewall of interconnect die 50A can be measured, such as... Figure 5B As shown in the diagram. In some embodiments, the distance D1 can be less than 20 micrometers. This dimensional characteristic represents the amount of die material extending beyond the edge of the passivation layer. Additionally, the sidewalls of the passivation layer 68 form an angle (θ) measured from the top surface of the wiring structure 54. In some embodiments, the angle θ is in the range of 70 to 90 degrees, which creates an outwardly sloping profile at the edge of the passivation layer.

[0048] The non-planar sidewall configuration of the interconnect die 50A includes different slopes and may contain micro-irregularities resulting from the sizing process. The sidewall profile may include multiple distinct regions with different roughness and tilt. The semiconductor substrate 52 region may exhibit one type of non-planar surface characteristic, while the wiring structure 54 region may exhibit different non-planar profiles due to different material compositions and their respective responses to the sizing process. In some embodiments, the sidewalls of the wiring structure 54 may have a different slope than the sidewalls of the semiconductor substrate 52. For example, in Figure 5BIn the specific embodiment shown, the slope of the sidewall of the wiring structure has at least a portion that has a slope value less than that of any portion of the sidewall of the semiconductor substrate 52.

[0049] Furthermore, non-planar sidewall configurations can occur at interfaces between different material layers, particularly at the interface between the semiconductor substrate 52 and the wiring structure 54, including microsteps or stair-like features. These micro-features are a result of varying material removal rates during the individualization process. The degree of non-planarity may vary around the periphery of the die, with corner regions potentially exhibiting more pronounced non-planar characteristics compared to straight edge regions.

[0050] Conversely, the individualization process may not be applied to the passivation layer 68. For example, as described above, the passivation layer 68 in the scribing region 60 can be removed by photolithography and etching. As a result, the sidewalls of the passivation layer 68 can be substantially planar and can have a different surface roughness than the non-planar sidewalls of the substrate 52 and / or wiring structure 54.

[0051] Figure 5C A plan view of interconnect die 50A is shown. Die region 56 is surrounded by sealing ring structure 58. Alignment marks 62 are located at each corner of die region 56. In some embodiments, a portion of scribe line 60 is retained at the edge of interconnect die 50A. Passivation layer edge 68E extends along the periphery of die region 56 and, in some embodiments, has an octagonal shape in the plan view (see [reference]). Figure 8B Alignment mark 62 is located between scribe line 60 at the corner of interconnect die 50A and passivation layer edge 68E.

[0052] The octagonal shape of the passivation layer edge 68E (see...) Figure 8B The octagonal shape offers advantages over other patterns (such as rectangles or circles). This geometry improves stress distribution at the corners, reducing the likelihood of delamination or cracking during thermal cycling. The octagonal design also provides improved alignment visibility by creating distinct reference points, while maintaining structural integrity. Furthermore, the octagonal pattern helps minimize edge chipping during individualization processes by avoiding sharp 90-degree angles that could lead to stress concentration and material failure.

[0053] Alignment marks 62 in interconnect die 50A can be exposed through openings in passivation layer 68. This exposure allows for improved visibility and accuracy during subsequent alignment processes. Exposed alignment marks 62 are less prone to deformation or damage, whereas they could be deformed or damaged if covered by passivation layer 68. Exposed alignment marks 62 enable more precise positioning during packaging processes, potentially improving electrical connectivity and overall package reliability.

[0054] Figures 6-15 A cross-sectional view is shown of an intermediate stage in the manufacture of a semiconductor package 100 according to some embodiments.

[0055] Figure 6 A cross-sectional view of a semiconductor package 100 during an intermediate stage of assembly is shown. The semiconductor package 100 includes a carrier substrate 102, which serves as a substrate structure for subsequent processing steps. A release layer 104 is disposed on the carrier substrate 102, extending on the upper surface of the carrier substrate 102. In later manufacturing stages, the release layer 104 can facilitate the separation of the completed package from the carrier substrate 102.

[0056] The release layer 104 may be formed of a polymer-based material, which can be removed together with the carrier substrate 102 from the overlay structure to be formed in subsequent steps. In some embodiments, the release layer 104 is an epoxy-based thermally release material that loses its adhesiveness upon heating, such as a photothermal conversion (LTHC) release coating. In other embodiments, the release layer 104 may be a UV adhesive that loses its adhesiveness upon exposure to UV light. The release layer 104 may be dispensed as a liquid and cured, and may be a laminated film laminated onto the carrier substrate 102, or the like.

[0057] A metallization pattern 110 is formed on the release layer 104. The metallization pattern 110 may include various conductive traces and pads that provide electrical connections within the semiconductor package 100. In some embodiments, the metallization pattern 110 may be formed using photolithography and etching processes to create the desired conductive pattern.

[0058] As an example of forming the metallization pattern 110, a seed layer is formed above the release layer 104. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD). Photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 110. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. The photoresist, as well as the portions of the seed layer on which no conductive material is formed, are then removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer can be removed, for example, by using an acceptable etching process, such as wet etching or dry etching. The remaining portion of the seed layer and the conductive material form a metallization pattern 110.

[0059] exist Figure 7 In this embodiment, interconnect die 50A is mounted on carrier substrate 102. Interconnect die 50A can be derived from the previously described interconnect structure 50, which has undergone a single-die process to separate individual dies.

[0060] Interconnect die 50A includes a semiconductor substrate 52 having a wiring structure 54 formed on a front side 52F. Conductive components 66 are located on the upper surface of interconnect die 50A, and a passivation layer 68 covers these conductive components 66.

[0061] The adhesive film 92 can be used to secure the interconnect die 50A to the carrier substrate 102. During subsequent processing steps, the adhesive film 92 can provide temporary adhesion to keep the interconnect die 50A in place.

[0062] Through-holes 116 are formed on any side of the interconnect die 50A. The through-holes 116 extend vertically from the metallization pattern 110 on the release layer 104. In some embodiments, the through-holes 116 can be formed by creating openings in the structure and filling these openings with a conductive material.

[0063] Photoresist is deposited and patterned over a carrier substrate 102 to expose at least a portion of the metallization pattern 110. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The photoresist pattern corresponds to the through-hole 116. A conductive material is formed in the openings of the photoresist and on the exposed portions of the metallization pattern 110. The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc. In some embodiments, the conductive material can be formed by directly plating, such as electroplating or electroless plating, on the metallization pattern 110 without a seed layer. After forming the through-hole 116, the photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma.

[0064] exist Figure 8A and Figure 8B In the process, a sealant 120 is formed to surround the interconnect die 50A and the through hole 116. Figure 8B It is along Figure 8A The plan view of line AA in the diagram. Sealant 120 provides structural support and protection for the interconnect die 50A and other components within the semiconductor package 100. (As shown...) Figure 8B As shown in the plan view, the area occupied by the sealant 120 is larger than the area occupied by the interconnect die 50A. In this embodiment, the sealant covers the alignment marks 62 in the wiring structure 54. In some embodiments, the alignment marks 62 are covered by an insulating layer prior to sealing.

[0065] The sealant 120 can be formed using a molding process. In some cases, a molding compound can be injected around the interconnect die 50A and the through-hole 116. The molding compound can then be cured to form a solid sealant 120. The sealant 120 can extend laterally to seal the sides of the interconnect die 50A and can also extend above the alignment mark 62.

[0066] The sealant 120 can be a molding compound, which may include a base material such as a resin or epoxy resin, and also includes filler particles in the base material. The filler particles may be dielectric particles such as SiO2 or Al2O3, and may have a spherical shape. Furthermore, the spherical filler particles may have various diameters. The sealant 120 can be applied by compression molding, transfer molding, or the like. For example, the sealant 120 may be applied in liquid or semi-liquid form and then subsequently cured. In other embodiments, other sealant materials, such as oxide interstitial fillers, may be used.

[0067] exist Figure 9In this process, a planarization process can be performed on the upper surface of the sealant 120. This planarization process ensures a flat surface for the formation of subsequent layers. The planarization process also exposes the top surfaces of the conductive components 66 and the through-holes 116, thereby allowing for electrical connections in subsequent processing.

[0068] Planarization processes can include, for example, chemical mechanical polishing (CMP) and grinding processes. After a planarization process within the range of process variations, the top surfaces of the through-hole 116, the conductive component 66, the passivation layer 68, and the sealant 120 are substantially coplanar.

[0069] exist Figure 10 In this configuration, a front redistribution structure 122 is formed above the interconnect die 50A, the sealant 120, and the through-hole 116. The front redistribution structure 122 can be formed above the sealant 120 and can be electrically connected to the conductive component 66 of the interconnect die 50A and the through-hole 116.

[0070] The front redistribution structure 122 may include multiple layers of dielectric material and conductive patterns. In some cases, the front redistribution structure 122 may include dielectric layers 124, 128, and 132. These dielectric layers may provide insulation between conductive elements or serve as a base for constructing the redistribution structure.

[0071] Metallization pattern 126 can be formed within or above dielectric layer 124. Similarly, metallization pattern 130 can be formed within or above dielectric layer 128, and metallization pattern 134 can be formed within or above dielectric layer 132. These metallization patterns can provide electrical wiring paths within the front redistribution structure 122.

[0072] The front redistribution structure 122 is shown as an example of three dielectric layers and three metallization pattern layers. More or fewer dielectric layers and metallization patterns can be formed in the front redistribution structure 122. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be repeated.

[0073] The metallization patterns 126, 130, and 134 can be formed using various deposition and patterning techniques. In some cases, these metallization patterns can be formed using processes such as sputtering, electroplating, or chemical vapor deposition, and then the desired pattern can be created by photolithography and etching.

[0074] The formation of the front redistribution structure 122 may include depositing a dielectric layer 124 on the top surface of the through-hole 116, the sealant 120, and the conductive component 66. In some embodiments, the dielectric layer 124 is formed of a photosensitive material such as PBO, polyimide, benzocyclobutene (BCB), etc., which can be patterned using a photolithographic mask. The dielectric layer 124 can be formed by spin coating, lamination, CVD, etc., or combinations thereof. The dielectric layer 124 is then patterned. The patterning creates openings in the conductive component 66 and the through-hole 116. The patterning can be implemented using acceptable processes, such as by exposing the dielectric layer 124 to light and developing it, or by etching it using, for example, anisotropic etching.

[0075] Metallization pattern 126 is then formed. Metallization pattern 126 includes extending along the main surface of dielectric layer 124 (e.g., a conductor portion) and extending through dielectric layer 124 (e.g., a conductive via portion) to physically and electrically couple to conductive component 66 and through-hole 116. As an example of forming metallization pattern 126, a seed layer is formed above dielectric layer 124 and in openings extending through dielectric layer 124. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, PVD. Photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to metallization pattern 126. Patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. This conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, and their alloys. In some embodiments, a pad can be formed in the openings before the conductive material. A pad (not shown separately), such as a diffusion barrier layer or adhesive layer, and the conductive material are formed in the openings. The pad can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The photoresist, and the portions of the seed layer on which no conductive material is formed, are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist has been removed, the exposed portions of the seed layer can be removed, for example, by using an acceptable etching process, such as wet etching or dry etching. The remaining portions of the seed layer and the conductive material combine to form a metallization pattern 126.

[0076] Next, a dielectric layer 128 is deposited on the metallization pattern 126 and the dielectric layer 124. The dielectric layer 128 may have a similar material to the dielectric layer 124 and may be formed in a similar manner. Then, a metallization pattern 130 is formed. The metallization pattern 130 includes portions located on and extending along the main surface of the dielectric layer 128. The metallization pattern 130 also includes portions extending through the dielectric layer 128 to physically and electrically couple the metallization pattern 126. The metallization pattern 130 may be formed in a similar manner and with similar materials to the metallization pattern 126.

[0077] Next, a dielectric layer 132 is deposited on the metallization pattern 130 and the dielectric layer 128. The dielectric layer 132 may have a similar material to the dielectric layer 124 and may be formed in a similar manner. The metallization pattern 134 is then formed. The metallization pattern 134 may be formed in a similar manner to the metallization pattern 126 and may include a similar material to the metallization pattern 126. According to some embodiments, the dielectric layer 132 is the topmost dielectric layer of the redistribution structure 122, and the metallization pattern 134 is the topmost metallization pattern for external interconnection. The metallization pattern 134 may have via portions extending through the dielectric layer 132 to physically and electrically couple the metallization pattern 130. The metallization pattern 134 may be electrically coupled to the interconnect die 50A and / or through-hole 116.

[0078] The front redistribution structure 122 allows electrical connections to be redistributed from the interconnect die 50A to other locations on the surface of the semiconductor package 100. This redistribution enables more flexible placement of external connections and facilitates integration of the semiconductor package 100 with other components or packages. In some embodiments, the metallization pattern of the redistribution structure 122 serves as signal lines, power lines, and / or ground lines for the package structure.

[0079] exist Figure 11 In this embodiment, integrated circuit device 150 is integrated into a package structure. Integrated circuit device 150 is mounted on a front redistribution structure 122. In some embodiments, integrated circuit device 150 may be a flip-chip device, wherein the active circuitry faces the redistribution structure 122. Integrated circuit device 150 is electrically connected to redistribution structure 122 via conductive connectors 156. These conductive connectors 156 may be solder balls, copper pillars, or other suitable conductive structures that provide an electrical path between integrated circuit device 150 and the underlying redistribution structure 122.

[0080] External connectors 152 can be formed on the front redistribution structure 122. These external connectors 152 can provide additional electrical connections for the semiconductor package 100, allowing for communication with external devices or circuit boards.

[0081] The integrated circuit device 150 can be placed on the front redistribution structure 122 using, for example, a pick-and-place tool. The conductive connector 156 can be formed from a reflowable conductive material such as solder, and may also include other conductive materials such as copper, aluminum, gold, nickel, silver, palladium, tin, lead, etc., or combinations thereof. In some embodiments, the conductive connector 156 is formed by initially forming a solder layer via methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Connecting the integrated circuit device 150 to the front redistribution structure 122 may include placing the integrated circuit device 150 on the front redistribution structure 122 and reflowing the conductive connector 156. The conductive connector 156 forms a bond between a corresponding metallization pattern 134 of the front redistribution structure 122 and a corresponding external connector 152 of the integrated circuit device 150, electrically connecting the integrated circuit device 150 to the interconnect die 50A and / or through-hole 116.

[0082] An underfill 158 can be distributed between the integrated circuit device 150 and the front redistribution structure 122. The underfill 158 surrounds the conductive connector 156, providing mechanical support and protection for these electrical connections. In some cases, the underfill 158 helps to distribute stress and provides protection against environmental factors such as moisture. The underfill 158 can be formed from an underfill material such as epoxy resin. The underfill 158 can be formed by a capillary flow process after the integrated circuit device 150 is attached to the front redistribution structure 122, or it can be formed by a suitable deposition method before the integrated circuit device 150 is attached to the front redistribution structure 122. The underfill 158 can be applied in a liquid or semi-liquid form and then subsequently cured.

[0083] In addition, Figure 11 In this process, a sealant 160 is formed over the integrated circuit device 150 and the front redistribution structure 122. The sealant 160 can provide additional protection for the integrated circuit device 150 and other components of the semiconductor package 100. In some cases, the sealant 160 can be a molding compound applied using a molding process.

[0084] Sealant 160 seals the integrated circuit device 150 and the underfill 158. Therefore, the integrated circuit device 150 is buried or covered by sealant 160. Sealant 160 can be a molding compound, which may include a base material such as resin or epoxy resin, and also includes filler particles in the base material. The filler particles may be dielectric particles such as SiO2 or Al2O3, and may have a spherical shape. Furthermore, the spherical filler particles may have various different diameters. Sealant 160 can be applied by compression molding, transfer molding, etc. For example, sealant 160 can be applied in liquid or semi-liquid form, and then subsequently cured.

[0085] exist Figure 12 In this configuration, the semiconductor package 100 can be mounted on the second carrier substrate 170. A release layer 172 can be provided between the semiconductor package 100 and the second carrier substrate 170. This configuration allows for further processing steps or testing on the semiconductor package 100 before final separation from the second carrier substrate 170.

[0086] Figure 13 The diagram shows the state of the semiconductor package 100 after separation from the second carrier substrate 170. The release layer 172 facilitates the separation process, allowing the completed semiconductor package 100 to be removed without damaging its components. The second carrier substrate 170 and the release layer 172 may be similar to the carrier substrate 102 and the release layer 104 described above, and will not be repeated here.

[0087] exist Figure 13 In this process, a planarization process is performed on the back side 52B of the semiconductor substrate 52, for example on sealant 120 and sealant 90, to expose the through-hole 116 and possibly the semiconductor substrate 52. In some embodiments, a debonding process may be performed prior to the planarization process to separate the carrier substrate 102. In some embodiments, the debonding process includes projecting light, such as laser or UV light, onto the release layer 104, causing the release layer 104 to decompose and the carrier substrate 102 to be removed. In some embodiments, the debonding process is skipped, and the planarization process includes removing the carrier substrate 102 and the release layer 104. Regardless of whether the debonding process is performed, the planarization process can remove material from the metallization pattern 110, the adhesive film 92, the through-hole 116, and the semiconductor substrate 52 until the through-hole 116 is fully exposed. After a planarization process within a range of process variations, the top surfaces of the through-hole 116, sealant 120, and semiconductor substrate 52 are substantially coplanar. The planarization process may be, for example, chemical mechanical polishing (CMP), grinding, etc.

[0088] In some embodiments, the through-hole includes a portion within the semiconductor substrate 52 (e.g., in...). Figure 1A-Figure 1B(at or before the stage), and it will be exposed through this flattening step.

[0089] Figure 14 The formation of the back redistribution structure 180 is shown. The back redistribution structure 180 can be formed on the side of the interconnect die 50A opposite to the front redistribution structure 122.

[0090] The back redistribution structure 180 may be constructed similarly to the front redistribution structure 122. In some cases, the back redistribution structure 180 may include multiple layers of dielectric material and conductive patterns. These layers may provide additional wiring options for electrical connections within the semiconductor package 100.

[0091] The formation of the back-side redistribution structure 180 may involve several processing steps. In some cases, the semiconductor substrate 52 of the interconnect die 50A may be thinned to reduce the overall thickness of the semiconductor package 100. This thinning process can be implemented using techniques such as grinding, chemical mechanical polishing, or etching.

[0092] After thinning, a back redistribution structure 180 can be formed on the exposed back side 52B of the semiconductor substrate 52. This process may involve depositing alternating layers of dielectric material and conductive patterns, similar to the formation of the front redistribution structure 122.

[0093] The back redistribution structure 180 can provide several benefits to the semiconductor package 100. In some cases, the back redistribution structure 180 can allow additional electrical connections to the interconnect die 50A, potentially improving the overall functionality of the semiconductor package 100. The back redistribution structure 180 can also facilitate heat dissipation from the interconnect die 50A, potentially improving the thermal performance of the semiconductor package 100.

[0094] Figure 15 A cross-sectional view of a completed semiconductor package 100 mounted on a substrate 190 is shown. The substrate 190 can be used as a platform for integrating the semiconductor package 100 into a larger electronic system.

[0095] Semiconductor package 100 can be electrically and mechanically connected to substrate 190 via conductive connector 192 (also referred to as conductive terminal 192). In some cases, conductive connector 192 can be solder balls, copper pillars, or other types of conductive structures. Conductive connector 192 can provide an electrical path between semiconductor package 100 and substrate 190, thereby allowing the transmission of signals and power.

[0096] The mounting process of the semiconductor package 100 on the substrate 190 may involve several steps. In some cases, a conductive connector 192 may be formed on the back redistribution structure 180 of the semiconductor package 100. The semiconductor package 100 can then be aligned with corresponding connection points on the substrate 190. Heat can be applied to reflow the conductive connector 192, thereby establishing a reliable electrical and mechanical connection between the semiconductor package 100 and the substrate 190. The conductive connector 192 can provide an electrical connection between the semiconductor package 100 and a ground or power supply voltage to an external component, and the conductive connector 192 and its corresponding portions of the back redistribution structure 180 may include solder areas and intermetallic compound (IMC) areas.

[0097] The completed semiconductor package 100 mounted on substrate 190 can represent a fully functional electronic component ready for integration into a larger system. The combination of the front redistribution structure 122, the back redistribution structure 180, and the mounting on substrate 190 provides a high degree of flexibility in electrical wiring and system integration.

[0098] In some cases, the semiconductor package 100 may include Figure 15 Additional components or features not explicitly shown in the diagram. For example, underfill material can be used to further secure the semiconductor package 100 to the substrate 190 and provide additional protection against environmental factors.

[0099] Semiconductor packages 100 with dual redistribution structures and mounting capabilities offer several advantages. The packages provide a high degree of integration, allowing complex electronic systems to be built with a compact form factor. The use of both front and back redistribution structures enables more flexible electrical signal routing, potentially improving the overall performance of the electronic system.

[0100] Figure 16A , Figure 16B ,and Figure 17 A cross-sectional view of an intermediate stage in the manufacture of a semiconductor package 200 according to some embodiments is shown. This embodiment is similar to semiconductor package 100 and also includes an insulating layer 202 over an interconnect die 50A. Details of previous embodiments similar to this embodiment are not repeated here. Figures 16A-16B It is consistent with the description above. Figure 7 Similar processing stages will not be described again here.

[0101] In this embodiment, an insulating layer 202 is formed over a single interconnect die 50A. The insulating layer 202 may be formed over alignment marks 62 to provide additional protection and functionality.

[0102] In some embodiments, the insulating layer 202 may be a transparent layer. The transparency of the insulating layer 202 allows the alignment marks 62 to be aligned by visible light. This feature can improve the visibility and accuracy of the alignment process during subsequent manufacturing steps.

[0103] The insulating layer 202 may comprise a material selected from the group consisting of BCB, polyimide, and PBO. These materials can provide specific properties beneficial to the semiconductor package 200, such as low dielectric constant, high thermal stability, or good adhesion properties.

[0104] Figure 16B Provided Figure 16A A more detailed cross-sectional view of the structure is shown. An insulating layer 202 is formed above the interconnect die 50A, covering alignment marks 62 and other components. In some cases, the insulating layer 202 can be formed by a lamination process. This process allows for uniform coverage and good adhesion to the underlying structure.

[0105] Figure 17 A cross-sectional view of the semiconductor package 200 is shown during a later assembly stage. The semiconductor package 200 includes an interconnect die 50A, which includes an insulating layer 202. Figures 16A-16B and Figure 17 The processing steps are similar to steps 7 to 15 described above, and will not be repeated here.

[0106] Figure 18A , Figure 18B ,and Figure 19 A cross-sectional view of an intermediate stage in the manufacture of a semiconductor package 210 according to some embodiments is shown. This embodiment is similar to semiconductor package 100 and also includes an insulating layer 212 located above interconnect die 50A. Details similar to those of previous embodiments are not repeated here. Figures 18A-18B It is consistent with the description above. Figure 7 Similar processing stages will not be described again here.

[0107] In this embodiment, an insulating layer 212 is conformally formed over the interconnect die 50A, covering both the passivation layer 68 and the conductive component 66. The insulating layer 212 extends over the surface of the interconnect die 50A and provides protection for the underlying structure. In some cases, the insulating layer 212 can be formed by atomic layer deposition (ALD) or physical vapor deposition (PVD). These deposition techniques allow for precise control over the thickness and composition of the insulating layer.

[0108] Figure 18BA more detailed cross-sectional view of the semiconductor package 210 is provided. An insulating layer 212 is formed over portions of the structure, covering alignment marks 62 and extending over adjacent areas. In some cases, the insulating layer 212 may include low-oxygen-permissive materials, such as nitrides, metal films, or adhesion promoters. These materials can provide additional protection against oxidation or other environmental factors.

[0109] Figure 17 A cross-sectional view of the semiconductor package 210 is shown during a later assembly stage. The semiconductor package 210 includes an interconnect die 50A, which includes an insulating layer 212. Figures 18A-18B and Figure 19 The processing steps are similar to steps 7 to 15 described above, and will not be repeated here.

[0110] Including insulating layer 202 or 212 in these embodiments provides several benefits. The insulating layer can provide additional protection for alignment mark 62 and other sensitive components of interconnect die 50A. This protection can help maintain the integrity and visibility of alignment mark 62 throughout various manufacturing processes, potentially improving alignment accuracy in subsequent steps.

[0111] In some embodiments, the conformal nature of the insulating layer 212 can provide uniform coverage on the surface of the interconnect die 50A. This uniform coverage may help distribute stress and provide protection against environmental factors such as moisture or contaminants.

[0112] Using transparent materials for the insulating layer allows for alignment processes that utilize visible light, potentially simplifying the alignment process or enabling the use of certain types of alignment equipment. Selecting specific materials for the insulating layer, such as BCB, PI, or PBO, allows for customization of the layer's properties to meet specific packaging requirements or performance targets.

[0113] By combining these embodiments with an insulating layer, semiconductor packages 200 and 210 can provide enhanced protection, improved alignment capabilities, and potentially greater flexibility in manufacturing processes. These features can contribute to the overall reliability and performance of the semiconductor packages in a variety of applications.

[0114] The semiconductor package and manufacturing method described in this disclosure offer several advantages in the field of integrated circuit packaging. By exposing alignment marks through openings in the passivation layer and optionally covering them with different insulating materials, the accuracy and reliability of die alignment during package assembly can be significantly improved. This method addresses the problem that passivation layer damage during individualization affects the visibility of alignment marks and leads to an increased failure rate in the packaging process.

[0115] The disclosed method is compatible with existing semiconductor manufacturing processes, allowing for easy integration into current production lines without requiring substantial changes to established workflows or equipment. This compatibility ensures the benefits of improved alignment are achieved without significantly disrupting manufacturing operations.

[0116] The semiconductor package described herein offers enhanced flexibility in electrical wiring and system integration. The use of both front and back redistribution structures enables more complex interconnects within a compact form factor. This design approach allows for higher connection density and can potentially improve overall system performance.

[0117] The sealing techniques and redistribution structures described in this disclosure contribute to the robustness and reliability of semiconductor packages. The sealant provides protection against environmental factors and mechanical stresses, while the redistribution structure offers flexibility in designing electrical connections for a variety of applications.

[0118] The semiconductor packages and manufacturing methods described in this disclosure have potential applications in a wide range of electronic devices where compact size, high performance, and reliability are critical. These may include smartphones, tablets, wearable devices, automotive electronics, and various Internet of Things (IoT) devices. The improved alignment accuracy and packaging flexibility offered by this method enable the development of more advanced and compact electronic systems in these and other fields.

[0119] In one embodiment, a method includes: forming an interconnect structure including a plurality of die regions separated by scribe lines, at least one of the die regions including a semiconductor substrate, and a wiring structure on the semiconductor substrate including alignment marks adjacent to the scribe lines; forming a passivation layer over the wiring structure; removing a portion of the passivation layer to expose the alignment marks; and performing a unitization process to separate the interconnect structure into individual dies.

[0120] The described embodiments may also include one or more of the following features. The method further includes: mounting one of the individual dies on a carrier substrate; forming a sealant that laterally seals the individual dies and extends over exposed alignment marks; and forming a redistribution structure over the sealant, wherein the redistribution structure is electrically connected to a wiring structure. The method further includes: mounting an integrated circuit device on the redistribution structure and electrically coupling the integrated circuit device to the redistribution structure; and distributing an underfill between the integrated circuit device and the redistribution structure. The method further includes: forming an insulating layer over the exposed alignment marks prior to forming the sealant; the insulating layer comprising a material different from the passivation layer. The insulating layer comprises a material selected from the group consisting of benzocyclobutene (BCB), polyimide (PI), and polybenzoxazole (PBO). Removing a portion of the passivation layer includes performing a photolithography process to form an opening having an octagonal shape in a planar view. Performing a singlet process includes laser grooving and blade sawing. In some embodiments, removing said portion of the passivation layer includes performing a photolithography process to form an opening having angled corners in a planar view.

[0121] In one embodiment, a method includes: forming a passivation layer over a wiring structure of a die, the wiring structure being located on a semiconductor substrate, the wiring structure including a plurality of conductive layers and a plurality of dielectric layers, alignment marks, and a sealing ring structure; removing a portion of the passivation layer to form an opening exposing the alignment marks, the opening having an octagonal shape in a plan view; after exposing the alignment marks, forming a sealant that laterally seals the die and extends over the alignment marks; and forming a redistribution structure over the sealant, the redistribution structure being electrically connected to the wiring structure, the redistribution structure including conductors and conductive vias, wherein the conductors and conductive vias include an adhesive layer and a copper-containing conductive layer located above the adhesive layer, and wherein the conductors serve as signal lines, power lines, or ground lines.

[0122] The described embodiments may also include one or more of the following features. The method further includes: forming an insulating layer over alignment marks, the insulating layer comprising a material different from the passivation layer, the insulating layer being a conformal layer. The insulating layer comprises a material selected from the group consisting of benzocyclobutene (BCB), polyimide (PI), and polybenzoxazole (PBO). The method further includes: mounting an integrated circuit device on the redistribution structure, wherein the integrated circuit device is electrically connected to the redistribution structure. The method further includes: forming a conductive connector, electrically coupling the integrated circuit device and the redistribution structure, and distributing an underfill between the integrated circuit device and the redistribution structure, wherein the underfill surrounds the conductive connector. A portion of removing the passivation layer includes performing a photolithography process to pattern and etch the passivation layer.

[0123] In one embodiment, the semiconductor package includes: an interconnect die, the interconnect die including: a semiconductor substrate having a first side and a second side opposite to the first side; a wiring structure located on the first side of the semiconductor substrate, the wiring structure including a plurality of metallization layers disposed in a plurality of dielectric layers, the wiring structure including a die region, a sealing ring structure, and alignment marks, the sealing ring structure including a wall-like metal member surrounding the die region of the wiring structure; a die connector located on the die region of the wiring structure; a passivation layer laterally surrounding the die connector, the alignment marks being laterally spaced from the passivation layer; and a sealant extending along the sidewall of the interconnect die, the sealant extending above the alignment marks, wherein, in a plan view, the area occupied by the sealant is larger than the area occupied by the interconnect die.

[0124] The described embodiments may also include one or more of the following features: The semiconductor package further includes an insulating layer laterally surrounding the passivation layer and located on the sidewalls of the interconnect die, the insulating layer covering alignment marks. The insulating layer has a different material composition than the passivation layer. The insulating layer is a conformal layer located above the alignment marks and on the sidewalls of the interconnect die. The semiconductor package further includes a redistribution structure located above a sealant and electrically connected to a wiring structure, on which an integrated circuit device is located and electrically connected. The semiconductor package further includes a conductive connector electrically coupling the integrated circuit device to the redistribution structure, and an underfill located between the integrated circuit device and the redistribution structure, the underfill surrounding the conductive connector. The interconnect die includes non-planar sidewalls with different slopes between the top and bottom of the sidewalls.

[0125] Embodiments of this application also provide a method for forming a semiconductor package, comprising: forming a passivation layer over a wiring structure of a die, the wiring structure being located on a semiconductor substrate, the wiring structure including a plurality of conductive layers and a plurality of dielectric layers, alignment marks, and a sealing ring structure; removing a portion of the passivation layer to form an opening exposing the alignment marks in a plan view; after exposing the alignment marks, forming a sealant that laterally seals the die and extends over the alignment marks; and forming a redistribution structure over the sealant, the redistribution structure being electrically connected to the wiring structure, the redistribution structure including conductors and conductive vias, wherein the conductors and the conductive vias include a copper-containing conductive layer, and wherein the conductors serve as signal lines, power lines, or ground lines. In some embodiments, the method further comprises: forming an insulating layer over the alignment marks, the insulating layer comprising a material different from the passivation layer, the insulating layer being a conformal layer. In some embodiments, the insulating layer comprises a material selected from the group consisting of benzocyclobutene (BCB), polyimide (PI), and polybenzoxazole (PBO). In some embodiments, the method further includes: mounting an integrated circuit device on the redistribution structure, wherein the integrated circuit device is electrically connected to the redistribution structure. In some embodiments, the method further includes: forming a conductive connector that electrically couples the integrated circuit device and the redistribution structure; and distributing an underfill material between the integrated circuit device and the redistribution structure, wherein the underfill material surrounds the conductive connector. In some embodiments, removing the portion of the passivation layer includes performing a photolithography process to pattern and etch the passivation layer, and wherein, after forming the opening, the passivation layer has an octagonal shape in the planar view.

[0126] Embodiments of this application also provide a semiconductor package including an interconnect die and a sealant. The interconnect die includes: a semiconductor substrate, a wiring structure, a die connector, and a passivation layer. The semiconductor substrate has a first surface and a second surface opposite to the first surface. The wiring structure is located on the first surface of the semiconductor substrate. The wiring structure includes a plurality of metallization layers disposed among a plurality of dielectric layers. At least one of the metallization layers includes a barrier layer connected to one of the dielectric layers and a filler metal spaced apart from the one of the dielectric layers by the barrier layer. The conductivity of the barrier layer is lower than that of the filler metal. The wiring structure includes a die region, a sealing ring structure, and alignment marks. The sealing ring structure includes a wall-like metal component surrounding the die region of the wiring structure, and the sealing ring structure includes a material containing more than 80% copper. A die connector is located on the die region of the wiring structure. A passivation layer laterally surrounds the die connector, and the alignment marks are laterally spaced from the passivation layer. A sealant extends along the sidewall of the interconnect die, and in a plan view, the area occupied by the sealant is larger than the area occupied by the interconnect die. In some embodiments, the semiconductor package further includes an insulating layer laterally surrounding the passivation layer and located on the sidewall of the interconnect die, the insulating layer covering the alignment marks. In some embodiments, the insulating layer has a different material composition than the passivation layer. In some embodiments, the insulating layer is a conformal layer located above the alignment marks and on the sidewall of the interconnect die. In some embodiments, the semiconductor package further includes: a redistribution structure located above the sealant and electrically connected to the wiring structure; and an integrated circuit device located on the redistribution structure and electrically connected to the redistribution structure. In some embodiments, the semiconductor package further includes: a conductive connector electrically coupling the integrated circuit device to the redistribution structure; and an underfill located between the integrated circuit device and the redistribution structure, the underfill surrounding the conductive connector. In some embodiments, the substrate includes non-planar sidewalls with different slopes between the top and bottom of the sidewalls, and wherein the passivation layer includes planar sidewalls.

[0127] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor package, comprising: An interconnect structure is formed, the interconnect structure including a plurality of die regions separated by scribe lines, at least one of the plurality of die regions including a semiconductor substrate and a wiring structure located on the semiconductor substrate, the wiring structure including alignment marks adjacent to the scribe lines; A passivation layer is formed above the wiring structure; Remove a portion of the passivation layer to expose the alignment mark; as well as A single-die process is implemented to separate the interconnect structure into individual dies.

2. The method according to claim 1, further comprising: One of the individual dies is mounted on a carrier substrate; and A sealant is formed that laterally seals the individual die and extends above the exposed alignment mark; and A redistribution structure is formed over the sealant, wherein the redistribution structure is electrically connected to the wiring structure.

3. The method according to claim 2, further comprising: An integrated circuit device is mounted on the redistribution structure, and the integrated circuit device is electrically coupled to the redistribution structure; and A bottom filler is distributed between the integrated circuit device and the redistributed structure.

4. The method according to claim 2, further comprising: Before the sealant is formed, an insulating layer is formed over the exposed alignment marks, the insulating layer comprising a material different from the passivation layer.

5. The method according to claim 4, wherein, The insulating layer comprises a material selected from the group consisting of benzocyclobutene (BCB), polyimide (PI), and polybenzoxazole (PBO).

6. The method according to claim 1, wherein, Removing the portion of the passivation layer includes performing a photolithography process to form an opening with an angled corner in a planar view.

7. The method according to claim 1, wherein, The individualization process includes laser grooving and blade sawing.

8. A method of forming a semiconductor package, comprising: A passivation layer is formed above the wiring structure of the die, the wiring structure being located on a semiconductor substrate, the wiring structure including multiple conductive layers and multiple dielectric layers, alignment marks, and a sealing ring structure; A portion of the passivation layer is removed to form an opening that exposes the alignment mark in the plan view; After the alignment mark is exposed, a sealant is formed that laterally seals the die and extends above the alignment mark; as well as A redistribution structure is formed over the sealant, the redistribution structure being electrically connected to the wiring structure, the redistribution structure including conductors and conductive vias, wherein the conductors and the conductive vias include a copper conductive layer, and wherein the conductors serve as signal lines, power lines, or ground lines.

9. The method according to claim 8, further comprising: An insulating layer is formed over the alignment mark. The insulating layer comprises a material different from the passivation layer and is a conformal layer.

10. A semiconductor package, comprising: Interconnect die, the interconnect die comprising: A semiconductor substrate having a first surface and a second surface opposite to the first surface; A wiring structure is located on the first surface of the semiconductor substrate. The wiring structure includes a plurality of metallization layers disposed in a plurality of dielectric layers. At least one of the metallization layers includes a barrier layer connected to one of the dielectric layers and a fill metal spaced apart from the one of the dielectric layers by the barrier layer. The conductivity of the barrier layer is lower than that of the fill metal. The wiring structure includes a die region, a sealing ring structure, and alignment marks. The sealing ring structure includes a wall-like metal component surrounding the die region of the wiring structure. The sealing ring structure includes a material containing more than 80% copper. A die connector is located on the die area of ​​the wiring structure; and A passivation layer laterally surrounds the die connector, and the alignment marks are laterally spaced from the passivation layer; and The sealant extends along the sidewall of the interconnect die, and in a plan view, the area occupied by the sealant is larger than the area occupied by the interconnect die.

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