Semiconductor package

Abstract

A semiconductor package is disclosed. The semiconductor package includes a wiring structure. The wiring structure includes a first insulating layer, a conductive pad on the first insulating layer, a second insulating layer on the conductive pad, a via through the second insulating layer and overlapping the conductive pad, a protrusion pattern disposed on the conductive pad and in the via, and an under bump metallization (UBM) layer contacting upper and side surfaces of the protrusion pattern and connected to the conductive pad. A semiconductor chip is connected to the UBM layer and disposed on the wiring structure.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to a semiconductor package, and more specifically, to a semiconductor package including electrodes and a method of forming a semiconductor package including electrodes. Background Technology

[0002] In response to the miniaturization of semiconductor packages, the technology for mounting semiconductor chips on substrates including wiring has become increasingly difficult. Semiconductor chips can be electrically connected to wiring in the substrate via conductive interconnects. The connections between conductive interconnects and adjacent components affect the electrical characteristics and reliability of the semiconductor package. Summary of the Invention

[0003] In one embodiment, a semiconductor package may include a wiring structure. The wiring structure may include a first insulating layer, conductive pads on the first insulating layer, a second insulating layer on the conductive pads, vias penetrating the second insulating layer and overlapping the conductive pads, protruding patterns disposed on the conductive pads and located in the vias, and an under-bump metallization (UBM) layer contacting the upper and side surfaces of the protruding patterns and connected to the conductive pads. A semiconductor chip is connected to the UBM layer and disposed on the wiring structure.

[0004] In one embodiment, a semiconductor package may include a wiring structure. The wiring structure may include a first insulating layer, a plurality of conductive pads on the first insulating layer, a second insulating layer on the plurality of conductive pads, a plurality of vias passing through the second insulating layer and overlapping the plurality of conductive pads, a plurality of protruding patterns respectively disposed on the plurality of conductive pads and located in the plurality of vias, and a plurality of UBM layers respectively contacting the upper and side surfaces of the plurality of protruding patterns and connected to the plurality of conductive pads. A first semiconductor chip and a second semiconductor chip may be disposed on the wiring structure. A packaging layer covering the first semiconductor chip and the second semiconductor chip may be disposed on the wiring structure.

[0005] In one embodiment, a semiconductor package may include conductive pads located on a first insulating layer. A second insulating layer may be disposed on the conductive pads. A via may be provided through the second insulating layer and overlapping the conductive pads. A protruding pattern having a horizontal width smaller than the via may be disposed on the conductive pads and located within the via. A UBM layer may be provided, contacting the upper and side surfaces of the protruding pattern and having a horizontal width greater than the via. The upper surface of the UBM layer may have a recessed region overlapping the space between the protruding pattern and the second insulating layer. A semiconductor chip may be disposed on the UBM layer. Attached Figure Description

[0006] Figure 1 This is a cross-sectional view showing a semiconductor package according to an embodiment of the present disclosure.

[0007] Figure 2 It is shown Figure 1 Implementation of a partial cross-sectional view of a portion.

[0008] Figure 3 and Figure 4 This is a cross-sectional view showing a partial configuration of a semiconductor package according to an embodiment of the present disclosure.

[0009] Figure 5 and Figure 6 This is a perspective view showing a partial configuration of a semiconductor package according to an embodiment of the present disclosure.

[0010] Figure 7 and Figure 8 This is a cross-sectional view showing a semiconductor package according to an embodiment of the present disclosure.

[0011] Figures 9 to 19 This is a cross-sectional view illustrating a method for forming a semiconductor package according to an embodiment of the present disclosure. Detailed Implementation

[0012] Embodiments of this disclosure are described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples illustrating the concepts disclosed in this application. These embodiments or examples of the concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0013] Crosshairs running through the figures indicate corresponding or similar areas between figures, but do not indicate the material associated with these areas.

[0014] When one element is identified as "connected" or "joined" to another element, the two elements can be directly connected or joined, or connected or joined through an intermediate element between the two elements. When two elements are identified as "directly connected" or "directly joined," one element is directly connected or joined to the other element without any intermediate element between the two elements.

[0015] When one element is identified as being "above", "below", or "under" another element, the two elements can be in direct contact with each other, or an intermediate element can be placed between the two elements.

[0016] Terms such as "vertical," "horizontal," "top," "bottom," "above," "below," "under," "below," "over," "upper," "side," "upper part," "topmost," "lowest part," "bottommost," "front," "back," "left," "right," "column," "row," and "height," as well as other terms that suggest relative spatial relationships or orientations, are used for the purpose of description or reference to the accompanying drawings and are not intended to be limiting. Other spatial relationships or orientations not shown in the drawings or described in the specification may exist within the scope of this disclosure.

[0017] Terms such as "first" and "second" are used to distinguish various elements without implying the size, order, priority, number, or importance of the elements. For example, in one example, the first element may be named the second element, while in another example, the second element may be named the first element.

[0018] In the specification, when an element included in an embodiment is described in the singular, the element can be interpreted as including multiple elements that perform the same or similar functions.

[0019] Embodiments of this disclosure aim to provide a semiconductor package including electrodes and a method for forming the semiconductor package.

[0020] According to embodiments of the present disclosure, a semiconductor package including electrodes and a method for forming the semiconductor package can be provided.

[0021] Figure 1 This is a cross-sectional view showing a semiconductor package according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 Implementation of a partial cross-sectional view of part 110. Figure 3 and Figure 4 This is a cross-sectional view showing a partial configuration of a semiconductor package according to an embodiment of the present disclosure. Figure 5 and Figure 6 This is a perspective view showing a partial configuration of a semiconductor package according to an embodiment of the present disclosure.

[0022] Reference Figure 1 The semiconductor package according to embodiments of the present disclosure may include a wiring structure 21, a first semiconductor chip 90, a substrate chip 310, core chips 320, 330 and 340, a top chip 350, external solder interconnects 572, a first packaging layer 591 and a second packaging layer 592.

[0023] The wiring structure 21 may include a first insulating layer 23, a second insulating layer 25, a third insulating layer 27, a first via electrode 31, a first horizontal electrode 38, a second via electrode 41, a conductive pad 48, a second horizontal electrode 48', a raised pattern 57, a metallization under bump (UBM) layer 63, and an external electrode 589. In an embodiment, the wiring structure 21 may include a silicon-free interposer (SLIP) or redistribution layer (RDL) substrate.

[0024] The first insulating layer 23, the second insulating layer 25, and the third insulating layer 27 can be stacked sequentially. The first through-hole electrode 31 can penetrate the first insulating layer 23 in the vertical direction VD. The first horizontal electrode 38 can be disposed between the first insulating layer 23 and the second insulating layer 25. The first through-hole electrode 31 can contact the side surface of the first horizontal electrode 38. The vertical direction VD is perpendicular to the upper surface of the wiring structure 21. The horizontal direction HD is one of the directions parallel to the upper surface of the wiring structure 21.

[0025] The second through-hole electrode 41 can penetrate the second insulating layer 25 in the vertical direction VD and contact the first horizontal electrode 38. The conductive pad 48 and the second horizontal electrode 48' can be disposed between the second insulating layer 25 and the third insulating layer 27. The second horizontal electrode 48' can contact the second through-hole electrode 41. The conductive pad 48 can contact the side surface of the second horizontal electrode 48'.

[0026] A raised pattern 57 can be disposed on the conductive pad 48. A UBM layer 63 can be disposed on the conductive pad 48 and the raised pattern 57. A first solder interconnect 72 can be disposed on the UBM layer 63. (Refer to...) Figures 2 to 6 The UBM layer 63 and the protruding pattern 57 are described again.

[0027] A first semiconductor chip 90 can be mounted on a wiring structure 21. The first semiconductor chip 90 may include a first solder interconnect 72, a chip electrode 89, a first substrate 91, and a first circuit layer 93. The first circuit layer 93 may be disposed on the lower surface of the first substrate 91. The chip electrode 89 may be disposed on the lower surface of the first circuit layer 93. The first solder interconnect 72 may be disposed between the UBM layer 63 and the chip electrode 89.

[0028] The substrate chip 310, core chips 320, 330, and 340, top chip 350, and first encapsulation layer 591 can constitute a multi-chip package. In an embodiment, the substrate chip 310, core chips 320, 330, and 340, top chip 350, and first encapsulation layer 591 can be a high-bandwidth memory (HBM) package. The substrate chip 310 can include a substrate 311, a substrate circuit layer 317, and a substrate through-electrode 319. The substrate circuit layer 317 can be disposed on the lower surface of the substrate 311. The substrate through-electrode 319 can penetrate the substrate 311 in the vertical direction VD and is connected to the substrate circuit layer 317. In an embodiment, each of the substrate chip 310, core chips 320, 330, and 340, and top chip 350 can be a semiconductor chip.

[0029] Core chips 320, 330, and 340 may include a first core chip 320, a second core chip 330, and a third core chip 340. The first core chip 320 may include a first core substrate 321, a first core circuit layer 327, and a first core through-electrode 329. The first core circuit layer 327 may be disposed on the lower surface of the first core substrate 321. The first core through-electrode 329 may penetrate the first core substrate 321 in the vertical direction VD and be connected to the first core circuit layer 327.

[0030] The second core chip 330 may include a second core substrate 331, a second core circuit layer 337, and a second core through electrode 339. The second core circuit layer 337 may be disposed on the lower surface of the second core substrate 331. The second core through electrode 339 may penetrate the second core substrate 331 in the vertical direction VD and be connected to the second core circuit layer 337.

[0031] The third core chip 340 may include a third core substrate 341, a third core circuit layer 347, and a third core through electrode 349. The third core circuit layer 347 may be disposed on the lower surface of the third core substrate 341. The third core through electrode 349 may penetrate the third core substrate 341 in the vertical direction VD and be connected to the third core circuit layer 347.

[0032] The top chip 350 may include a top substrate 351 and a top circuit layer 357. The top circuit layer 357 may be disposed on the lower surface of the top substrate 351.

[0033] Core chips 320, 330, and 340 can be sequentially stacked on the base chip 310. A top chip 350 can be stacked on the topmost core chip. In one embodiment, the top chip 350 can be stacked on the third core chip 340. A first encapsulation layer 591 can cover the base chip 310, core chips 320, 330, and 340, and the top chip 350. The first encapsulation layer 591 can extend between the base chip 310, core chips 320, 330, and 340, and the top chip 350. The upper surface of the first encapsulation layer 591 and the upper surface of the top chip 350 can form substantially the same plane. In one embodiment, another core chip or multiple other core chips can be additionally stacked between the base chip 310 and the first core chip 320, between the core chips 320, 330, and 340, and between the third core chip 340 and the top chip 350. Figure 1 In this embodiment, three core chips 320, 330, and 340 are arranged between the base chip 310 and the top chip 350, but this disclosure is not limited thereto. One or more core chips may be arranged between the base chip and the top chip.

[0034] The substrate chip 310 may include a back electrode 416. The back electrode 416 may be disposed on the upper surface of the substrate 311. The back electrode 416 may overlap with the through electrode 319. The back electrode 416 may contact the upper end of the substrate through the through electrode 319. A first core front electrode 429 may be disposed on the lower surface of the first core circuit layer 327. A second solder interconnect 472 may be disposed between the back electrode 416 and the first core front electrode 429.

[0035] The first core chip 320 may include a first core rear electrode 426. The first core rear electrode 426 may be disposed on the upper surface of the first core substrate 321. The first core rear electrode 426 may overlap with the first core through electrode 329. The first core rear electrode 426 may contact the upper end of the first core through electrode 329. The second core front electrode 439 may be disposed on the lower surface of the second core circuit layer 337. The second solder interconnect 472 may be disposed between the first core rear electrode 426 and the second core front electrode 439.

[0036] The second core chip 330 may include a second core rear electrode 436. The second core rear electrode 436 may be disposed on the upper surface of the second core substrate 331. The second core rear electrode 436 may overlap with the second core through electrode 339. The second core rear electrode 436 may contact the upper end of the second core through electrode 339. The third core front electrode 449 may be disposed on the lower surface of the third core circuit layer 347. The second solder interconnect 472 may be disposed between the second core rear electrode 436 and the third core front electrode 449.

[0037] The third core chip 340 may include a third core rear electrode 446. The third core rear electrode 446 may be disposed on the third core substrate 341. The third core chip 340 may overlap with the third core through electrode 349. The third core rear electrode 446 may contact the upper end of the third core through electrode 349. The top front electrode 459 may be disposed on the lower surface of the top circuit layer 357. The second solder interconnect 472 may be disposed between the third core rear electrode 446 and the top front electrode 459.

[0038] The substrate chip 310 may include a substrate chip electrode 189. The substrate chip electrode 189 may be disposed on the lower surface of the substrate circuit layer 317. A third solder interconnect 172 may be disposed between the UBM layer 63 and the substrate chip electrode 189.

[0039] Although not shown, the second solder interconnect 472 may be omitted in the embodiment. The first core front electrode may contact the substrate rear electrode. The second core front electrode may contact the first core rear electrode. The third core front electrode may contact the second core rear electrode. The top front electrode may contact the third core rear electrode. The substrate chip, core chip, and top chip may be connected using a hybrid bonding technique.

[0040] The second encapsulation layer 592 may cover the wiring structure 21, the first semiconductor chip 90, the substrate chip 310, the core chips 320, 330 and 340, the top chip 350, and the first encapsulation layer 591. The second encapsulation layer 592 may extend between the wiring structure 21 and the first semiconductor chip 90, and between the wiring structure 21 and the substrate chip 310. In an embodiment, the second encapsulation layer 592 may directly contact the side surfaces of the UBM layer 63, the first solder interconnect 72, the chip electrode 89, the third solder interconnect 172, and the substrate chip electrode 189.

[0041] The wiring structure 21 may include an external electrode 589. The external electrode 589 may be disposed on the lower surface of the first insulating layer 23. The external electrode 589 may overlap with the first through-hole electrode 31. The external electrode 589 may be connected to the first through-hole electrode 31. An external solder interconnect 572 may be disposed on the external electrode 589.

[0042] In one embodiment, the first semiconductor chip 90 may include a graphics processing unit, a controller, an application processor, a microprocessor, or a combination thereof. The substrate chip 310 may include logic circuitry. In one embodiment, the substrate chip 310 may include a silicon through-electrode, such as a substrate through-electrode 319. The substrate chip 310 may be used to control the memory included in the core chips 320, 330, and 340. The substrate chip 310 may perform calculations. The core chips 320, 330, and 340, and the top chip 350, may include volatile memory, non-volatile memory, or a combination thereof. The top chip 350 may include a dummy chip.

[0043] Reference Figure 2 Conductive pads 48 and second horizontal electrodes 48' can be disposed on the second insulating layer 25. The conductive pads 48 and second horizontal electrodes 48' may include sequentially stacked first barrier layers 43 and 43', first seed layers 44 and 44', and first conductive layers 45 and 45'. The first seed layers 44 and 44' and the first conductive layers 45 and 45' may be composed of the same material. In this case, the boundary between the first seed layers 44 and 44' and the first conductive layers 45 and 45' may be difficult to identify. Although not shown, the first seed layers 44 and 44' may be omitted in embodiments. A third insulating layer 27 can be disposed on the second insulating layer 25, conductive pads 48, and second horizontal electrodes 48'. The third insulating layer 27 may cover the second insulating layer 25, conductive pads 48, and second horizontal electrodes 48'. A via 27H may be configured to extend through the third insulating layer 27. The via 27H may overlap with the conductive pads 48.

[0044] The second barrier layer 53 can be configured to conformally cover the bottom and sidewalls of the via 27H. The second barrier layer 53 can further extend onto the third insulating layer 27. The second barrier layer 53 can contact the first conductive layer 45 of the conductive pad 48. The second barrier layer 53 can contact the side and top surfaces of the third insulating layer 27. A second seed layer 54 can be disposed on the second barrier layer 53.

[0045] The protruding pattern 57 can be disposed on the second seed layer 54. The protruding pattern 57 can overlap with the center of the through hole 27H. The uppermost surface of the protruding pattern 57 can be at substantially the same height as the uppermost surface of the third insulating layer 27, or lower than the uppermost surface of the third insulating layer 27.

[0046] UBM layer 63 can be disposed on the second seed layer 54 and the protruding pattern 57. UBM layer 63 can be disposed such that it fills the via 27H and extends onto the third insulating layer 27. UBM layer 63 can cover the upper and side surfaces of the protruding pattern 57. UBM layer 63 can overlap with the conductive pad 48. The upper surface of UBM layer 63 can be disposed at a height higher than the uppermost surface of the third insulating layer 27.

[0047] The substrate chip 310 may include a substrate 311, a substrate circuit layer 317, an insulating spacer 318, and a substrate through electrode 319. The substrate circuit layer 317 may be disposed on the lower surface of the substrate 311. The substrate circuit layer 317 may include multiple conductive patterns 313 and multiple circuit insulating layers 315. The multiple conductive patterns 313 may include chip pads. The substrate through electrode 319 penetrates the substrate 311 in the vertical direction VD. The multiple conductive patterns 313 may be connected to each other. The insulating spacer 318 may surround the side surface of the substrate through electrode 319. The substrate through electrode 319 may be insulated from the substrate 311 by the insulating spacer 318.

[0048] The substrate chip 310 may include a substrate chip electrode 189 disposed on the lower surface of the substrate circuit layer 317. The substrate chip electrode 189 may penetrate the circuit insulating layer 315 and be connected to the conductive pattern 313. In an embodiment, the substrate chip electrode 189 may include a third barrier layer 83, a third seed layer 84, a second conductive layer 85, and a third conductive layer 88 stacked sequentially.

[0049] The third solder interconnect 172 can be disposed between the UBM layer 63 and the substrate chip electrode 189. The first intermetallic compound layer IM1 can be disposed between the UBM layer 63 and the third solder interconnect 172. The second intermetallic compound layer IM2 can be disposed between the third solder interconnect 172 and the substrate chip electrode 189.

[0050] According to embodiments of this disclosure, the raised pattern 57 is configured to reduce topographic variations on the upper surface of the UBM layer 63. In this embodiment, topographic variations in the UBM layer 63 can be minimized by the raised pattern 57. The raised pattern 57 can make the upper surface of the central region of the UBM layer 63 and the upper surface of the edge regions at the same or similar height. This can reduce the height difference across the UBM layer 63. In this embodiment, the formation of defects such as voids between the third solder interconnect 172 and the UBM layer 63 can be prevented or reduced. In this embodiment, a reliable mechanical and / or electrical connection can be achieved between the third solder interconnect 172 and the UBM layer 63.

[0051] In the implementation, the first circuit layer 93 (see...) Figure 1), First core circuit layer 327 (see Figure 1 ), second core circuit layer 337 (see Figure 1 ), third core circuit layer 347 (see Figure 1 ) and top circuit layer 357 (see Figure 1 Each of the plurality of conductive patterns 313 and the plurality of circuit insulating layers 315 may include components substantially the same as those of the plurality of conductive patterns 313 and the plurality of circuit insulating layers 315.

[0052] Reference Figure 3 The lower end of the through-hole 27H may have a smaller horizontal width than the upper end of the through-hole 27H. The through-hole 27H may have a wider opening at the top and a narrower portion at the bottom, thereby defining an inverted trapezoidal cross-sectional shape. The through-hole 27H may have inclined sidewalls defined by the inclined side surface of the third insulating layer 27.

[0053] In one embodiment, a second barrier layer 53 may be disposed between the conductive pad 48 and the raised pattern 57. The second barrier layer 53 may extend on the conductive pad 48 between the third insulating layer 27 and the raised pattern 57. The second barrier layer 53 may overlap with the conductive pad 48.

[0054] A protruding pattern 57 can be disposed on the second seed layer 54 within the via 27H. The protruding pattern 57 can have a horizontal width smaller than that of the via 27H. The horizontal width of the via 27H is W1. The horizontal width of the protruding pattern 57 is W2. W2 is smaller than W1. The protruding pattern 57 can have a horizontal width smaller than that of the second seed layer 54. The protruding pattern 57 can have a horizontal width smaller than that of the second barrier layer 53. The horizontal width of the second barrier layer 53 and the horizontal width of the second seed layer 54 are both W3. W2 is smaller than W3.

[0055] The horizontal width of UBM layer 63 can be greater than the horizontal width of via 27H. The horizontal width of UBM layer 63 is W3. W3 is greater than W1. UBM layer 63 can fill the space between the sidewall of via 27H and the protruding pattern 57. UBM layer 63 can contact the second seed layer 54 in the region between the sidewall of via 27H and the protruding pattern 57. The protruding pattern 57 helps reduce topographic variations on the upper surface of UBM layer 63. As a result, UBM layer 63 can have a substantially flat upper surface.

[0056] A cover layer 65 may be disposed on the UBM layer 63. The cover layer 65 may have a thickness less than that of the UBM layer 63. The cover layer 65 may conformally cover the UBM layer 63. In some embodiments, the cover layer 65 may be omitted. A second barrier layer 53 and a second seed layer 54 may be disposed between the conductive pad 48 and the raised pattern 57. A second barrier layer 53 and a second seed layer 54 may be disposed between the conductive pad 48 and the UBM layer 63. A second barrier layer 53 and a second seed layer 54 may be disposed between the third insulating layer 27 and the UBM layer 63.

[0057] In this embodiment, UBM layer 63 may include a first segment 68A1, a second segment 68A2, and a third segment 68A3. The first segment 68A1 of UBM layer 63 may overlap with the protruding pattern 57. The first segment 68A1 of UBM layer 63 may overlap with the center of the via 27H. The second segment 68A2 of UBM layer 63 may overlap with the space between the third insulating layer 27 and the protruding pattern 57. The second segment 68A2 of UBM layer 63 does not overlap with the third insulating layer 27. The second segment 68A2 of UBM layer 63 may extend to the outside of the first segment 68A1 of UBM layer 63. The third segment 68A3 of UBM layer 63 may overlap with the third insulating layer 27. The third segment 68A3 of UBM layer 63 may extend to the outside of the second segment 68A2 of UBM layer 63. The second segment 68A2 of the UBM layer 63 can be disposed between the first segment 68A1 and the third segment 68A3 of the UBM layer 63. The upper surfaces of the first segment 68A1, the second segment 68A2 and the third segment 68A3 of the UBM layer 63 can be disposed at a height higher than the uppermost end of the third insulating layer 27.

[0058] In this embodiment, the upper surfaces of the first segment 68A1, the second segment 68A2, and the third segment 68A3 of the UBM layer 63 can form substantially the same plane. The upper surfaces of the first segment 68A1, the second segment 68A2, and the third segment 68A3 of the UBM layer 63 can be positioned at substantially the same height.

[0059] Reference Figure 4 The upper surface of the first segment 68A1 of the UBM layer 63 can be set at approximately the same height as the upper surface of the third segment 68A3 of the UBM layer 63. The distance between the upper surface of the first segment 68A1 of the UBM layer 63 and the conductive pad 48 can be approximately the same as the distance between the upper surface of the third segment 68A3 of the UBM layer 63 and the conductive pad 48.

[0060] The upper surface of the second segment 68A2 of the UBM layer 63 may include a recessed region 68C. In an embodiment, the UBM layer 63 may be formed using an electroplating method. The process of forming the UBM layer 63 may include forming a nickel (Ni) layer at a substantially uniform ratio along the surface of the second seed layer 54' and the surface of the protruding pattern 57. The nickel layer formed by electroplating may be formed along the surface profile. The recessed region 68C may be formed corresponding to the height difference between the surface of the second seed layer 54' and the surface of the protruding pattern 57.

[0061] The via 27H can pass through the third insulating layer 27 in the vertical direction VD. The third segment 68A3 of the UBM layer 63 can be defined as the area overlapping with the third insulating layer 27. The first segment 68A1 of the UBM layer 63 can be defined as the area overlapping with the protruding pattern 57. The second segment 68A2 of the UBM layer 63 can be defined between the first segment 68A1 and the third segment 68A3. The second segment 68A2 of the UBM layer 63 does not overlap with the third insulating layer 27 or the protruding pattern 57. A recessed region 68C can be formed in the middle of the second segment 68A2 of the UBM layer 63. The recessed region 68C can overlap with the middle between the third insulating layer 27 and the protruding pattern 57. The distance between the bottom of the recessed region 68C and the conductive pad 48 can be less than the distance between the top of the third segment 68A3 of the UBM layer 63 and the conductive pad 48. The distance between the bottom of the recessed region 68C and the conductive pad 48 can be less than the distance between the top of the first segment 68A1 of the UBM layer 63 and the conductive pad 48.

[0062] The cover layer 65 can conformally cover the UBM layer 63. An undercut region UC1 can be disposed between the third insulating layer 27 and the UBM layer 63. The second barrier layer 53' and the second seed layer 54' can have a narrower horizontal width than the UBM layer 63. The horizontal width of the UBM layer 63 is W3'. Each of the horizontal widths of the second barrier layer 53' and the second seed layer 54' is W4'. W4' is less than W3'.

[0063] Reference Figure 5 and Figure 6 The protruding pattern 57' can be cylindrical. The UBM layer 63 can cover the protruding pattern 57' and fill the through-hole 27H. (Similar to reference...) Figure 4 As described, the upper surface of UBM layer 63 may include a recessed region 68C formed corresponding to the height difference between the surface of the second seed layer 54 and the surface of the protruding pattern 57'. The recessed region 68C may be aligned along the space between the third insulating layer 27 and the protruding pattern 57'. The recessed region 68C may be formed in a circular groove shape. In an embodiment, the recessed region 68C may overlap the middle between the third insulating layer 27 and the protruding pattern 57'.

[0064] Figure 7 and Figure 8 This is a cross-sectional view showing a semiconductor package according to an embodiment of the present disclosure.

[0065] Reference Figure 7 The semiconductor package according to embodiments of the present disclosure may include a wiring structure 21, a first semiconductor chip 90, a second semiconductor chip 97, an external solder interconnect 572, an external electrode 589, and a package layer 593.

[0066] The first semiconductor chip 90 and the second semiconductor chip 97 can be mounted on the wiring structure 21. The second semiconductor chip 97 may include a semiconductor chip of a different type than the first semiconductor chip 90. The second semiconductor chip 97 may include a fourth solder interconnect 72', a second chip electrode 89', a second substrate 95, and a second circuit layer 96. The second circuit layer 96 may be disposed on the lower surface of the second substrate 95. The second chip electrode 89' may be disposed on the second circuit layer 96. The fourth solder interconnect 72' may be disposed between the UBM layer 63 and the second chip electrode 89'. The encapsulation layer 593 may cover the wiring structure 21, the first semiconductor chip 90, and the second semiconductor chip 97.

[0067] Reference Figure 8 The semiconductor package according to embodiments of the present disclosure may include a wiring structure 21, a substrate chip 310, core chips 320, 330 and 340, a top chip 350, external solder interconnects 572, a first packaging layer 591, and a second packaging layer 592'. A multi-chip package including a substrate chip 310, core chips 320, 330 and 340, a top chip 350, and a first packaging layer 591 may be mounted on the wiring structure 21.

[0068] The substrate chip 310 may include substrate chip electrodes 189 disposed on the substrate circuit layer 317. A third solder interconnect 172 may be disposed between the UBM layer 63 and the substrate chip electrodes 189. A second package layer 592' may cover the wiring structure 21, the substrate chip 310, the core chips 320, 330, and 340, the top chip 350, and the first package layer 591. The second package layer 592' may extend between the wiring structure 21 and the substrate chip 310. The second package layer 592' may directly contact the side surfaces of the UBM layer 63, the third solder interconnect 172, and the substrate chip electrodes 189.

[0069] Figure 9 and Figures 16 to 19 This is a cross-sectional view illustrating a method for forming a semiconductor package according to an embodiment of the present disclosure. Figures 10 to 15 It is shown Figure 9 and Figure 16 Partial cross-sectional view of section 110'.

[0070] Reference Figure 9 and Figure 10 A buffer layer 212 can be formed on a carrier substrate 211. A wiring structure 21 can be formed on the buffer layer 212. The wiring structure 21 may include a first insulating layer 23, a second insulating layer 25, a third insulating layer 27, a via 27H, a first via electrode 31, a first horizontal electrode 38, a second via electrode 41, a conductive pad 48, and a second horizontal electrode 48'. The conductive pad 48 and the second horizontal electrode 48' may include a first barrier layer 43 and 43', a first seed layer 44 and 44', and a first conductive layer 45 and 45'.

[0071] A first insulating layer 23 may be formed on a buffer layer 212. A first through-hole electrode 31 may penetrate the first insulating layer 23 in the vertical direction VD. A first horizontal electrode 38 may be formed on the first insulating layer 23. The first through-hole electrode 31 may contact the side surface of the first horizontal electrode 38.

[0072] The second insulating layer 25 may cover the first insulating layer 23, the first via electrode 31, and the first horizontal electrode 38. The second via electrode 41 may penetrate the second insulating layer 25 in the vertical direction VD. The second via electrode 41 may contact the first horizontal electrode 38. Conductive pads 48 and a second horizontal electrode 48' may be formed on the second insulating layer 25. The second horizontal electrode 48' may contact the second via electrode 41. The conductive pads 48 may contact the side surface of the second horizontal electrode 48'.

[0073] The third insulating layer 27 may cover the second insulating layer 25, the second via electrode 41, the conductive pad 48, and the second horizontal electrode 48'. The via 27H may pass through the third insulating layer 27 in the vertical direction VD. The via 27H may overlap with the conductive pad 48. The conductive pad 48 may be exposed at the bottom of the via 27H.

[0074] The carrier substrate 211 may include a glass wafer or a silicon wafer. The buffer layer 212 may include a release layer, an adhesive, or a combination thereof. Each of the first insulating layer 23, the second insulating layer 25, and the third insulating layer 27 may include polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), polyhydroxystyrene (PHS), polyimide isoindoquinazolinidone (PIQ), or a combination thereof.

[0075] In an embodiment, each of the first through-hole electrode 31, the first horizontal electrode 38, the second through-hole electrode 41, the conductive pad 48, and the second horizontal electrode 48' may be formed using an electroplating method. Each of the first through-hole electrode 31, the first horizontal electrode 38, the second through-hole electrode 41, the conductive pad 48, and the second horizontal electrode 48' may include a copper layer.

[0076] In an embodiment, the conductive pad 48 and the second horizontal electrode 48' may include first barrier layers 43 and 43', first seed layers 44 and 44' located on the first barrier layers 43 and 43', and first conductive layers 45 and 45' located on the first seed layers 44 and 44'. The first barrier layers 43 and 43' may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof. The first seed layers 44 and 44' may include a conductive material such as copper. The first seed layers 44 and 44' may be formed using a PVD method. The first conductive layers 45 and 45' may include copper layers. The first conductive layers 45 and 45' may be formed using an electroplating method. In an embodiment, the electroplating method may be advantageous when forming a copper layer with low resistivity within a short time period. In an embodiment, the thin film formation rate of the electroplating method may be faster than that of the PVD or CVD methods.

[0077] Reference Figure 11 The second barrier layer 53 may be formed on the third insulating layer 27. The second barrier layer 53 may conformally cover the inner wall of the via 27H. The second barrier layer 53 may contact the conductive pad 48. The second barrier layer 53 may contact the side surface and the top surface of the third insulating layer 27. The second barrier layer 53 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof.

[0078] A second seed layer 54 may be formed on the second barrier layer 53. The second seed layer 54 may include a conductive material such as copper. In some embodiments, the second seed layer 54 may be omitted.

[0079] Reference Figure 12 The first mask pattern 57M can be formed on the second barrier layer 53 and the second seed layer 54. The first mask pattern 57M can cover the edge of the via 27H.

[0080] Reference Figure 13The protruding pattern 57 can be formed on the portion of the second seed layer 54 not covered by the first mask pattern 57M. The space between the protruding pattern 57 and the sidewall of the via 27H can be covered by the first mask pattern 57M. The protruding pattern 57 can have a smaller horizontal width than the via 27H. The protruding pattern 57 can overlap with the center of the via 27H. The uppermost surface of the protruding pattern 57 can be formed at substantially the same height as the uppermost surface of the third insulating layer 27 or at a height lower than the uppermost surface of the third insulating layer 27. In an embodiment, the protruding pattern 57 may include a copper layer. The protruding pattern 57 can be formed using an electroplating method.

[0081] Reference Figure 14 A second mask pattern 62M can be formed on the second seed layer 54. The second mask pattern 62M can be formed after removing the first mask pattern 57M. Alternatively, the second mask pattern 62M can be formed by additionally processing the first mask pattern 57M. The second seed layer 54 can be exposed between the second mask pattern 62M and the protruding pattern 57.

[0082] Reference Figure 15 UBM layer 63 can be formed on the protruding pattern 57 and the second seed layer 54 not covered by the second mask pattern 62M. UBM layer 63 covers the protruding pattern 57 and fills the via 27H. Capping layer 65 can be formed on UBM layer 63. In an embodiment, UBM layer 63 may include a nickel (Ni) layer. UBM layer 63 can be formed using an electroplating method. Capping layer 65 may include a gold (Au) layer.

[0083] UBM layer 63 can completely fill the via 27H. UBM layer 63 can extend onto the third insulating layer 27. UBM layer 63 can have a larger horizontal width than the via 27H. UBM layer 63 can cover the side and top surfaces of the protruding pattern 57. UBM layer 63 can fill the space between the sidewalls of the via 27H and the protruding pattern 57.

[0084] The process of forming the UBM layer 63 may include forming an electroplated layer at a substantially uniform ratio along the surface of the electrode. In an embodiment, the process of forming the UBM layer 63 may include forming a nickel (Ni) layer at a substantially uniform ratio along the surface of the second seed layer 54 and the surface of the protrusion pattern 57. In an embodiment, because the nickel layer formed by electroplating is formed along the surface profile, the nickel layer formed on the surface including the via 27H may have a morphological variation corresponding to the shape of the via 27H. In an embodiment, when solder interconnects are formed on the morphological variation corresponding to the shape of the via 27H, voids may be formed due to the morphological variation, which may weaken the connection strength of the solder interconnects. In an embodiment, the protrusion pattern 57 is configured to reduce the morphological variation of the upper surface of the UBM layer. In an embodiment, the morphological variation of the UBM layer 63 can be minimized by the protrusion pattern 57.

[0085] Cover layer 65 may cover UBM layer 63. Cover layer 65 may have a smaller thickness than UBM layer 63. Cover layer 65 may be omitted.

[0086] Reference Figure 16 By removing the second mask pattern 62M and partially removing the second barrier layer 53 and the second seed layer 54, the UBM layer 63 and the third insulating layer 27 can be exposed. The UBM layer 63 and the third insulating layer 27 may include, for example: Figures 3 to 6 The various shapes shown.

[0087] In an embodiment, the process of removing the second barrier layer 53 and the second seed layer 54 to expose the third insulating layer 27 may include an etching process. For example... Figure 4 As shown, when the etching process is performed, the second barrier layer 53 and the second seed layer 54 may be over-etched, thereby forming an undercut region UC1 between the third insulating layer 27 and the UBM layer 63.

[0088] Reference Figure 17 The first semiconductor chip 90 can be mounted on the wiring structure 21. The first semiconductor chip 90 may include a first substrate 91 and a first circuit layer 93. Chip electrodes 89 can be formed on the first circuit layer 93. A first solder interconnect 72 can be formed between the UBM layer 63 and the chip electrodes 89.

[0089] A multi-chip package, including a base chip 310, core chips 320, 330, and 340, a top chip 350, and a first packaging layer 591, can be mounted on the wiring structure 21. Base chip electrodes 189 can be disposed on the base circuit layer 317 of the base chip 310. A third solder interconnect 172 can be formed between the UBM layer 63 and the base chip electrodes 189.

[0090] Refer again Figure 2 , Figure 3 and Figure 17 Each of the chip electrode 89, the substrate chip electrode 189, the conductive pattern 313, the substrate through electrode 319, the first core through electrode 329, the second core through electrode 339, the third core through electrode 349, the substrate rear electrode 416, the first core rear electrode 426, the second core rear electrode 436, the third core rear electrode 446, the first core front electrode 429, the second core front electrode 439, the third core front electrode 449, and the top front electrode 459 may include a metal, a metal nitride, conductive carbon, or a combination thereof.

[0091] In an embodiment, the third barrier layer 83 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The third seed layer 84 may include a conductive material such as copper. The second conductive layer 85 may include a columnar shape. The second conductive layer 85 may be formed using an electroplating method. The second conductive layer 85 may include a copper layer. A third conductive layer 88 may be formed on the second conductive layer 85. The third conductive layer 88 may be formed using an electroplating method. The third conductive layer 88 may include a nickel (Ni) layer.

[0092] Each of the first solder interconnect 72, the third solder interconnect 172, and the second solder interconnect 472 may include tin (Sn), silver (Ag), copper (Cu), bismuth (Bi), indium (In), zinc (Zn), gold (Au), palladium (Pd), antimony (Sb), or combinations thereof. The first intermetallic compound layer IM1 may include all materials forming the third solder interconnect 172 and the UBM layer 63. In an embodiment, the first intermetallic compound layer IM1 may include all materials forming the third solder interconnect 172, the UBM layer 63, and the capping layer 65 (see [link to previous embodiment]). Figure 15 The second intermetallic compound layer IM2 may include all the materials forming the third solder interconnect 172 and the third conductive layer 88.

[0093] Each of the first substrate 91, base substrate 311, first core substrate 321, second core substrate 331, third core substrate 341, and top substrate 351 may include a semiconductor substrate such as a silicon wafer or a silicon-on-insulator (SOI) wafer. Each of the first substrate 91, base substrate 311, first core substrate 321, second core substrate 331, third core substrate 341, and top substrate 351 may include a group III-V semiconductor substrate (e.g., a compound semiconductor substrate such as gallium arsenide (GaAs)). Each of the first substrate 91, base substrate 311, first core substrate 321, second core substrate 331, third core substrate 341, and top substrate 351 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or combinations thereof.

[0094] The first encapsulation layer 591 may include an epoxy molding compound.

[0095] Reference Figure 18 A second encapsulation layer 592 can be formed, covering the wiring structure 21, the first semiconductor chip 90, the substrate chip 310, the core chips 320, 330 and 340, the top chip 350, and the first encapsulation layer 591. The second encapsulation layer 592 can extend between the wiring structure 21 and the first semiconductor chip 90, and between the wiring structure 21 and the substrate chip 310. The second encapsulation layer 592 may include epoxy molding compound.

[0096] Reference Figure 19 The carrier substrate 211 and buffer layer 212 can be removed. An external electrode 589 can be formed on the lower surface of the wiring structure 21. The external electrode 589 can contact the first through-hole electrode 31. An external solder interconnect 572 can be formed on the external electrode 589. A dicing process can be used to divide the semiconductor package.

[0097] External electrode 589 may include copper (Cu). External solder interconnect 572 may include tin (Sn), silver (Ag), copper (Cu), bismuth (Bi), indium (In), zinc (Zn), gold (Au), palladium (Pd), antimony (Sb), or combinations thereof.

[0098] While detailed embodiments of the present disclosure have been presented herein, those skilled in the art will understand that various modifications, additions, and substitutions related to these embodiments can be made without departing from the scope and concept of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the foregoing embodiments. All variations within the meaning and equivalents of the claims are included within the scope of the claims.

[0099] Cross-reference to related applications

[0100] This application claims priority to Korean Patent Application No. 10-2024-0191559, filed on December 19, 2024, with the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor package, the semiconductor package comprising: The wiring structure includes a first insulating layer, a conductive pad on the first insulating layer, a second insulating layer on the conductive pad, a via through the second insulating layer and overlapping the conductive pad, a protruding pattern disposed on the conductive pad and located in the via, and a bump under metallization (UBM) layer that contacts the upper surface and side surface of the protruding pattern and is connected to the conductive pad. as well as A semiconductor chip disposed on the wiring structure and connected to the UBM layer.

2. The semiconductor package according to claim 1, wherein, The protruding pattern has a smaller horizontal width than the through hole.

3. The semiconductor package according to claim 1, wherein, The protruding pattern overlaps with the center of the through hole.

4. The semiconductor package according to claim 1, wherein, The uppermost surface of the protruding pattern is positioned at the same height as or at a lower height than the uppermost surface of the second insulating layer.

5. The semiconductor package according to claim 1, wherein, The UBM layer includes a first segment overlapping the protruding pattern, a second segment overlapping the space between the second insulating layer, and a third segment overlapping the second insulating layer. The upper surfaces of the first section, the second section, and the third section are positioned at a height higher than the uppermost surface of the second insulating layer.

6. The semiconductor package according to claim 5, wherein, The upper surfaces of the first segment, the second segment, and the third segment form approximately the same plane.

7. The semiconductor package according to claim 5, wherein, The upper surface of the second segment includes a recessed area, and The distance between the recessed area and the conductive pad is less than the distance between the upper surface of the third segment and the conductive pad.

8. The semiconductor package according to claim 5, wherein, The upper surface of the second segment includes a recessed area, and The distance between the recessed area and the conductive pad is less than the distance between the upper surface of the first segment and the conductive pad.

9. The semiconductor package according to claim 5, wherein, The upper surface of the second segment includes a recessed area, and The recessed area overlaps with the middle of the second insulating layer and the protruding pattern.

10. The semiconductor package of claim 1, further comprising: A barrier layer is disposed between the raised pattern and the conductive pad, extends onto the conductive pad between the raised pattern and the second insulating layer, and extends between the UBM layer and the second insulating layer. The barrier layer comprises titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof.

11. The semiconductor package of claim 10, further comprising: A seed layer is located between the protruding pattern and the barrier layer, and between the UBM layer and the barrier layer. The seed layer includes a conductive material.

12. The semiconductor package according to claim 1, wherein, The prominent pattern includes a copper (Cu) layer.

13. The semiconductor package according to claim 1, wherein, The UBM layer includes a nickel (Ni) layer.

14. The semiconductor package according to claim 1, further comprising: Solder interconnects are located between the UBM layer and the semiconductor chip. The solder interconnects include tin (Sn), silver (Ag), copper (Cu), bismuth (Bi), indium (In), zinc (Zn), gold (Au), palladium (Pd), antimony (Sb), or combinations thereof.

15. A semiconductor package, the semiconductor package comprising: The wiring structure includes a first insulating layer, a plurality of conductive pads on the first insulating layer, a second insulating layer on the plurality of conductive pads, a plurality of vias passing through the second insulating layer and overlapping the plurality of conductive pads, a plurality of protruding patterns disposed on the plurality of conductive pads and located in the plurality of vias, and a plurality of under-bump metallization (UBM) layers that contact the upper and side surfaces of the plurality of protruding patterns and are connected to the plurality of conductive pads. A first semiconductor chip and a second semiconductor chip are disposed on the wiring structure; as well as An encapsulation layer is disposed on the wiring structure and covers the first semiconductor chip and the second semiconductor chip.

16. The semiconductor package of claim 15, further comprising: Multiple solder interconnects are respectively disposed between the multiple UBM layers and the first semiconductor chip, and between the multiple UBM layers and the second semiconductor chip. The encapsulation layer extends between the wiring structure and the first semiconductor chip, and between the wiring structure and the second semiconductor chip. The encapsulation layer contacts the side surfaces of the plurality of UBM layers and the side surfaces of the plurality of solder interconnects.

17. The semiconductor package of claim 15, wherein, Each of the plurality of UBM layers includes a first segment overlapping a corresponding protruding pattern among the plurality of protruding patterns, a second segment spatially overlapping the second insulating layer and the corresponding protruding pattern among the plurality of protruding patterns but not overlapping the second insulating layer, and a third segment overlapping the second insulating layer. The upper surfaces of the first section, the second section, and the third section are positioned at a height higher than the uppermost surface of the second insulating layer.

18. The semiconductor package of claim 17, wherein, The upper surface of the second segment includes a recessed area, and The distance between the recessed area and the corresponding conductive pad among the plurality of conductive pads is less than the distance between the upper surface of the third segment and the corresponding conductive pad among the plurality of conductive pads.

19. The semiconductor package of claim 17, wherein, The upper surface of the second segment includes a recessed area, and The distance between the recessed area and the corresponding conductive pad among the plurality of conductive pads is less than the distance between the upper surface of the first segment and the corresponding conductive pad among the plurality of conductive pads.

20. A semiconductor package, the semiconductor package comprising: First insulating layer; A conductive pad, wherein the conductive pad is located on the first insulating layer; A second insulating layer is located on the conductive pad; A through-hole, the through-hole passing through the second insulating layer and overlapping with the conductive pad; A raised pattern is provided on the conductive pad and located in the via, and includes a horizontal width smaller than that of the via; Under-bump metallized UBM layer, the UBM layer contacts the upper and side surfaces of the protruding pattern and includes a horizontal width larger than the via, the upper surface of the UBM layer including a recessed region that overlaps with the space between the protruding pattern and the second insulating layer; as well as A semiconductor chip located on the UBM layer.

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