Semiconductor device package and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device package and a method of manufacturing the same. The semiconductor device package includes a first electronic component having an active surface and a back surface opposite to the active surface, and a first antenna layer disposed on the back surface of the first electronic component. The semiconductor device package further includes a first dielectric layer covering the first antenna layer, and a second antenna layer disposed over the first antenna layer. The second antenna layer is spaced apart from the first antenna layer by the first dielectric layer.

Description

[0001] This application is a divisional application of the invention patent application filed on November 19, 2020, with application number 202011300775.2 and title "Semiconductor Device Packaging and Manufacturing Method Thereof". Technical Field

[0002] This disclosure generally relates to a semiconductor device package and a method of manufacturing the same, and more particularly to a semiconductor device package having an antenna layer. Background Technology

[0003] Wireless communication devices such as mobile phones may include one or more semiconductor device packages with antennas for transmitting signals (e.g., radio frequency (RF) signals). As the operating frequency increases (e.g., equal to or greater than 28 GHz), the resonant cavities (e.g., height or distance) between the antennas must be wider to enable frequency agility and increase bandwidth. However, this increased distance inevitably increases the package size, and heat dissipation issues may become severe. Summary of the Invention

[0004] In one or more embodiments, this disclosure provides a semiconductor device package. The semiconductor device package includes: a first electronic component having an active surface and a back surface opposite to the active surface; and a first antenna layer disposed on the back surface of the first electronic component. The semiconductor device package further includes a first dielectric layer covering the first antenna layer; and a second antenna layer disposed on top of the first antenna layer. The second antenna layer is spaced apart from the first antenna layer by the first dielectric layer.

[0005] In one or more embodiments, this disclosure provides a semiconductor device package. The semiconductor device package includes: an electronic component having an active surface and a back surface; and an antenna pattern disposed directly on the back surface of the electronic component. The semiconductor device package further includes a dielectric layer disposed on the back surface of the electronic component and covering the antenna pattern.

[0006] In one or more embodiments, this disclosure provides a method for manufacturing a semiconductor device package. The method includes providing an electronic component having an active surface and a back surface opposite the active surface. The method further includes: forming an antenna layer on the back surface of the electronic component; and forming a dielectric layer on the back surface of the electronic component to cover the antenna layer. Attached Figure Description

[0007] When with attachment Figure 1When reading the following detailed description, various aspects of this disclosure can be readily understood. It should be noted that the various features may not necessarily be drawn to scale. For clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 This is a cross-sectional view of a semiconductor device package according to an embodiment of the present disclosure.

[0009] Figure 2 This is a cross-sectional view of a semiconductor device package according to another embodiment of the present disclosure.

[0010] Figure 3A One or more stages of a method for manufacturing a substrate structure according to some embodiments of the present disclosure are shown.

[0011] Figure 3B One or more stages of a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure are shown.

[0012] Figure 3C One or more stages of a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure are shown.

[0013] Figure 3D One or more stages of a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure are shown.

[0014] Figure 3E One or more stages of a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure are shown.

[0015] Figure 3F One or more stages of a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure are shown.

[0016] Figure 3G One or more stages of a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure are shown.

[0017] Figure 3H One or more stages of a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure are shown.

[0018] Throughout the accompanying drawings and detailed description, common reference numerals are used to indicate the same or similar elements. This disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, references to forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0021] Figure 1 This is a cross-sectional view of a semiconductor device package 1 according to an embodiment of the present disclosure. The semiconductor device package 1 includes electronic components 10 and 18, antenna layers 11 and 13, dielectric layer 12, electrical contacts 14 and 17, interconnect structure 15, and package body 16.

[0022] Electronic component 10 may include, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. Electronic component 10 may include active components, such as integrated circuit (IC) chips or dies. Electronic component 10 may include, for example, but not limited to, silicon (Si), gallium arsenide (GaAs), glass, or other suitable materials. In some embodiments, electronic component 10 may be a semiconductor wafer or panel, such as a silicon wafer, and may include multiple semiconductor chips.

[0023] Electronic component 10 includes a surface 101, a surface 102 opposite to surface 101, and a surface 103 extending between surface 101 and surface 102. In some embodiments, surface 102 is an active surface, and surface 101 is a passive surface or a back surface. A plurality of conductive elements 11c may be adjacent to surface 102, adjacent to surface 102, embedded in surface 102, and / or partially exposed from surface 102. The conductive elements 11c are positioned closer to surface 102 than surface 101. In some embodiments, the conductive elements 11c include a fan-out structure.

[0024] Examples of conductive element 11c may include, for example, conductive pads, conductive pillars, solder bumps, grounding elements, radio frequency (RF) routing layers, etc. Electronic assembly 10 may include a passivation layer 10d on surface 102, the passivation layer being used to fully expose conductive element 11c or expose at least a portion of the conductive element, thereby enabling electrical connection. In some embodiments, the surface of passivation layer 10d is substantially coplanar with the surface 103 of electronic assembly 10.

[0025] Antenna layer 11 is disposed on surface 101 (e.g., passive surface or back surface) of electronic component 10. In some embodiments, antenna layer 11 is disposed directly on surface 101 of electronic component 10. For example, antenna layer 11 is in direct contact with surface 101 of electronic component 10.

[0026] In some embodiments, the antenna layer 11 is substantially coplanar. For example, the antenna layer 11 has a horizontal or flat surface and no protrusions or depressions. For example, the antenna layer 11 is substantially flush with the surface 101 of the electronic component 10.

[0027] In some embodiments, antenna layer 11 may be a patch antenna. In some embodiments, antenna layer 11 may comprise a conductive material such as a metal or metal alloy. Examples of conductive materials include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof. In some embodiments, antenna layer 11 may also be referred to as an antenna pattern.

[0028] The antenna layer 11 on surface 101 is electrically connected to the conductive element 11c on surface 102 via a via 11v. In some embodiments, the via 11v can be a feed line. In some embodiments, the via 11v can provide a signal to the antenna layer 11. For example, a signal can be transmitted between the conductive element 11c, the via 11v, and the antenna layer 11. The via 11v passes through the electronic component 10. For example, the via 11v penetrates from surface 101 of the electronic component 10 to surface 102 of the electronic component 10.

[0029] The dielectric layer 12 is disposed on the surface 101 of the electronic component 10 and covers the antenna layer 11. The antenna layer 11 is disposed within the dielectric layer 12. For example, the antenna layer 11 may be encapsulated, covered or surrounded by the dielectric layer 12.

[0030] The dielectric layer 12 includes a surface 121, a surface 122 opposite to surface 121, and a surface 123 extending between surfaces 121 and 122. Surface 122 of the dielectric layer 12 contacts the surface 101 of the antenna layer 11 and the electronic component 10. Surface 121 of the dielectric layer 12 contacts the antenna layer 13. In some embodiments, surface 123 of the dielectric layer 12 is substantially coplanar with surface 103 of the electronic component 10.

[0031] In some embodiments, dielectric layer 12 may comprise, for example, but not limited to, polytetrafluoroethylene (PTFE), polyimide (PI), polyphenylene ether (PPE), polystyrene (PS), any combination thereof, or other suitable materials. In some embodiments, dielectric layer 12 may comprise a ceramic material. In some embodiments, dielectric layer 12 may comprise a material different from that of electronic component 10.

[0032] In some embodiments, the dielectric constant (Dk) of dielectric layer 12 is lower than that of electronic component 10. In some embodiments, the dielectric constant of dielectric layer 12 is lower than about 4.0. In some embodiments, the dielectric constant of dielectric layer 12 is between about 1.0 and about 4.0, such as about 3.5.

[0033] The arrangement of the antenna layer 11 on surface 101 of the electronic component 10 according to this disclosure can be referred to as an antenna-on-chip (AoC) structure. The height or thickness of the electronic component 10, measured between surface 101 and surface 102, defines the resonant cavity between the antenna layer 11 and the reference layer or ground layer (located on surface 102 of the electronic component 10). A dielectric layer 12 with a low dielectric constant (e.g., lower than the dielectric constant of the electronic component 10) facilitates frequency agility and increases the bandwidth of the antenna layer 11.

[0034] Compared to a comparative embodiment where the antenna layer is disposed on the active surface of the electronic component, heat generated from the electronic component 10 can be dissipated through the surface (i.e., the active surface) 102 without being blocked by the antenna layer 11. Furthermore, since electrical interconnections or signal transmissions can be achieved through electrical contacts 14 disposed on the surface 102 of the electronic component 10, such electrical interconnections or signal transmissions can be facilitated.

[0035] Antenna layer 13 is disposed on dielectric layer 12. Antenna layer 13 is in contact with dielectric layer 12. Antenna layer 13 is disposed on top of antenna layer 11. Antenna layer 13 is spaced apart from antenna layer 11 by dielectric layer 12.

[0036] In some embodiments, antenna layer 13 partially overlaps antenna layer 11 in a direction substantially perpendicular to surface 102 (or surface 101) of electronic component 10. For example, the projected region of antenna layer 13 partially overlaps with the projected region of antenna layer 11. In some embodiments, the projected region of antenna layer 13 may be equal to or larger than the projected region of antenna layer 11.

[0037] Similarly, in some embodiments, antenna layer 13 is substantially coplanar. In some embodiments, antenna layer 13 may be a patch antenna.

[0038] In some embodiments, signals can be transmitted between antenna layer 13 and antenna layer 11 via coupling. In some embodiments, the semiconductor device package 1 may contain only antenna layer 11 and may omit antenna layer 13. In some embodiments, embodiments having antenna layers 11 and 13 can enable higher frequency wireless transmissions compared to embodiments having only antenna layer 11.

[0039] Interconnection structure 15 is electrically connected to electronic component 10 via electrical contact 14. Interconnection structure 15 includes a surface 151 facing the surface 102 of electronic component 10 and a surface 152 opposite to surface 151. Electrical contact 14 is disposed on surface 151. Electrical contact 17 and electronic component 18 are disposed on surface 152.

[0040] Interconnect structure 15 may include, for example, an interconnect layer (e.g., a redistribution layer, RDL) and a dielectric layer. A portion of the interconnect layer is covered or encapsulated by the dielectric layer, while another portion of the interconnect layer may be exposed from the dielectric layer to provide electrical connections between electronic component 10 and electronic component 18.

[0041] Electronic component 18 is electrically connected to conductive element 11c on surface 102 of electronic component 10 via electrical contact 14 and interconnection structure 15.

[0042] In some embodiments, electronic component 18 may include passive electrical components such as capacitors, resistors, or inductors. In some embodiments, electronic component 18 may include multiple discrete components. In some embodiments, electronic component 18 may include an integrated passive device (IPD) or an integrated passive component (IPC), wherein electronic components (such as resistors, capacitors, inductors / coils, microstrip lines, impedance matching elements, or any combination thereof) are integrated into a package. In some embodiments, electronic component 18 may act as an impedance matching device for matching the input / output impedance of antenna layer 11 and / or antenna layer 13. In some embodiments, electronic component 18 may act as a decoupling capacitor to suppress unwanted noise.

[0043] In some embodiments, such as Figure 1 As shown, the interconnect structure 15 defines a cavity on surface 152, and the electronic component 18 is disposed within the cavity. The cavity is defined within the interconnect structure 15. The cavity is recessed from surface 152 into surface 151. In some embodiments, the depth of the cavity is equal to or greater than the height of the highest or thickest electronic component 18 mounted on surface 152, in order to protect the electronic component 18 from damage.

[0044] Package 16 is disposed on surface 151 of interconnect structure 15 and surrounds electronic component 10. Package 16 covers or surrounds surface 103 of electronic component 10. Package 16 is disposed between surface 102 of electronic component 10 and surface 151 of interconnect structure 15.

[0045] The encapsulation 16 may contain, for example, an epoxy resin with filler, a molding material (e.g., an epoxy resin molding material or other molding material), a polyimide, a phenolic material or material, a material having silicone dispersed therein, or a combination thereof.

[0046] In some embodiments, the amount of filler in the package 16 can affect the thermal conductivity of the package 16. For example, the package 16 has a better heat transfer capability than the bottom filler because the amount of filler in the package 16 is greater than the amount of filler in the bottom filler. In some embodiments, the package 16 covering the surface 102 of the electronic component 10 can help dissipate heat generated from the electronic component 10.

[0047] In some embodiments, the roughness of the upper surface of the package 16 (such as the surface facing away from the interconnect structure 15) is greater than the roughness of the surface 101 of the electronic component 10. For example, the average roughness (Ra) of the package 16 is from about 1.0 micrometers (μm) to about 3.0 μm, and the Ra of the package 16 subjected to a polishing operation is from about 0.4 μm to about 0.8 μm. However, the Ra of the surface 101 of the electronic component 10 is less than 0.08 μm.

[0048] In addition, the adhesion of the antenna layer 11 to the package 16 is weaker than the adhesion of the antenna layer 11 to the surface 101 of the electronic component 10.

[0049] In a comparative embodiment, the antenna layer (such as antenna layer 11) may be disposed on a package (e.g., package 16), which may have a relatively rough surface compared to the electronic component 10. A seed layer may be necessary to increase the adhesion between the antenna layer and the package. Both the relatively rough surfaces of the package and the seed layer may degrade the antenna performance of the antenna layer.

[0050] In contrast, in this disclosure, the antenna layer 11 is disposed on the surface 101 of the electronic component 10 and spaced apart from the package 16, which helps to enhance the antenna performance of the antenna layer 11. Additionally, the antenna layer 11 can be disposed on the surface 101 of the electronic component 10 without a seed layer.

[0051] Figure 2 This is a cross-sectional view of a semiconductor device package 2 according to an embodiment of the present disclosure. Figure 2 Semiconductor device package 2 in the middle is similar to Figure 1 The semiconductor device package 1 is described below, and the differences therebetween are also described below.

[0052] The semiconductor device package 2 further includes a dielectric layer 20 disposed on the dielectric layer 12 and covering the antenna layer 13. The antenna layer 21 is disposed on the dielectric layer 20 and overlaps with the antenna layer 13. The semiconductor device package 2 is a dual-band antenna structure or a dual-frequency antenna structure, such as an antenna structure for 28 / 39 GHz.

[0053] The number of antenna and dielectric layers shown in the accompanying drawings is for illustrative purposes only, and this disclosure is not limited thereto. The antenna and dielectric layers in a semiconductor device package according to this disclosure may have any number of layers, depending on design rules or requirements. For example, other dielectric layers and other antenna layers may be disposed on top of dielectric layer 20.

[0054] In some embodiments, the dielectric constant of dielectric layer 20 is different from that of dielectric layer 12. In some embodiments, the dielectric constant of dielectric layer 20 is lower than that of dielectric layer 12. In some embodiments, the coefficient of thermal expansion (CTE) of dielectric layer 20 is greater than that of dielectric layer 12. The larger CTE of dielectric layer 20 can help balance the stress introduced from passivation layer 10d on surface 102 and help mitigate warpage. For example, since both dielectric layer 20 and passivation layer 10d disposed on opposite sides of electronic component 10 have larger CTEs than other layers located internally, stress can be balanced and warpage problems in the manufacturing process can be resolved.

[0055] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G and Figure 3H These are cross-sectional views of a semiconductor device packaged according to some embodiments of the present disclosure at various manufacturing stages. At least some of these figures have been simplified to provide a better understanding of aspects of the present disclosure.

[0056] refer to Figure 3A Electronic component 10 is provided. Electronic component 10 includes a surface (or passive surface or back surface) 101, a surface (or active surface) 102 opposite to surface 101, and a surface extending between surface 101 and surface 102 (e.g., ...). Figure 1 Surface 103 is shown in the figure. A conductive pad 10p is provided on surface 102.

[0057] In some embodiments, electronic component 10 may be a semiconductor wafer (panel or substrate) comprising a plurality of units that can be separated from each other by scribe lines. Since each of the units undergoes similar or identical processes in the manufacturing process, for convenience, only exemplary units are shown and described in the following description.

[0058] refer to Figure 3B A plurality of conductive elements 11c are disposed on surface 102, and the plurality of conductive elements are connected to conductive pads 10p. A passivation layer 10d is disposed on surface 102 to fully expose the conductive elements 11c or expose at least a portion of the conductive elements.

[0059] Afterwards, refer to Figure 3C A via 11v is formed in the electronic component 10, and a portion of the via 11v is exposed from the surface 102 of the electronic component 10.

[0060] refer to Figure 3D An antenna layer 11 is disposed on surface 101, and the antenna layer is connected to a through-hole 11v. The antenna layer 11 can be formed by, for example but not limited to, electroplating Au, Ag, Cu or another metal.

[0061] refer to Figure 3E A dielectric layer 12 is disposed on the surface 101 of the electronic component 10 to cover the antenna layer 11. The dielectric layer 12 may be disposed by, for example, coating, lamination or other suitable processes.

[0062] Subsequently, reference Figure 3F An antenna layer 13, which at least partially overlaps with the antenna layer 11, is disposed on the dielectric layer 12. In some embodiments, the dielectric layer 12 and the antenna layer 13 are disposed on the surface 101 of the electronic component 10 before performing a single-cut operation (such as a package sawing or splitting operation) to separate individual semiconductor package devices. In this way, the edge distance standard D1 (in Figure 3F (As shown in the top view (b)) can be precisely aligned. On the other hand, if a single-cut operation is performed before forming the dielectric layer 12 and the antenna layer 13, the edge distance standard may deviate from the design due to unavoidable deviations or stresses caused by the single-cut operation.

[0063] Then, refer to Figure 3G The interconnect structure 15 is electrically connected to the electronic component 10 via electrical contacts 14 disposed on the surface 102. The interconnect structure 15 includes a cavity, hole, or recess 15h on the side opposite to the electronic component 10.

[0064] Next, refer to Figure 3HElectronic components 18 can be attached or bonded to the recessed portion 15h of interconnect structure 15 using batch reflow technology, flip-chip bonding technology, or one or more other suitable technologies. One or more electrical contacts 17 can be attached or bonded to conductive pads on interconnect structure 15.

[0065] A package (or encapsulation layer) can be formed on the interconnect structure 15, such as Figure 1 The package 16 shown is used to cover or encapsulate electronic components 10 and 18. In some embodiments, the package can be formed using molding techniques such as transfer molding or compression molding. A single-cut operation (e.g., using a cutting saw, laser, punching machine, or other suitable cutting technique) can be performed to cut out shapes such as... Figure 1 The discrete device package shown.

[0066] In this document, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “left,” and “right” may be used for ease of description to describe the relationship between one element or feature as shown in the accompanying drawings and one or more other elements or features. In addition to the orientations depicted in the accompanying drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or there may be an intermediate element present.

[0067] As used herein, the terms “approximately,” “substantially,” “essentially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurs precisely or instances where the event or situation is close to occurring. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. A range may be expressed herein as a distance from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise specified. The term “substantially coplanar” may mean that the positional difference between two surfaces located along the same plane is within a few micrometers (μm), such as within 10 μm, 5 μm, 1 μm, or 0.5 μm. When a numerical value or characteristic is referred to as “substantially” the same, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of said values.

[0068] The foregoing has summarized the features of several embodiments and detailed aspects of this disclosure. The embodiments described in this disclosure can readily serve as the basis for designing or modifying other processes and structures to achieve the same or similar purposes and / or realize the same or similar advantages of the embodiments described herein. Such equivalent constructions do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device package comprising: A first electronic component has a first surface and a second surface opposite to the first surface, the first electronic component including a conductive element adjacent to the first surface; A first antenna layer is disposed on the second surface of the first electronic component. The first antenna layer has a first surface and a second surface opposite to the first surface. The first surface of the first antenna layer directly contacts the second surface of the first electronic component. The first antenna layer has a patterned first portion and a patterned second portion. The patterned first portion of the first antenna layer is adjacent to the periphery of the second surface of the first electronic component. In a cross-sectional view, the patterned second portion of the first antenna layer is disposed between the patterned first portions of the first antenna layer. A first dielectric layer is disposed on the second surface of the first electronic component and encapsulates the first antenna layer, wherein the first dielectric layer contacts the second surface of the first electronic component and the second surface of the first antenna layer. as well as A patterned layer, spaced apart from and perpendicularly overlapping the first antenna layer, the patterned layer having a patterned first portion and a patterned second portion, the patterned first portion of the patterned layer being adjacent to the periphery of the second surface of the first electronic component, and the patterned second portion of the patterned layer being disposed between the patterned first portions of the patterned layer in a cross-sectional view.

2. The semiconductor device package of claim 1, wherein the patterned layer is a second antenna layer having a plurality of patterned antennas.

3. The semiconductor device package of claim 2, wherein the width of the patterned first portion of the patterned layer is greater than the width of the patterned first portion of the first antenna layer in a cross-sectional view.

4. The semiconductor device package of claim 1, wherein the width of the patterned second portion of the first antenna layer is greater than the width of the patterned first portion of the first antenna layer in a cross-sectional view.

5. The semiconductor device package of claim 1, further comprising a third antenna layer disposed above the first surface of the first electronic component, the third antenna layer overlapping the patterned second portion of the first antenna layer and a portion of a plurality of patterned antennas of the patterned layer in a direction substantially perpendicular to the first surface of the first electronic component.

6. The semiconductor device package of claim 5, wherein the third antenna layer overlaps the conductive element in a direction substantially perpendicular to the first surface of the first electronic component, the conductive element transmitting signals in the vertical direction.

7. The semiconductor device package of claim 6, further comprising a second dielectric layer located below the first electronic component, wherein the conductive element penetrates the second dielectric layer.

8. The semiconductor device package of claim 7, further comprising a package body surrounding the side of the first electronic component.

9. The semiconductor device package of claim 8, wherein the package body surrounds the sidewalls of the second dielectric layer.

10. The semiconductor device package of claim 8, wherein the first electronic component is electrically connected to an interconnect structure via electrical contacts, the electrical contacts being surrounded by the package body.

11. The semiconductor device package of claim 10, wherein the first antenna layer and the electrical contacts are projected perpendicularly onto the projected area of ​​the first electronic component, and the electrical contacts are located between the patterned first portions of the first antenna layer.

12. A semiconductor device package comprising: A first electronic component has a first surface and a second surface opposite to the first surface, the first electronic component including a conductive element adjacent to the first surface; A first antenna layer has a patterned first portion and a patterned second portion, wherein the patterned first portion of the first antenna layer is adjacent to the periphery of the second surface of the first electronic component, and the patterned second portion of the first antenna layer is disposed between the patterned first portions of the first antenna layer in a cross-sectional view. The first dielectric layer encapsulates and contacts the first antenna layer; as well as A second antenna layer, spaced apart from the first antenna layer, has a patterned first portion and a patterned second portion. The patterned first portion of the second antenna layer is adjacent to the periphery of the second surface of the first electronic component, and the patterned second portion of the second antenna layer is disposed between the patterned first portions of the second antenna layer in a cross-sectional view.

13. The semiconductor device package of claim 12, wherein the first antenna layer is closer to the first surface of the first electronic component than the second antenna layer, the first antenna layer and the second antenna layer are located on the same side relative to the first surface, and wherein the first surface is an active surface and the second surface is a back surface.

14. The semiconductor device package of claim 13, wherein the second antenna layer has a plurality of patterned antennas, and the projected area of ​​the patterned second portion of the second antenna layer on the first electronic component is greater than the projected area of ​​the patterned second portion of the first antenna layer on the first electronic component.

15. The semiconductor device package of claim 12, wherein the patterned second portion of the first antenna layer is electrically connected to the conductive element via a via.

16. The semiconductor device package of claim 15, wherein the patterned second portion of the second antenna layer overlaps the via in a direction substantially perpendicular to the first surface of the first electronic component.

17. The semiconductor device package of claim 16, further comprising a third antenna layer disposed above the first antenna layer, the third antenna layer overlapping the patterned second portion of the first antenna layer and the via in a direction substantially perpendicular to the first surface of the first electronic component.

18. The semiconductor device package of claim 12, further comprising a package body that encapsulates and contacts the side surface of the first electronic component and the first surface.

19. The semiconductor device package of claim 18, wherein the first dielectric layer contacts the first antenna layer, the second antenna layer, and the package.

20. A method for manufacturing a semiconductor device package, the method comprising: An electronic component is provided, the electronic component having an active surface and a back surface opposite to the active surface; An antenna layer is formed on the back surface of the electronic component; as well as A dielectric layer is formed on the back surface of the electronic component to cover the antenna layer.

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