A packaging method of a power device and a power device

Abstract

The application relates to the technical field of semiconductor packaging, and discloses a packaging method of a power device and the power device. The packaging method of the power device disclosed by the application controls the first positioning copper column, the upper surfaces of the first power module substrate and the second power module substrate to be in the same plane, and after the first chip and the second chip are installed on the first power module substrate and the second power module substrate, the electrically conductive surfaces of the front surface electrodes and the back surface electrodes of the chips and the surfaces of the conductive layers of the power module substrates are in the same plane. Therefore, when a redistribution layer is arranged on the power device, the depths of the vias can be uniform, and the chip electrodes can be led out only by once via electroplating connection. The via process complexity in vertical interconnection is reduced, and the packaging thickness is reduced. The application also provides a power device. By using the structural design of the power device, the process complexity in vertical interconnection is reduced, and the packaging process efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a packaging method for packaging a power device comprising at least two chips, and a power device. Background Technology

[0002] As power electronics technology advances towards higher power density, higher efficiency, and higher reliability, traditional power module packaging technologies, such as wire bonding, are increasingly unable to meet the application requirements of advanced power devices (such as SiC and GaN) due to their inherent large parasitic parameters, limited heat dissipation capabilities, and reliability issues. Therefore, in existing technologies, power devices are packaged using a power module substrate, such as a DBC substrate, combined with a molding compound. Typically, after chip mounting, multiple molding and wiring processes are required to connect the multiple chip electrodes within the package and extend the chip electrodes outside the package, facilitating chip mounting onto specific circuit boards or other devices. However, the height differences between chip electrodes and the DBC wiring layer, between different chip electrodes, and between the front and back electrodes of the same chip complicate the subsequent chip interconnection process, affecting the efficiency of chip packaging. Summary of the Invention

[0003] To address the problem that existing power devices manufactured by combining a power module substrate and a molding compound have a height difference between the chip electrode surface and the wiring layer of the power module substrate, which leads to complex chip interconnection processes during subsequent wiring and affects chip packaging efficiency, this application provides a power device packaging method and a power device manufactured using the above packaging method.

[0004] The power device packaging method provided in the first embodiment of this application includes the following steps:

[0005] S100. Establish a frame reference: Select a temporary carrier plate with parallel upper and lower planes, and apply temporary bonding adhesive to the upper surface of the temporary carrier plate; select a first positioning copper pillar, a first power module substrate, and a second power module substrate of equal height; fix the bottom surface of the first positioning copper pillar to the upper surface of the temporary carrier plate using the temporary bonding adhesive; fix the heat dissipation end of the first power module substrate and the heat dissipation end of the second power module substrate to a predetermined area on the upper surface of the temporary carrier plate. S200, Frame Construction: The first positioning copper pillar, the first power module substrate, and the second power module substrate are wrapped and fixed with molding compound to form a first molding body; the molding compound on the upper surface of the first molding body is ground to expose the upper surface of the first positioning copper pillar. Using the upper surface of the first positioning copper pillar as a reference, grinding is continued to expose the conductive layers of the first power module substrate and the second power module substrate, so that the upper surface of the first positioning copper pillar, the conductive layers of the first power module substrate and the second power module substrate are on the same plane. S300, Forming chip mounting cavities: A first cavity and a second cavity are formed from the conductive layer surface of the first power module substrate and the second power module substrate toward the ceramic layer, respectively; the depth of the first cavity is equal to the sum of the thickness of the first chip and the thickness of the chip mounting material after curing, and the depth of the second cavity is equal to the sum of the thickness of the second chip and the thickness of the chip mounting material after curing. S400, Chip Mounting: Chip mounting material is coated on the bottom of the first cavity and the second cavity. A high-precision pick-and-place machine is used to fix the back side of the first chip in the first cavity and the back side of the second chip in the second cavity. The chip mounting material enables the first chip to be bonded to the first power module substrate and the second chip to be bonded to the second power module substrate. At the same time, the electrode surfaces of the front of the first chip and the second chip are in the same plane as the conductive layer surfaces of the first power module substrate and the second power module substrate. S500. Establishing a wiring reference: Select a second positioning copper pillar. The height of the second positioning copper pillar is equal to the sum of the height of the first positioning copper pillar and the preset via depth. Apply temporary bonding adhesive to the upper surface of the temporary carrier board. Fix the bottom surface of the second positioning copper pillar to the upper surface of the temporary carrier board using the temporary bonding adhesive. Encapsulate the first molding compound, the first chip, the second chip, and the second positioning copper pillar on one side of the upper surface of the temporary carrier board using molding compound to form a second molding compound. Grind the upper surface of the second molding compound on the side away from the temporary carrier board until the upper surface of the second positioning copper pillar is exposed. Grind the upper surface of the second molding compound until it is on the same plane as the upper surface of the second positioning copper pillar. S600, Vertical Interconnection and Internal Routing: The electrode positions of the first and second chips, and the conductive layer positions of the first and second power module substrates, are determined based on the second positioning copper pillars. Via positions are determined based on the electrode and conductive layer positions. Holes are drilled at the via positions according to a preset via depth to form vias connecting the upper surface of the second molding compound and the electrodes of the first and second chips, the conductive layers of the first and second power module substrates. A seed layer is formed on the upper surface of the second molding compound and on the vias. A redistribution layer is formed on the upper surface of the second molding compound using patterning and electroplating filling processes according to the designed circuit. A vertical interconnect channel is formed in the via. The redistribution layer connects the first and second chip electrodes, the conductive layers of the first and second power module substrates, and the conductive layers of the second power module substrates through the vertical interconnect channel. This achieves the connection between the electrodes of the first and second chips, between the first chip and the conductive layer of the first power module substrate, between the second chip and the conductive layer of the second power module substrate, and between the conductive layers of the first and second power module substrates according to the designed circuit. Power device pins are formed on the redistribution layer. S700, Post-processing: Remove the temporary carrier by eliminating the adhesive force of the temporary bonding adhesive, and then complete the post-processing to obtain the power device.

[0006] The power device packaging method provided in this application provides a flat base bearing surface through a temporary carrier board. The selected first positioning copper pillar, first power module substrate, and second power module substrate have the same height, so that the upper surface of the first positioning copper pillar, the conductive layer of the first power module substrate, and the conductive layer of the second power module substrate, which are installed on the same plane of the temporary carrier board, are on the same plane. During the first grinding process, using the upper surface of the first positioning copper pillar as a reference, a flat surface can be formed on the upper surface of the first molding compound. This ensures that the upper surface of the first positioning copper pillar, the conductive layer of the first power module substrate, and the conductive layer of the second power module substrate are all on the flat surface. Then, by precisely controlling the depth of the first and second cavities, as well as the mounting position and mounting accuracy of the first and second chips, the electrodes on the front of the first and second chips are all in the same flat plane as the upper surface of the first positioning copper pillar, the conductive layer of the first power module substrate, and the conductive layer of the second power module substrate. If the first and second chips have electrodes on their back sides, these electrodes are connected to the conductive layer of the first power module substrate and / or the conductive layer of the second power module substrate through chip mounting material. This raises the connection position of the electrodes that may be located on the back of the first and second chips to be in the same plane as the electrodes on their front sides. In other words, the positions where the subsequent redistribution layer needs to connect with all the electrodes of the chip are in the same plane. Then, the planar positions and via depths of all electrode connections are positioned using the second positioning copper pillar. Therefore, when the upper surface of the second molding compound is ground until it is flush with the upper surface of the second positioning copper pillar, the distances between the upper surface of the second molding compound and the electrodes of all chips, as well as the conductive layers of the first and second power module substrates, are equal and equal to the preset via depth. Drilling and electroplating at the preset via depth achieves connectivity between the upper surface of the second molding compound and all chip electrodes, thus completing the lead-out of the chip electrodes. This significantly reduces the complexity of the via process during vertical interconnection and improves packaging process efficiency. Furthermore, the power devices packaged using the power device packaging method provided in this application possess advantages such as high-density integration, low parasitic parameters, excellent heat dissipation performance, and high reliability. Simultaneously, it effectively reduces the thickness of the package, making the packaged power devices thinner and lighter, which is beneficial for the miniaturization of power devices.

[0007] This application embodiment also provides a power device, including a molding compound, a first power module substrate, a second power module substrate, a first positioning copper pillar, a second positioning copper pillar, a first chip, and a second chip; the molding compound includes an upper surface plane and a lower surface plane, the upper surface plane of the molding compound being parallel to the lower surface plane; the first power module substrate, the second power module substrate, and the first positioning copper pillar are of equal height, and the molding compound encapsulates the first power module substrate, the second power module substrate, the first positioning copper pillar, and the second positioning copper pillar into a whole; the heat dissipation ends of the first power module substrate and the second power module substrate, and the lower surfaces of the first positioning copper pillar and the second positioning copper pillar are all flush with the lower surface plane of the molding compound; a first cavity and a second cavity are respectively provided on the conductive layers of the first power module substrate and the second power module substrate; the first chip is fixed in the first cavity by a chip mounting material, such that the electrode on the front side of the first chip is in the same plane as the conductive layer surface of the first power module substrate; the second chip is fixed in the first cavity by a chip mounting material. The material is fixed in the second cavity, so that the electrode on the front of the second chip and the conductive layer surface of the second power module substrate are in the same plane; the upper surface of the second positioning copper pillar is in the same plane as the upper surface of the molding compound, and the height of the second positioning copper pillar is equal to the sum of the height of the first positioning copper pillar and the via depth; a redistribution layer is provided on the upper surface of the molding compound, and a via is provided between the upper surface of the molding compound and the chip electrode, the first power module substrate, and the conductive layer of the second power module substrate. A vertical interconnect channel is provided in the via, and the redistribution layer connects the first chip electrode, the second chip electrode, the conductive layer of the first power module substrate, and the conductive layer of the second power module substrate through the vertical interconnect channel; thereby realizing the connection between the first chip and the second chip electrode, between the first chip and the first power module substrate conductive layer, between the second chip and the second power module substrate conductive layer, and between the first power module substrate conductive layer and the second power module substrate conductive layer according to the designed circuit; power device pins are formed on the redistribution layer.

[0008] The power device provided in this application has the following beneficial effects: 1. High-density integration and low parasitic parameters: By using an embedded cavity structure and redistribution layer technology, traditional bonding wires are replaced, significantly reducing parasitic inductance and resistance.

[0009] 2. Excellent heat dissipation performance: The back of the power module substrate is directly exposed as a heat dissipation path, and combined with silver chip mounting material technology, efficient top insulation heat dissipation is achieved.

[0010] 3. High precision and high reliability: Two molding and thinning processes ensure structural flatness, cavity positioning improves placement accuracy, and silver chip mounting material connection enhances thermomechanical reliability. Simultaneously, the package thickness is effectively reduced, resulting in thinner and lighter power devices, which is beneficial for power device miniaturization.

[0011] 4. Simplified process: By utilizing the coplanarity of the chip electrodes and the copper foil of the power module substrate, the need to create interconnecting vias is eliminated. The copper of the power module substrate itself is used to pull the back electrode of the chip to the same plane as the front electrode, enabling controllable depth of subsequent drilling processes and simplifying laser drilling and hole metallization processes. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the power device packaging process provided in Embodiment 1 of this application; Figures 2A to 2H for Figure 1 A schematic diagram of the specific component assembly structure for each step in the power device packaging process; Figure 3 The circuit diagram of the IGBT parallel diode power device provided in Example 1; Figures 4A to 4E This is a schematic diagram of the IGBT parallel diode power device provided in Example 1, from chip mounting to forming the device pin structure; Figures 5A to 5B This is a schematic diagram of the cross-sectional structure of the IGBT parallel diode power device in Example 1; Figure 6 The circuit diagram of a half-bridge packaged power device composed of two SiC MOS transistors is provided in Example 2; Figures 7A to 7E This is a schematic diagram of the process from chip mounting to forming the device pin structure for a half-bridge power device composed of two SiC MOS transistors provided in Example 1. Figures 8A to 8B This is a schematic diagram of the cross-sectional structure of a power device consisting of two SiC MOS transistors in a half-bridge package, as provided in Example 2. Figure 9 This is a circuit diagram of a SiC MOS half-bridge power device including a driver chip, provided in Embodiment 3 of this application; Figures 10A to 10EThis is a schematic diagram of the SiC MOS half-bridge power device including a driver chip from chip mounting to forming the device pin structure, provided in Example 3. Figures 11A to 11B This is a schematic diagram of the cross-sectional structure of the SiC MOS half-bridge power device containing the driver chip provided in Example 3.

[0014] In the picture: 10. Temporary carrier board; 11. First positioning copper pillar; 12. First power module substrate; 13. Second power module substrate; 14. First molding compound; 15. First cavity; 16. Second cavity; 17. Chip mounting material; 18. First chip; 19. Second chip; 20. Second positioning copper pillar; 21. Second molding compound; 22. Redistribution layer; 23. Vertical interconnect channel; 24. Insulating layer; 103. First copper foil area; 104. Second copper foil area; 105. Third copper foil area; 106. Power device collector pin C; 107. Power device gate pin G; 108. Power device emitter pin E; 201. SiC MOS Q4; 202. SiC MOS Q5; 205, Fourth copper foil area; 206, Fifth copper foil area; 207, Sixth copper foil area; 208, Seventh copper foil area; 209, Eighth copper foil area; 210, Ninth copper foil area; 211, Tenth copper foil area; 212, Device pin DC+; 213, Device pin SW; 214, Device pin DC-; 215, Device pin G2; 216, Device pin S2; 217, Device pin G1; 218, Device pin S1; 301, SiC MOS Q2; 302, Driver chip IC; 303, SiC MOS Q3; 307, Eleventh Copper Foil Area; 308, Twelfth Copper Foil Area; 309, Thirteenth Copper Foil Area; 310, Fourteenth Copper Foil Area; 311, Fifteenth Copper Foil Area; 312, Sixteenth Copper Foil Area; 313, Seventeenth Copper Foil Area; 314, Eighteenth Copper Foil Area; 315, Nineteenth Copper Foil Area; 316, Twentieth Copper Foil Area; 317, Twenty-first Copper Foil Area; 318, Device Pin DC+; 319, Device Pin SW; 320, Device Pin DC-; 321, Device Pin VB; 322, Device Pin VS; 323, Device Pin VCC; 324, Device Pin GND; 325, Device Pin HIN; 326, Device Pin LIN. Detailed Implementation

[0015] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0016] It is important to note that terms such as "first," "second," "symmetric," and "array" are used only to distinguish between descriptive and positional descriptions and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features specified with terms such as "first" or "symmetric" may explicitly or implicitly include one or more of that feature; similarly, when the quantity of certain features is not limited by words such as "two" or "three," it should be noted that such features also explicitly or implicitly include one or more features. In this invention, unless otherwise explicitly specified and limited, terms such as "installation," "connection," and "fixation" should be interpreted broadly; for example, they can refer to a fixed connection, a detachable connection, or an integral molding; they can refer to a mechanical connection, a direct connection, a welding connection, or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the accompanying drawings and specific circumstances.

[0017] Existing power devices, such as IGBT parallel diode packages, two SiC MOS half-bridge packages, and SiC MOS half-bridge power devices including driver chips, all integrate at least two chips. Each chip is mounted on its own power module substrate, requiring multiple encapsulation and wiring processes to achieve connections between chips within the power device, between the chips and the conductive layers of the power module substrate, and between chip electrodes and pads. However, because the distances between the conductive layers of the chips and the power module substrate, and between the electrodes of each chip, especially between the electrodes on the front and back sides of the same chip, vary within the encapsulation and on the top surface of the encapsulation, different drilling depths need to be determined and set when setting vias. This results in complex wiring interconnection processes and relatively low packaging efficiency.

[0018] Based on this, this application has made improvements to the actual power device packaging process. Through multiple precise control steps, it ensures that the electrodes of the chip encapsulated in the plastic package and the conductive layer of the power module substrate and the chip electrodes are all in the same plane. This allows all vias to be set up by drilling only one depth, which greatly reduces the complexity of the wiring interconnection process and improves packaging efficiency.

[0019] The power device packaging method provided in the embodiments of this application, such as Figure 1 As shown, it includes the following steps: S100. Establish framework benchmarks: such as Figure 2AAs shown, a temporary carrier plate 10 with parallel upper and lower planes is selected, and temporary bonding adhesive is applied to the upper surface of the temporary carrier plate; a first positioning copper pillar 11, a first power module substrate 12, and a second power module substrate 13 of equal height are selected; the lower bottom surface of the first positioning copper pillar 11 is fixed to the upper surface of the temporary carrier plate 10 using the temporary bonding adhesive; the heat dissipation end of the first power module substrate 12 and the heat dissipation end of the second power module substrate 13 are fixed to a predetermined area on the upper surface of the temporary carrier plate 10.

[0020] The temporary carrier 10 provided in this application is used to support various components of the power device during the packaging process, such as positioning copper pillars, power module substrates, molding compound, etc. The lower surface of the temporary carrier provides a planar reference. Simultaneously, the temporary substrate 10 needs to remain undeformed at a certain high temperature, so that the temporary carrier maintains structural stability under the influence of the temperature of the molding compound on its upper surface during the molding process. In this embodiment, a glass carrier is selected as the temporary carrier. A suitable glass carrier is selected (e.g., it can withstand a high temperature of not less than 200 degrees Celsius to meet the molding requirements, its thickness meets the strength requirements, and the flatness of its upper and lower surfaces meets the requirements). After cleaning and drying, the glass carrier is placed on the packaging platform. Then, temporary bonding adhesive is applied to the upper surface of the glass carrier to temporarily fix the components mounted on it. The temporary bonding adhesive provided in this application is used to temporarily fix components during the semiconductor device packaging process. The temporary bonding adhesive provided in this application can be selected from heat-release adhesives, photosensitive release adhesives, etc. In this embodiment, the temporary bonding adhesive is selected as a heat-release adhesive, preferably a high-temperature bonding heat-release adhesive, which can remain stable at temperatures exceeding 200 degrees Celsius, thus preventing component displacement due to the instability of the temporary bonding adhesive during the subsequent molding process.

[0021] After applying temporary bonding adhesive to the upper surface of the glass substrate, the first positioning copper pillar 11, the first power module substrate 12, and the second power module substrate 13, all selected at equal heights, are placed in predetermined positions according to the pre-designed packaging drawings. Specifically, the first positioning copper pillar 11 is first fixed to the upper surface of the glass substrate with its lower surface using temporary bonding adhesive, and then the first power module substrate 12 and the second power module substrate 13 are fixed to the upper surface of the glass substrate with their heat dissipation ends using temporary bonding adhesive, respectively, in their predetermined positions.

[0022] In this design, multiple power devices can be packaged in a single encapsulation. This involves simultaneously placing multiple groups of components, each consisting of a first positioning copper pillar 11, a first power module substrate 12, and a second power module substrate 13, onto a single glass substrate according to design requirements. However, when fixing the components onto the glass substrate, all the first positioning copper pillars 11 can be fixed at predetermined positions as a first positioning copper pillar group. Then, all the first power module substrates 12 can be fixed at predetermined positions next to their respective first positioning copper pillar groups as first power module substrate groups. Finally, all the second power module substrates 13 can be fixed at predetermined positions next to their respective first positioning copper pillar groups as second power module substrate groups. Preferably, the first and second power module substrates are DBC substrates (Direct Bonded Copper). A DBC substrate is a "sandwich" structure chip carrier board where copper foil is directly bonded to both sides of a ceramic substrate (such as alumina or aluminum nitride) through a high-temperature eutectic reaction. The ceramic substrate is an insulating and thermally conductive substrate, allowing one side of the copper foil to function as a heat sink and the other side as a conductive layer.

[0023] S200, Framework Construction: such as Figure 2B As shown, the first positioning copper pillar 11, the first power module substrate 12, and the second power module substrate 13 are wrapped and fixed with molding compound to form a first molding body 14. The molding compound on the upper surface area of ​​the first molding body is ground to expose the upper surface of the first positioning copper pillar. With the upper surface of the first positioning copper pillar as a reference, grinding is continued to expose the conductive layers of the first power module substrate and the second power module substrate, so that the upper surface of the first positioning copper pillar, the conductive layers of the first power module substrate and the second power module substrate are on the same plane.

[0024] When all the first positioning copper pillars 11, the first power module substrate 12, and the second power module substrate 13 are fixed in their preset positions on the glass carrier according to the design requirements, a low-stress epoxy molding compound is used to perform the first molding on all components located on the upper surface of the glass carrier. This wraps and fixes all the first positioning copper pillars 11, the first power module substrate 12, and the second power module substrate 13 in their set positions, forming the first molding body 14. The surface of the first molding body 14 furthest from the temporary carrier is defined as the upper surface of the first molding body. The upper surface of the first molding body 14 is ground until the upper surfaces of the first positioning copper pillars 11, the conductive layer surfaces of the first power module substrate 12, and the conductive layer surfaces of the second power module substrate 13 are exposed and on the same flat surface. During the grinding process, grinding begins layer by layer from the area where the first positioning copper pillars are placed. When the upper surface of the first positioning copper pillars is exposed, it indicates that the required position has been reached. The entire layer containing the upper surface of the first positioning copper pillars is ground into a flat plane, forming the flat upper surface of the first molding body. The first molding compound 14 can serve as a framework for subsequent chip mounting. In this embodiment, mechanical grinding or chemical mechanical polishing can be used to achieve a coplanar reference plane with nanometer-level flatness on the upper surface of the first positioning copper pillar group, the conductive layer surface of the first power module substrate group, and the conductive layer surface of the second power module substrate group. This step provides an important reference plane for subsequent chip mounting and drilling.

[0025] S300, forming a chip mounting cavity: such as Figure 2C As shown, a first cavity 15 and a second cavity 16 are formed from the conductive layer surface of the first power module substrate 12 and the second power module substrate 13 toward the ceramic layer, respectively; the depth of the first cavity 15 is equal to the sum of the thickness of the first chip and the thickness of the chip mounting material after curing, and the depth of the second cavity 16 is equal to the sum of the thickness of the second chip and the thickness of the chip mounting material after curing.

[0026] In this embodiment, a first cavity 15 and a second cavity 16 for accommodating the first chip and the second chip need to be fabricated on the conductive copper foil of the first power module substrate and the second power module substrate. In the power device provided in this embodiment, when it includes a first chip and a second chip, the first chip is generally a power chip and the second chip is a driver chip. When it includes a third chip, the first chip and the second chip are generally power chips, and the third chip is a driver chip. The core objective of step S300 is to ensure that the electrode surface of the mounted chip is completely flush with the top surface of the copper foil of the DBC board. Precise control of the cavity depth is a core prerequisite for achieving this objective. The chip dimensions of the first chip, second chip, and third chip required for the power device, including size and thickness, are accurate to the micrometer level. These dimensions can be obtained from data provided by the chip manufacturer or measured with micrometer-level precision using precision measuring instruments. Furthermore, the shrinkage rate and final cured thickness of the chip mounting material under a specified sintering process can be determined through process experiments. Therefore, in order to ensure that the chip electrodes are flush with the surface of the copper foil conductive layer of the DBC board after chip mounting, the depth of the first cavity needs to be equal to the sum of the thickness of the first chip and the cured thickness of the chip mounting material after sintering, and the depth of the second cavity needs to be equal to the sum of the thickness of the second chip and the cured thickness of the chip mounting material after sintering. In a further preferred embodiment provided in this application, a power device encapsulated with a third chip is also provided. In this case, a third cavity can be formed on the upper surface of the first positioning copper pillar towards the temporary carrier board, and the depth of the third cavity is equal to the thickness of the third chip and the cured thickness of the chip mounting material after sintering. In this case, the first positioning copper pillar can serve as a positioning reference during grinding. Simultaneously, since the third chip is a driver chip with its electrodes located on the front side and the back side used only for heat dissipation, the third positioning copper pillar can also serve as a mounting substrate for the third chip, providing heat dissipation without the need for a separate power module substrate. This saves raw materials, reduces installation steps, saves limited space in the power device, and facilitates miniaturization of the power device. In the embodiments of this application, the preferred chip mounting material is nano-silver sintering paste.

[0027] In this embodiment, cavities for mounting chips can be precisely controlled and formed on the exposed conductive copper foil of the DBC board through photolithography (including resist coating, exposure, and development) and etching processes. Similarly, when the power device design requires the use of two power chips and one driver chip, a third cavity for mounting the third chip can be simultaneously formed on the first positioning copper pillar in one step.

[0028] S400, chip mounting: such as Figure 2DAs shown, chip mounting material 17 is coated on the bottom of the first cavity 15 and the second cavity 16. A high-precision pick-and-place machine is used to fix the back of the first chip 18 in the first cavity 15 and the back of the second chip 19 in the second cavity 16. The chip mounting material 17 makes the first chip 18 bonded to the first power module substrate 12 and the second chip 19 bonded to the second power module substrate 13. At the same time, the electrode surfaces of the front of the first chip 18 and the second chip 19 are located in the same plane as the conductive layer surfaces of the first power module substrate 12 and the second power module substrate 13.

[0029] In this embodiment, a high-precision pick-and-place machine is used to mount the first chip 18 and the second chip 19 onto the chip mounting material 17 at the bottom of the first cavity 15 and the second cavity 16. When a third chip needs to be mounted, it is also mounted onto the chip mounting material at the bottom of the third cavity simultaneously. Current high-precision pick-and-place machines can control the mounting accuracy to ±0.5μm, ensuring that the chip is completely flat on the chip mounting material at the bottom of the cavity, without tilting or warping, avoiding height differences caused by mounting misalignment. Simultaneously, during the sintering and curing of the chip mounting material, programmed temperature rise sintering is performed under inert gas protection, precisely controlling the shrinkage rate of the chip mounting material, ensuring that the thickness of the cured chip mounting material is completely consistent with the design value, avoiding height deviations caused by abnormal shrinkage. This ensures that after the chip mounting material is fixed, the electrodes on the front of the first chip, the second chip, and the third chip are flush with the upper surfaces of the first power module substrate, the second power module substrate, and the first positioning copper pillar, and are in the same plane. Meanwhile, when the first chip and the second chip are used as power chips, the drain on the back of the chip can be connected to the conductive layer of the first power module substrate and the second power module substrate through chip mounting material. At this time, the electrical connection surfaces of the electrodes on the front and back of the first chip and the second chip are all in the same plane, which is equivalent to raising the electrodes on the back of the chip to the same plane as the electrodes on the front of the chip.

[0030] S500, Establishing a wiring reference: such as Figure 2E As shown, a second positioning copper pillar 20 is selected. The height of the second positioning copper pillar 20 is equal to the sum of the height of the first positioning copper pillar 11 and the preset via depth. Temporary bonding adhesive is applied to the upper surface of the temporary carrier board 10, and the bottom surface of the second positioning copper pillar 20 is fixed to the upper surface of the temporary carrier board 10 by the temporary bonding adhesive. The first molding compound, the first chip 18, the second chip 19 and the second positioning copper pillar 20 on one side of the upper surface of the temporary carrier board are molded with molding compound to form a second molding compound 21. The upper surface of the second molding compound 21 on the side away from the temporary carrier board is ground until the upper surface of the second positioning copper pillar 20 is exposed. The upper surface of the second molding compound 21 is ground until it is on the same plane as the upper surface of the second positioning copper pillar 20.

[0031] In this embodiment, the via is a drilled hole formed on the molded package to connect the wiring layer on the outer surface of the molded package to the chip electrodes inside the molded package. The depth of the via is designed during the design of the power device, and its placement and depth are set on the drilling equipment, which will drill to the preset via depth. The second positioning copper pillar 20 provided in this application is used to position the reference surface for drilling by the drilling equipment, and also to position the specific positions of each chip electrode within the reference surface plane. Therefore, the height of the second positioning copper pillar 20 provided in this application is the sum of the height of the first positioning copper pillar 11 and the via depth. During the first molding process in step S200, a position can be reserved where the second positioning copper pillar needs to be placed, according to the design. The same temporary bonding adhesive as in step S100 is applied to the reserved position on the temporary carrier board. Then, the lower surface of the second positioning copper pillar 20 is fixed to the temporary carrier board 10 with temporary bonding adhesive. Temporary films are applied to the structure after chip mounting, such as the upper surface of the first positioning copper pillar, the conductive layer of the first power module substrate and the second power module substrate, the first chip, and the front side of the second chip, to protect these structures. Then, the first molding body located on one side of the upper surface of the temporary carrier board 10, each chip installed in the cavity, and the second positioning copper pillar 20 installed on the temporary carrier board 10 are integrally molded with molding material to form the second molding body 21. After the second molding compound 21 has cured, its upper surface (the side furthest from the temporary carrier 10) is thinned using mechanical grinding or chemical mechanical polishing until the upper surface of the second positioning copper pillar 20 is exposed. Then, using the upper surface of the second positioning copper pillar 20 as a reference, the upper surface of the second molding compound is ground to a flat surface that is flush with the upper surface of the second positioning copper pillar, serving as the upper surface of the second molding compound. The thinned and flattened upper surface of the second molding compound will serve as the redistribution layer layout surface for the entire power device, and also as the reference surface for vias.

[0032] S600, Vertical Interconnection and Internal Routing: such as Figure 2F , Figure 2GAs shown, the electrode positions of the first chip 18 and the second chip 19, as well as the conductive layer positions of the first power module substrate 12 and the second power module substrate 13, are determined according to the second positioning copper pillar 20. The via positions are determined based on the electrode positions and conductive layer positions. A via is drilled at the via position according to a preset via depth to form a via connecting the upper surface of the second molding compound and the electrodes of the first chip, the second chip, the conductive layers of the first power module substrate, and the conductive layers of the second power module substrate. A seed layer is formed on the upper surface of the second molding compound and on the via. According to the designed circuit, a patterning process and an electroplating filling process are used to fill the via. A redistribution layer 22 is formed on the upper surface of the second molding compound, and a vertical interconnect channel 23 is formed in the via. The redistribution layer 22 connects the first chip electrode, the second chip electrode, the first power module substrate conductive layer, and the second power module substrate conductive layer through the vertical interconnect channel 23. This enables the connection between the first chip and the second chip electrode, between the first chip and the first power module substrate conductive layer, between the second chip and the second power module substrate conductive layer, and between the first power module substrate conductive layer and the second power module substrate conductive layer according to the designed circuit. Power device pins are formed on the redistribution layer 22.

[0033] The upper surface of the second positioning copper pillar 20 is exposed on the upper surface of the second molding compound, forming a precise metal alignment mark. Besides serving as a positioning endpoint during the thinning of the upper surface of the second molding compound 21, it also serves to determine the positions of the electrodes of the first chip 18 in the first cavity 15 on the first power module substrate 12 and the electrodes of the second chip 19 in the second cavity 16 on the second power module substrate 13, based on the position of the second positioning copper pillar 20 and its positional relationship with the first power module substrate 12 and the second power module substrate 13 in the design drawing. This allows for the determination of the locations where vias need to be set, and drilling is performed using a drilling device at a preset via depth. The second positioning copper pillar, as a metal alignment mark, also serves as a marker for the subsequent formation of the seed layer and redistribution layer on the upper surface of the second molding compound. When a third chip needs to be set on the first positioning copper pillar 11, the position of the third chip's electrodes is also determined. In this embodiment, a UV laser drilling device is used. Since the electrodes of all chips, such as the source, gate, and drain of power chips, the anode and cathode of diodes, and the emitter, collector, and gate of IGBT chips, are all located in the same plane as the conductive layer surface of the first power module substrate, the second power module substrate, and the upper surface of the first positioning copper pillar, the drilling equipment only needs to drill holes at all the required drilling locations according to a single via depth to complete all via drilling.

[0034] After all vias are set up, a seed layer is formed on the upper surface of the second molding compound 21 and in the vias by sputtering or chemical plating. A redistribution layer 22 is then formed on the upper surface of the second molding compound using electroplating and patterning processes (including dry film lamination, exposure, development, and etching). Vertical interconnect channels 23 are formed in the vias, connecting the redistribution layer 22 to the electrodes of the first chip 18 and the second chip 19 within the molding compound, as well as the conductive layers of the first power module substrate 12 and the second power module substrate 13. Connections between the electrodes of the first chip 18 and the second chip 19, between the first chip 18 and the conductive layer of the first power module substrate 12, between the second chip 19 and the conductive layer of the second power module substrate 13, and between the conductive layers of the first power module substrate 12 and the second power module substrate 13 can all be achieved by connecting to the redistribution layer 22 through the vertical interconnect channels 23 in the vias. Simultaneously, vias and interconnect redistribution layers can be repeated according to the packaging topology requirements. Power device pins, such as power device drains, power device sources, and power device gates, are formed on the redistribution layer.

[0035] In this embodiment, the redistribution layer may include a first redistribution layer 221 and a second redistribution layer 222. The first redistribution layer 221 is disposed on the upper surface of the second molding compound 21 and interconnects with the chip electrodes and the conductive layer of the power module substrate within the molding compound through vertical interconnect channels 23 in the vias. This allows interconnection between chip electrodes and between chip electrodes and the conductive layer of the power module substrate via the first redistribution layer 221, achieving the core interconnection between the power circuit and signal circuit within the module. An insulating layer 24 is then disposed on the first redistribution layer 221, and a second redistribution layer 222 is disposed on the insulating layer 24. The second redistribution layer 222 is connected to the first redistribution layer 221 through vias and is mainly used for the outlining and patterning of external device pins, fanning out internal interconnect nodes to a standard package pin layout. Compared to traditional bonding wire connections between chip electrodes and between chip electrodes and the conductive layer of the power module substrate, the redistribution layer uses planar copper foil wiring, which significantly reduces parasitic inductance and resistance, making it suitable for applications of high-frequency power devices such as SiC. At the same time, it has higher wiring density, stronger integration, better mechanical reliability and thermal stability, and avoids problems such as bonding wire detachment and fatigue failure.

[0036] S700, Subsequent Processes: such as Figure 2H As shown, the temporary carrier 10 is removed by eliminating the adhesive force of the temporary bonding adhesive, and after the completion process, a power device is obtained.

[0037] When a photosensitive release adhesive is used as the temporary bonding agent, the temporary carrier can be exposed to light, causing the photosensitive release adhesive to lose its stickiness and allowing the temporary carrier to detach from the packaged power device. When a thermal release adhesive is used, the temporary carrier can be heated until the temperature exceeds the release temperature of the thermal release adhesive, at which point the temporary carrier detaches from the molding compound, exposing the lower surface of the second molding compound, the heat dissipation terminals of the first and second power module substrates, and the lower surfaces of the first and second positioning copper pillars. Post-processing can then be performed on the packaged power device, including bottom pin patterning and solder masking: at the bottom of the module, the underlying circuit traces are formed using a patterning process, defining the external pin pads of the module. Solder mask ink is applied to the underlying circuit, and the pad areas are exposed through exposure and development.

[0038] Further post-processing includes surface treatment (such as electroless nickel-palladium-gold plating) on ​​the exposed pads. Electrical performance testing is then performed on the packaged panel, and finally, it is cut into individual power modules.

[0039] Meanwhile, for automotive-grade high-reliability power devices, after completing all redistribution layer wiring and pin fabrication, a third molding process is also included. The surface of the power device, except for the power device pins, is wrapped with molding material to protect the entire surface of the power device and prevent oxidation of the redistribution layer and mechanical damage.

[0040] Example 1 like Figure 3 The diagram shown is a circuit diagram of an IGBT parallel diode power device. This embodiment will explain the specific packaging process of the IGBT parallel diode power device in conjunction with the above-mentioned power device packaging method.

[0041] The IGBT parallel diode power device provided in this application includes two chips: a first chip is an IGBT chip, and a second chip is a diode chip. Steps S100 to S400 in the aforementioned power device packaging method are basic steps. During the packaging process of the IGBT parallel diode power device provided in this application, after steps S100 to S400, the resulting structure is shown in Figure 4A. In this figure, the black blocks represent the power module substrate, and the gray blocks represent the chips. The first power module substrate 12 and the second power module substrate 13 are DBC boards. A is the positive electrode A of the diode chip, and the negative electrode K of the diode chip is connected to the conductive layer of the second power module substrate 13 through a chip mounting material. E is the emitter E of the IGBT chip, G is the gate G of the IGBT chip, and the collector C of the IGBT chip is connected to the conductive layer of the first power module substrate 12 through a chip mounting material. Figures 4B to 4E This is a schematic diagram showing the upper surface of the packaged device during steps S500 to S600. Figure 4BA schematic diagram of a first redistribution layer disposed on the upper surface of a second molding compound is provided. The first redistribution layer includes a first copper foil region 103, a second copper foil region 104, and a third copper foil region 105. The first copper foil region 103 corresponds to the emitter E of the IGBT chip and the positive electrode A of the diode. The second copper foil region 104 corresponds to the conductive layer of the first power module substrate 12 and the second power module substrate 13. The third copper foil region 105 corresponds to the gate G of the IGBT chip. Figure 4C This diagram illustrates the connection between the first redistribution layer and the copper foil on the top of the DBC board, as well as the electrodes of the IGBT and diode chips, achieved through vias. A cross-sectional view of the resulting power device is shown below. Figure 5A As shown; Figure 4D A schematic diagram of a second redistribution layer structure is provided on the first redistribution layer and an insulating layer is provided on the insulating layer. The second redistribution layer forms the pins of the device, namely the power device gate pin G107, the power device emitter pin E108, and the power device collector pin C106. Figure 4E This is a schematic diagram showing the connection between the second redistribution layer and the first redistribution layer via vias, forming a schematic diagram of the cross-sectional structure of the power device. Figure 5B As shown.

[0042] The IGBT parallel diode power device packaged in the above manner can achieve the following specific connection: 1. The IGBT chip is soldered to the etched power module substrate 12 using chip mounting material, thereby connecting the IGBT C electrode to the top copper foil of the power module substrate 12.

[0043] 2. The diode chip is soldered to the etched second power module substrate 13 using chip mounting material, thereby connecting the diode K electrode to the top copper foil of the second power module substrate 13.

[0044] 3. The first copper foil region 103 of the first redistribution layer is connected to the diode chip A electrode and the IGBT chip E electrode through vias.

[0045] 4. The second copper foil region 104 of the first redistribution layer is connected to the top copper foil of the first power module substrate 12 and the top copper foil of the second power module substrate 13 through vias, thereby realizing the connection between the C electrode of the IGBT chip and the K electrode of the diode chip.

[0046] 5. The third copper foil region 105 of the first redistribution layer is connected to the G electrode of the IGBT chip through a via.

[0047] 6. The collector pin C 106 of the power device is connected to the second copper foil area 104 of the first redistribution layer through a via, thereby enabling the collector pin C 106 of the power device to be connected to the C electrode of the internal IGBT chip and the K electrode of the diode chip.

[0048] 7. The power device gate pin G 107 is connected to the third copper foil area 105 of the first redistribution layer through a via, thereby enabling the power device gate pin G 107 to be connected to the G electrode of the internal IGBT chip.

[0049] 8. The emitter pin E 108 of the power device is connected to the first copper foil area 103 of the first redistribution layer through a via, thereby enabling the emitter pin E 108 of the power device to be connected to the E electrode of the internal IGBT chip and the A electrode of the diode chip.

[0050] Example 2 like Figure 6 The diagram shown is a circuit diagram of a power device consisting of two SiC MOS components forming a half-bridge encapsulation. This embodiment will explain the specific packaging process of the power device consisting of two SiC MOS components forming a half-bridge encapsulation, in conjunction with the power device packaging method described above.

[0051] The two SiC MOS chips in this embodiment form a half-bridge encapsulated power device, including a first chip SiC MOS Q4 and a second chip SiC MOS Q5. During the packaging process of the two SiC MOS chips forming a half-bridge encapsulated power device provided in this application, after steps S100 to S400, the resulting structure diagram is shown in Figure 7A. In this diagram, the black blocks represent the power module substrate, and the gray blocks represent the chips. The first power module substrate 12 and the second power module substrate 13 are DBC boards. The first chip SiC MOS Q4 201 has S as its source, G as its gate, and D connected to the conductive layer of the first power module substrate 12 through chip mounting material. The second chip SiC MOS Q5 202 has S as its source, G as its gate, and D connected to the conductive layer of the second power module substrate 13 through chip mounting material. Figures 7B to 7E This is a schematic diagram showing the upper surface of the packaged device during steps S500 to S600. Figure 7B A schematic diagram illustrating the application of a first redistribution layer on the upper surface of the second molding compound; Figure 7C The diagram shows the connection between the first redistribution layer and the copper foil on the top of the DBC board, as well as the electrodes of the first chip SiC MOS Q4 and the second chip SiC MOS Q5, achieved through vias. A schematic diagram of the cross-sectional structure of the resulting power device is shown below. Figure 8A As shown; Figure 7D A schematic diagram of a structure for setting an insulating layer on a first redistribution layer and setting a second redistribution layer on the insulating layer, wherein the second redistribution layer forms the device pins; Figure 7E This is a schematic diagram showing the connection between the second redistribution layer and the first redistribution layer via vias, forming a schematic diagram of the cross-sectional structure of the power device. Figure 8B As shown.

[0052] Two SiC MOS transistors packaged in the above manner can be combined to form a half-bridge encapsulated power device, which can achieve the following specific connection: 1. The first chip SiC MOS Q4 201 is soldered to the etched first power module substrate 12 using chip mounting material, thereby connecting the D electrode of the first chip SiC MOS Q4 201 to the top copper foil of the first power module substrate 12.

[0053] 2. The second chip, SiC MOS Q5 202, is soldered to the etched second power module substrate 13 using chip mounting material, thereby connecting the D electrode of the second chip, SiC MOS Q5 202, to the top copper foil of the second power module substrate 13.

[0054] 3. The fourth copper foil region 205 of the first redistribution layer is connected to the top copper foil of the first power module substrate through a via, thereby realizing the connection between the fourth copper foil region 205 of the first redistribution layer and the D electrode of the first chip SiC MOS Q4 201.

[0055] 4. The fifth copper foil region 206 of the first redistribution layer is connected to the S electrode of the front electrode of the first chip SiC MOS Q4 201 and the top copper foil of the second power module substrate 13 through a via, thereby realizing the connection between the S electrode of the front electrode of the first chip SiC MOS Q4 201 and the D electrode of the second chip SiC MOS Q5 202.

[0056] 5 The sixth copper foil region 207 of the first redistribution layer is connected to the S electrode of the second chip SiC MOS Q5 202 through a via.

[0057] 6. The seventh copper foil region 208 of the first redistribution layer is connected to the G electrode of the first chip SiC MOS Q4 201 through a via.

[0058] 7. The eighth copper foil region 209 of the first redistribution layer is connected to the S electrode of the first chip SiC MOS Q4 201 (the Kelvin source pin of the first chip SiC MOS Q4 201) through a via. By introducing this independent pin, it is specifically used as the return path for the gate drive. This pin does not carry a large current and can physically isolate the high-noise power main circuit from the sensitive drive circuit, thereby providing a clean and stable reference ground for the gate.

[0059] 8. The ninth copper foil region 210 of the first redistribution layer is connected to the G electrode of the second chip SiC MOS Q5 202 through a via.

[0060] 9. The tenth copper foil region 211 of the first redistribution layer is connected to the S electrode of the second chip SiC MOS Q5 202 through a via (the Kelvin source pin of the second chip SiC MOS Q5 202. By introducing this independent pin, it is specifically used as the return path for the gate drive; this pin does not carry a large current, which can physically isolate the high-noise power main circuit from the sensitive drive circuit, thereby providing a clean and stable reference ground for the gate).

[0061] 10. Device pin DC+ 212 is connected to the fourth copper foil area 205 of the first redistribution layer through a via, thereby realizing the connection between device pin DC+ 212 and the D electrode of the first chip SiC MOS Q4 201.

[0062] 11. Device pin SW 213 is connected to the fifth copper foil area 206 of the first redistribution layer through a via, thereby enabling device pin SW 213 to be connected to the S electrode of the first internal chip SiC MOS Q4 201 and the D electrode of the second internal chip SiC MOS Q5 202.

[0063] 12. Device pin DC-214 is connected to the sixth copper foil area 207 of the first redistribution layer through a via, thereby enabling device pin DC-214 to be connected to the S electrode of the second chip SiC MOS Q5 202.

[0064] 13. Device pin G2 215 is connected to the seventh copper foil area 208 of the first redistribution layer through a via, thereby enabling device pin G2 215 to be connected to the G electrode of the internal first chip SiC MOS Q4 201.

[0065] 14. Device pin S2 216 is connected to the eighth copper foil area 209 of the first redistribution layer through a via, thereby realizing the connection between device pin S2 216 and the S electrode of the internal first chip SiC MOS Q4 201.

[0066] 15. Device pin G1 217 is connected to the ninth copper foil area 210 of the first redistribution layer through a via, thereby enabling device pin G1 217 to be connected to the G electrode of the internal second chip SiC MOS Q5 202.

[0067] 16. Device pin S1 218 is connected to the tenth copper foil area 211 of the first redistribution layer through a via, thereby enabling device pin S1 218 to be connected to the S electrode of the internal second chip SiC MOS Q5 202.

[0068] Example 3 like Figure 9The diagram shown is a circuit diagram of a SiC MOS half-bridge power device containing a driver chip. This embodiment will describe the specific packaging process of the SiC MOS half-bridge power device containing a driver chip in conjunction with the above-mentioned power device packaging method.

[0069] The SiC MOS half-bridge power device including a driver chip provided in this application embodiment includes a first chip SiCMOS Q2, a second chip SiC MOS Q3, and a driver chip IC. During the packaging process of the SiC MOS half-bridge power device including a driver chip provided in this application, after steps S100 to S400, the resulting structure is shown in Figure 10A. The black blocks represent the power module substrate and the first positioning copper pillar, while the gray blocks represent the chips. The first power module substrate 12 and the second power module substrate 13 are DBC boards. The first chip SiC MOS Q2 301 has S as its source, G as its gate, and its drain D connected to the conductive layer of the first power module substrate 12 via chip mounting material. The driver chip IC 302 is also present. The second chip SiC MOS Q3 303 has S as its source, G as its gate, and its drain D connected to the conductive layer of the second power module substrate 13 via chip mounting material. Figures 10B to 10E This is a schematic diagram showing the upper surface of the packaged device during steps S500 to S600. Figure 10B A schematic diagram illustrating the application of a first redistribution layer on the upper surface of the second molding compound; Figure 10C The diagram shows the first redistribution layer connected to the top copper foil of the DBC board, the first chip SiC MOS Q2, the driver chip IC, and the electrodes of the second chip SiC MOS Q3 via vias. A cross-sectional view of the resulting power device is shown below. Figure 11A As shown; Figure 10D A schematic diagram of a structure for setting an insulating layer on a first redistribution layer and setting a second redistribution layer on the insulating layer, wherein the second redistribution layer forms the pins of the device; Figure 10E This is a schematic diagram showing the connection between the second redistribution layer and the first redistribution layer via vias, forming a schematic diagram of the cross-sectional structure of the power device. Figure 11B As shown.

[0070] The SiC MOS half-bridge power device containing the driver chip, packaged in the manner described above, can achieve the following specific connections: 1. The first chip SiC MOS Q2 301 is soldered to the etched first power module substrate 12 using chip mounting material, thereby connecting the D electrode of the first chip SiC MOS Q2 301 to the top copper foil of the first power module substrate 12.

[0071] 2. The second chip, SiC MOS Q3 303, is soldered to the etched second power module substrate 13 using nano-silver chip mounting material, thereby connecting the D electrode of the second chip, SiC MOS Q3 303, to the top copper foil of the second power module substrate 13.

[0072] 3. The driver chip IC 302 is soldered to the etched first positioning copper pillar 11 using nano-silver chip mounting material. The substrate of the driver IC chip 302 is insulated, and mounting it on the first positioning copper pillar 11 provides a heat dissipation channel for the driver chip IC 302.

[0073] 4. The eleventh copper foil region 307 of the first redistribution layer is connected to the top copper foil of the first power module substrate 12 through a via, thereby realizing the connection between the eleventh copper foil region 307 of the first redistribution layer and the D electrode of the first chip SiC MOS Q2 301.

[0074] 5. The twelfth copper foil region 308 of the first redistribution layer is connected to the front S electrode of the first chip SiC MOS Q2 301 and the top copper foil of the second power module substrate 13 through a via, thereby realizing the connection between the front S electrode of the first chip SiC MOS Q2 301 and the D electrode of the second chip SiC MOS Q3 303.

[0075] 6. The thirteenth copper foil region 309 of the first redistribution layer is connected to the S electrode of the second chip SiC MOS Q3 303 through a via.

[0076] 7. The fourteenth copper foil region 310 of the first redistribution layer is connected to the VB electrode of the driver chip IC 302 through vias; the fifteenth copper foil region 311 of the first redistribution layer is connected to the VS electrode of the driver chip IC 302 and the front S electrode of the first chip SiC MOS Q2301 through vias; the sixteenth copper foil region 312 of the first redistribution layer is connected to the HO electrode of the driver chip IC 302 and the front G electrode of the first chip SiC MOS Q2301 through vias; the seventeenth copper foil region 313 of the first redistribution layer is connected to the VCC electrode of the driver chip IC 302 through vias; the eighteenth copper foil region 314 of the first redistribution layer is connected to the HIN electrode of the driver chip IC 302 through vias; the nineteenth copper foil region 315 of the first redistribution layer is connected to the LIN electrode of the driver chip IC 302 through vias; the twentieth copper foil region 316 of the first redistribution layer is connected to the GND electrode of the driver chip IC 302 and the second chip SiC MOS Q3 through vias. 303 is the front electrode S electrode; the 21st copper foil region 317 of the first redistribution layer is connected to the LO electrode of the driver chip IC 302 and the G electrode of the front electrode of the second chip SiC MOS Q3 303 through vias.

[0077] 8. Device pin DC+ 318 is connected to the eleventh copper foil area 307 of the first redistribution layer through a via, thereby enabling device pin DC+ 318 to be connected to the D electrode of the internal first chip SiC MOS Q2 301.

[0078] 9. Device pin SW 319 is connected to the twelfth copper foil area 308 of the first redistribution layer through a via, thereby enabling device pin SW 319 to be connected to the S electrode of the first internal chip SiC MOS Q2 301 and the D electrode of the second chip SiC MOS Q3 303.

[0079] 10. Device pin DC-320 is connected to the thirteenth copper foil region 309 of the first redistribution layer through a via, thereby enabling device pin DC-320 to be connected to the S electrode of the internal second chip SiC MOS Q3 303.

[0080] 11. Device pin VB 321 is connected to the fourteenth copper foil area 310 of the first redistribution layer through a via, thereby enabling device pin VB 321 to be connected to the VB electrode of the internal driver chip IC 302.

[0081] 12. Device pin VS 322 is connected to the fifteenth copper foil area 311 of the first redistribution layer through a via, thereby enabling device pin VS 322 to be connected to the VS electrode of the internal driver chip IC 302 and the front S electrode of the first chip SiC MOS Q2 301.

[0082] 13. Device pin VCC 323 is connected to the seventeenth copper foil area 313 of the first redistribution layer through a via, thereby enabling device pin VCC 323 to be connected to the VCC electrode of the internal driver chip IC 302.

[0083] 14. Device pin GND 324 is connected to the twentieth copper foil area 316 of the first redistribution layer through a via, thereby enabling device pin GND 324 to be connected to the GND electrode of the driver chip IC 302 and the front S electrode of the second chip SiC MOS Q3 303.

[0084] 15. Device pin HIN 325 is connected to the eighteenth copper foil area 314 of the first redistribution layer through a via, thereby enabling device pin HIN 325 to be connected to the HIN electrode of the internal driver chip IC 302.

[0085] 16. Device pin LIN 326 is connected to the nineteenth copper foil area 315 of the first redistribution layer through a via, thereby enabling device pin LIN 326 to be connected to the LIN electrode of the internal driver chip IC 302.

[0086] Based on the power device packaging method provided in the above embodiments, this application also provides a power device packaged using the above method.

[0087] Combination Figures 2F to 2H As shown in the embodiments of this application, the power device includes a molding compound, a first power module substrate 12, a second power module substrate 13, a first positioning copper pillar 11, a second positioning copper pillar 20, a first chip 15, and a second chip 16. The molding compound includes an upper surface plane and a lower surface plane, and the upper surface plane of the molding compound is parallel to the lower surface plane. The first power module substrate 12, the second power module substrate 13, and the first positioning copper pillar 11 are of equal height. The molding compound holds the first power module substrate 12, the second power module substrate 13, the first positioning copper pillar 11, and the second positioning copper pillar 16 together. The two positioning copper pillars 20 are packaged into a single unit; the heat dissipation ends of the first power module substrate 12 and the second power module substrate 13, the lower surfaces of the first positioning copper pillar 11 and the second positioning copper pillar 20 are all flush with the lower surface plane of the molding compound; a first cavity and a second cavity are respectively provided on the conductive layers of the first power module substrate 12 and the second power module substrate 13; the first chip 15 is fixed in the first cavity by chip mounting material, such that the electrodes on the front of the first chip 15 are located in the same plane as the conductive layer surface of the first power module substrate 13; The second chip 16 is fixed in the second cavity by chip mounting material, such that the electrode on the front of the second chip 16 is in the same plane as the conductive layer surface of the second power module substrate 13; the upper surface of the second positioning copper pillar 20 is in the same plane as the upper surface of the molding compound, and the height of the second positioning copper pillar 20 is equal to the sum of the height of the first positioning copper pillar 11 and the via depth; a redistribution layer 22 is provided on the upper surface of the molding compound, and vias are provided between the upper surface of the molding compound and the chip electrode, the first power module substrate, and the conductive layer of the second power module substrate, and vertical interconnect channels 23 are provided in the vias, and the redistribution layer 22 connects the first chip electrode, the second chip electrode, the first power module substrate conductive layer, and the second power module substrate conductive layer through the vertical interconnect channels 23; thereby realizing the connection between the first chip and the second chip electrode, between the first chip and the first power module substrate conductive layer, between the second chip and the second power module substrate conductive layer, and between the first power module substrate conductive layer and the second power module substrate conductive layer according to the designed circuit; power device pins are formed on the redistribution layer.

[0088] like Figure 2HAs shown, the redistribution layer 22 includes a first redistribution layer 221 and a second redistribution layer 222. The first redistribution layer 221 is disposed on the upper surface of the molding compound. The first redistribution layer 221 is connected to the first chip, the second chip electrode, and the conductive layers of the first power module substrate and the second power module substrate through a vertical interconnect channel 23. An insulating layer 24 is disposed on the upper surface of the first redistribution layer 221, and the second redistribution layer 222 is disposed on the insulating layer 24. Power device pins are disposed on the second redistribution layer 222. The power device pins are connected to the first redistribution layer through vias, thereby realizing the connection with the first chip electrode and the second chip electrode.

[0089] In a preferred embodiment provided in this application, such as Figure 11A , Figure 11B As shown, it also includes a third chip, forming a third cavity on the upper surface of the first positioning copper pillar towards the temporary carrier board. The third chip is fixed in the third cavity by chip mounting material, and the electrodes on the front of the third chip are in the same plane as the upper surface of the first positioning copper pillar.

[0090] A preferred embodiment of the power device provided in this application is an IGBT parallel diode power device, such as... Figure 3 , Figures 4A to 4E ,as well as Figures 5A to 5B As shown, the first chip is an IGBT chip, and the second chip is a diode chip. The IGBT chip is soldered to the first cavity using chip mounting material, which connects the collector C of the IGBT chip to the top copper foil of the first power module substrate. The diode chip is soldered to the second cavity using chip mounting material, which connects the negative terminal K of the diode to the top copper foil of the second power module substrate. The first redistribution layer includes a first copper foil region 103, a second copper foil region 104, and a third copper foil region 105. The first copper foil region 103 is connected to the positive electrode A of the diode chip and the emitter E of the IGBT chip through a vertical interconnect channel. The second copper foil region 104 is connected to the top copper foil of the first power module substrate 12 and the second power module 13 through a vertical interconnect channel, thereby connecting the collector C of the IGBT chip and the negative electrode K of the diode chip. The third copper foil region 105 is connected to the gate G of the IGBT chip through a vertical interconnect channel. The second redistribution layer includes a power device collector pin C 106, a power device gate pin G 107, and a power device emitter pin E 108. The power device collector pin C 106 is connected to the second copper foil area 104 of the first redistribution layer through a via, thereby connecting the power device collector pin C 106 to the collector C of the internal IGBT chip and the negative terminal K of the diode chip. The power device gate pin G 107 is connected to the third copper foil area 105 of the first redistribution layer through a via, thereby connecting the power device gate pin G 107 to the gate G of the internal IGBT chip. The power device emitter pin E 108 is connected to the first copper foil area 103 of the first redistribution layer through a via, thereby connecting the power device emitter E of the internal IGBT chip and the positive terminal A of the diode chip.

[0091] In a preferred embodiment of the power device provided in this application, the power device is a half-bridge encapsulated power device composed of two SiC MOS transistors, such as... Figure 6 , Figures 7A to 7E ,as well as Figures 8A to 8B As shown, the first chip is a SiCMOS Q4 201, and the second chip is a SiC MOS Q5 202; The SiC MOS Q4 201 chip is soldered onto the first cavity using chip mounting material, thus connecting the drain D of the SiC MOS Q4 201 chip to the top copper foil of the first power module substrate 12; the SiC MOS Q5 202 chip is soldered onto the second cavity using chip mounting material, thus connecting the drain D of the SiC MOS Q5 202 chip to the top copper foil of the second power module substrate 13. The first redistribution layer includes a fourth copper foil region 205, a fifth copper foil region 206, a sixth copper foil region 207, a seventh copper foil region 208, an eighth copper foil region 209, a ninth copper foil region 210, and a tenth copper foil region 211. The fourth copper foil region 205 is connected to the top copper foil of the first power module substrate 12 via a vertical interconnect channel, thereby connecting the fourth copper foil region 205 to the drain D of the SiC MOS Q4 201 chip. The fifth copper foil region 206 is connected to the front source S of the SiC MOS Q4 201 chip and the top copper foil of the second power module substrate 13 via a vertical interconnect channel, thereby connecting the front source S of the SiC MOS Q4 201 chip and the drain D of the SiC MOS Q5 202. The sixth copper foil region 207 is connected to the source S of the SiC MOS Q5 202 via a vertical interconnect channel. The seventh copper foil region 208 is connected to the SiC MOS Q4 202 via a vertical interconnect channel. The gate G of the 201 chip; the eighth copper foil region 209 is connected to the source S of the SiC MOS Q4 201 through a vertical interconnect channel; the ninth copper foil region 210 is connected to the gate G of the SiC MOS Q5 202 chip through a vertical interconnect channel; the tenth copper foil region 211 is connected to the source S of the SiC MOS Q5 202 through a vertical interconnect channel; The second redistribution layer includes device pins DC+212, SW213, DC-214, G1217, S1218, G22215, and S2216. Device pin DC+212 is connected to the fourth copper foil region 205 via a via, thus connecting device pin DC+212 to the drain D of the SiC MOS Q4201. Device pin SW213 is connected to the fifth copper foil region 206 via a via, thus connecting device pin SW213 to the source S of the internal SiC MOS Q4201 chip and the drain D of the SiC MOS Q5202 chip. Device pin DC-214 is connected to the sixth copper foil region 207 via a via, thus connecting device pin DC-214 to the source S of the SiC MOS Q5202. Device pin G1217, S1218, G2215, and S2216 are also connected. Device pin G2 215 is connected to the seventh copper foil region 208 through a via, thereby connecting device pin G2 215 to the gate G of the internal SiC MOS Q4 201 chip; device pin S2 216 is connected to the eighth copper foil region 209 through a via, thereby connecting device pin S2 216 to the source S of the internal SiC MOS Q4 201 chip; device pin G1 217 is connected to the ninth copper foil region 210 through a via, thereby connecting device pin G1 217 to the gate G of the internal SiC MOS Q5 202 chip; device pin S1 218 is connected to the tenth copper foil region 211 through a via, thereby connecting device pin S1 218 to the source S of the internal SiC MOS Q5 202 chip.

[0092] In the third preferred embodiment provided in this application, the power device is a SiC MOS half-bridge power device including a driver chip, such as... Figure 9 , Figures 10A to 10E ,as well as Figures 11A to 11B The first chip shown is a SiC MOS Q2301, the second chip is a SiC MOS Q3 303, and the third chip is a driver chip IC 302. The SiC MOS Q2 301 chip is soldered to the first cavity using chip mounting material, connecting the drain D of the SiC MOS Q2 301 chip to the top copper foil of the first power module substrate 12; the SiC MOS Q3 303 chip is soldered to the second cavity using chip mounting material, connecting the drain D of the SiC MOS Q3 303 chip to the top copper foil of the second power module substrate 13; the driver chip IC 302 is soldered to the third cavity on the first positioning copper pillar 11 using chip mounting material. The first redistribution layer includes an eleventh copper foil region 307, a twelfth copper foil region 308, a thirteenth copper foil region 309, a fourteenth copper foil region 310, a fifteenth copper foil region 311, a sixteenth copper foil region 312, a seventeenth copper foil region 313, an eighteenth copper foil region 314, a nineteenth copper foil region 315, a twentieth copper foil region 316, and a twenty-first copper foil region 317. The eleventh copper foil region 307 is connected to the top copper foil of the first power module substrate 12 via a vertical interconnect channel, thereby connecting the eleventh copper foil region 307 to the drain D of the SiC MOS Q2 301 chip. The twelfth copper foil region 308 is connected to the source S of the SiC MOS Q2 301 chip and the top copper foil of the second power module substrate 13 via a vertical interconnect channel, thereby connecting the source S electrode of the SiC MOS Q2 301 chip and the drain D of the SiCMOS Q3 303 chip. The thirteenth copper foil region 309 is connected to the SiC MOS... The source S of Q3 303; the fourteenth copper foil region 310 is connected to the VB electrode of the driver chip IC through a vertical interconnect channel; the fifteenth copper foil region 311 is connected to the VS electrode of the driver chip IC and the source S of SiC MOS Q2 301 through a vertical interconnect channel; the sixteenth copper foil region 312 is connected to the HO electrode of the driver chip IC and the gate G of SiC MOS Q2 301 through a vertical interconnect channel; the seventeenth copper foil region 313 is connected to the VCC electrode of the driver chip IC through a vertical interconnect channel; the eighteenth copper foil region 314 is connected to the ICHIN electrode of the driver chip IC through a vertical interconnect channel; the nineteenth copper foil region 315 is connected to the LIN electrode of the driver chip IC through a vertical interconnect channel; the twentieth copper foil region 316 is connected to the GND electrode of the driver chip IC and the source S of SiC MOS Q3 303 chip through a vertical interconnect channel; the twenty-first copper foil region 317 is connected to the LO electrode of the driver chip IC and the gate G of SiC MOS Q3 303 chip through a vertical interconnect channel. The second redistribution layer includes device pins DC+ 318, SW 319, DC- 320, VB 321, VS 322, VCC 323, GND 324, HIN 325, and LIN 326. Device pin DC+ 318 is connected to the eleventh copper foil region 307 via a via, thus connecting device pin DC+ 318 to the drain D of the internal SiC MOS Q2 301. Device pin SW 319 is connected to the twelfth copper foil region 308 via a via, thus connecting device pin SW 319 to the source S of the internal SiC MOS Q2 301 chip and the drain D of the SiC MOS Q3 303 chip. Device pin DC- 320 is connected to the thirteenth copper foil region 309 via a via, thus connecting device pin DC- 320 to the source S of the internal SiC MOS Q3 303 chip. Device pin VB... Device pin VB 321 is connected to the fourteenth copper foil region 310 via a via, thereby connecting device pin VB 321 to the VB electrode of the internal driver chip IC; device pin VS 322 is connected to the fifteenth copper foil region 311 via a via, thereby connecting device pin VS 322 to the VS electrode of the internal driver chip IC and the source S of the SiC MOS Q2 301 chip; device pin VCC 323 is connected to the seventeenth copper foil region 313 via a via, thereby connecting device pin VCC 323 to the VCC electrode of the internal driver chip IC; device pin GND 324 is connected to the twentieth copper foil region 316 via a via, thereby connecting device pin GND 324 to the GND electrode of the driver chip IC and the source S of the SiC MOS Q3 303 chip; device pin HIN 325 is connected to the eighteenth copper foil region 314 via a via, thereby connecting device pin HIN 325 to the HIN electrode of the internal driver chip IC; device pin LIN... 326 is connected to the nineteenth copper foil area 315 through a via, thereby enabling the device pin LIN 325 to be connected to the internal driver chip IC LIN electrode.

[0093] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in the present invention, and these should all be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A packaging method for a power device, characterized in that, Includes the following steps: S100. Establish a frame reference: Select a temporary carrier plate with parallel upper and lower planes, and apply temporary bonding adhesive to the upper surface of the temporary carrier plate; select a first positioning copper pillar, a first power module substrate, and a second power module substrate of equal height; fix the bottom surface of the first positioning copper pillar to the upper surface of the temporary carrier plate using the temporary bonding adhesive; set the heat dissipation end of the first power module substrate and the heat dissipation end of the second power module substrate in a predetermined area on the upper surface of the temporary carrier plate. S200, Frame Construction: The first positioning copper pillar, the first power module substrate, and the second power module substrate are wrapped and fixed with molding compound to form a first molding body; the molding compound on the upper surface of the first molding body is ground to expose the upper surface of the first positioning copper pillar. Using the upper surface of the first positioning copper pillar as a reference, grinding is continued to expose the conductive layers of the first power module substrate and the second power module substrate, so that the upper surface of the first positioning copper pillar, the conductive layers of the first power module substrate and the second power module substrate are on the same plane. S300, Forming chip mounting cavities: A first cavity and a second cavity are formed from the conductive layer surface of the first power module substrate and the second power module substrate toward the ceramic layer, respectively; the depth of the first cavity is equal to the sum of the thickness of the first chip and the thickness of the chip mounting material after curing, and the depth of the second cavity is equal to the sum of the thickness of the second chip and the thickness of the chip mounting material after curing. S400, Chip Mounting: Chip mounting material is coated on the bottom of the first cavity and the second cavity. A high-precision pick-and-place machine is used to fix the back side of the first chip in the first cavity and the back side of the second chip in the second cavity. The chip mounting material enables the first chip to be bonded to the first power module substrate and the second chip to be bonded to the second power module substrate. At the same time, the electrode surfaces of the front of the first chip and the second chip are in the same plane as the conductive layer surfaces of the first power module substrate and the second power module substrate. S500. Establishing a wiring reference: Select a second positioning copper pillar. The height of the second positioning copper pillar is equal to the sum of the height of the first positioning copper pillar and the preset via depth. Apply temporary bonding adhesive to the upper surface of the temporary carrier board. Fix the bottom surface of the second positioning copper pillar to the upper surface of the temporary carrier board using the temporary bonding adhesive. Encapsulate the first molding compound, the first chip, the second chip, and the second positioning copper pillar on one side of the upper surface of the temporary carrier board using molding compound to form a second molding compound. Grind the upper surface of the second molding compound on the side away from the temporary carrier board until the upper surface of the second positioning copper pillar is exposed. Grind the upper surface of the second molding compound until it is on the same plane as the upper surface of the second positioning copper pillar. S600, Vertical Interconnection and Internal Routing: The electrode positions of the first chip and the second chip, as well as the conductive layer positions of the first power module substrate and the second power module substrate, are determined based on the second positioning copper pillars. The via positions are determined based on the electrode positions and conductive layer positions. A via is formed at the via position according to a preset via depth, connecting the upper surface of the second molding compound and the electrodes of the first chip, the electrodes of the second chip, the conductive layer of the first power module substrate, and the conductive layer of the second power module substrate. A seed layer is formed on the upper surface of the second molding compound and on the via. According to the designed circuit, a redistribution layer is formed on the upper surface of the second molding compound through patterning and electroplating filling processes. A vertical interconnect channel is formed in the via. The redistribution layer connects the first chip electrode, the second chip electrode, the first power module substrate conductive layer, and the second power module substrate conductive layer via vertical interconnect channels; thereby realizing the connection between the first chip and the second chip electrode, between the first chip and the first power module substrate conductive layer, between the second chip and the second power module substrate conductive layer, and between the first power module substrate conductive layer and the second power module substrate conductive layer according to the designed circuit; power device pins are formed on the redistribution layer; S700, Post-processing: Remove the temporary carrier by eliminating the adhesive force of the temporary bonding adhesive, and then complete the post-processing to obtain the power device.

2. The method as described in claim 1, characterized in that, Step S300 further includes forming a third cavity from the upper surface of the first positioning copper pillar toward the temporary carrier plate, wherein the depth of the third cavity is equal to the sum of the thickness of the third chip and the thickness of the chip mounting material after curing; step S400 further includes coating the bottom of the third cavity with chip mounting material, fixing the back of the third chip in the third cavity, and using the chip mounting material to fix the third chip to the first positioning copper pillar, and making the front electrode of the third chip and the upper surface of the first positioning copper pillar lie in the same plane.

3. The method as described in claim 2, characterized in that, In step S600, the redistribution layer includes a first redistribution layer and a second redistribution layer. The first redistribution layer is formed on the upper surface of the second molding compound. The first redistribution layer connects the first chip, the second chip electrode, and the conductive layers of the first power module substrate and the second power module substrate through vertical interconnect channels. Then, an insulating layer is disposed on the upper surface of the first redistribution layer, and the second redistribution layer is disposed on the insulating layer. Power device pins are disposed on the second redistribution layer. The power device pins are connected to the first redistribution layer through vias, thereby realizing the connection with the first chip electrode and the second chip electrode.

4. The method as described in claim 1, characterized in that, After step S700, a third molding process is performed on the surface of the power device, excluding the power device pins.

5. A power device, characterized in that, The system includes a molding compound, a first power module substrate, a second power module substrate, a first positioning copper pillar, a second positioning copper pillar, a first chip, and a second chip. The molding compound includes an upper surface and a lower surface, with the upper surface parallel to the lower surface. The first power module substrate, the second power module substrate, and the first positioning copper pillar are of equal height, and the molding compound encapsulates them into a single unit. The heat dissipation ends of the first and second power module substrates, as well as the lower surfaces of the first and second positioning copper pillars, are flush with the lower surface of the molding compound. A first cavity and a second cavity are respectively disposed on the conductive layers of the first and second power module substrates. The first chip is fixed in the first cavity using a chip mounting material, such that the electrodes on the front of the first chip are in the same plane as the conductive layer surface of the first power module substrate. The second chip is fixed in the second cavity using a chip mounting material. In this configuration, the electrodes on the front of the second chip and the conductive layer surface of the second power module substrate are located in the same plane; the upper surface of the second positioning copper pillar is located in the same plane as the upper surface of the molding compound, and the height of the second positioning copper pillar is equal to the sum of the height of the first positioning copper pillar and the via depth; a redistribution layer is provided on the upper surface of the molding compound, and vias are provided between the upper surface of the molding compound and the chip electrodes, the first power module substrate, and the conductive layer of the second power module substrate, with vertical interconnect channels provided in the vias; the redistribution layer connects the first chip electrodes, the second chip electrodes, the conductive layer of the first power module substrate, and the conductive layer of the second power module substrate through the vertical interconnect channels; thereby realizing the connection between the first chip and the second chip electrodes, between the first chip and the first power module substrate conductive layer, between the second chip and the second power module substrate conductive layer, and between the first power module substrate conductive layer and the second power module substrate conductive layer according to the designed circuit; power device pins are formed on the redistribution layer.

6. The power device as described in claim 5, characterized in that, The redistribution layer includes a first redistribution layer and a second redistribution layer. The first redistribution layer is disposed on the upper surface of the molding compound. The first redistribution layer connects the first chip, the second chip electrode, and the conductive layers of the first power module substrate and the second power module substrate through vertical interconnect channels. An insulating layer is disposed on the upper surface of the first redistribution layer, and the second redistribution layer is disposed on the insulating layer. Power device pins are disposed on the second redistribution layer. The power device pins are connected to the first redistribution layer through vias, thereby realizing the connection with the first chip electrode and the second chip electrode.

7. The power device as described in claim 6, characterized in that, It also includes a third chip, which forms a third cavity on the upper surface of the first positioning copper pillar toward the temporary carrier board. The third chip is fixed in the third cavity by chip mounting material, and the electrodes on the front of the third chip are in the same plane as the upper surface of the first positioning copper pillar.

8. The power device as described in claim 6, characterized in that, The power device is an IGBT parallel diode power device, the first chip is an IGBT chip, and the second chip is a diode chip; the IGBT chip is soldered to the first cavity through chip mounting material, realizing the connection between the collector C of the IGBT chip and the top copper foil of the first power module substrate; the diode chip is soldered to the second cavity through chip mounting material, realizing the connection between the negative terminal K of the diode and the top copper foil of the second power module substrate. The first redistribution layer includes a first copper foil region, a second copper foil region, and a third copper foil region. The first copper foil region is connected to the positive electrode A of the diode chip and the emitter E of the IGBT chip through a vertical interconnect channel. The second copper foil region is connected to the top copper foil of the first power module substrate and the second power module through a vertical interconnect channel, thereby connecting the collector C of the IGBT chip and the negative electrode K of the diode chip. The third copper foil region is connected to the gate G of the IGBT chip through a vertical interconnect channel. The second redistribution layer includes device pin C, device pin G, and device pin E. Device pin C is connected to the second copper foil area of ​​the first redistribution layer through a via, thereby connecting device pin C to the collector C of the internal IGBT chip and the negative terminal K of the diode chip. Device pin G is connected to the third copper foil area of ​​the first redistribution layer through a via, thereby connecting device pin G to the gate G of the internal IGBT chip. Device pin E is connected to the first copper foil area of ​​the first redistribution layer through a via, thereby connecting device pin E to the emitter E of the internal IGBT chip and the positive terminal A of the diode chip.

9. The power device as described in claim 6, characterized in that, The power device is a half-bridge packaged power device composed of two SiC MOS chips, the first chip being SiC MOS Q4 and the second chip being SiC MOS Q5; The SiC MOS Q4 chip is soldered to the first cavity using chip mounting material, thus connecting the drain D of the SiC MOS Q4 chip to the top copper foil of the first power module substrate; the SiC MOS Q5 chip is soldered to the second cavity using chip mounting material, thus connecting the drain D of the SiC MOS Q5 chip to the top copper foil of the second power module substrate. The first redistribution layer includes a fourth copper foil region, a fifth copper foil region, a sixth copper foil region, a seventh copper foil region, an eighth copper foil region, a ninth copper foil region, and a tenth copper foil region. The fourth copper foil region is connected to the top copper foil of the first power module substrate through a vertical interconnect channel, thereby connecting the fourth copper foil region to the drain D of the SiC MOS Q4 chip. The fifth copper foil region is connected to the front source S of the SiC MOS Q4 chip and the top copper foil of the second power module substrate through a vertical interconnect channel, thereby connecting the front source S of the SiC MOS Q4 chip and the drain D of the SiC MOS Q5 chip. The sixth copper foil region is connected to the source S of the SiC MOS Q5 chip through a vertical interconnect channel. The seventh copper foil region is connected to the gate G of the SiC MOS Q4 chip through a vertical interconnect channel. The eighth copper foil region is connected to the source S of the SiC MOS Q4 chip through a vertical interconnect channel. The ninth copper foil region is connected to the gate G of the SiC MOS Q5 chip through a vertical interconnect channel. The tenth copper foil region is connected to the source S of the SiC MOS Q5 chip through a vertical interconnect channel. The second redistribution layer includes device pins DC+, SW, DC-, G1, S1, G2, and S2. Device pin DC+ is connected to the fourth copper foil region via a via, thus connecting device pin DC+ to the drain D of the SiC MOS Q4. Device pin SW is connected to the fifth copper foil region via a via, thus connecting device pin SW to the source S of the internal SiC MOS Q4 chip and the drain D of the SiC MOS Q5 chip. Device pin DC- is connected to the sixth copper foil region via a via, thus connecting device pin DC- to the source S of the SiC MOS Q5 chip. Device pin G2 is connected to the seventh copper foil region via a via, thus connecting device pin G2 to the gate G of the internal SiC MOS Q4 chip. Device pin S2 is connected to the eighth copper foil region via a via, thus connecting device pin S2 to the source S of the internal SiC MOS Q4 chip. Device pin G1 is connected to the ninth copper foil region via a via, thus connecting device pin G1 to the internal SiC MOS Q5 chip. The gate G of the MOS Q5 chip is connected; the device pin S1 is connected to the tenth copper foil region through a via, thereby connecting the device pin S1 to the source S of the internal SiCMOS Q5.

10. The power device as claimed in claim 7, characterized in that, The power device is a SiCMOS half-bridge power device containing a driver chip, wherein the first chip is a SiC MOS Q2, the second chip is a SiC MOS Q3, and the third chip is a driver chip IC. The SiC MOS Q2 chip is soldered to the first cavity using chip mounting material, thus connecting the drain D of the SiC MOS Q2 chip to the top copper foil of the first power module substrate; the SiC MOS Q3 chip is soldered to the second cavity using chip mounting material, thus connecting the drain D of the SiC MOS Q3 chip to the top copper foil of the second power module substrate; the driver chip IC is soldered to the third cavity on the first positioning copper pillar using chip mounting material. The first redistribution layer includes an eleventh copper foil region, a twelfth copper foil region, a thirteenth copper foil region, a fourteenth copper foil region, a fifteenth copper foil region, a sixteenth copper foil region, a seventeenth copper foil region, an eighteenth copper foil region, a nineteenth copper foil region, a twentieth copper foil region, and a twenty-first copper foil region. The eleventh copper foil region is connected to the top copper foil of the first power module substrate through a vertical interconnect channel, thereby connecting the eleventh copper foil region to the drain D of the SiC MOS Q2 chip. The twelfth copper foil region is connected to the source S of the SiC MOS Q2 chip and the top copper foil of the second power module substrate through a vertical interconnect channel, thereby connecting the source S electrode of the SiC MOS Q2 chip and the drain D of the SiC MOS Q3 chip. The thirteenth copper foil region is connected to the source S of the SiCMOS Q3 chip through a vertical interconnect channel. The fourteenth copper foil region is connected to the VB electrode of the driver chip IC through a vertical interconnect channel. The fifteenth copper foil region is connected to the VS electrode of the driver chip IC and the SiC MOS Q2 chip through a vertical interconnect channel. Source S; the sixteenth copper foil region is connected to the driver chip IC HO electrode and the SiC MOS Q2 gate G through a vertical interconnect channel; the seventeenth copper foil region is connected to the driver chip IC VCC electrode through a vertical interconnect channel; the eighteenth copper foil region is connected to the driver chip IC HIN electrode through a vertical interconnect channel; the nineteenth copper foil region is connected to the driver chip IC LIN electrode through a vertical interconnect channel; the twentieth copper foil region is connected to the driver chip IC GND electrode and the SiC MOS Q3 chip source S through a vertical interconnect channel; the twenty-first copper foil region is connected to the driver chip IC LO electrode and the SiC MOS Q3 chip gate G through a vertical interconnect channel. The second redistribution layer includes device pins DC+, SW, DC-, VB, VS, VCC, GND, HIN, and LIN. Device pin DC+ is connected to the eleventh copper foil region via a via, thus connecting device pin DC+ to the drain D of the internal SiC MOS Q2. Device pin SW is connected to the twelfth copper foil region via a via, thus connecting device pin SW to the source S of the internal SiC MOS Q2 chip and the drain D of the SiCMOS Q3 chip. Device pin DC- is connected to the thirteenth copper foil region via a via, thus connecting device pin DC- to the source S of the internal SiC MOS Q3. Device pin VB is connected to the fourteenth copper foil region via a via, thus connecting device pin VB to the VB electrode of the internal driver chip IC. Device pin VS is connected to the fifteenth copper foil region via a via, thus connecting device pin VS to the VS electrode of the internal driver chip IC and the SiC MOS. The source (S) of the Q2 chip is connected; the VCC pin is connected to the seventeenth copper foil area through a via, thus connecting the VCC pin to the VCC electrode of the internal driver chip IC; the GND pin is connected to the twentieth copper foil area through a via, thus connecting the GND pin to the GND electrode of the driver chip IC and the source (S) of the SiC MOS Q3 chip; the HIN pin is connected to the eighteenth copper foil area through a via, thus connecting the HIN pin to the HIN electrode of the internal driver chip IC; the LIN pin is connected to the nineteenth copper foil area through a via, thus connecting the LIN pin to the LIN electrode of the internal driver chip IC.

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