Package substrate, method of manufacturing the same, and semiconductor package structure

Abstract

The application provides a packaging board, a preparation method thereof and a semiconductor packaging structure. The packaging board comprises: a glass substrate comprising a glass through hole arranged through in a thickness direction; a first conductive structure located in the glass through hole; a buffer structure located at at least one side aperture of the glass through hole; the buffer structure comprises a buffer hole penetrating through the buffer structure in the thickness direction; and a second conductive structure arranged in the buffer hole, and the second conductive structure is electrically connected with the first conductive structure. By arranging the buffer structure at the aperture of the glass through hole, external stress can be absorbed and buffered, so that the stress is prevented from directly acting on the interface between the brittle glass substrate and the first conductive structure. Furthermore, by arranging the buffer hole in the buffer structure and arranging the second conductive structure, the electrical connection function is realized, and the stress concentration problem caused by the direct contact between the large-size metal column and the glass aperture is avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a packaging substrate and its preparation method, and a semiconductor packaging structure. Background Technology

[0002] With the development of high-performance chips, chip integration is becoming increasingly higher and interconnect density is becoming increasingly dense. Traditional organic substrates can no longer meet the requirements in terms of flatness, fine lines, and signal transmission rates. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a packaging substrate and its preparation method, as well as a semiconductor packaging structure, to reduce the stress on the glass substrate.

[0004] In view of the above objectives, firstly, this application provides a packaging carrier board, comprising: A glass substrate, including a glass through-hole disposed throughout the thickness direction; The first conductive structure is located inside the glass through-hole; A buffer structure is located at at least one side of the opening within a glass through-hole; the buffer structure includes a buffer hole that extends through the buffer structure along its thickness direction. The second conductive structure is disposed inside the buffer hole and is electrically connected to the first conductive structure.

[0005] Optionally, the buffer structure has multiple buffer holes, and multiple second conductive structures fill the corresponding buffer holes respectively.

[0006] Optionally, the plurality of buffer holes are arranged in a centrally symmetrical array, including a central hole located at the center and a plurality of dispersed holes evenly distributed around the central hole in a circular pattern.

[0007] Optionally, the number of dispersion holes is 6 to 10; Optionally, the ratio of the diameter of the central hole to the diameter of the dispersion hole is greater than or equal to 1.1 and less than or equal to 1.5. Optionally, the edge spacing between adjacent dispersion holes is 0.05 to 0.15 times the diameter of the glass through-hole.

[0008] Optionally, the plurality of buffer holes are distributed in multiple concentric circles, including an inner circle of buffer holes and at least one outer circle of buffer holes. The number of the inner circle of buffer holes is 1 to 3, and the number of the outermost outer circle of buffer holes is 4 to 10. Optionally, the diameter of the buffer hole decreases along the direction away from the center of the glass through-hole.

[0009] Optionally, it also includes: The first seed layer covers at least a portion of the wall of the glass via, and the first conductive structure is in contact with the first seed layer.

[0010] Optionally, it also includes: The second seed layer covers the bottom and walls of the buffer hole, and the second conductive structure is in contact with the second seed layer.

[0011] Optionally, the first conductive structure has a buffer structure and a second conductive structure on both opposite sides in the thickness direction.

[0012] Optionally, the ratio of the dimension of the first conductive structure in the thickness direction to the dimension of the glass via in the thickness direction is 0.7 to 0.9.

[0013] Optionally, the first conductive structure and the second conductive structure are made of different materials.

[0014] Optionally, the material of the first conductive structure is copper or a copper-tungsten alloy, and the material of the second conductive structure is silver, gold, or a copper-nickel alloy.

[0015] Optionally, it also includes: A redistribution layer is disposed on at least one side of a glass substrate, and the redistribution layer is electrically connected to a first conductive structure through a second conductive structure.

[0016] Optionally, it also includes: A solder resist layer is disposed on the side of the redistribution layer away from the glass substrate, and the solder resist layer includes multiple conductive openings; Multiple conductive bumps are located within conductive openings and are electrically connected to the redistribution layer.

[0017] Secondly, this application also provides a method for preparing a packaging carrier, comprising: A glass substrate is provided, and a glass through-hole is formed in the glass substrate in the thickness direction; A first conductive structure is disposed within the glass through-hole; A buffer structure is provided at least one side of the opening within the glass through-hole; A buffer hole is formed within the buffer structure, extending through the buffer structure along the thickness direction; A second conductive structure is formed inside the buffer hole, and the second conductive structure is electrically connected to the first conductive structure.

[0018] Optionally, after forming the buffer hole and before forming the second conductive structure, the method further includes: A second seed layer is formed on the bottom, wall, and end face of the buffer hole; A second conductive structure is formed on the second seed layer using an electroplating process, and the second conductive structure fills the buffer holes. Remove the second seed layer and the second conductive structure from the end face of the buffer structure.

[0019] Thirdly, this application also provides a semiconductor packaging structure, including a circuit board, a chip, and a packaging carrier as described in any of the first aspects above, wherein the packaging carrier is located between the circuit board and the chip, and realizes the electrical connection between the circuit board and the chip.

[0020] The encapsulation substrate provided in this application has a buffer structure at the opening of the glass through-hole, which can absorb and buffer external stress, preventing stress from acting directly on the interface between the brittle glass substrate and the first conductive structure. By opening a buffer hole in the buffer structure and setting a second conductive structure, both the electrical connection function is achieved and the stress concentration problem that may be caused by using a large-sized metal pillar to directly contact the glass opening is avoided. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of a packaging carrier provided in an embodiment of this application; Figure 2 This is a schematic diagram of a buffer structure in a packaging carrier provided in an embodiment of this application; Figure 3 This is a partial structural diagram of another packaging carrier provided in an embodiment of this application; Figure 4 This is a schematic diagram of another buffer structure in a packaging carrier provided in this application embodiment; Figure 5 This is a schematic diagram of another buffer structure in a packaging carrier provided in this application embodiment; Figure 6 This is a schematic diagram of another buffer structure in a packaging carrier provided in this application embodiment; Figure 7 This is a schematic diagram of another buffer structure in a packaging carrier provided in this application embodiment; Figure 8 This is a schematic diagram of another packaging carrier provided in an embodiment of this application; Figure 9 This is a schematic flowchart of a method for preparing a packaging substrate provided in an embodiment of this application; Figure 10 This is a schematic diagram illustrating the structural changes of the packaging carrier provided in the embodiments of this application during the manufacturing process; Figure 11 This is a schematic diagram illustrating the structural changes of the packaging carrier provided in the embodiments of this application during the manufacturing process; Figure 12 This is a schematic diagram of the structure of a packaging carrier provided in an embodiment of this application.

[0023] Marker explanation: 1000 Semiconductor package structure; 100 Package carrier; 10 Glass substrate; 11 Glass via; 20 First conductive structure; 30 Buffer structure; 31 Buffer hole; 311 Center hole; 312 Dispersion hole; 301 Inner ring buffer hole; 302 Outer ring buffer hole; 40 Second conductive structure; 51 First seed layer; 52 Second seed layer; 60 Redundancy layer; 61 Surface treatment layer; 70 Solder mask layer; 71 Conductive opening; 80 Conductive bump; 200 Circuit board; 300 Chip; 400 Package insulating layer. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0025] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0026] With the continuous development of high-performance chips, chip integration density is constantly increasing, and interconnect density is rising daily. Traditional organic substrates are gradually becoming insufficient to meet the demands of advanced packaging in terms of flatness, fine-line processing capabilities, and signal transmission rates. Glass substrates, due to their physical, chemical, and electrical properties, have become a potential alternative to organic substrates. Specifically, glass can withstand higher processing temperatures than organic materials, and its coefficient of thermal expansion is similar to that of silicon chips, helping to reduce warping problems caused by thermal mismatch. Furthermore, the flatness and low roughness of the glass surface facilitate denser wiring. The low dielectric constant and low dielectric loss of glass materials also contribute to improved signal transmission speed and signal integrity.

[0027] In glass substrate applications, vias need to be formed in the glass to achieve vertical electrical interconnections. However, glass is a brittle material, and the inventors discovered that during the via forming process, micro-damage or geometric abrupt changes can easily occur at the via opening edge, creating stress concentration points. During subsequent packaging processes or thermal cycling, these stress concentration areas are prone to crack initiation and potential propagation leading to device failure. Therefore, reducing the stress at the via opening and suppressing crack initiation and propagation is a pressing problem in this field.

[0028] An embodiment of this application provides a packaging carrier 100. See also... Figure 1 The encapsulation carrier 100 includes a glass substrate 10, a first conductive structure 20, a buffer structure 30, and a second conductive structure 40. The glass substrate 10 includes a through-hole 11 extending along its thickness direction. The first conductive structure 20, the buffer structure 30, and the second conductive structure 40 are located within the through-hole 11. The buffer structure 30 is located at at least one opening within the through-hole 11 and includes a buffer hole 31 extending along its thickness direction. The second conductive structure 40 is disposed within the buffer hole 31 and is electrically connected to the first conductive structure 20.

[0029] Specifically, the glass substrate 10 serves as a carrier substrate, having a first surface and a second surface opposite each other along the thickness direction, and including glass through-holes 11 disposed through the first surface and the second surface. The material of the glass substrate 10 can be borosilicate glass, quartz glass, or other glass materials suitable for semiconductor packaging, and its thickness, the diameter and distribution of the glass through-holes 11 can be determined according to actual wiring requirements and mechanical strength requirements.

[0030] The first conductive structure 20 is disposed within the glass through-hole 11 to achieve vertical electrical interconnection. The material of the first conductive structure 20 can be conductive metals such as copper, aluminum, nickel, and gold; considering conductivity and cost factors, copper is preferred. The first conductive structure 20 can be formed by electroplating filling, and its filling height can be equal to or less than the depth of the glass through-hole 11, thereby reserving space for the buffer structure 30 at the orifice opening.

[0031] A buffer structure 30 is disposed at at least one side of the aperture within the glass through-hole 11. In other words, the buffer structure 30 may be disposed only at the aperture on the first surface side of the glass substrate 10, or it may be disposed simultaneously at the apertures on both the first and second surfaces side. The material of the buffer structure 30 is a dielectric material with stress-buffering properties, such as polyimide, Ajinomoto film, or other organic polymer materials. A buffer hole 31 is formed in the buffer structure 30, extending through the buffer structure 30 along its thickness direction.

[0032] The second conductive structure 40 is disposed within the buffer hole 31 and forms an electrical connection with the first conductive structure 20. The material of the second conductive structure 40 may be the same as or different from that of the first conductive structure 20, such as copper, aluminum, nickel, gold, etc. The function of the second conductive structure 40 is to lead the electrical signal of the first conductive structure 20 from inside the glass through hole 11 to the surface of the glass substrate 10, so as to connect with the subsequent redistribution layer.

[0033] The encapsulation carrier 100 provided in this embodiment has a buffer structure 30 disposed at the opening of the glass through-hole 11, which can absorb and buffer external stress, preventing stress from acting directly on the interface between the brittle glass substrate 10 and the first conductive structure 20. By opening a buffer hole 31 in the buffer structure 30 and providing a second conductive structure 40, both the electrical connection function is achieved and the stress concentration problem that may be caused by using a large-sized metal pillar to directly contact the glass opening is avoided.

[0034] In some embodiments, such as Figure 2 As shown, the buffer structure 30 has multiple buffer holes 31, and multiple second conductive structures 40 respectively fill the corresponding buffer holes 31. Specifically, multiple tiny conductive channels are formed in the buffer structure 30, and these conductive channels are arranged in an array in a plane parallel to the surface of the glass substrate 10.

[0035] In some embodiments, the plurality of buffer holes 31 are arranged in a centrally symmetrical array, that is, the plurality of buffer holes 31 are evenly distributed around a central point. The plurality of buffer holes 31 include a central hole 311 located at the center and a plurality of dispersed holes 312 evenly distributed around the central hole 311 in a circular pattern.

[0036] In one embodiment, the number of dispersion holes 312 is 6 to 10. Specifically, they can be arranged in a quincunx pattern, for example, as shown below. Figure 5 As shown, there are six dispersion holes 312, which together with the central hole 311 form a quincunx array. The number of dispersion holes 312 can also be seven, eight, nine, or ten. This arrangement of multiple dispersion holes 312 can balance space utilization and stress dispersion effect.

[0037] Correspondingly, the multiple second conductive structures 40 are also distributed in the same centrally symmetrical array.

[0038] In one embodiment, the ratio of the diameter of the central hole 311 to the diameter of the dispersion hole 312 is greater than or equal to 1.1 and less than or equal to 1.5. For example, the ratio of the diameter of the central hole 311 to the diameter of the dispersion hole 312 is 1.1, 1.2, 1.3, 1.4 or 1.5.

[0039] When the ratio of the diameter of the central hole 311 to the diameter of the dispersion hole 312 is less than 1.1, the size difference between the central hole 311 and the dispersion hole 312 is too small, and the problem of stress concentration in the central region is not significantly improved.

[0040] When the ratio of the diameter of the central hole 311 to the diameter of the dispersion hole 312 is greater than 1.5, the size of the central hole 311 is too large, which compresses the layout space of the dispersion hole 312 and affects the overall effect of the multi-point interconnection structure.

[0041] In one embodiment, such as Figure 5 As shown, the edge spacing L between adjacent dispersion holes 312 is preferably 0.05 to 0.15 times the diameter D of the glass through-hole 11, i.e., L = (0.05~0.15) × D. For example, when the diameter D of the glass through-hole 11 is 50 μm, the edge spacing L between adjacent dispersion holes 312 is 2.5 μm to 7.5 μm. The lower limit of 0.05 times ensures that the buffer structure 30 has sufficient material strength between the holes, avoiding structural cracking due to excessively thin material between the holes. The upper limit of 0.15 times ensures that a sufficient number of buffer holes 31 can be arranged within the limited cross-section of the glass through-hole, achieving multi-point interconnection.

[0042] The ratio of the diameter of the central hole to the diameter of the distribution holes is controlled within the range of 1.1 to 1.5 to avoid stress concentration in the central area. The distance between the edges of adjacent distribution holes is controlled within 0.05 to 0.15 times the diameter of the glass through-hole, which ensures structural strength while allowing a sufficient number of buffer holes to be arranged within a limited cross-section.

[0043] In one embodiment, to further optimize stress dispersion and improve signal transmission performance, the multiple buffer holes 31 within the buffer structure 30 are arranged in a multi-ring concentric circle array. For example... Figure 6 , Figure 7As shown, the plurality of buffer holes 31 include an inner ring buffer hole 301 and one or more outer ring buffer holes 302. The number of inner ring buffer holes 301 is 1 to 3, located in the central region of the glass through hole 11; the number of outer ring buffer holes 302 located in the outermost ring is 4 to 10, distributed circumferentially around the inner ring.

[0044] In one embodiment, the diameter of the buffer hole 31 decreases along the direction away from the center of the glass through hole 11.

[0045] The outermost buffer hole 302 has a smaller diameter than the inner buffer hole 301, forming a gradient structure with decreasing diameter from the inside out. For example, the inner buffer hole 301 has a diameter of 15μm to 20μm, and the outer buffer hole 302 has a diameter of 8μm to 12μm. The edge spacing between adjacent buffer holes 31 is controlled within the range of 2μm to 6μm to ensure the mechanical integrity of the buffer structure 30, while providing multiple parallel transmission paths for electrical signals.

[0046] The multi-ring gradient arrangement structure effectively disperses stress concentrated in the central region outwards during thermal cycling or mechanical impact, reducing the stress peak at the opening of the glass through-hole 11. Simultaneously, the total cross-sectional area of ​​the multiple parallel and independent small-sized conductive channels is not reduced compared to a single large-sized metal pillar, thus not increasing DC resistance. Furthermore, due to the reduced channel diameter, the skin depth of each channel is independent at high frequencies, resulting in a smaller increase in equivalent resistance compared to a single large conductor, thereby optimizing high-frequency signal transmission performance.

[0047] The inner buffer hole 301 has a larger diameter, allowing it to withstand greater thermal stress in the central region. The outer buffer hole 302 has a smaller diameter, allowing it to accommodate more holes within a limited space, increasing the number of conductive channels. The decreasing hole diameter creates a stress gradient buffer region, causing thermal stress to gradually decrease from the center outwards, further reducing the stress peak at the interface. Multiple second conductive structures 40 within the buffer holes 31 form multiple micro-conductive channels, replacing the structure of a single large-sized metal pillar. When the encapsulation substrate 100 experiences temperature changes or mechanical stress, the thermal or mechanical stress that might have been concentrated at a single interface is dispersed into multiple independent micro-conductive channels, thereby reducing the stress value borne by each conductive channel and inhibiting the initiation and propagation of cracks at the glass opening. By dispersing the current and stress carried by a traditional single large-sized metal pillar into multiple independent conductive channels, when the encapsulation substrate 100 experiences temperature changes, the thermal stress caused by thermal expansion mismatch is shared by multiple second conductive structures 40, further reducing the local stress at the interface of each conductive channel.

[0048] In some embodiments, such as Figure 3As shown, the encapsulation substrate 100 also includes a first seed layer 51. The first seed layer 51 at least covers a portion of the hole wall of the glass via 11, and the first conductive structure 20 is in contact with the first seed layer 51.

[0049] The first seed layer 51 enhances the adhesion between the first conductive structure 20 and the glass substrate 10, and provides a conductive substrate for the electroplating filling process. The first seed layer 51 is a composite layer structure, comprising an adhesion layer and a conductive seed layer sequentially stacked along the direction away from the glass substrate 10. The adhesion layer is made of at least one of titanium, titanium-tungsten alloy, and chromium, and has a thickness of 50 nm to 200 nm, used to enhance the adhesion between the metal and the glass substrate 10. The conductive seed layer is made of copper and has a thickness of 100 nm to 500 nm, used to provide a uniform conductive substrate for subsequent electroplating processes. The composite layer structure reduces interface resistance and improves electromigration reliability while ensuring adhesion.

[0050] In some embodiments, such as Figure 3 , Figure 4 As shown, the packaging substrate 100 also includes a second seed layer 52. The second seed layer 52 covers the bottom and walls of the buffer hole 31, and the second conductive structure 40 is in contact with the second seed layer 52.

[0051] Specifically, the second seed layer 52 enhances the bonding force between the second conductive structure 40 and the buffer structure 30, and provides a conductive substrate for the electroplating process. The material of the second seed layer 52 can be the same as the first seed layer 51; for example, the second seed layer 52 can also be a composite layer structure, including an adhesive layer and a conductive seed layer. The adhesive layer can be made of titanium or a titanium-tungsten alloy, which has good affinity with organic materials, and has a thickness of 50 nm to 200 nm. The conductive seed layer is also made of copper, with a thickness of 100 nm to 500 nm. During the fabrication process, the second seed layer 52 is initially formed on the bottom and walls of the buffer hole 31 and on the end face of the buffer structure 30. Subsequently, the end face portion is removed by grinding or chemical mechanical polishing, so that the second seed layer 52 is only retained in the bottom and wall areas of the hole in the final product. This structure ensures a strong bond between the second conductive structure 40 and the buffer structure 30, while preventing end face residue from causing short circuits in the wiring layer.

[0052] By setting a seed layer, the interfacial bonding performance between the conductive structure and the substrate is improved, ensuring the long-term reliability of the electrical connection.

[0053] In some embodiments, such as Figure 1 As shown, the first conductive structure 20 has a buffer structure 30 and a second conductive structure 40 on both opposite sides in the thickness direction.

[0054] Specifically, a buffer structure 30 and a second conductive structure 40 are provided on both the upper and lower main surface sides of the glass substrate 10, that is, on the first surface side and the second surface side of the glass substrate 10, to achieve double-sided lead-out.

[0055] Furthermore, the ratio of the thickness dimension of the first conductive structure 20 to the thickness dimension of the glass through-hole 11 is controlled within the range of 0.7 to 0.9. For example, the ratio of the thickness dimension of the first conductive structure 20 to the thickness dimension of the glass through-hole 11 is 0.7, 0.8, or 0.9, etc. That is, the first conductive structure 20 does not completely fill the entire glass through-hole 11, but reserves some space at both ends of the hole for setting the buffer structure 30. It should be noted that the ratio range of 0.7 to 0.9 is related to the specific process implementation method. For example, when using the method of controlling the electroplating filling amount, the filling height can be controlled at about 80% of the depth of the through-hole, that is, the ratio is 0.8; when using the method of etching after complete filling, about 10% depth can be etched from both sides of the hole, and a ratio of 0.8 can also be obtained.

[0056] The optimal fill-to-height ratio of 0.7 to 0.9 was achieved through optimization: if the ratio is less than 0.7, the cross-sectional area of ​​the first conductive structure 20 is too small, leading to a decrease in conductivity; if the ratio is greater than 0.9, the reserved space for the buffer structure is too small, limiting the buffering effect and failing to significantly improve the stress concentration problem. Maintaining the ratio between 0.7 and 0.9 ensures conductivity while providing sufficient space for the buffer structure, thus achieving a stress buffering effect.

[0057] In some embodiments, to further optimize conductivity and thermal matching characteristics, the first conductive structure 20 and the second conductive structure 40 are made of different materials, which can optimize high-frequency performance while ensuring thermal matching. For example, the first conductive structure uses a copper-tungsten alloy with a coefficient of thermal expansion matching that of glass, while the second conductive structure uses silver or gold with high conductivity.

[0058] Specifically, the first conductive structure 20 mainly undertakes vertical electrical interconnection and, as a glass via filler, needs to match the coefficient of thermal expansion of the glass substrate 10. Preferably, the material of the first conductive structure 20 is copper or a copper-tungsten alloy. The coefficient of thermal expansion of the copper-tungsten alloy can be adjusted in the range of 6-8 ppm / °C to match the coefficient of thermal expansion of the glass substrate 10 (approximately 3-8 ppm / °C), thereby reducing overall thermal stress.

[0059] The second conductive structure 40 is disposed within the buffer hole 31 and mainly serves to extract signals, requiring high high-frequency performance. Preferably, the material of the second conductive structure 40 is silver, gold, or a copper-nickel alloy. Silver has higher conductivity than copper, which can reduce the insertion loss of high-frequency signals; gold has anti-oxidation properties and is suitable for high-reliability applications; copper-nickel alloys have higher mechanical strength and better resistance to thermal fatigue.

[0060] By employing different conductive materials, thermal matching can be ensured while high-frequency performance can be optimized. In some embodiments, such as Figure 8 As shown, the encapsulation substrate 100 also includes a redistribution layer 60, which is disposed on one side or opposite sides of the glass substrate 10. The redistribution layer 60 is electrically connected to the first conductive structure 20 through the second conductive structure 40.

[0061] Specifically, the redistribution layer 60 is used to fan out or rearrange the electrical signals led out from the first conductive structure 20 to accommodate subsequent connection requirements with chips or other electronic components. The redistribution layer 60 may include one or more layers of metal traces, the material of which may be copper, aluminum, nickel, gold, etc., and a dielectric layer is disposed between adjacent metal trace layers for insulation isolation. For example, the redistribution layer 60 can be formed by alternately stacking dielectric layers and metal traces, and creating corresponding vias in each dielectric layer, thus forming a redistribution layer containing multiple dielectric layers and metal trace layers.

[0062] By setting up a redistribution layer 60, flexible wiring from glass vias to external connection points is achieved, improving the applicability of the packaging substrate 100.

[0063] In some embodiments, the packaging substrate 100 further includes a solder resist layer 70 and a plurality of conductive bumps 80. The solder resist layer 70 is disposed on the side of the redistribution layer 60 away from the glass substrate 10, and includes a plurality of conductive openings 71. The conductive bumps 80 are located within the corresponding conductive openings 71, and the conductive bumps 80 are electrically connected to the redistribution layer 60.

[0064] Specifically, the solder mask layer 70 is disposed on the side of the redistribution layer 60 away from the glass substrate 10 to protect the redistribution layer 60 and prevent bridging during soldering. The solder mask layer 70 includes a plurality of conductive openings 71, which expose a portion of the redistribution layer 60 for subsequent formation of conductive bumps 80.

[0065] The conductive bump 80 is located within the conductive opening 71 and is electrically connected to the redistribution layer 60. The conductive bump 80 is used to achieve physical and electrical connections with the chip or other packaged components. The material of the conductive bump 80 can be tin, tin-silver alloy, copper, copper-nickel-gold, etc., and its formation process can be electroplating, printing, or ball-mounting, etc.

[0066] By setting the solder mask layer 70 and the conductive bumps 80, a complete packaging interface is formed, so that the packaging substrate 100 can be directly used for packaging processes such as flip-chip bonding.

[0067] Specifically, the electrically conductive surface of the redistribution layer 60 exposed in the conductive opening 71 is surface-treated to form a surface treatment layer 61. The surface treatment layer 61 includes suitable materials for surface finishing, such as organic solderable corrosion inhibitors, nickel immersion gold, electroless nickel immersion palladium immersion gold, electroless nickel and electroless palladium immersion gold, chemical tin, etc.

[0068] In a specific example, the glass substrate 10 is made of borosilicate glass with a thickness of 200 μm. The glass vias 11 have a diameter of 50 μm and are arranged in an array, with a center-to-center spacing of 120 μm between adjacent vias. The first seed layer 51 is a composite layer structure, including an adhesion layer formed by a 150 nm thick titanium layer and a conductive seed layer formed by a 300 nm thick copper layer. The first conductive structure 20 is filled with electroplated copper, with a filling height of 80% of the depth of the glass vias 11, i.e., 160 μm. There is a reserved space between the end of the first conductive structure 20 and the first surface of the glass substrate 10 to accommodate the buffer structure 30. The material of the buffer structure 30 is photosensitive polyimide with a glass transition temperature greater than 350°C, which can withstand lead-free reflow soldering processes. The buffer structure 30 completely fills the reserved space recessed between the end of the first conductive structure 20 and the surface of the glass substrate 10. Seven buffer holes 31 are formed in the buffer structure 30, arranged in a centrally symmetrical array. The specific arrangement is as follows: Six buffer holes 31 are evenly distributed on a circle with a radius of 15 μm, centered on the central axis of the glass through-hole 11. A seventh buffer hole 31 is also placed at the center. This arrangement is a quincunx array. The edge spacing between adjacent dispersion holes 312 is 5 μm, which is 0.1 times the diameter of the glass through-hole 11. The diameter of the central hole 311 is 12.5 μm, and the diameter of the dispersion holes 312 is 10 μm, with a diameter ratio of 1.25. The diameter of the buffer holes 31 is 10 μm, and the depth is equal to the thickness of the buffer structure 30, with a depth-to-width ratio of 2:1. The second seed layer 52 also adopts a titanium / copper composite layer structure, where the titanium layer is 100 nm thick and the copper layer is 200 nm thick. After the process is completed, the end face of the buffer structure 30 is partially removed by chemical mechanical polishing, and the resulting second seed layer 52 only covers the hole walls of the buffer holes 31. The second conductive structure 40 is filled with electroplated copper, filling the 7 buffer holes 31.

[0069] Some embodiments of this application also provide a method for preparing a packaging carrier 100.

[0070] like Figure 9 As shown, the preparation method of the packaging substrate 100 specifically includes the following steps: Step S110: Provide a glass substrate 10 and form a glass through hole 11 extending along the thickness direction in the glass substrate 10.

[0071] Specifically, the glass via 11 can be formed using laser-induced wet etching to obtain a via with smooth sidewalls and controllable taper. It should be noted that the methods for forming the glass via 11 are not limited to those listed above; laser melting, focused discharge, plasma etching, or electrochemical discharge processing can also be used. The specific method chosen can be determined comprehensively based on factors such as the material and thickness of the glass substrate 10, the via size, and the processing cost.

[0072] Step S120: Set a first conductive structure 20 inside the glass through hole 11.

[0073] Specifically, a first seed layer 51 is formed on the wall of the glass via 11 by methods such as physical vapor deposition sputtering; then, metal is electroplated onto the first seed layer 51 using an electroplating process to fill the glass via 11. The filling degree can be controlled as needed, for example, filling to about 80% of the via depth, i.e., leaving some space; or after complete filling, about 10% of the metal is removed from each side of the via opening by an etching process, thereby forming reserved space.

[0074] Step S130: Provide a buffer structure 30 at at least one side of the opening in the glass through hole 11.

[0075] Specifically, the material of the buffer structure 30 can be a photolithographic or laser-processable dielectric material such as polyimide or Ajinomoto stacked film. The buffer structure 30 can be formed by spin coating, spraying, or lamination. After formation, it undergoes a curing process. Ajinomoto stacked film is a composite film material primarily composed of epoxy resin, possessing insulation, thermal stability, and mechanical properties, making it suitable for interlayer insulation in high-density interconnects.

[0076] Step S140: A buffer hole 31 is formed in the buffer structure 30, extending through the buffer structure 30 along the thickness direction.

[0077] Specifically, if the buffer structure 30 is made of a photosensitive material (such as photosensitive polyimide), the buffer hole 31 can be formed by an exposure and development process. When forming the buffer hole 31 by an exposure and development process, the appropriate exposure wavelength and development conditions can be selected according to the photosensitivity characteristics of the photosensitive polyimide.

[0078] The number of buffer holes 31 can be one or more. When multiple buffer holes 31 are used, they can be designed to be distributed in a centrally symmetrical array, such as a plum blossom pattern.

[0079] Step S150: A second conductive structure 40 is formed in the buffer hole 31, and the second conductive structure 40 is electrically connected to the first conductive structure 20.

[0080] Please see Figure 10 and Figure 11 The diagram illustrates the structural changes of the packaging substrate 100 at different stages of its fabrication. Specifically, the material of the second conductive structure 40 may be the same as or different from that of the first conductive structure 20, such as copper, aluminum, nickel, gold, etc. The function of the second conductive structure 40 is to lead the electrical signal of the first conductive structure 20 from inside the glass via 11 to the surface of the glass substrate 10 for connection with the subsequent redistribution layer.

[0081] In the method for preparing the encapsulation substrate 100 provided in this application embodiment, a buffer structure 30 is provided at the opening of the glass through-hole 11 to absorb and buffer external stress, preventing stress from acting directly on the interface between the brittle glass substrate 10 and the first conductive structure 20. By opening a buffer hole 31 in the buffer structure 30 and providing a second conductive structure 40, both the electrical connection function and the stress concentration problem that may be caused by using a large-sized metal pillar to directly contact the glass opening are achieved.

[0082] In some embodiments, after forming the buffer hole 31 in step S140 and before forming the second conductive structure 40 in step S150, the method for preparing the encapsulation carrier 100 further includes the following steps: Step S151: A second seed layer 52 is formed on the bottom, wall and end face of the buffer hole 31; Step S152: A second conductive structure 40 is formed on the second seed layer 52 by electroplating process, and the second conductive structure 40 fills the buffer hole 31. Step S153: Remove the second seed layer 52 and the second conductive structure 40 from the end face of the buffer structure 30.

[0083] Specifically, the first seed layer 51 is used to enhance the adhesion between the first conductive structure 20 and the glass substrate 10, and to provide a conductive substrate for the electroplating filling process. The material of the first seed layer 51 can be a titanium / copper composite layer or a titanium-tungsten / copper composite layer, formed by a physical vapor deposition process. The titanium layer or titanium-tungsten layer serves as the adhesion layer in the first seed layer 51, and the copper layer serves as the electroplating seed layer in the first seed layer 51.

[0084] When electroplating the buffer holes 31, either direct current electroplating or pulse electroplating processes can be used. The current density for direct current electroplating can be controlled within the range of 1.0-2.0 A / dm², while pulse electroplating can further improve the deep plating capability and enhance the filling quality. The electroplating solution can use a conventional copper sulfate system, with the addition of appropriate amounts of brighteners and leveling agents to achieve a void-free filling effect.

[0085] The second seed layer 52 enhances the bonding force between the second conductive structure 40 and the buffer structure 30, and provides a conductive substrate for the electroplating process. The material of the second seed layer 52 can be the same as that of the first seed layer 51, for example, titanium / copper or titanium-tungsten / copper composite layers. Removing the second seed layer 52 and excess conductive material from the end face of the buffer structure 30 by chemical mechanical polishing or grinding can prevent short circuits of the second conductive structures 40 between different buffer holes 31 at the end face, ensuring electrical isolation, and obtaining a flat surface to facilitate the subsequent fabrication of the redistribution layer 60.

[0086] Following the above steps, redistribution layer 60, solder mask layer 70, and conductive bumps 80 can be further formed as needed. For example, forming redistribution layer 60 includes: fabricating one or more layers of metal traces through physical vapor deposition sputtering, resist coating, photolithography, development, electroplating, resist removal, and etching. The metal trace material can be copper, aluminum, nickel, gold, etc. When multi-layer wiring is required, a dielectric layer can be formed between each layer of metal traces. The dielectric layer can be formed by coating or lamination. The number of layers in redistribution layer 60 can be determined according to wiring density and electrical performance requirements. For medium-density interconnects, 1-2 layers of metal traces can be used; for high-density fan-out packages, 3-5 layers or even more layers of metal traces can be used. Each layer of metal traces is isolated by a dielectric layer and vertically interconnected through interlayer vias.

[0087] Forming a solder resist layer 70 and a conductive opening 71 includes: applying an electrically insulating solder resist material to the side of the redistribution layer 60 away from the glass substrate 10 to form a solder resist layer 70. Subsequently, the solder resist layer 70 is patterned to form a conductive opening 71, exposing a portion of the electrically conductive surface of the redistribution layer 60.

[0088] Forming conductive bumps 80 includes forming conductive bumps 80 within conductive openings 71. The material of conductive bumps 80 can be tin, tin-silver alloy, copper / tin-silver composite structure, copper / nickel / tin-silver composite structure, copper, etc.; the forming process can be electroplating, printing, or ball bonding, etc. The material selection for conductive bumps 80 can be determined based on the soldering process and reliability requirements. Tin-silver alloy is currently the mainstream choice for lead-free reflow soldering; for fine-pitch applications, a copper pillar with a tin cap structure can be used to control collapse; for applications requiring high mechanical strength, all-copper bumps combined with thermoforming bonding can be used.

[0089] Optionally, before forming the conductive bumps 80, the exposed electrically conductive surface can be surface-treated to form a surface treatment layer 61. The material of the surface treatment layer 61 can be an organic solderable corrosion inhibitor, nickel immersion gold, electroless nickel immersion palladium immersion gold, electroless nickel and electroless palladium immersion gold, chemical tin, etc.

[0090] Some embodiments of this application also provide a semiconductor package structure 1000, such as Figure 12 As shown, the semiconductor packaging structure 1000 includes a circuit board 200, a chip 300, and a packaging carrier 100 as described in any of the above embodiments. The packaging carrier 100 is located between the circuit board 200 and the chip 300 and realizes the electrical connection between the circuit board 200 and the chip 300.

[0091] The semiconductor package structure 1000 also includes a package insulating layer 400, which is at least partially located on the side of the chip 300 away from the package carrier 100. The package insulating layer 400 covers the chip 300 to provide electrical isolation and protect internal circuitry.

[0092] Specifically, the semiconductor package structure 1000 includes, from top to bottom, a chip 300, a package carrier 100 of any of the above embodiments, and a circuit board 200, wherein the circuit board 200 is a printed circuit board. The package carrier 100 is located between the circuit board 200 and the chip 300, and is electrically connected to the electrodes of the chip 300 through conductive bumps 80, and electrically interconnected with the circuit board 200 through solder balls or conductive pillars. The chip 300 may be a logic chip, a memory chip, a radio frequency chip, or a microelectromechanical system sensor, etc. The redistribution layer 60, the second conductive structure 40, and the first conductive structure 20 inside the package carrier 100 together constitute the signal transmission path from the chip 300 to the circuit board 200.

[0093] Specifically, at least one chip can be mounted on the packaging substrate 100, with the electrodes of the chip electrically connected to the conductive bumps 80 of the packaging substrate 100, and the chip interconnected with the external circuit through the redistribution layer 60, the second conductive structure 40 and the first conductive structure 20 inside the packaging substrate 100.

[0094] In the encapsulation substrate 100, a buffer structure is set at the opening of the glass through-hole. Multiple buffer holes are formed in a centrally symmetrical array within the buffer structure, and a second conductive structure is filled to create multi-point interconnected conductive channels. This solves the problem of stress concentration and crack initiation caused by thermal expansion mismatch at the opening of the glass through-hole in the glass substrate. This structure disperses the thermal stress originally concentrated at a single interface into multiple tiny conductive channels, reducing local stress peaks and suppressing crack propagation. Furthermore, by optimizing the filling height ratio of the first conductive structure, sufficient space is provided for the buffer structure while ensuring conductivity. The multi-point interconnection structure also increases the heat conduction path, mitigating the inherent defect of low thermal conductivity in glass.

[0095] The packaging substrate 100 provided in this application solves the problem of stress concentration and crack initiation caused by thermal expansion mismatch at the glass through-hole opening of the glass substrate by setting a buffer structure and opening multiple buffer holes distributed in a centrally symmetrical array in the buffer structure and filling them with a second conductive structure to form a multi-point interconnected conductive channel. This structure can be widely used in various high-performance packaging scenarios. The following describes its technical effects and applicability in conjunction with specific application fields.

[0096] With the continuous increase in the computing power and bandwidth requirements of AI chips, the signal transmission path between the chip and the substrate needs to be shortened as much as possible to reduce latency and power consumption. The packaging substrate of this application uses a glass substrate, whose low dielectric constant and low dielectric loss help maintain signal integrity in dense wiring; at the same time, the multi-point buffer structure of the glass via aperture reduces thermal stress caused by the high-frequency operation of the chip, avoiding failures caused by glass cracks. Flip-chip mounting the AI ​​chip onto the packaging substrate of this application enables high-density interconnection, supports the integration of high-bandwidth memory and computing cores, and meets the needs of high-computing-power scenarios.

[0097] The 6G communication frequency band is expected to expand to over 100GHz, placing extremely high demands on the dielectric loss and dimensional stability of the packaging substrate. The intrinsic low-loss characteristics of glass substrates make them a preferred material for millimeter-wave / terahertz packaging. The packaging substrate of this application suppresses microcracks at the glass via openings through a multi-point interconnect structure, avoiding scattering and reflection of high-frequency signals by the cracks and ensuring low-loss transmission of RF signals. Furthermore, waveguide structures can be embedded within the glass substrate, combined with 3D stacking technology, to achieve integrated antenna and RF front-end chip integration, meeting the application requirements of ultra-large-scale antenna arrays.

[0098] Microelectromechanical system (MEMS) sensors (such as inertial sensors, miniature mass spectrometers, and pressure sensors) are extremely sensitive to residual stress in their packaging, which can lead to zero-point drift or structural deformation. The packaging substrate in this application uses a glass substrate, whose coefficient of thermal expansion matches that of silicon, reducing packaging stress introduced by thermal mismatch. Simultaneously, the buffer structure at the glass via opening further absorbs transient stress generated by external mechanical shocks or thermal cycling, protecting the sensitive structures of the MEMS. Furthermore, the electrical insulation of glass provides electrical isolation for MEMS devices, reducing parasitic capacitance and improving the signal-to-noise ratio.

[0099] In high-performance computing scenarios, chips have high power density and present significant challenges in thermal management. The packaging substrate in this application utilizes a multi-point copper interconnect structure, increasing the total cross-sectional area of ​​the metal conductors and the heat conduction path. This helps to quickly dissipate the heat generated by the chip to the cooling system, mitigating the inherent drawback of low thermal conductivity in glass. Simultaneously, the low-warpage glass substrate supports the integration of larger-sized chips, improving the integration density of the computing system.

[0100] In summary, the packaging substrate of this application overcomes the defects of glass substrates, such as high brittleness and easy stress cracking, through the glass through-hole buffer structure, while retaining the electrical and physical advantages of glass substrates. It can be widely used in cutting-edge fields such as AI computing, 6G communication, and microelectromechanical system sensing.

[0101] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A packaging carrier board, characterized in that, include: A glass substrate, including a glass through-hole disposed throughout the thickness direction; The first conductive structure is located inside the glass through-hole; A buffer structure is located at at least one side opening within the glass through-hole; the buffer structure includes a buffer hole penetrating the buffer structure along the thickness direction. A second conductive structure is disposed within the buffer hole, and the second conductive structure is electrically connected to the first conductive structure.

2. The packaging carrier board according to claim 1, characterized in that, The buffer structure has multiple buffer holes, and multiple second conductive structures respectively fill the corresponding buffer holes.

3. The packaging carrier board according to claim 2, characterized in that, The buffer holes are arranged in a centrally symmetrical array, including a central hole at the center and a plurality of dispersed holes evenly distributed around the central hole in a circular pattern.

4. The packaging carrier board according to claim 3, characterized in that, The number of dispersion holes is 6 to 10; The ratio of the diameter of the central hole to the diameter of the dispersion hole is greater than or equal to 1.1 and less than or equal to 1.5; the edge spacing between adjacent dispersion holes is 0.05 to 0.15 times the diameter of the glass through hole.

5. The packaging carrier board according to claim 2, characterized in that, The buffer holes are arranged in multiple concentric circles, including an inner circle of buffer holes and at least one outer circle of buffer holes. The number of the inner circle of buffer holes is 1 to 3, and the number of the outermost outer circle of buffer holes is 4 to 10. The diameter of the buffer holes decreases along the direction away from the center of the glass through hole.

6. The packaging carrier board according to claim 1, characterized in that, Also includes: A first seed layer covers at least a portion of the wall of the glass via, and the first conductive structure is in contact with the first seed layer.

7. The packaging carrier board according to claim 1, characterized in that, Also includes: The second seed layer covers the bottom and wall of the buffer hole, and the second conductive structure is in contact with the second seed layer.

8. The packaging carrier board according to claim 1, characterized in that, The first conductive structure has the buffer structure and the second conductive structure disposed on opposite sides in the thickness direction.

9. The packaging carrier board according to claim 1, characterized in that, The ratio of the dimension of the first conductive structure in the thickness direction to the dimension of the glass through-hole in the thickness direction is 0.7 to 0.

9.

10. The packaging carrier board according to claim 1, characterized in that, The first conductive structure and the second conductive structure are made of different materials.

11. The packaging carrier board according to claim 1, characterized in that, Also includes: A redistribution layer is disposed on at least one side of the glass substrate, and the redistribution layer is electrically connected to the first conductive structure through the second conductive structure; A solder resist layer is disposed on the side of the redistribution layer away from the glass substrate, and the solder resist layer includes a plurality of conductive openings; Multiple conductive bumps are located within the conductive opening and are electrically connected to the redistribution layer.

12. A method for preparing a packaging carrier, characterized in that, include: A glass substrate is provided, and a glass through-hole extending along the thickness direction is formed in the glass substrate; A first conductive structure is provided inside the glass through-hole; A buffer structure is provided at at least one side of the opening within the glass through-hole; A buffer hole is formed within the buffer structure, extending through the buffer structure along the thickness direction. A second conductive structure is formed within the buffer hole, and the second conductive structure is electrically connected to the first conductive structure.

13. The method for preparing the encapsulation carrier according to claim 12, characterized in that, After forming the buffer hole and before forming the second conductive structure, the method further includes: A second seed layer is formed on the bottom, wall, and end face of the buffer hole; A second conductive structure is formed on the second seed layer using an electroplating process, and the second conductive structure fills the buffer hole; Remove the second seed layer and the second conductive structure from the end face of the buffer structure.

14. A semiconductor packaging structure, characterized in that, include: Circuit board; chip; as well as The packaging carrier board according to any one of claims 1 to 11, wherein the packaging carrier board is located between the circuit board and the chip, and realizes the electrical connection between the circuit board and the chip.

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