Chip packaging structure and chip packaging method

Abstract

The application discloses a chip packaging structure and a chip packaging method. The chip packaging structure comprises a first chip, a second chip, a redistribution layer, a receiving groove, a first metal bump and a filling layer. The size of the first chip is smaller than that of the second chip. The second chip comprises a functional surface and a second pad, and the second pad is arranged on the functional surface. The redistribution layer is arranged on the second chip and is electrically connected to the second pad. The first chip has a direct projection on the second chip, at least part of the direct projection overlaps with the receiving groove, the redistribution layer extends into the receiving groove, and the first chip and the redistribution layer are electrically connected. The first metal bump is arranged on the redistribution layer and surrounds the first chip. The inner metal bump is arranged adjacent to the outer edge of the first chip. The maximum clearance distance between at least two adjacent inner metal bumps is greater than the interval distance between other adjacent inner metal bumps. The filling layer is arranged in the receiving groove and fills the gap between the first chip and the second chip. The maximum clearance distance provides space for the preparation of the filling layer.

Description

Technical Field

[0001] This invention relates to the field of chip manufacturing and packaging, and in particular to a chip packaging structure and a chip packaging method. Background Technology

[0002] As semiconductor devices continue to evolve towards higher performance, higher integration, and miniaturization, chip stacking technology has become one of the key paths to achieving these goals. One typical technical solution involves integrating smaller chiplets onto larger chips using a flip-chip method, forming a heterogeneous integration or high-density interconnect packaging structure.

[0003] In existing dual-chip stacked packaging structures, combined with Figure 1 As shown, the small chip is flip-chip bonded to the middle area of ​​the non-functional side of the large chip, with its functional side facing down. Electrical connections and mechanical fixation are achieved between the small chip and corresponding pads on the large chip via solder balls. Multiple large metal protrusions are arranged around the small chip to facilitate electrical interconnection between the stacked package structure and external circuitry.

[0004] Because the small chip occupies part of the non-functional surface of the large chip, and the metal bumps need to be arranged as many as possible to increase the density of electrical contacts, the physical space between the edge of the small chip and the innermost metal bumps becomes very narrow. Since the small chip is mounted after the large chip, it is usually necessary to fill the connection between the small and large chips to fill the gap. The narrow space between the edge of the small chip and the inner metal bumps makes this filling process difficult.

[0005] When filling in confined spaces, it is easy for the filler material to contaminate the surface of the chip or metal protrusions. Since filler materials are often fluid colloids, as they flow into the gaps between chips driven by capillary action, they tend to fill the gaps between solder balls on the outer side of the chip, rather than being guided to the solder balls in the center area. This results in uneven colloid distribution, and voids can easily form in the central area at the bottom of the chip, affecting the reliability of the chip stack structure. Summary of the Invention

[0006] One of the objectives of this invention is to provide a chip packaging structure to solve the technical problems in the prior art where the narrow filling space of stacked chip structures leads to undesirable filling coverage, increased process difficulty, and reduced reliability of stacked packaging structures.

[0007] To achieve one of the above-mentioned objectives, one embodiment of the present invention provides a chip packaging structure, comprising:

[0008] First chip; The second chip includes a functional surface and a second pad, the second pad being disposed on the functional surface; the size of the first chip is smaller than that of the second chip; a redistribution layer is disposed on the second chip and electrically connected to the second pad; A receiving slot, wherein the first chip has an orthographic projection onto the second chip, at least a portion of the orthographic projection overlapping the receiving slot; the redistribution layer extends into the receiving slot, and the first chip and the redistribution layer are electrically connected; The first metal bump is disposed on the redistribution layer and located on the periphery of the first chip, including an inner metal bump. The inner metal bump is disposed adjacent to the outer periphery of the first chip, and there is a maximum clearance distance between at least two adjacent inner metal bumps. The maximum clearance distance is greater than the interval distance between other two adjacent inner metal bumps. A filling layer, located within the receiving slot, fills the gap between the first chip and the second chip.

[0009] As a further improvement of one embodiment of the present invention, the maximum avoidance distance is greater than the maximum size of a single first metal protrusion, or the maximum avoidance distance is between 200 and 500 micrometers.

[0010] As a further improvement of one embodiment of the present invention, the second chip includes a filling groove that is recessed from the non-functional surface and communicates with the receiving groove. The filling groove is located between two inner metal protrusions having the maximum clearance distance, and the filling layer extends from the filling groove into the receiving groove.

[0011] As a further improvement of one embodiment of the present invention, the filling groove and the receiving groove form a convex shape.

[0012] As a further improvement of one embodiment of the present invention, the first metal protrusion surrounds the common outer side of the receiving groove and the filling groove.

[0013] As a further improvement of one embodiment of the present invention, the receiving groove has a first bottom surface, the filling groove has a second bottom surface, the first bottom surface is connected to the second bottom surface, and the lowest point of the second bottom surface is higher than or level with the first bottom surface.

[0014] As a further improvement of one embodiment of the present invention, the redistribution layer is disposed on the non-functional surface of the second chip, the functional surface and the non-functional surface are disposed opposite to each other, and the receiving groove is formed by recessing from the non-functional surface.

[0015] As a further improvement of one embodiment of the present invention, the chip packaging structure includes a buffer layer, the buffer layer is disposed on the functional surface or non-functional surface of the second chip, the functional surface and the non-functional surface are disposed opposite to each other, the redistribution layer is disposed on the buffer layer, and at least a portion of the receiving groove is formed by recessing from the buffer layer.

[0016] As a further improvement of one embodiment of the present invention, the chip packaging structure includes a solder mask layer, the redistribution layer is located between the functional surface and the solder mask layer, or the redistribution layer is located between the non-functional surface and the solder mask layer, the functional surface and the non-functional surface are disposed opposite to each other, and at least a portion of the receiving groove is formed by recessing from the solder mask layer.

[0017] As a further improvement of one embodiment of the present invention, the first chip includes a first surface and a first pad, the first pad being disposed on the first surface; the chip packaging structure includes a plurality of second metal bumps, the second metal bumps connecting the first pad and the redistribution layer; the fill layer covers the second metal bumps and the first surface.

[0018] To achieve one of the above-mentioned objectives, one embodiment of the present invention provides a chip packaging method, comprising the steps of: A second chip package is provided, including a second chip, a redistribution layer, and a receiving slot; The second chip includes a functional surface and a second pad, the second pad being disposed on the functional surface; the redistribution layer is disposed on the second chip and electrically connected to the second pad, the redistribution layer extending into the receiving groove; A first metal protrusion is laid out and fabricated, the first metal protrusion connecting the redistribution layer, the first metal protrusion including an inner metal protrusion, the inner metal protrusion being adjacent to the outer periphery of the receiving groove; when laying out the first metal protrusion, at least two adjacent inner metal protrusions have a maximum clearance distance, and two adjacent inner metal protrusions with the maximum clearance distance form a clearance channel; the maximum clearance distance is greater than the interval distance between other two adjacent inner metal protrusions; A first chip is provided, which is disposed at a corresponding receiving slot and electrically connected to the redistribution layer; the size of the first chip is smaller than that of the second chip. A filling layer is formed by injecting a filling material into the receiving groove through the avoidance channel. The filling material is fluid and flows into the gap between the first chip and the second chip. The filling material is cured to obtain the filling layer.

[0019] As a further improvement of one embodiment of the present invention, the injection of filler material includes the steps of dripping filler material, each drop of filler material spreading out after dripping, and several drops of filler material connecting together after spreading out; each drop of filler material has a maximum spreading outer diameter after spreading out, and the maximum avoidance distance is greater than or equal to the maximum spreading outer diameter.

[0020] As a further improvement of one embodiment of the present invention, when arranging the first metal protrusion, at least one position of the first metal protrusion is left empty, or at least a distance of 200-500 micrometers is left empty, in order to form the maximum avoidance distance.

[0021] As a further improvement to one embodiment of the present invention, providing a second chip includes the following steps: A filling groove is fabricated, wherein the receiving groove and the filling groove are adjacent and connected; wherein the filling groove constitutes part of the avoidance channel, and the filling groove is located between two adjacent inner metal protrusions with the maximum avoidance distance.

[0022] As a further improvement of one embodiment of the present invention, providing a second chip package includes the steps of: forming the receiving groove and the filling groove on the non-functional surface of the second chip, wherein the non-functional surface and the functional surface are disposed opposite to each other; and forming the redistribution layer on the non-functional surface of the second chip.

[0023] As a further improvement of one embodiment of the present invention, the fabrication of the receiving groove and the filling groove on the non-functional surface includes: fabricating a recessed structure on the non-functional surface in a single step to obtain the receiving groove and the filling groove, wherein the first bottom surface of the receiving groove and the second bottom surface of the filling groove are flush; or, fabricating a recessed structure on the non-functional surface multiple times to obtain the receiving groove and the filling groove, wherein the lowest point of the filling groove is higher than or flush with the first bottom surface of the receiving groove.

[0024] As a further improvement of one embodiment of the present invention, providing a second chip package includes the steps of: fabricating a buffer layer, fabricating at least a portion of the receiving groove in the buffer layer, and fabricating a redistribution layer in the buffer layer; the buffer layer is disposed on the functional surface or non-functional surface of the second chip, and the functional surface and the non-functional surface are disposed opposite to each other.

[0025] As a further improvement of one embodiment of the present invention, a solder resist layer is fabricated, and at least a portion of the receiving groove is fabricated in the solder resist layer; the solder resist layer is disposed on the buffer layer, or the solder resist layer is disposed on the functional surface or non-functional surface of the second chip.

[0026] As a further improvement of one embodiment of the present invention, the fabrication of the filling layer includes: injecting a filling material into the filling groove, wherein the filling material flows into the receiving groove.

[0027] Compared with the prior art, the present invention provides a chip packaging structure in which the non-functional surface of the second chip is provided with a receiving groove, and the filling layer is located in the receiving groove. The receiving groove serves to limit the extension of the filling layer and prevent the filling layer from contaminating the first chip and the first metal protrusion. At least two adjacent inner metal protrusions have a maximum avoidance distance to form an avoidance channel, which expands the filling channel for the fabrication of the filling layer. The structural stability of the filling layer is improved, thereby improving the stability of the chip packaging structure. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a chip packaging structure in the prior art.

[0029] Figure 2 This is a schematic diagram of the chip packaging structure in the first embodiment of the present invention.

[0030] Figure 3 This is a schematic diagram of the chip packaging structure in the second embodiment of the present invention.

[0031] Figure 4 This is a schematic diagram of the chip packaging structure in the third embodiment of the present invention.

[0032] Figure 5 This is a top view of the chip packaging structure in the first embodiment of the present invention.

[0033] Figure 6 This is a side view of the fabrication of the receiving groove and filling groove in the first embodiment of the present invention.

[0034] Figure 7 This is a top view of the fabrication of the receiving groove and filling groove in the first embodiment of the present invention.

[0035] Figure 8-11 This is a schematic diagram illustrating the fabrication of the receiving groove and filling groove in several embodiments of the present invention.

[0036] Figure 12 This is a side view of a second chip package and a layout of a first metal protrusion provided in one embodiment of the present invention.

[0037] Figure 13 This is a top view of a second chip package and a layout of a first metal protrusion provided in one embodiment of the present invention.

[0038] Figure 14 This is a schematic diagram of a first chip provided in one embodiment of the present invention.

[0039] Figure 15 This is a schematic diagram of the fabrication of a filling layer according to one embodiment of the present invention.

[0040] Figure 16 This is a schematic diagram of the first chip and the receiving slot in several embodiments of the present invention.

[0041] Figure 17 This is a schematic diagram of the solder resist layer in several embodiments of the present invention.

[0042] Figure Description: Chip package structure 100, first chip 10, first surface 11, first pad 12, second chip 20, functional surface 201, non-functional surface 202, second pad 203, functional area 29, receiving groove 21, first bottom surface 211, filling groove 22, second bottom surface 221, redistribution layer 23, buffer layer 24, solder mask layer 25, insulating layer 26, conductive interconnect structure 27, first metal bump 30, inner metal bump 31, special metal bump 311, filling layer 40, cover plate 60, maximum clearance distance L. Detailed Implementation

[0043] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of the present invention.

[0044] It should be noted that the term "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," "third," "fourth," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0045] The terms “connection,” “connected to,” or any other variations are intended to encompass various relative positions where a connection exists, including both direct and indirect connections. A direct connection can be formed through a pneumatic conduit, while an indirect connection can be formed through devices such as valves or sensors, through pneumatic components such as brake control units, or through any other medium such as air.

[0046] Please see Figure 2 This is a schematic diagram of a chip packaging structure 100 provided in an embodiment of the present invention.

[0047] The chip packaging structure 100 includes a first chip 10 and a second chip 20. The size of the first chip 10 is smaller than that of the second chip 20, thereby realizing the stacking and packaging of chips of different sizes, effectively improving the space utilization and functional integration of the chip packaging structure.

[0048] Specifically, the first chip 10 and the second chip 20 can be semiconductor devices with different or complementary functions. The first chip 10 can be a logic operation chip, and the second chip 20 can be an image sensing chip. After the two chips are stacked and packaged, the signal transmission path between them is shortened, and the signal transmission delay and power consumption are reduced.

[0049] The second chip 20 includes a functional surface 201 and a second pad 203, the second pad 203 being disposed on the functional surface 201; the second pad 203 is used for signal transmission of the second chip 20. The chip package structure 100 includes a redistribution layer 23, the redistribution layer 23 being disposed on the second chip 20 and electrically connected to the second pad 203.

[0050] The chip package structure 100 includes a receiving groove 21, a first chip 10 having an orthographic projection on a second chip 20, at least partially overlapping the receiving groove 21; a redistribution layer 23 extends into the receiving groove 21, the first chip 10 and the redistribution layer 23 are electrically connected, thereby achieving an electrical connection with a second pad 203, in other words, the first chip 10 and the second chip 20 are electrically connected, and the first chip 10 is stacked on the second chip 20 at the location corresponding to the receiving groove 21.

[0051] Multiple first metal bumps 30 are disposed on the redistribution layer 23 and surround the first chip 10. The second chip 20 is electrically connected to the external circuit through the first metal bumps 30.

[0052] The first metal bump 30 includes an inner metal bump 31, which is disposed adjacent to the outer periphery of the first chip 10; at least two adjacent inner metal bumps 31 have a maximum clearance distance L, which is greater than the spacing between other two adjacent inner metal bumps 31; at least two adjacent inner metal bumps 31 have a maximum clearance distance L, thereby forming a clearance channel for fabricating the filling layer 40; A filler layer 40, located within a receiving groove 21, fills the gap between the first chip 10 and the second chip 20. Firstly, the filler layer 40 is situated within the receiving groove 21, which functions as a dam to prevent the filler layer 40 from extending outwards towards the first metal protrusion 30, thus reducing contamination of the first metal protrusion 30. Specifically, the filler layer 40 is typically manufactured using a dispensing process; the adhesive has fluidity and, after curing, forms the filler layer 40.

[0053] When the colloid begins to fall, it can enter the containment tank 21 and is thus restricted by the dam from the containment tank 21, preventing it from spreading away from the first chip 10 and thus preventing it from contaminating the inner metal protrusion 31.

[0054] Secondly, the avoidance channel expands the filling channel of the filling layer 40, thereby facilitating the fabrication process of the filling layer 40. With sufficient filling channels, the contamination of the back of the chip by the colloid is also improved. With sufficient filling channels, it is beneficial for the filling layer 40 to be spread evenly, reducing the void structure inside the filling layer 40, increasing the structural stability of the filling layer 40, and thus increasing the stability of the chip packaging structure 100.

[0055] Specifically, in practical applications, the filler layer 40 is manufactured using a dispensing process. During dispensing, several drops of adhesive can enter the receiving tank 21 through the clearance channel, and after curing within the receiving tank 21, the filler layer 40 is formed. The maximum clearance distance L in the chip packaging structure 100 is visually represented by an increased distance between at least two first metal protrusions 30. In actual manufacturing, the maximum clearance distance L is determined based on the maximum spread outer diameter of each drop of adhesive.

[0056] The colloid is fluid and will naturally spread out after dripping onto two adjacent first metal protrusions 30, forming the maximum spreading outer diameter. The maximum avoidance distance L of this application needs to be greater than or equal to the maximum spreading outer diameter to avoid contaminating the two adjacent first metal protrusions 30 after each drop of colloid spreads out.

[0057] In the existing technology, a portion of the area of ​​the second chip 20 is occupied by the first chip 10, reducing the space for the first metal bump 30 and posing a challenge to the size of the first metal bump 30. If the size of the first metal bump 30 is too large, there is insufficient layout space; if the size of the first metal bump 30 is too small, the height difference between the first metal bump 30 and the first chip 10 is too small, making the first metal bump 30 prone to cold solder joints after the subsequent chip package structure is soldered onto an external circuit board. To ensure the height difference between the first metal bump 30 and the first chip 10 and to provide more layout space for the first metal bump 30, the thickness of the first chip 10 must be reduced to the limit, which also presents a significant challenge for the first chip 10.

[0058] The first metal protrusion 30 is higher than the surface of the first chip 10 and away from the filler layer 40. (Combined) Figure 2 As shown, in this application, the first chip 10 is stacked on top of the second chip 20 at the receiving slot 21. Due to the arrangement of the receiving slot 21, the height of the first chip 10 is lowered overall, thereby increasing the height difference between the first metal protrusion 30 and the first chip 10. Therefore, depending on the actual situation, the thickness of the first chip 10 can be increased to increase its structural strength, or a smaller first metal protrusion 30 can be selected to provide more layout space.

[0059] Combination Figure 3As shown, when the first metal protrusions 30 are arranged, there is a gap between each pair of adjacent first metal protrusions 30. A small gap indicates that the two first metal protrusions 30 are arranged closely, while a large gap indicates that the two first metal protrusions 30 are arranged loosely. Typically, the multiple first metal protrusions 30 are arranged in a matrix. In order to reserve more layout space for the first metal protrusions 30, the gaps between the multiple first metal protrusions 30 along the length and width directions are relatively small.

[0060] If adhesive is applied directly between two adjacent inner metal protrusions 31, the adhesive will contaminate the inner metal protrusions 31. In this application, the spacing between the two inner metal protrusions 31 is relatively large, that is, the maximum avoidance distance L is significantly greater than the spacing between other first metal protrusions 30, and is greater than or equal to the maximum spreading outer diameter of the adhesive droplet, so as to avoid contamination of the first metal protrusions 30 when making the filling layer 40.

[0061] In one specific embodiment, the maximum avoidance distance L is greater than the maximum size of a single first metal protrusion 30. Specifically, in combination with Figure 5 As shown, the inner metal protrusion 31 includes two special metal protrusions 311, with a maximum clearance distance L between them. In a specific actual structure, the space between the two special metal protrusions 311 is such that at least one inner metal protrusion 31 is left empty, thereby increasing the spacing between the two special metal protrusions 311, which is significantly greater than the spacing between other inner metal protrusions 31.

[0062] In one specific embodiment, two special metal protrusions 311 are arranged along the width direction of the chip package structure 100. The inner metal protrusions 31 have a width dimension along the width direction. When the inner metal protrusions 31 are uniformly arranged along the width direction, adjacent inner metal protrusions 31 have an equal width spacing distance. It can be seen that the maximum clearance distance L can be the width dimension of one inner metal protrusion 31, or it can be the sum of the width dimension of one inner metal protrusion 31 and the width spacing distance of two segments. When the inner metal protrusion 30 is a solder ball, the width dimension of the inner metal protrusion 30 is the diameter.

[0063] In one specific embodiment, the maximum clearance distance L can be between 200 and 500 micrometers, which is intuitively reflected from a dimensional perspective. As mentioned above, in actual manufacturing processes, the maximum clearance distance L is not intentionally designed to leave exactly an inner metal protrusion 31, but is determined by the maximum spread outer diameter of the colloid. Therefore, the maximum clearance distance L has a relatively large degree of freedom in terms of structure.

[0064] Combination Figure 1As shown, in the prior art, when dispensing adhesive between the small chip 10' and the inner metal protrusion 31' for filling, the nozzle dispenses adhesive between the small chip and the inner metal protrusion, and between two adjacent inner metal protrusions 31'. The dispensing space is narrow, and the adhesive easily touches the back of the small chip or the inner metal protrusion. When the adhesive enters between the small chip 10' and the large chip 20', due to the siphon effect, the adhesive 40' easily spreads to the side of the inner metal protrusion away from the small chip. Dispensing adhesive to fill the connection gap between the small chip and the large chip, covering the back of the small chip 10' and the inner metal protrusion 31', is undesirable. Furthermore, due to the slow flow of the adhesive during this process, it cannot flow smoothly, and there is a high probability of uneven adhesive filling and void structures in areas of the first chip far from the filling side, resulting in unreliable filling between the small chip 10' and the large chip 20'.

[0065] When the maximum clearance distance L is achieved between the two special metal protrusions 311, the filling channel is expanded in the horizontal direction. Specifically, the first side of the receiving groove 21 is the filling side in the manufacturing process, and the two special metal protrusions 311 correspond to the first side of the receiving groove 21. The length space between the two special metal protrusions 311 on the first side edge of the receiving groove 21 can be used for adhesive filling, reducing the probability of contact with the back surface of the first chip 10 and the inner metal protrusions 31.

[0066] In one specific embodiment, the maximum clearance distance L between the two special metal protrusions 311 is less than the overall length of the first side of the receiving groove 21, and the length space of the first side edge of the receiving groove 21 corresponding to the maximum clearance distance can be used for adhesive filling.

[0067] After the adhesive space is expanded, the adhesive can spread more quickly between the first and second chips. The later-dropped adhesive can squeeze the earlier-dropped adhesive more quickly, guiding the adhesive to enter the space between the first and second chips more smoothly, thus achieving a more uniform and fuller filling.

[0068] The second chip 20 includes a filling slot 22, which is adjacent to and connected to a receiving slot 21. The filling slot 22 forms a partial clearance channel and is located between two inner metal protrusions 31 with a maximum clearance distance L. The filling layer 40 extends from the filling slot 22 into the receiving slot 21. Figure 5-7 As shown, a filling groove 22 is opened between the two inner metal protrusions 31 with the maximum clearance distance L. The filling groove 22 also has the function of a dam to prevent the filling layer 40 from extending outward toward the first metal protrusion 30 and reduce the contamination of the first metal protrusion 30.

[0069] When the filling groove 22 is opened between the two special metal protrusions 311, it is equivalent to expanding the glue application space along the thickness direction of the chip package structure 100. The area above the filling groove 22 can be used for glue application. The glue enters the filling groove 22 and flows from the filling groove 22 into the receiving groove 21.

[0070] The filling groove 22 and the receiving groove 21 form a convex shape, combined with Figure 7 As shown, the filling groove 22 is located on the first side of the receiving groove 21, which is the filling side in the manufacturing process.

[0071] The first metal protrusion 30 surrounds the common outer side of the receiving groove 21 and the filling groove 22. Figure 7 As shown, after multiple first metal protrusions 30 are arranged and combined, at least two inner metal protrusions 31 near the receiving groove 21 are spaced apart by a maximum clearance distance L to form a filling groove 22. In one specific embodiment, a first metal protrusion 30 or a gap of 200-500 micrometers is left between two special metal protrusions 311 to make the filling groove 22. Then, multiple first metal protrusions 30 are arranged around the filling groove 22 to prevent the filling layer 40 from undesirably covering the first metal protrusions 30.

[0072] In one specific embodiment, the maximum cross-sectional area of ​​the filling groove 22 is smaller than the minimum cross-sectional area of ​​the receiving groove 21, and the maximum cross-sectional area of ​​the filling groove 22 is larger than the maximum cross-sectional area of ​​a single first metal protrusion 30. The maximum cross-sectional area of ​​the filling groove 22 does not need to be particularly large. On the one hand, the actual dispensing channel does not require a large space. On the other hand, a larger filling groove 22 means that more space needs to be left aside, increasing the difficulty of arranging and designing the first metal protrusions 30.

[0073] The receiving groove 21 has a first bottom surface 211, and the filling groove 22 has a second bottom surface 221. The first bottom surface 211 is connected to the second bottom surface 221. The lowest point of the second bottom surface 221 is higher than or level with the first bottom surface 211, so that the adhesive can flow from the filling groove 22 into the receiving groove 21 when dispensing. The first bottom surface 211 of the receiving groove 21 is a plane.

[0074] The redistribution layer 23 is disposed on the non-functional surface 202 of the second chip 20. The functional surface 201 and the non-functional surface 202 are disposed opposite to each other. The receiving groove 21 is recessed from the non-functional surface 202. The receiving groove 21 is used to correspondingly dispose of the first chip 10. When the receiving groove 21 is recessed from the non-functional surface 202, it can be seen that the first chip 10 is disposed on the non-functional surface 202 of the second chip 20, thereby realizing the vertical stacking of the second chip 20.

[0075] When the chip package structure 100 is applied to an image sensor chip or other special function chip, the functional surface 201 has an optical functional area or needs to be set with other functions, so the functional surface 201 cannot be etched to form the receiving groove 21 and / or filling groove 22. The receiving groove 21 is formed by recessing from the non-functional surface 202, which is suitable for application scenarios where the functional surface 201 cannot be set with the receiving groove and / or filling groove 22.

[0076] In this application, when the receiving groove 21 is formed by recessing from the non-functional surface 202, the receiving groove 21 and the filling groove 22 can be formed in various ways. In the first embodiment, the second bottom surface 221 is a plane, and the first bottom surface 211 and the second bottom surface 221 are coplanar. (Refer to...) Figure 6 , 8 a. At this point, the filling groove 22 and the receiving groove 21 can be obtained through a single etching, thus optimizing the manufacturing process.

[0077] In the second embodiment, refer to Figure 8 b. The second bottom surface 221 is a plane, and the second bottom surface 221 is higher than the first bottom surface 211. The filling groove 22 and the receiving groove 21 can be formed by multiple etching processes. By making a clear spatial separation between the filling groove 22 and the receiving groove 21, more filling material can enter the receiving groove 21 instead of being solidified in the filling groove 22. Theoretically, the filling groove 22 does not need filling material. Using too much filling material to fill the filling groove 22 leads to cost waste.

[0078] In the third and fourth embodiments, refer to Figure 8 c, 8d, the second bottom surface 221 is an inclined bottom surface, which is conducive to the colloid sliding into the first bottom surface 211 of the receiving groove 21. The inclined bottom surface is also divided into a single-segment inclined bottom surface or a multi-segment inclined bottom surface, which can be formed by multiple etchings or optionally by grayscale photolithography.

[0079] Combination Figure 2 As shown, after the receiving groove 21 and the filling groove 22 are formed by etching on the non-functional surface 202, the insulating layer 26, the buffer layer 24, the redistribution layer 23 and the solder mask layer 25 are formed in sequence, wherein the solder mask layer 25 can be selectively set.

[0080] The chip package structure 100 includes a buffer layer 24, which is disposed on the functional surface 201 or the non-functional surface 202 of the second chip 20. The functional surface 201 and the non-functional surface 202 are disposed opposite to each other. A redistribution layer 23 is disposed on the buffer layer 24. At least a portion of the receiving groove 21 is recessed from the buffer layer 24, which can be applied to application scenarios that require the receiving groove 21 and the first chip 10 to be disposed on the functional surface 201 of the second chip 20.

[0081] Combination Figure 3-4As shown, the receiving groove 21 is no longer formed by recessing from the non-functional surface 202 of the second chip 20, but is formed during the subsequent fabrication of the buffer layer 24. It is understood that this is mainly because the functional surface 201 of the second chip 20 cannot be etched to form a groove. When the receiving groove 21 can be formed through the buffer layer 24, the arrangement of the receiving groove 21 and the first chip 10 is not limited to the functional surface 201 or the non-functional surface 202 of the second chip 20.

[0082] in Figure 3 In the second embodiment of the corresponding chip packaging structure 100, the receiving groove 21 is located on the non-functional surface 202 side. The receiving groove 21 is formed by recesses of the buffer layer 24 and the solder mask layer 25, and the filling groove 22 is also formed by recesses of the buffer layer 24 and the solder mask layer 25; while Figure 4 In the third embodiment of the corresponding chip packaging structure 100, the receiving groove 21 is located on the functional surface 201 side, and the receiving groove 21 is formed by the recess of the buffer layer 24 and the solder mask layer 25.

[0083] Combination Figure 3-4 As shown in Figure 9, the chip packaging structure 100 includes an insulating layer 26, which is laid on the functional surface 201 or the non-functional surface 202. A buffer layer 24 is fabricated on the insulating layer 26. After a receiving groove 21 is fabricated on the buffer layer 24, a redistribution layer 23 is fabricated.

[0084] The chip package structure 100 includes a solder mask layer 25, a redistribution layer 23 located between the functional surface 201 and the solder mask layer 25, or the redistribution layer 23 located between the non-functional surface 202 and the solder mask layer 25. Specifically, the redistribution layer 23 is located between the buffer layer 24 and the solder mask layer 25.

[0085] Combination Figure 9 As shown in Figure a, the filling groove 22 is formed by a buffer layer 24 and a solder resist layer 25, and the second bottom surface 221 of the filling groove 22 is flush with the first bottom surface 211 of the receiving groove 21. Figure 9 As shown in Figure b, the filling groove 22 is formed by a buffer layer 24 and a solder resist layer 25. The second bottom surface 221 of the filling groove 22 is an inclined surface, and the lowest point of the second bottom surface 221 connects to the first bottom surface 211 of the receiving groove 21. Figure 9 As shown in c, the filling groove 22 is formed only in the solder mask layer 25, and the lowest point of the filling groove 22 is located in the solder mask layer 25. It is understood that this does not affect the flow of the filling material from the filling groove 22 into the receiving groove 21.

[0086] At least part of the receiving groove 21 is formed by the recess of the solder mask layer 25, combined with Figure 10As shown, in other embodiments, although a buffer layer 24 is provided, to facilitate the installation of the redistribution layer 23, the receiving groove 21 may not be provided in the buffer layer 24. Considering that providing the receiving groove 21 in the buffer layer 24 would increase the manufacturing difficulty of the redistribution layer 23 to some extent, the receiving groove 21 is only provided through the height of the solder mask layer 25. In this way, the buffer layer 24 is flat, and the redistribution layer 23 is also flat on the buffer layer 24.

[0087] Combination Figure 10 As shown in a and 10b, the filling groove 22 is formed by the solder resist layer 25, and the second bottom surface 221 of the filling groove 22 can be etched as a flat surface or an inclined surface.

[0088] At least part of the receiving groove 21 is formed by the recess of the solder mask layer 25, combined with Figure 11 As shown, in other embodiments, a redistribution layer 23 is directly formed on the insulating layer 26, a solder resist layer 25 is formed on the redistribution layer 23, and then a receiving groove 21 and a filling groove 22 are formed. Combined with... Figure 11 As shown in a and 11b, the second bottom surface 221 of the filling groove 22 can be etched as a flat surface or an inclined surface.

[0089] The above describes various embodiments of the receiving slot 21 and the filling slot 22 in this application. It is understood that different positions and arrangements of the receiving slot 21 and the filling slot 22 do not affect the setting of the maximum avoidance distance L. Combined with... Figure 2-4 As shown, regardless of how the receiving slot 21 is set, the space around the receiving slot 21 should be left with a maximum clearance distance L for filling with glue. The filling slot 22 is located at the location corresponding to the maximum clearance distance L and is connected to the receiving slot 21.

[0090] The first chip 10 includes a first surface 11 and a first pad 12, with the first pad 12 disposed on the first surface 11; the chip package structure 100 includes a plurality of second metal bumps 50, the second metal bumps 50 connecting the first pad 12 and the redistribution layer 23; the fill layer 40 covers the second metal bumps 50 and the first surface 11, and the function of the fill layer 40 is to ensure a stable connection between the second metal bumps 50, the redistribution layer 23 and the first pad 12.

[0091] In the first embodiment of the chip packaging structure 100, combined with Figure 12-13 As shown, the redistribution layer 23 is disposed on the non-functional surface of the second chip 20. The redistribution layer 23 extends into the receiving groove 21. The redistribution layer 23 includes a third pad 231 located in the receiving groove 21. The third pad 231 is located on the first bottom surface 211 and is used for electrical connection with the second metal bump 50. The second metal bump 50 connects the first pad 12 and the third pad 231.

[0092] The receiving slot 21 has a first side surface 212 and a first bottom surface 211. The first side surface 212 connects the non-functional surface 202 and the first bottom surface 211. The redistribution layer 23 extends to the first bottom surface 211. The included angle α between the first side surface 212 and the first bottom surface 211 is between 100° and 120°. Figure 6 As shown, the non-functional surface 202 of the second chip 20 is thinned to form a receiving groove 21, but the redistribution layer 23 has not yet been fabricated.

[0093] When making the containment tank 21, the first side 212 should not be too steep, otherwise the stress on the redistribution layer 23 at the turning corner will be too great, increasing the probability of reliability failure; the first side 212 should not be too gentle, otherwise the slope area occupied by the first side 212 will be too large, and its ability to act as a dam to block the colloid will be reduced.

[0094] Combination Figure 14-15 As shown, the first pad 12 is exposed to lead out the electrical signal of the first chip 10. The first pad 12 faces the receiving groove 21 and is electrically connected to the third pad 231 through the second metal protrusion 50. The first chip 10 and the second chip 20 are electrically connected.

[0095] The first chip 10 has an orthographic projection onto the second chip 20, at least partially overlapping the receiving groove 21, including complete overlap, meaning the size of the first chip 10 is smaller than the maximum cross-sectional area of ​​the receiving groove 21. Figure 15 The first chip 10 is disposed at the receiving groove 21, meaning that along the thickness direction of the chip package structure, the first chip 10 is located directly above the receiving groove 21, and only the second metal protrusion 50 is located inside the receiving groove 21. The filling layer 40 wraps the first pad 12 and the second metal protrusion 50. Due to capillary action, the filling layer 40 also extends a short distance beyond the second chip 20, covering part of the side of the first chip 10.

[0096] Combination Figure 16 As shown in Figure a, the first chip 10 is disposed in the receiving groove 21. This can also mean that, along the thickness direction of the chip package structure, the second metal protrusion 50 is located in the receiving groove 21, and at least part of the first chip 10 is also located in the receiving groove 21 or the entire first chip 10 is located in the receiving groove 21. In this case, the filling layer 40 is completely located in the receiving groove 21 and will not exceed the second chip 20.

[0097] The first chip 10 has an orthographic projection onto the second chip 20, at least partially overlapping with the receiving groove 21, including a partial orthographic projection that completely coincides with the receiving groove 21, which means that the size of the first chip 10 is larger than the maximum cross-sectional area of ​​the receiving groove 21. Figure 16As shown in b, the first chip 10 cannot be accommodated in the receiving groove 21. The first chip 10 is higher than the receiving groove 21, and the second metal protrusion 50 and the filling layer 40 are both higher than the receiving groove 21.

[0098] The first metal protrusion 30 is higher than the surface of the first chip 10 away from the filling layer 40, which facilitates the connection between the first metal protrusion 30 and the external circuit.

[0099] The second chip 20 includes a functional region 29, a second pad 203, and a conductive interconnect structure 27. The functional region 29 and the second pad 203 are disposed on the functional surface 201. The second pad 203 is connected to the redistribution layer 23 through the conductive interconnect structure 27. Figure 12 As shown, the second pad 203 is located outside the functional area 29, and the conductive interconnect structure 27 is a through-silicon via (TSV) structure. The conductive interconnect structure 27 connects the second pad 203 and the redistribution layer 23 along the thickness direction of the chip package structure. In the first embodiment of the chip package structure 100, the non-functional surface 202 of the second chip 20 is sequentially provided with an insulating layer 26, a buffer layer 24, a redistribution layer 23, and a solder resist layer 25. The insulating layer 26 and the buffer layer 24 are fabricated first to isolate the second chip 20 and the redistribution layer 23, and the buffer layer 24 can provide a better substrate for the redistribution layer 23.

[0100] Because the conductive interconnect structure 27 is a through-silicon via (TSV) structure, the actual fabrication process requires a certain silicon thickness for TSV structures. TSV structures are suitable for structures with relatively thin silicon. In one embodiment, the overall silicon thickness of the second chip 20 meets the requirements of the TSV process, allowing for direct hole opening and the fabrication of a conductive layer within the hole.

[0101] In one embodiment, the silicon thickness of the second chip 20 cannot meet the requirements of the through-silicon via (TSV) process. Therefore, the area of ​​the second chip 20 where the TSV structure needs to be formed is first thinned by cutting, in conjunction with the present application. Figure 12 As shown, the thickness of the second chip 20 is reduced at the position of the conductive interconnect structure 27, thereby forming a tilted surface structure on the non-functional surface 202, and the subsequently fabricated insulating layer 26, redistribution layer 23, and solder mask layer 25 are all formed with tilted slope structures.

[0102] Combination Figure 17 a. The first metal protrusion 30 is typically a solder ball structure, which has high fluidity at high temperatures. Therefore, a solder resist layer 25 needs to be laid on the redistribution layer 23. The solder resist layer 25 located around the receiving tank 21 can also play a role in preventing the flow of the colloid. Figure 17 b. Alternatively, a solder resist layer 25 may be laid on the first bottom surface 211 of the receiving tank 21 as needed; or, combined with Figure 17 c. Solder mask 25 is applied only around the first bottom surface 211 relative to the third pad 231. In other embodiments, when the first metal protrusion 30 is a gold ball, solder mask 25 may not be applied.

[0103] Combination Figure 2 As shown, the chip package structure 100 also includes a cover plate 60, which is bonded to the second chip 20, with the functional area 29 facing the cover plate 60. The solder resist layer 25 is an insulating material. The functional chip body 200 is thinned at the corresponding conductive interconnect structure 27, and the solder resist layer 25 extends at an angle, further wrapping around the side of the second chip 20 and the surface of the cover plate 60 to enhance the sealing performance of the chip package structure 100.

[0104] This application also includes a chip packaging method, comprising the steps of: S1: Provide a second chip package, including a second chip 20, a redistribution layer 23, and a receiving slot 21; The second chip 20 includes a functional surface 201 and a second pad 203, the second pad 203 being disposed on the functional surface 201; a redistribution layer 23 is disposed on the second chip 20 and electrically connected to the second pad 203, the redistribution layer 23 extending into the receiving groove 21. S2: Lay out and fabricate a first metal protrusion 30, the first metal protrusion 30 is connected to the redistribution layer 23, the first metal protrusion 30 includes an inner metal protrusion 31, the inner metal protrusion 31 and the outer periphery of the receiving groove 21 are adjacent to each other; when laying out the inner metal protrusion 31, at least two adjacent inner metal protrusions 31 have a maximum clearance distance L, and two adjacent inner metal protrusions 31 with a maximum clearance distance L form a clearance channel; the maximum clearance distance L is greater than the interval distance between other two adjacent inner metal protrusions 31; S3: Provide a first chip 10, which is disposed in the corresponding receiving slot 21 and electrically connected to the redistribution layer 23; the size of the first chip 10 is smaller than that of the second chip 20. S4: Create a filling layer 40. Inject filling material 400 into the receiving groove 21 through the self-avoiding channel. The filling material has fluidity and flows into the gap between the first chip and the second chip. After the filling material is solidified, the filling layer 40 is obtained.

[0105] The first chip 10 is located at the corresponding receiving slot 21, and its overall height is lowered, thereby increasing the height difference between the first metal protrusion 30 and the first chip 10. Therefore, depending on the actual situation, the thickness of the first chip 10 can be increased to increase its structural strength, or a smaller first metal protrusion 30 can be selected to provide more layout space.

[0106] The filler material 400 is usually a colloid. Under the premise that the first metal protrusion 30 can have more layout space, the maximum avoidance distance L between two adjacent inner metal protrusions 31 is reserved to form an avoidance channel, which is used to expand the glue dispensing space, reduce the difficulty of dispensing, and make it less likely to contaminate the first chip 10 and the first metal protrusion 30; it is beneficial to the structural stability of the filler layer 40.

[0107] The injection of filler material 400 includes the following steps: dripping filler material 400, each drop spreading out after being dripped, and several drops of filler material connecting together after spreading; each drop of filler material has a maximum spreading outer diameter after spreading, and the maximum clearance distance L is greater than or equal to the maximum spreading outer diameter. Filler material 400 is a colloid with fluidity, and each drop of filler material 400 will naturally flow and spread out after being dripped, forming the maximum spreading outer diameter.

[0108] When laying out the first metal protrusion 30, leave at least one position of the first metal protrusion 30 unused, or at least leave a distance of 200-500 micrometers, to form the maximum clearance distance L. In practice, the maximum spreading outer diameter of each drop of filler material 400 should be pre-calculated. The maximum clearance distance L should be confirmed based on the calculated maximum spreading outer diameter before starting the dispensing process.

[0109] Structurally, in one specific embodiment, a space is left empty for an inner metal protrusion 31. This creates a maximum clearance distance L between two special metal protrusions 311, which is significantly greater than the spacing between other inner metal protrusions 31. A clearance channel is formed between the two special metal protrusions 311. Alternatively, the spacing between the two special metal protrusions 311 can be 200-500 micrometers.

[0110] It is understandable that the second chip package has undergone packaging processes on the second chip 20, such as setting a redistribution layer 23, but the first metal bump 30 has not yet been fabricated on the second chip 20.

[0111] Providing a second chip package includes step S11: combining Figure 6 As shown, a second chip 20 is provided. The second chip 20 is an image sensor chip. The functional surface 201 of the second chip 20 has a functional area 29 and a second pad 203. The functional surface 201 is used for bonding with the cover plate 60.

[0112] Combination Figure 12As shown, in the first embodiment of the chip packaging structure 100, the non-functional surface 202 of the second chip 20 is fabricated with a receiving groove 21, an insulating layer 26, a buffer layer 24, a redistribution layer 23, and a solder mask layer 25. The insulating layer 26, the buffer layer 24, and the redistribution layer 23 extend into the receiving groove 21, and the solder mask layer 25 may be partially laid in the receiving groove 21, fully laid, or not laid, depending on the requirements.

[0113] Providing the second chip package includes step S111: A filling groove 22 is made, and the receiving groove 21 and the filling groove 22 are adjacent and connected; an avoidance channel connects the filling groove 22, and the filling groove 22 is located between two adjacent inner metal protrusions 31 with the maximum avoidance distance.

[0114] Combination Figure 12-13 As shown in Figure 15, the filling groove 22 is located between two special metal protrusions 311. The filling groove 22 is located below the clearance channel. The second bottom surface 221 of the filling groove 22 expands the adhesive space along the thickness direction of the second chip 20. It can catch the falling adhesive and prevent it from spreading in an undesirable direction.

[0115] Providing a second chip package includes the steps of: fabricating a receiving groove 21 and a filling groove 22 on the non-functional surface 202 of the second chip, with the non-functional surface 202 and the functional surface 201 disposed opposite to each other; and fabricating a redistribution layer 23 on the non-functional surface 202 of the second chip. In a first embodiment, the receiving groove 21 is formed by etching a recess on the non-functional surface 202.

[0116] When fabricating the receiving slot 21, the angle of the turning corner of the receiving slot 21 needs to be considered to ensure effective electrical connection of the redistribution layer 23. The redistribution layer 23 includes a third pad 231 located on the first bottom surface 211, which is used for electrical connection with the first pad 12 of the first chip 10.

[0117] The fabrication of the receiving groove 21 and the filling groove 22 on the non-functional surface 202 includes: fabricating a recessed structure on the non-functional surface 202 in a single step to obtain the receiving groove 21 and the filling groove 22, wherein the first bottom surface 211 of the receiving groove 21 and the second bottom surface 221 of the filling groove 22 are flush; or, fabricating a recessed structure on the non-functional surface 202 multiple times to obtain the receiving groove 21 and the filling groove 22, wherein the lowest point of the filling groove 22 is higher than or flush with the first bottom surface 211 of the receiving groove 21.

[0118] Combination Figure 8 As shown in Figure a, when the first bottom surface 211 and the second bottom surface 221 are coplanar, a single etching process can obtain the receiving groove 21 and the filling groove 22, combined with... Figure 8 As shown in b, when the second bottom surface 221 is a plane but higher than the first bottom surface 211, the receiving groove 21 and the filling groove 22 can be obtained by etching both sides; combined with Figure 8As shown in c and 8d, when the second bottom surface 221 is an inclined surface, the receiving groove 21 can be obtained by a single etching, and the filling groove 22 can be obtained by multiple etchings or grayscale photolithography.

[0119] The above describes the receiving groove 21 and the filling groove 22 located on the non-functional surface 202 of the second chip 20. After the receiving groove 21 and the filling groove 22 are formed by recessing from the non-functional surface 202, an insulating layer 26, a buffer layer 24, a redistribution layer 23 and a solder resist layer 25 are sequentially provided on the non-functional surface 202.

[0120] The following provision of the second chip package may further include the steps of: fabricating a buffer layer 24, and after fabricating at least a portion of the receiving groove 21 in the buffer layer 24, fabricating a redistribution layer 23 in the buffer layer 24; the buffer layer 24 is disposed on the functional surface 201 or the non-functional surface 202 of the second chip, with the functional surface 201 and the non-functional surface 202 disposed opposite to each other. In the second and third embodiments of the chip package structure 100, combined with... Figure 9 As shown, in order to be applicable to more application scenarios, the receiving slot 21 is formed by the buffer layer 24 and the solder mask layer 25, so that there is no need to cut a slot on the surface of the second chip 20. The receiving slot 21 is suitable for the functional surface 201 or the non-functional surface 202.

[0121] When the buffer layer 24 and the receiving groove 21 are fabricated on the non-functional surface 202, the following can be obtained: Figure 3 In the second embodiment of the chip packaging structure 100 shown, when a buffer layer 24 and a receiving groove 21 are fabricated on the functional surface 201, the following can be obtained: Figure 4 The third embodiment of the chip packaging structure 100 shown.

[0122] Combination Figure 9 As shown, after fabricating the redistribution layer 23, the solder mask layer 25 is then fabricated. When fabricating the filler groove 22, it can be selectively removed as needed. Figure 9 As shown in Figure a, part of the buffer layer 24 and the solder mask layer 25 are removed, and the second bottom surface 221 of the filling groove 22 is a plane; combined with Figure 9 As shown in b, part of the buffer layer 24 and the solder mask layer 25 are removed, and the second bottom surface 221 of the filling groove 22 is a slope; combined with Figure 9 As shown in c, part of the solder resist layer 25 can be removed; the filling groove 22 corresponds to the groove after removal along the dotted line.

[0123] Providing a second chip package includes the steps of: fabricating at least a portion of a receiving groove 21 in the solder mask layer 25; and combining... Figure 10 As shown, the buffer layer 24 may be optional, without grooves, and the receiving groove 21 may be formed solely by the solder mask layer 25; combined with Figure 10 As shown in a and 10b, a filling groove 22 is made in the solder resist layer 25. The second bottom surface 221 can be a plane or an inclined surface. The filling groove 22 corresponds to the groove after the dotted line is removed.

[0124] Combination Figure 11 As shown, the second chip package may optionally omit the buffer layer 24, directly lay the redistribution layer 23 on the insulating layer 26, then fabricate the solder mask layer 25, and form the receiving groove 21 from the solder mask layer 25; combined with Figure 11 As shown in a and 11b, a filling groove 22 is made in the solder resist layer 25. The second bottom surface 221 can be a plane or an inclined surface. The filling groove 22 corresponds to the groove after the dotted line is removed.

[0125] The process of making the filling layer 40 includes: injecting filling material 400 into the filling groove 22, the filling material 400 flowing into the receiving groove 21, the filling material 400 being a colloid, the filling groove 22 having a dam function, the nozzle being able to enter the clearance channel above the filling groove 22, and injecting filling material into the filling groove 22 from the clearance channel, the clearance channel and the filling groove 22 being considered to together constitute the glue dispensing space.

[0126] The beneficial effects of this invention are as follows: at least two inner metal protrusions 31 have a maximum clearance distance L, which expands the adhesive space in the horizontal direction; the filling layer 40 is located in the receiving groove 21, which has the function of a dam, preventing the filling layer 40 from extending outward toward the first metal protrusion 30 and reducing contamination of the first metal protrusion 30; the first chip 10 is stacked on the second chip 20 corresponding to the receiving groove 21, and the height of the first chip 10 is lowered as a whole due to the setting of the receiving groove 21, thereby increasing the height difference between the first metal protrusion 30 and the first chip 10; the filling groove 22 expands the adhesive space in the thickness direction, preventing the filling layer 40 from extending outward toward the first metal protrusion 30 and reducing contamination of the first metal protrusion 30.

[0127] This can be formed by referring to any of the technical solutions provided above, and will not be elaborated here.

[0128] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0129] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A chip packaging structure, characterized in that, include: First chip; The second chip includes a functional surface and a second pad, wherein the second pad is disposed on the functional surface; The size of the first chip is smaller than that of the second chip; A redistribution layer is disposed on the second chip and electrically connected to the second pad; A receiving slot, wherein the first chip has an orthographic projection onto the second chip, at least a portion of the orthographic projection overlaps with the receiving slot; The redistribution layer extends into the receiving slot, and the first chip is electrically connected to the redistribution layer. The first metal bump is disposed on the redistribution layer and located on the periphery of the first chip, including an inner metal bump. The inner metal bump is disposed adjacent to the outer periphery of the first chip, and there is a maximum clearance distance between at least two adjacent inner metal bumps. The maximum clearance distance is greater than the interval distance between other two adjacent inner metal bumps. A filling layer, located within the receiving slot, fills the gap between the first chip and the second chip.

2. The chip packaging structure according to claim 1, characterized in that, The maximum avoidance distance is greater than or equal to the maximum size of a single first metal protrusion, or the maximum avoidance distance is between 200 and 500 micrometers.

3. The chip packaging structure according to claim 1, characterized in that, The second chip includes a filling slot and a receiving slot that are adjacent to and connected. The filling slot is located between two inner metal protrusions having the maximum clearance distance, and the filling layer extends from the filling slot into the receiving slot.

4. The chip packaging structure according to claim 3, characterized in that, The filling groove and the receiving groove form a convex shape.

5. The chip packaging structure according to claim 3, characterized in that, The first metal protrusion surrounds the common outer side of the receiving groove and the filling groove.

6. The chip packaging structure according to claim 3, characterized in that, The receiving slot has a first bottom surface, the filling slot has a second bottom surface, the first bottom surface is connected to the second bottom surface, and the lowest point of the second bottom surface is higher than or level with the first bottom surface.

7. The chip packaging structure according to claim 1, characterized in that, The redistribution layer is disposed on the non-functional surface of the second chip, the functional surface and the non-functional surface are disposed opposite to each other, and the receiving groove is formed by recessing from the non-functional surface.

8. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure includes a buffer layer, which is disposed on the functional or non-functional surface of the second chip, with the functional and non-functional surfaces being disposed opposite to each other. The redistribution layer is disposed on the buffer layer, and at least a portion of the receiving groove is formed by recesses in the buffer layer.

9. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure includes a solder mask layer, the redistribution layer is located between the functional surface and the solder mask layer, or the redistribution layer is located between the non-functional surface and the solder mask layer, the functional surface and the non-functional surface are disposed opposite to each other, and at least a portion of the receiving groove is formed by recessing from the solder mask layer.

10. The chip packaging structure according to claim 1, characterized in that, The first chip includes a first surface and a first pad, the first pad being disposed on the first surface; the chip packaging structure includes a plurality of second metal bumps, the second metal bumps connecting the first pad and the redistribution layer; the fill layer covers the second metal bumps and the first surface.

11. A chip packaging method, characterized in that, Including the following steps: A second chip package is provided, including a second chip, a redistribution layer, and a receiving slot; The second chip includes a functional surface and a second pad, the second pad being disposed on the functional surface; the redistribution layer is disposed on the second chip and electrically connected to the second pad, the redistribution layer extending into the receiving groove; A first metal protrusion is laid out and fabricated, the first metal protrusion being disposed on the redistribution layer, the first metal protrusion including an inner metal protrusion, the inner metal protrusion being disposed adjacent to the outer periphery of the receiving groove; when laying out the first metal protrusion, at least two adjacent inner metal protrusions have a maximum clearance distance, and two adjacent inner metal protrusions with the maximum clearance distance form a clearance channel; the maximum clearance distance is greater than the interval distance between other two adjacent inner metal protrusions. A first chip is provided, which is disposed at a corresponding receiving slot and electrically connected to the redistribution layer; the size of the first chip is smaller than that of the second chip. A filling layer is formed by injecting a filling material into the receiving groove through the avoidance channel. The filling material is fluid and flows into the gap between the first chip and the second chip. The filling material is cured to obtain the filling layer.

12. The chip packaging method according to claim 11, characterized in that, The injection of filler material includes the steps of dripping filler material, each drop of filler material spreading out after dripping, and several drops of filler material connecting together after spreading out; each drop of filler material has a maximum spreading outer diameter after spreading out, and the maximum avoidance distance is greater than or equal to the maximum spreading outer diameter.

13. The chip packaging method according to claim 11, characterized in that, When arranging the first metal protrusion, leave at least one position of the first metal protrusion unoccupied, or leave at least a distance of 200-500 micrometers unoccupied, in order to form the maximum avoidance distance.

14. The chip packaging method according to claim 13, characterized in that, Providing a second chip package includes the following steps: A filling groove is fabricated, wherein the receiving groove and the filling groove are adjacent and connected; wherein the filling groove constitutes part of the avoidance channel, and the filling groove is located between two adjacent inner metal protrusions with the maximum avoidance distance.

15. The chip packaging method according to claim 14, characterized in that, Providing a second chip package includes the steps of: fabricating the receiving groove and filling groove on the non-functional side of the second chip, wherein the non-functional side and the functional side are disposed opposite to each other; and fabricating the redistribution layer on the non-functional side of the second chip.

16. The chip packaging method according to claim 14, characterized in that, The process of creating a receiving groove and a filling groove on the non-functional surface includes: creating a recessed structure on the non-functional surface in a single step to obtain the receiving groove and the filling groove, wherein the first bottom surface of the receiving groove and the second bottom surface of the filling groove are flush; or, creating a recessed structure on the non-functional surface multiple times to obtain the receiving groove and the filling groove, wherein the lowest point of the filling groove is higher than or flush with the first bottom surface of the receiving groove.

17. The chip packaging method according to claim 14, characterized in that, Providing a second chip package includes the steps of: fabricating a buffer layer, fabricating at least a portion of the receiving slot in the buffer layer, and fabricating a redistribution layer in the buffer layer; the buffer layer is disposed on the functional surface or non-functional surface of the second chip, and the functional surface and the non-functional surface are disposed opposite to each other.

18. The chip packaging method according to claim 17, characterized in that, A solder resist layer is fabricated, and at least a portion of the receiving groove is fabricated on the solder resist layer; the solder resist layer is disposed on the buffer layer, or the solder resist layer is disposed on the functional surface or non-functional surface of the second chip.

19. The chip packaging method according to claim 14, characterized in that, The process of creating the filling layer includes injecting a filling material into the filling groove, the filling material flowing into the receiving groove.

Images