Shift register and driving method thereof, gate driving circuit and display device

Abstract

A shift register and a driving method thereof, a display substrate and a display device, the shift register comprising: a shift sub-circuit and an output sub-circuit; the shift sub-circuit is configured under control of at least one of a signal input end (IN), a first clock signal end (CK1), a second clock signal end (CK2) and a third clock signal end (CK3), to provide a signal of one of a second power supply end (VGL) and the second clock signal end (CK2) to a second node (N2), to provide a signal of the signal input end (IN) to a third node (N3), and to provide a signal of one of a first power supply end (VGH) and the third clock signal end (CK3) to a cascade signal output end (Carry) under control of signals of the second node (N2) and the third node (N3); the output sub-circuit is configured to provide a signal of one of the first power supply end (VGH) and the third clock signal end (CK3) to a driving signal output end (GOUT) under control of signals of at least one of the second node (N2), the third node (N3), a first control signal end (G1), a second control signal end (G2), the signal input end (IN) and a masking signal end (MS).

Description

Shift register and driving method thereof, gate driving circuit and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, in particular to a shift register and driving method thereof, a gate driving circuit and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-luminous, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices with OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, the present disclosure provides a shift register, comprising: a shift sub-circuit and an output sub-circuit;

[0006] The shift sub-circuit is electrically connected with a signal input end, a first clock signal end, a second clock signal end, a third clock signal end, a first power supply end, a second power supply end, a cascade signal output end, a second node and a third node, respectively, and is configured to provide the second node with a signal of one of the second power supply end and the second clock signal end, provide the third node with a signal of the signal input end, and provide the cascade signal output end with a signal of one of the first power supply end and the third clock signal end under the control of signals of the second node and the third node;

[0007] The output sub-circuit is electrically connected with the second node, the third node, the signal input end, the first control signal end, the second control signal end, the masking signal end, the third clock signal end, the first power supply end, the second power supply end and the driving signal output end respectively, and is configured to provide the signal of one of the first power supply end and the third clock signal end to the driving signal output end under the control of the signals of at least one of the second node, the third node, the first control signal end, the second control signal end, the signal input end and the masking signal end.

[0008] In an example embodiment, the number of the shift registers is multiple, and the multiple shift registers are cascaded;

[0009] The cascaded signal output end of the at least one level of shift register is electrically connected with the signal input end of the at least one level of shift register and the first control signal end of the at least one level of shift register respectively;

[0010] The shift register in which the signal input end connected with the cascaded signal output end of the at least one level of shift register is located is different from the shift register in which the first control signal end connected with the cascaded signal output end of the at least one level of shift register is located.

[0011] In an example embodiment, the shift sub-circuit includes the first transistor to the eighth transistor and the first capacitor to the third capacitor, and at least one capacitor of the first capacitor to the third capacitor includes a first plate and a second plate.

[0012] The control electrode of the first transistor is electrically connected with the first clock signal end, the first electrode of the first transistor is electrically connected with the signal input end, and the second electrode of the first transistor is electrically connected with the first node;

[0013] The control electrode of the second transistor is electrically connected with the first node, the first electrode of the second transistor is electrically connected with the second clock signal end, and the second electrode of the second transistor is electrically connected with the second node;

[0014] The control electrode of the third transistor is electrically connected with the second clock signal end, the first electrode of the third transistor is electrically connected with the second power supply end, and the second electrode of the third transistor is electrically connected with the second node;

[0015] The control electrode of the fourth transistor is electrically connected with the second node, the first electrode of the fourth transistor is electrically connected with the first power supply end, and the second electrode of the fourth transistor is electrically connected with the cascaded signal output end;

[0016] The control electrode of the fifth transistor is electrically connected with the third node, the first electrode of the fifth transistor is electrically connected with the third clock signal end, and the second electrode of the fifth transistor is electrically connected with the cascaded signal output end;

[0017] The control electrode of the sixth transistor is electrically connected with the second node, the first electrode of the sixth transistor is electrically connected with the first power supply end, and the second electrode of the sixth transistor is electrically connected with the fourth node;

[0018] The control electrode of the seventh transistor is electrically connected with the third clock signal end, the first electrode of the seventh transistor is electrically connected with the fourth node, and the second electrode of the seventh transistor is electrically connected with the first node;

[0019] The control electrode of the eighth transistor is electrically connected with the second power supply end, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with the third node;

[0020] The first electrode plate of the first capacitor is electrically connected with the second node, and the second electrode plate of the first capacitor is electrically connected with the first power supply end;

[0021] The first electrode plate of the second capacitor is electrically connected with the third node, and the second electrode plate of the second capacitor is electrically connected with the cascade signal output end;

[0022] The first electrode plate of the third capacitor is electrically connected with the first power supply end, and the second electrode plate of the third capacitor is electrically connected with the cascade signal output end.

[0023] In an example embodiment, the output sub-circuit comprises a node control sub-circuit and an output control sub-circuit;

[0024] The node control sub-circuit is electrically connected with the second node, the third node, the fifth node, the sixth node, the signal input end, the masking signal end, the first control signal end, the second control signal end and the second power supply end respectively, and is configured to provide the signal of the second node to the fifth node and provide the signal of the third node to the sixth node under the control of the signals of at least one of the first control signal end, the second control signal end, the signal input end, the masking signal end and the second power supply end;

[0025] The output control sub-circuit is electrically connected with the fifth node, the sixth node, the first power supply end, the third clock signal end and the driving signal output end respectively, and is configured to provide the signal of the first power supply end to the driving signal output end under the control of the signal of the fifth node and provide the signal of the third clock signal end to the driving signal output end under the control of the signal of the sixth node.

[0026] In an example embodiment, the output control sub-circuit comprises a ninth transistor, a tenth transistor, a fourth capacitor, a fifth capacitor and a sixth capacitor, and at least one of the fourth capacitor to the sixth capacitor comprises a first electrode plate and a second electrode plate;

[0027] The control electrode of the ninth transistor is electrically connected with the fifth node, the first electrode of the ninth transistor is electrically connected with the first power supply end, and the second electrode of the ninth transistor is electrically connected with the driving signal output end.

[0028] a control electrode of the tenth transistor is electrically connected with the sixth node, a first electrode of the tenth transistor is electrically connected with the third clock signal terminal, and a second electrode of the tenth transistor is electrically connected with the driving signal output terminal;

[0029] a first plate of the fourth capacitor is electrically connected with the fifth node, and a second plate of the fourth capacitor is electrically connected with the first power supply terminal;

[0030] a first plate of the fifth capacitor is electrically connected with the sixth node, and a second plate of the fifth capacitor is electrically connected with the driving signal output terminal;

[0031] a first plate of the sixth capacitor is electrically connected with the sixth node, and a second plate of the sixth capacitor is electrically connected with the seventh node.

[0032] In the example embodiment, the node control sub-circuit comprises: eleventh to fifteenth transistors.

[0033] a control electrode of the eleventh transistor is electrically connected with the seventh node, a first electrode of the eleventh transistor is electrically connected with the second node, and a second electrode of the eleventh transistor is electrically connected with the fifth node;

[0034] a control electrode of the twelfth transistor is electrically connected with the seventh node, a first electrode of the twelfth transistor is electrically connected with the third node, and a second electrode of the twelfth transistor is electrically connected with the sixth node;

[0035] a control electrode of the thirteenth transistor is electrically connected with the first control signal terminal, a first electrode of the thirteenth transistor is electrically connected with the seventh node, and a second electrode of the thirteenth transistor is electrically connected with the eighth node;

[0036] a control electrode of the fourteenth transistor is electrically connected with the signal input terminal, a first electrode of the fourteenth transistor is electrically connected with the masking signal terminal, and a second electrode of the fourteenth transistor is electrically connected with the eighth node;

[0037] a control electrode of the fifteenth transistor is electrically connected with the second control signal terminal, a first electrode of the fifteenth transistor is electrically connected with the second power supply terminal, and a second electrode of the fifteenth transistor is electrically connected with the seventh node.

[0038] In a second aspect, the present disclosure further provides a display substrate, comprising: a display area and a non-display area surrounding at least one side of the display area, the display substrate comprising: a first gate drive circuit located in the non-display area, the first gate drive circuit comprising: a plurality of cascaded first shift registers, the first shift register being the above-mentioned shift register.

[0039] In an example embodiment, at least one first shift register in the plurality of cascaded first shift registers comprises: a second capacitor and a third capacitor, the second capacitor and the third capacitor comprising: a first plate and a second plate;

[0040] The second plate of the second capacitor and the second plate of the third capacitor in the at least one first shift register are the same plate.

[0041] In an example embodiment, the cascade signal output end of the nth first shift register is electrically connected with the signal input end of the n+X first shift register and the first control signal end of the n+Y first shift register respectively, 1≤n≤N, N is the total number of stages of the first shift register, and X<Y.

[0042] In an example embodiment, further comprising: a plurality of cross-stage connection lines located in the non-display area;

[0043] One of the plurality of cross-stage connection lines is electrically connected with the cascade signal output end of the at least one first shift register, the signal input end of the at least one first shift register, and the first control signal end of the at least one first shift register respectively;

[0044] At least two shift registers of the shift register in which the cascade signal output end connected by the same cross-stage connection line, the shift register in which the signal input end connected, and the shift register in which the first control signal end connected are different stage shift registers.

[0045] In an example embodiment, the cross-stage connection line comprises: a first cross-stage connection part, a second cross-stage connection part, and a third cross-stage connection part, at least one of the first cross-stage connection part, the second cross-stage connection part, and the third cross-stage connection part extends at least partially along the second direction;

[0046] The second cross-stage connection part is electrically connected with the first cross-stage connection part and the third cross-stage connection part respectively, and at least two of the first cross-stage connection part, the second cross-stage connection part, and the third cross-stage connection part are arranged in different layers.

[0047] In an example embodiment, the at least one first shift register comprises: a first transistor, a thirteenth transistor, a fourteenth transistor, a second capacitor, and a third capacitor, the second capacitor and the third capacitor comprising: a first plate and a second plate, wherein the first electrode of the first transistor and the control electrode of the fourteenth transistor are electrically connected with the signal input end of the first shift register respectively, the control electrode of the thirteenth transistor is electrically connected with the first control signal end of the first shift register, and the second plate of the second capacitor and the second plate of the third capacitor are electrically connected with the cascade signal output end of the first shift register respectively;

[0048] For the cross-stage connection line electrically connected with the cascade signal output end of the nth stage first shift register, the signal output end of the nth+X stage first shift register and the first control signal end of the nth+Y stage first shift register respectively, the first cross-stage connection part is electrically connected with the second plate of the second capacitor and the second plate of the third capacitor of the nth stage first shift register respectively, and the second cross-stage connection part is electrically connected with the first electrode of the first transistor and the control electrode of the fourteenth transistor of the nth+X stage first shift register, the control electrode of the thirteenth transistor of the nth+Y stage first shift register and the second cross-stage connection part respectively.

[0049] In an exemplary embodiment, at least one stage of the plurality of cascaded first shift registers comprises: a second capacitor, the second capacitor comprising: a first plate and a second plate;

[0050] For the cross-stage connection line electrically connected with the cascade signal output end of the nth stage first shift register, the first cross-stage connection part is an integral structure with the second plate of the second capacitor in the nth stage first shift register.

[0051] In an exemplary embodiment, further comprising: a substrate and a driving circuit layer disposed on the substrate; the first gate drive circuit is disposed on the driving circuit layer, and the driving circuit layer comprises: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer which are sequentially stacked on the substrate, and the at least one stage of the first shift register comprises: at least one transistor and at least one capacitor, the at least one transistor comprising: an active pattern, a control electrode, a first electrode and a second electrode, and the at least one capacitor comprising: a first plate and a second plate;

[0052] The semiconductor layer comprises: the active pattern of the at least one transistor of the at least one stage of the first shift register;

[0053] The first conductive layer comprises: the control electrode of the at least one transistor and the first plate of the at least one capacitor of the at least one stage of the first shift register;

[0054] The second conductive layer comprises: the second plate of the at least one capacitor of the at least one stage of the first shift register and the first cross-stage connection part of at least one cross-stage connection line of the plurality of cross-stage connection lines;

[0055] The third conductive layer comprises: the first electrode and the second electrode of the at least one transistor of the at least one stage of the first shift register and the second cross-stage connection part of at least one cross-stage connection line of the plurality of cross-stage connection lines;

[0056] The fourth conductive layer comprises: the third cross-stage connection part of at least one cross-stage connection line of the plurality of cross-stage connection lines.

[0057] In an exemplary embodiment, the at least one first shift register comprises: a first transistor, an eleventh transistor, a fourteenth transistor and a fifteenth transistor;

[0058] A first cross-stage connection portion in the at least one cross-stage connection line at least partially overlaps a first projection of a first electrode of the first transistor of the at least one first shift register on the substrate;

[0059] A second cross-stage connection portion in the at least one cross-stage connection line at least partially overlaps a first projection of a control electrode of the eleventh transistor of the at least one first shift register on the substrate;

[0060] A third cross-stage connection portion in the at least one cross-stage connection line at least partially overlaps a first projection of a control electrode of at least one of the thirteenth transistor and the fourteenth transistor of the at least one first shift register on the substrate.

[0061] In an exemplary embodiment, further comprising: a clock signal line group located in the non-display area, the clock signal line group being disposed in the driving circuit layer and located in the fourth conductive layer;

[0062] The plurality of cross-stage connection lines are located on a side of the clock signal line group close to the display area;

[0063] The clock signal line group comprises: a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line arranged in sequence close to the display area, at least one of the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line at least partially extending along the second direction.

[0064] In exemplary embodiments, the first clock signal terminal of the 4i-3 stage first shift register is electrically connected with the first clock signal line, the second clock signal terminal of the 4i-3 stage first shift register is electrically connected with the second clock signal line, the third clock signal terminal of the 4i-3 stage first shift register is electrically connected with the third clock signal line, the first clock signal terminal of the 4i-2 stage first shift register is electrically connected with the second clock signal line, the second clock signal terminal of the 4i-2 stage first shift register is electrically connected with the third clock signal line, the third clock signal terminal of the 4i-2 stage first shift register is electrically connected with the fourth clock signal line, the first clock signal terminal of the 4i-1 stage first shift register is electrically connected with the third clock signal line, the second clock signal terminal of the 4i-1 stage first shift register is electrically connected with the fourth clock signal line, the third clock signal terminal of the 4i-1 stage first shift register is electrically connected with the first clock signal line, the first clock signal terminal of the 4i stage first shift register is electrically connected with the fourth clock signal line, the second clock signal terminal of the 4i stage first shift register is electrically connected with the first clock signal line, and the third clock signal terminal of the 4i stage first shift register is electrically connected with the second clock signal line.

[0065] In exemplary embodiments, the at least one stage first shift register comprises a first transistor, a second transistor, a sixth transistor, a seventh transistor, and an eighth transistor.

[0066] The orthogonal projection of the clock signal line group on the substrate at least partially overlaps with the orthogonal projection of at least one of the first transistor, the second transistor, the sixth transistor, the seventh transistor, and the eighth transistor in the at least one stage first shift register on the substrate.

[0067] In exemplary embodiments, further comprising: a power signal line group and a clock signal line group located in the non-display region, the power signal line group and the clock signal line group being disposed in the driving circuit layer and located in the fourth conductive layer.

[0068] The power signal line group comprises two first power lines and two second power lines, the first power lines and the second power lines at least partially extending along the second direction.

[0069] The first second power line is located on the side of the clock signal line group away from the display region, the first first power line is located on the side of the clock signal line group close to the display region, the second second power line is located on the side of the first first power line close to the display region, the second first power line is located on the side of the second second power line close to the display region, and the plurality of cross-stage connection lines are located between the second second power line and the second first power line.

[0070] The first power line is electrically connected to a first power terminal of the at least one first shift register, and the second power line is electrically connected to a second power terminal of the at least one first shift register.

[0071] In an example embodiment, the at least one first shift register comprises a third transistor, a fourth transistor, a fifth transistor, a ninth transistor, a tenth transistor and a third capacitor.

[0072] A projection of the first power line on the substrate at least partially overlaps a projection of the fourth transistor and the fifth transistor of the at least one first shift register on the substrate, a projection of the first second power line on the substrate at least partially overlaps a projection of the third transistor of the at least one first shift register on the substrate, a projection of the second power line on the substrate at least partially overlaps a projection of the ninth transistor and the tenth transistor of the at least one first shift register on the substrate, and a projection of the second second power line on the substrate at least partially overlaps a projection of the third capacitor of the at least one first shift register on the substrate.

[0073] In an example embodiment, the display apparatus further comprises a scan initial signal line located in the non-display area, wherein the scan initial signal line is disposed in the driving circuit layer and located in the fourth conductive layer, and the scan initial signal line at least partially extends in the second direction.

[0074] The scan initial signal line is located between the first second power line and the clock signal line group.

[0075] The signal input terminal of the first stage first shift register and the signal input terminal of the second stage first shift register are respectively electrically connected to the scan initial signal line.

[0076] The at least one first shift register comprises a second transistor.

[0077] A projection of the scan initial signal line on the substrate at least partially overlaps a projection of the second transistor of the at least one first shift register on the substrate.

[0078] In an example embodiment, the power signal line group further comprises a third power line, and the third power line at least partially extends in the second direction.

[0079] The third power line is located between the first first power line and the second second power line.

[0080] The display area is provided with light emitting devices, and the third power line is electrically connected to a second electrode of at least one light emitting device.

[0081] The at least one first shift register comprises a first capacitor and a second capacitor.

[0082] a projection of the third power line on the substrate at least partially overlaps with a projection of the first capacitor and the second capacitor of the at least one stage of the first shift register on the substrate;

[0083] a length of the third power line in the first direction is greater than a length of at least one of the first power line and the second power line in the first direction.

[0084] In an exemplary embodiment, further comprising: a plurality of pixel initial signal lines located in the non-display region; at least one of the plurality of pixel initial signal lines is disposed in the driving circuit layer and located in the fourth conductive layer, and at least partially extends in the second direction;

[0085] the plurality of pixel initial signal lines are located on a side of the mask signal line close to the display region;

[0086] at least one of the plurality of pixel initial signal lines is electrically connected to a mask signal terminal of the at least one stage of the first shift register;

[0087] the at least one stage of the first shift register comprises: a fourth capacitor and a fifth capacitor;

[0088] a projection of the mask signal line on the substrate at least partially overlaps with a projection of the fourth capacitor and the fifth capacitor of the at least one stage of the first shift register on the substrate.

[0089] In an exemplary embodiment, further comprising: a plurality of pixel initial signal lines located in the non-display region; at least one of the plurality of pixel initial signal lines is disposed in the driving circuit layer and located in the fourth conductive layer, and at least partially extends in the second direction;

[0090] the plurality of pixel initial signal lines are located on a side of the mask signal line close to the display region;

[0091] a projection of at least one of the plurality of pixel initial signal lines on the substrate at least partially overlaps with a projection of the fourth capacitor and the fifth capacitor of the at least one stage of the first shift register on the substrate.

[0092] a length of at least one of the plurality of pixel initial signal lines in the first direction is greater than a length of the mask signal line in the first direction.

[0093] In an exemplary embodiment, further comprising: a second gate driving circuit located in the non-display region, the second gate driving circuit comprising: a plurality of cascaded second shift registers, the second shift register comprising: a light-emitting signal output terminal;

[0094] The display region is provided with a plurality of pixel driving circuits, and each pixel driving circuit comprises a light-emitting transistor and a write transistor.

[0095] At least one first shift register is electrically connected to the write transistor in at least one row of pixel driving circuits, and at least one second shift register is electrically connected to the light-emitting transistor in at least one row of pixel driving circuits.

[0096] The second control signal end of the at least one first shift register is electrically connected to the signal output end of the at least one second shift register.

[0097] In a third aspect, the present disclosure also provides a display device, comprising the above display substrate.

[0098] In a fourth aspect, the present disclosure also provides a driving method of a shift register configured to drive the above shift register, and the method comprises:

[0099] The shift sub-circuit provides the signal of one of the second power supply end and the second clock signal end to the second node, provides the signal of the signal input end to the third node, and provides the signal of one of the first power supply end and the third clock signal end to the cascaded signal output end under the control of the signals of the second node and the third node.

[0100] The output sub-circuit provides the signal of one of the first power supply end and the third clock signal end to the driving signal output end under the control of the signals of at least one of the second node, the third node, the first control signal end, the second control signal end, the signal input end and the masking signal end.

[0101] Other aspects can be apparent after reading and understanding the accompanying drawings and detailed description.

[0102] SUMMARY

[0103] The accompanying drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and together with the embodiments of the present disclosure, are used to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0104] FIG. 1 is a structural schematic diagram of a display device;

[0105] FIG. 2A is a planar structural schematic diagram of a display substrate;

[0106] FIG. 2B is a planar structural schematic diagram of a display substrate;

[0107] FIG. 2C is a planar structural schematic diagram of a display substrate;

[0108] Fig. 3 is an equivalent circuit schematic diagram of a pixel driving circuit;

[0109] Fig. 4 is a working timing diagram of the pixel driving circuit provided in Fig. 3;

[0110] Fig. 5A is a structural schematic diagram of a shift register provided in an embodiment of the present disclosure;

[0111] Fig. 5B is a structural schematic diagram of an output sub-circuit;

[0112] Fig. 6 is an equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0113] Fig. 7 is a working timing diagram of a shift sub-circuit in the shift register provided in Fig. 6;

[0114] Fig. 8 is a working timing diagram of an output sub-circuit in the shift register provided in Fig. 6 in a refresh frame;

[0115] Fig. 9 is a working timing diagram of the output sub-circuit in the shift register provided in Fig. 6 in a hold frame;

[0116] Fig. 10 is a structural schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0117] Fig. 11 is a connection schematic diagram of a cross-stage connection line;

[0118] Fig. 12 is another structural schematic diagram of a display substrate;

[0119] Fig. 13 is a signal timing diagram of a clock signal line;

[0120] Fig. 14 is a schematic diagram after forming a semiconductor layer pattern in Fig. 12;

[0121] Fig. 15 is a schematic diagram of a first conductive layer pattern in Fig. 12;

[0122] Fig. 16 is a schematic diagram after forming the first conductive layer pattern in Fig. 12;

[0123] Fig. 17 is a schematic diagram of a second conductive layer pattern in Fig. 12;

[0124] Fig. 18 is a schematic diagram after forming the second conductive layer pattern in Fig. 12;

[0125] Fig. 19 is a schematic diagram after forming a third insulating layer pattern in Fig. 12;

[0126] Fig. 20 is a schematic diagram of a third conductive layer pattern in Fig. 12;

[0127] Fig. 21 is a schematic diagram after forming the third conductive layer pattern in Fig. 12;

[0128] Fig. 22 is a schematic diagram after forming a planarization layer pattern in Fig. 12;

[0129] FIG. 23 is a schematic view of the fourth insulating layer pattern of FIG. 12;

[0130] FIG. 24 is a schematic view of FIG. 12 after forming the fourth insulating layer pattern.

[0131] DETAILED DESCRIPTION

[0132] For the purpose of making the objects, technical solutions and advantages of the present disclosure clearer, below, the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments can be implemented in multiple different forms. It can be easily understood by those skilled in the art that the manners and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and brief, the detailed description of some known functions and known components is omitted in the present disclosure. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed structures

[0133] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the length and spacing of each signal line in the first direction can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic views of the structures, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0134] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided in order to avoid confusion of the components, and are not intended to be limiting in terms of number.

[0135] In the present specification, in order to facilitate the description and simplify the description, the words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0136] In this specification, unless otherwise explicitly specified and limited, the terms "mount", "connected", and "linked" are to be interpreted broadly. For example, can be fixedly connected, or detachably connected, or integrally connected; can be mechanically connected, or electrically connected; can be directly connected, or indirectly connected via an intervening member, or internal communication of two elements. The specific meaning of the above terms in the present disclosure can be understood in light of the specific circumstances for those skilled in the art.

[0137] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current flows mainly.

[0138] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. The functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other in the case of using a transistor whose polarity is reversed or in the case where the direction of current flowing in a circuit is changed, and the like. Therefore, the "source electrode" and the "drain electrode" can be interchanged with each other in this specification.

[0139] In this specification, "electrically connected" includes the case where elements are connected through an element having a certain electrical action. The element having a certain electrical action is not particularly limited as long as it can transmit or receive an electrical signal between elements to be connected. Examples of the element having a certain electrical action include an electrode and a wiring as well as a switching element such as a transistor, a resistor, an inductor, a capacitor, and an element having another function.

[0140] In this specification, "parallel" refers to a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" refers to a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0141] In this specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be replaced with "a conductive film". Similarly, "an insulating film" can be replaced with "an insulating layer".

[0142] In the present specification, "co-deposition" refers to a structure formed by two (or more) structures being patterned by the same patterning process. The materials of the two (or more) structures can be the same or different. For example, the materials of the precursors forming the co-deposition structures can be the same, and the final materials can be the same or different.

[0143] In the present specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly defined, and can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon, etc. There can be some small deformations due to tolerances, and there can be rounded corners, arc edges, and deformations, etc.

[0144] FIG. 1 is a schematic diagram of a structure of a display device. As shown in FIG. 1, the display device can include a timing controller, a data driver, a gate driver, and a pixel array. The timing controller is connected to the data driver and the gate driver, respectively. The data driver is connected to a plurality of data signal lines (D1 to Dn), respectively. The gate driver is connected to a plurality of gate lines (G1 to Gm), respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers. At least one sub-pixel Pxij can include a circuit unit and a light emitting device connected to the circuit unit. The circuit unit can include a pixel driving circuit. The pixel driving circuit can be connected to the gate line and the data signal line, respectively.

[0145] In an exemplary embodiment, the timing controller can provide a gray scale value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, etc. suitable for the specification of the light emitting driver to the light emitting driver. The data driver can generate a data voltage to be provided to the data signal lines D1, D2, D3,..., and Dn using the gray scale value and the control signal received from the timing controller. For example, the data driver can sample the gray scale value using the clock signal, and apply a data voltage corresponding to the gray scale value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number.

[0146] In an exemplary embodiment, the gate driver can generate a scan signal to be provided to the gate lines G1, G2, G3,..., and Gm by receiving a clock signal, a gate start signal, etc. from the timing controller. For example, the scan driver can sequentially provide a scan signal having a turn-on level pulse to the gate lines G1 to Gm. For example, the gate driver can be configured in the form of a shift register, and can generate a scan signal in a manner that sequentially transfers a scan start signal provided in the form of a turn-on level pulse to a next stage circuit under the control of a clock signal. m can be a natural number.

[0147] FIG. 2A is a schematic diagram of a planar structure of a display substrate, FIG. 2B is a schematic diagram of a planar structure of a display substrate, and FIG. 2C is a schematic diagram of a planar structure of a display substrate. As shown in FIGS. 2A-2C, the display substrate can include a plurality of pixel units P arranged in a matrix manner, at least one of the plurality of pixel units P including a first sub-pixel P1 emitting first color light, a second sub-pixel P2 emitting second color light, and a third sub-pixel P3 emitting third color light, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each including a pixel driving circuit and a light emitting device. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected with a gate line and a data signal line, and are configured to receive a data voltage transmitted by the data signal line under the control of the gate line and output a corresponding current to the light emitting device. The light emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected with the pixel driving circuit of the sub-pixel in which the light emitting device is located, and are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which the light emitting device is located.

[0148] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 can be a green sub-pixel (G) emitting green light.

[0149] In an example embodiment, the shape of the sub-pixel can be rectangular, diamond, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal parallel, vertical parallel, or triangular manner, which is not limited in the present disclosure.

[0150] In an example embodiment, the pixel unit can include three sub-pixels, which can be arranged in a horizontal parallel, vertical parallel, or triangular manner, which is not limited in the present disclosure. FIGS. 2A and 2B are described by taking an example of a pixel unit including three sub-pixels. The three sub-pixels in FIG. 2A are arranged in a horizontal parallel manner, and the three sub-pixels in FIG. 2B are arranged in a triangular manner.

[0151] In an example embodiment, the pixel unit can include four sub-pixels, which can be arranged in a horizontal parallel, vertical parallel, or square manner, which is not limited in the present disclosure. FIG. 2C is described by taking an example of a pixel unit including four sub-pixels, and an example of the four sub-pixels being arranged in a square manner.

[0152] In an example embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure, which is not limited in the present disclosure.

[0153] Fig. 3 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in Fig. 3, the pixel driving circuit can include 8 transistors (first transistor M1 to eighth transistor M8) and 1 capacitor C. The gate electrode of the first transistor M1 is electrically connected with the first reset signal line Reset1, the first electrode of the first transistor M1 is electrically connected with the first initial signal line INIT1, and the second electrode of the first transistor M1 is electrically connected with the first node N1 or the third node N3. The gate electrode of the second transistor M2 is electrically connected with the second scan signal line Gate2, the first electrode of the second transistor M2 is electrically connected with the first node N1, and the second electrode of the second transistor M2 is electrically connected with the third node N3. The gate electrode of the third transistor M3 is electrically connected with the first node N1, the first electrode of the third transistor M3 is electrically connected with the second node N2, and the second electrode of the third transistor M3 is electrically connected with the third node N3. The gate electrode of the fourth transistor M4 is electrically connected with the first scan signal line Gate1, the first electrode of the fourth transistor M4 is electrically connected with the data signal line Data, and the second electrode of the fourth transistor M4 is electrically connected with the second node N2. The gate electrode of the fifth transistor M5 is electrically connected with the emission signal line EM, the first electrode of the fifth transistor M5 is electrically connected with the high-level power supply line VDD, and the second electrode of the fifth transistor M5 is electrically connected with the second node N2. The gate electrode of the sixth transistor M6 is electrically connected with the emission signal line EM, the first electrode of the sixth transistor M6 is electrically connected with the third node N3, and the second electrode of the sixth transistor M6 is electrically connected with the fourth node N4. The gate electrode of the seventh transistor M7 is electrically connected with the second reset signal line Reset2, the first electrode of the seventh transistor M7 is electrically connected with the second initial signal line INIT2, and the second electrode of the seventh transistor M7 is electrically connected with the fourth node N4. The gate electrode of the eighth transistor M8 is electrically connected with the third reset signal line Reset3, the first electrode of the eighth transistor M8 is electrically connected with the third initial signal line INIT3, and the second electrode of the eighth transistor M8 is electrically connected with the second node N2. The first plate of the capacitor C is electrically connected with the first node N1, and the second plate of the capacitor C is electrically connected with the high-level power supply line VDD. Fig. 3 is described by taking the second electrode of the first transistor M1 being electrically connected with the first node N1 as an example.

[0154] In an example embodiment, the first initial signal line INIT1 can receive a first initial signal. The first transistor M1 can be referred to as a first initial transistor. The first transistor M1 writes the first initial signal to the first node N1 or the third node N3 under the signal control of the first reset signal line Reset1.

[0155] In an example embodiment, the second initial signal line INIT2 can receive a second initial signal. The seventh transistor M7 can be referred to as a second initial transistor. The seventh transistor M7 writes the second initial signal to the first electrode of the light emitting device L under the signal control of the second reset signal line Reset2.

[0156] In an example embodiment, the third initial signal line INIT3 can receive a third initial signal. The eighth transistor M8 can be referred to as a second initial transistor. The eighth transistor M8 writes the third initial signal to the second node N2 under the signal control of the third reset signal line Reset3.

[0157] In an example embodiment, the pixel driving circuit can include at least one of the first transistor, the seventh transistor, and the eighth transistor, and FIG. 3 is an illustration taking the pixel driving circuit including the first transistor, the seventh transistor, and the eighth transistor as an example.

[0158] In an example embodiment, the third transistor M3 can be referred to as a driving transistor. The connection mode of the third transistor in the present disclosure can improve the output saturation characteristics of the third transistor M3.

[0159] In an example embodiment, the high-level power supply line VDD can receive a first power supply signal, the fifth transistor M5 can be referred to as a first light-emitting transistor, and the fifth transistor M5 writes the first power supply signal to the second node N2 under the signal control of the light-emitting signal line EM. The sixth transistor M6 can be referred to as a second light-emitting transistor, and the sixth transistor M6 writes the driving signal output by the third node N3 to the fourth node N4 under the signal control of the light-emitting signal line EM.

[0160] In an example embodiment, the fifth transistor M5 and the sixth transistor M6 can be referred to as light-emitting transistors.

[0161] In an example embodiment, the signal received by the second reset signal line Reset2 can be the same as the signal received by the first scan signal line Gate1, or can also be the same as the signal received by the first reset signal line Reset1, and the signal received by the third reset signal line Reset3 can be the same signal as the signal received by the second reset signal line Reset2.

[0162] In an example embodiment, the first to eighth transistors M1-M8 can be low temperature poly-silicon thin film transistors, or can be oxide thin film transistors, or can be low temperature poly-silicon thin film transistors and oxide thin film transistors. The active pattern of the low temperature poly-silicon thin film transistor is made of low temperature poly-silicon (LTPS), and the active pattern of the oxide thin film transistor is made of oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate forms an LTPO display substrate, which can take advantage of both and can achieve low-frequency driving, reduce power consumption, and improve display quality.

[0163] In an example embodiment, at least one of the first transistor M1 and the second transistor M2 is opposite in transistor type to at least one of the third to eighth transistors M3-M8. For example, the first transistor M1 and the second transistor M2 can be N-type transistors, and the third to eighth transistors M3-M8 can be P-type transistors, or the second transistor M2 can be an N-type transistor, and the first transistor M1, the third to eighth transistors M3-M8 can be P-type transistors.

[0164] In an example embodiment, the N-type transistor can be an oxide transistor, and the P-type transistor can be a low temperature poly-silicon transistor.

[0165] In an example embodiment, the voltage value of the signal of the first initial signal line INIT1 is constant and is a direct current signal, and the voltage value of the signal of the first initial signal line INIT1 can be -3V.

[0166] In an example embodiment, the voltage value of the signal of the second initial signal line INIT2 is constant and is a direct current signal, and the voltage value of the signal of the second initial signal line INIT2 can be 0V.

[0167] In an example embodiment, the voltage value of the signal of the third initial signal line INIT3 is constant and is a direct current signal, and the voltage value of the signal of the third initial signal line INIT3 can be 0V.

[0168] In an example embodiment, the light emitting device L can be electrically connected to the fourth node N4 and the low level power supply line VSS, respectively.

[0169] In an example embodiment, the high level power supply line VDD continuously provides a high level signal, and the low level power supply line VSS continuously provides a low level signal.

[0170] FIG. 4 is a timing diagram of the pixel driving circuit provided in FIG. 3. The working process of the pixel driving circuit exemplified by FIG. 3 in the display stage is described below. FIG. 4 is described by taking the second transistor M2 as an N-type transistor, the first transistor M1, the third transistor M3 to the eighth transistor M8 as P-type transistors, and the signal received by the third reset signal line Reset3, the signal received by the second reset signal line Reset2 and the signal received by the first reset signal line Reset1 being the same. The pixel driving circuit in FIG. 3 includes the first transistor M1 to the eighth transistor M8, one capacitor C and 11 signal lines (the data signal line Data, the first scan signal line Gate1, the second scan signal line Gate2, the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3, the first initial signal line INIT1, the second initial signal line INIT2, the third initial signal line INIT3, the light-emitting signal line EM and the high-level power supply line VDD).

[0171] In combination with FIG. 3 and FIG. 4, the working process of the pixel driving circuit can include:

[0172] In the first stage P1, referred to as the initialization stage, the signals of the first reset signal line Reset1, the second reset signal line Reset2 and the third reset signal line Reset3 are high-level signals, the first transistor M1 is turned on, the signal of the first initial signal line INIT1 is written to the first node N1 or the third node N3 through the turned-on first transistor M1, the first node N1 or the third node N3 is initialized (reset), the pre-stored voltage in the first node N1 or the third node N3 is emptied, the initialization is completed, the seventh transistor M7 is turned on, the signal of the second initial signal line INIT2 is written to the fourth node N4 through the turned-on seventh transistor M7, the first electrode of the light-emitting device L is initialized (reset), the pre-stored voltage in the first electrode of the light-emitting device L is emptied, the initialization is completed, the eighth transistor M8 is turned on, the signal of the third initial signal line INIT3 is written to the second node N2 through the turned-on eighth transistor M8, the second node N2 is initialized (reset), the pre-stored voltage in the second node N2 is emptied, the initialization is completed.

[0173] The second stage P2, referred to as a data writing stage or threshold compensation stage, the signal of the first scan signal line Gate 1 is a low level signal, the signal of the second scan signal line Gate 2 is a high level signal, and the data signal line Data outputs a data voltage. In this stage, since the first node N1 is a low level signal, the third transistor M3 is turned on. The signal of the first scan signal line Gate 1 is a low level signal, the fourth transistor M4 is turned on, the signal of the second scan signal line Gate 2 is a high level signal, and the second transistor M2 is turned on. The data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor M4, the second node N2, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage of the first node N1 is Vdata-|Vth|, where Vdata is the data voltage output by the data signal line Data, and Vth is the threshold voltage of the third transistor M3.

[0174] The third stage P3, referred to as a light emitting stage, the signal of the light emitting signal line EM is a low level signal, the fifth transistor M5 and the sixth transistor M6 are turned on, and the power voltage output by the high level power supply line VDD is provided to the first electrode of the light emitting device L through the turned-on fifth transistor M5, the third transistor M3, and the sixth transistor M6 to drive the light emitting device L to emit light.

[0175] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (the driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor M3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vdata+|Vth|)-Vth] 2 =K*(Vdd-Vdata) 2

[0176] where I is the driving current flowing through the third transistor M3, that is, the driving current driving the light emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3, and Vdd is the power voltage output by the high level power supply line VDD.

[0177] In an example embodiment, the light emitting device L can include any one of an organic light emitting diode (OLED), a quantum dot light emitting diode, and an inorganic light emitting diode. For example, the light emitting device can employ a micro-scale light emitting device, such as a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), or a micro organic light-emitting diode (Micro OLED), without limitation. For example, taking the organic electroluminescent diode (OLED) as an example, the light emitting device can include a first electrode (e.g., as an anode), an organic light emitting layer, and a second electrode (e.g., as a cathode) stacked.

[0178] In an example embodiment, the organic light emitting layer can include a light emitting layer (EML) and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an example embodiment, one or more of the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all sub-pixels can be a common layer connected together, the light emitting layers of adjacent sub-pixels can have a small amount of overlap, or can be isolated.

[0179] In an example embodiment, the gate driver includes at least one gate drive circuit. The number of gate drive circuits depends on the number of gate lines. Taking the display substrate including the pixel drive circuit provided in FIG. 3 as an example, the gate drive circuit includes a first scan drive circuit, a second scan drive circuit, and a light emitting drive circuit. The first scan drive circuit is electrically connected to the first scan signal line, the first reset signal line, the second reset signal line, and the third reset signal line. The second scan drive circuit is electrically connected to the second scan signal, and the light emitting drive circuit is electrically connected to the light emitting signal line.

[0180] In an example embodiment, any one of the gate drive circuits in the gate driver can include a plurality of cascaded shift registers.

[0181] When a display product displays a picture, a gate drive circuit generates a driving signal, and a pixel drive circuit performs initialization and data writing under the control of the driving signal, so as to realize display. When the display product displays a picture, the display product refreshes a picture in each frame, that is, the pixel drive circuit needs to be initialized and data written in each display frame. For some special pictures (for example, a black screen display picture, a static picture or a picture with less update, etc.), the pixel drive circuit does not need to be initialized and data written in at least part of the display frames, and the original brightness can be maintained through the pixel drive circuit with low leakage. The gate drive circuit of the display product generates a driving signal in each frame no matter which picture is displayed, and the pixel drive circuit is repeatedly initialized and data written, so that the power consumption of the display product is high.

[0182] Therefore, the present disclosure provides a shift register.

[0183] FIG. 5A is a structural schematic diagram of a shift register provided by an embodiment of the present disclosure. As shown in FIG. 5A, the shift register provided by the embodiment of the present disclosure includes a shift sub-circuit and an output sub-circuit. The shift sub-circuit is electrically connected with a signal input end IN, a first clock signal end CK1, a second clock signal end CK2, a third clock signal end CK3, a first power supply end VGH, a second power supply end VGL, a cascade signal output end Carry, a second node N2 and a third node N3 respectively, and is configured to provide, under the control of signals of at least one of the signal input end IN, the first clock signal end CK1, the second clock signal end CK2 and the third clock signal end CK3, a signal of one of the second power supply end VGL and the second clock signal end CK2 to the second node N2, a signal of the signal input end IN to the third node N3, and a signal of one of the first power supply end VGH and the third clock signal end CK3 to the cascade signal output end Carry under the control of signals of the second node N2 and the third node N3;

[0184] The output sub-circuit is electrically connected with the second node N2, the third node N3, the signal input end IN, a first control signal end G1, a second control signal end G2, a masking signal end MS, the third clock signal end CK3, the first power supply end VGH, the second power supply end VGL and a driving signal output end GOUT respectively, and is configured to provide, under the control of signals of at least one of the second node N2, the third node N3, the first control signal end G1, the second control signal end G2, the signal input end IN and the masking signal end MS, a signal of one of the first power supply end VGH and the third clock signal end CK3 to the driving signal output end GOUT.

[0185] The disclosure sets the shift sub-circuit to output the cascade signal provided for other stages of the shift register to the cascade signal output end, sets the output sub-circuit to output the driving signal provided for the pixel driving circuit to the driving signal output end, and realizes that the cascade signal and the driving signal are output by different sub-circuits, so that the driving signal can be output to the pixel driving circuit or not under the condition of normal output of the cascade signal.

[0186] The shift register provided by the embodiment of the disclosure can control the signal output by the driving signal output end according to the requirement of the display area refresh rate under the control of the signals at the first control signal end, the second control signal end and the signal input end, and lock the control signal of the corresponding masking signal end in the output sub-circuit, so as to realize the control of the signal output by the driving signal output end, realize different refresh rates in different areas, that is, high and low refresh rates coexist in the same frame of picture, and the embodiment of the disclosure is not limited to realizing different refresh rates in the fixed area of the display panel, but can realize dynamic refresh in any area, so as to reduce the power consumption of the display panel.

[0187] In the example embodiment, the number of shift registers is multiple, and the multiple shift registers are cascaded. The cascade signal output ends Carry of at least one stage of shift registers are respectively electrically connected with the signal input ends IN of at least one stage of shift registers and the first control signal ends G1 of at least one stage of shift registers. The shift register in which the signal input end IN connected with the cascade signal output end Carry is located is different from the shift register in which the first control signal end G1 connected is located.

[0188] In the example embodiment, FIG. 5B is a structural schematic diagram of the output sub-circuit. As shown in FIG. 5B, the output sub-circuit includes a node control sub-circuit and an output control sub-circuit. The node control sub-circuit is respectively electrically connected with the second node N2, the third node N3, the fifth node N5, the sixth node N6, the signal input end IN, the masking signal end MS, the first control signal end G1, the second control signal end G2 and the second power supply end VGL, and is configured to provide the signal of the second node N2 to the fifth node N5 and provide the signal of the third node N3 to the sixth node N6 under the control of the signals at at least one of the first control signal end G1, the second control signal end G2, the signal input end IN, the masking signal end MS and the second power supply end VGL. The output control sub-circuit is respectively electrically connected with the fifth node N5, the sixth node N6, the first power supply end VGH, the third clock signal end CK3 and the driving signal output end GOUT, and is configured to provide the signal of the first power supply end VGH to the driving signal output end GOUT under the control of the signal of the fifth node N5 and provide the signal of the third clock signal end CK3 to the driving signal output end GOUT under the control of the signal of the sixth node N6.

[0189] In an example embodiment, FIG. 6 is an equivalent circuit diagram of a shift register provided by an example embodiment. As shown in FIG. 6, the shift sub-circuit can include first to eighth transistors T1-T8 and first to third capacitors C1-C3, at least one of the first to third capacitors C1-C3 including a first plate and a second plate.

[0190] As shown in FIG. 6, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the second clock signal terminal CK2, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the second clock signal terminal CK2, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal VGH, and the second electrode of the fourth transistor T4 is electrically connected to the carry signal output terminal Carry; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is electrically connected to the third clock signal terminal CK3, and the second electrode of the fifth transistor T5 is electrically connected to the carry signal output terminal Carry; the control electrode of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VGH, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4; the control electrode of the seventh transistor T7 is electrically connected to the third clock signal terminal CK3, the first electrode of the seventh transistor T7 is electrically connected to the fourth node N4, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1; the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal VGL, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3; the first plate C11 of the first capacitor C1 is electrically connected to the second node N2, and the second plate C12 of the first capacitor C1 is electrically connected to the first power supply terminal VGH; the first plate C21 of the second capacitor C2 is electrically connected to the third node N3, and the second plate C22 of the second capacitor C2 is electrically connected to the carry signal output terminal Carry; the first plate C31 of the third capacitor C3 is electrically connected to the first power supply terminal VGH, and the second plate C32 of the third capacitor C3 is electrically connected to the carry signal output terminal Carry.

[0191] In an example embodiment, the shift sub-circuit can also be a circuit structure of 10T3C, 10T4C, 12T3C, 12T4C, 13T3C, 13T4C, 16T3C, or 16T4C, and the present disclosure does not make any limitation in this regard.

[0192] In an example embodiment, the first capacitor C1 can ensure the stability of the signal of the second node N2, the second capacitor C2 can ensure the stability of the signal of the third node N3, and the third capacitor C3 can ensure the stability of the signal of the cascade signal output end Carry.

[0193] In an example embodiment, as shown in FIG. 6, the output control sub-circuit can include a ninth transistor T9, a tenth transistor T10, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6, at least one capacitor of the fourth capacitor C4 to the sixth capacitor C6 includes a first plate and a second plate. Wherein the control electrode of the ninth transistor T9 is electrically connected with the fifth node N5, the first electrode of the ninth transistor T9 is electrically connected with the first power supply end VGH, and the second electrode of the ninth transistor T9 is electrically connected with the driving signal output end GOUT; the control electrode of the tenth transistor T10 is electrically connected with the sixth node N6, the first electrode of the tenth transistor T10 is electrically connected with the third clock signal end CK3, and the second electrode of the tenth transistor T10 is electrically connected with the driving signal output end GOUT; the first plate C41 of the fourth capacitor C4 is electrically connected with the fifth node N5, and the second plate C42 of the fourth capacitor C4 is electrically connected with the first power supply end VGH; the first plate C51 of the fifth capacitor C5 is electrically connected with the sixth node N6, and the second plate C52 of the fifth capacitor C5 is electrically connected with the driving signal output end GOUT; the first plate C61 of the sixth capacitor C6 is electrically connected with the sixth node N6, and the second plate C62 of the sixth capacitor C6 is electrically connected with the seventh node N7.

[0194] In an example embodiment, the fourth capacitor C4 can ensure the stability of the signal of the fifth node N5, and the fifth capacitor C5 and the sixth capacitor C6 can ensure the stability of the signal of the sixth node N6.

[0195] In an example embodiment, as shown in FIG. 6, the node control sub-circuit can include eleventh to fifteenth transistors T11-T15. The control electrode of the eleventh transistor T11 is electrically connected with the seventh node N7, the first electrode of the eleventh transistor T11 is electrically connected with the second node N2, and the second electrode of the eleventh transistor T11 is electrically connected with the fifth node N5; the control electrode of the twelfth transistor T12 is electrically connected with the seventh node N7, the first electrode of the twelfth transistor T12 is electrically connected with the third node N3, and the second electrode of the twelfth transistor T12 is electrically connected with the sixth node N6; the control electrode of the thirteenth transistor T13 is electrically connected with the first control signal terminal G1, the first electrode of the thirteenth transistor T13 is electrically connected with the seventh node N7, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth node N8; the control electrode of the fourteenth transistor T14 is electrically connected with the signal input terminal IN, the first electrode of the fourteenth transistor T14 is electrically connected with the masking signal terminal MS, and the second electrode of the fourteenth transistor T14 is electrically connected with the eighth node N8; and the control electrode of the fifteenth transistor T15 is electrically connected with the second control signal terminal G2, the first electrode of the fifteenth transistor T15 is electrically connected with the second power supply terminal VGL, and the second electrode of the fifteenth transistor T15 is electrically connected with the seventh node N7.

[0196] In an example embodiment, the thirteenth transistor T13 and the fourteenth transistor T14 in the node control sub-circuit can be referred to as a latch unit. When the signals of the signal output terminal IN and the first control signal terminal G1 are both valid level signals, the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, the signal of the masking signal terminal MS is written to the seventh node N7 and stored in the sixth capacitor C6, thereby controlling whether the eleventh transistor T11 and the twelfth transistor T12 are turned on, and whether the signal of the second node N2 is written to the fifth node N5 and whether the signal of the third node N3 is written to the sixth node N6, and whether the signal of the fifth node N5 and the signal of the sixth node N6 are written to the driving signal output terminal GOUT.

[0197] An example structure of the node control sub-circuit of the output control sub-circuit is shown in FIG. 6, and it is easy for those skilled in the art to understand that the implementation of the node control sub-circuit of the output control sub-circuit is not limited thereto.

[0198] In an example embodiment, the transistors can be classified into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the on voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the off voltage is a high voltage (e.g., 5V, 10V, or other suitable voltage). When the transistor is an N-type transistor, the on voltage is a high voltage (e.g., 5V, 10V, or other suitable voltage), and the off voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0199] In an example embodiment, at least one of the first transistor T1 to the eighth transistor T8 in the shift sub-circuit can be a P-type transistor.

[0200] In an example embodiment, at least one of the ninth transistor T9 to the fifteenth transistor T15 in the output sub-circuit can be a P-type transistor.

[0201] In an example embodiment, the signal of any one of the first clock signal end CK1 to the third clock signal end CK3 is a square wave signal repeatedly having a high voltage and a low voltage. For example, at least two of the first clock signal end CK1 to the third clock signal end CK3 can have the same period and can be configured as phase-shifted signals. The high voltage period in each period of the signal of any one of the first clock signal end CK1 to the third clock signal end CK3 can be set to be longer than the low voltage period.

[0202] In an example embodiment, the signal of the first power supply end VGH can be a high voltage signal, for example, 5V-10V; and the signal of the second power supply end VGL can be a low voltage signal, for example, -10V-5V.

[0203] In an example embodiment, the signal of the masking signal end MS can be a low voltage signal, or can be a high voltage signal. When the signal of the masking signal end MS is a low voltage signal, it can be -20V to -5V, and when the signal of the masking signal end MS is a high voltage signal, it can be 5V to 20V.

[0204] In an example embodiment, any of the first capacitor C1 to the sixth capacitor C6 can be a capacitor device made by a process, for example, the capacitor device can be realized by making special capacitor electrodes, and the multiple capacitor electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (for example, doped polysilicon), or the like. Alternatively, any of the first capacitor C1 to the sixth capacitor C6 can be a parasitic capacitor between multiple devices, which can be realized by a transistor itself and other devices, lines. The connection mode of any of the first capacitor C1 to the sixth capacitor C6 includes but is not limited to the above-described mode, and can be other applicable connection mode, and can only store the level of the corresponding node. Here, the example embodiment of the present disclosure does not limit this.

[0205] In an example embodiment, the driving signal output by the driving signal output end of the shift register is mainly used to control at least one transistor (for example, the fourth transistor M4) in the pixel driving circuit of the display area. When the display substrate is in a refresh frame, the driving signal output end outputs a high-level signal for a period of time, and outputs a low-level signal for the remaining period of time in a frame time, controls the fourth transistor M4 to be turned on, and realizes the refresh of the data voltage. When the display substrate is not in a refresh frame, the driving signal output end always outputs a low-level signal, and the fourth transistor M4 cannot be turned on.

[0206] In an example embodiment, the first control signal end G1 of the at least one stage of shift register is electrically connected with the cascade signal output end of the previous K1 stages of shift register, and the signal input end IN of the at least one stage of shift register is electrically connected with the cascade signal output end of the previous K2 stages of shift register, K1 is greater than K2, and the connection mode of the first control signal end and the signal input end of the shift register in the present disclosure can make the signal of the masking signal end MS can be written in advance, so as to ensure more sufficient writing.

[0207] In an example embodiment, FIG. 6 is an example for description, in which the signal received by the signal input end IN of the nth stage of shift register is the same as the signal output by the cascade signal output end Carry(n-2) of the n-2th stage of shift register, and the signal received by the first control signal end G1 of the nth stage of shift register is the same as the signal output by the cascade signal output end Carry(n-10) of the n-10th stage of shift register.

[0208] FIG. 7 is a working timing diagram of the shift sub-circuit in the shift register provided in FIG. 6. FIG. 6 is an example for description, in which the first transistor T1 to the eighth transistor T8 are all P-type transistors. In the working process of the shift register, the eighth transistor T8 is continuously turned on.

[0209] As shown in FIG. 7, the working process of the shift sub-circuit provided in an example embodiment can include the following stages:

[0210] The first stage S1, that is, the input stage, the signals of the signal input end IN and the first clock signal end CK1 are low level signals, and the signals of the second clock signal end CK2 and the third clock signal end CK3 are high level signals. The first transistor T1 is turned on, and the third transistor T3 and the seventh transistor T7 are turned off.

[0211] The first transistor T1 is turned on, and the low level signal of the signal input end IN is written into the first node N1. The low level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8. The fifth transistor T5 is turned on, and the high level signal of the third clock signal end CK3 is written into the cascade signal output end Carry. The second transistor T2 is turned on, and the high level signal of the second clock signal end CK2 is written into the second node N2. The fourth transistor T4 and the sixth transistor T6 are turned off.

[0212] In this stage, the signals of the first node N1 and the third node N3 are low level signals, the signal of the second node N2 is a high level signal, and the cascade signal output end Carry outputs a high level signal.

[0213] The second stage S2, the signal of the second clock signal end CK2 is a low level signal, and the signals of the signal input end IN, the first clock signal end CK1 and the third clock signal end CK3 are high level signals. The third transistor T3 is turned on, and the first transistor T1 and the seventh transistor T7 are turned off.

[0214] The first transistor T1 is turned off, and the high level signal of the signal input end IN cannot be written into the first node N1. Under the action of the second capacitor C2, the first node N1 and the third node N3 remain the low level signals of the last stage. The second transistor T2 is continuously turned on, the low level signal of the second clock signal end CK2 is written into the second node N2, the fifth transistor T5 is turned on, the high level signal of the third clock signal end CK3 is written into the cascade signal output end Carry, the third transistor T3 is turned on, the low level signal of the second power supply end VGL is written into the second node N2, the fourth transistor T4 is turned on, the high level signal of the first power supply end VGH is written into the cascade signal output end Carry, and the sixth transistor T6 is turned on. The high level signal of the first power supply end VGH is written into the fourth node N4.

[0215] In this stage, the signals of the first node N1, the second node N2 and the third node N3 are low level signals, the signal of the fourth node N4 is a high level signal, and the cascade signal output end Carry outputs a high level signal.

[0216] The third stage S3, the output stage, the signal of the third clock signal end CK3 is a low level signal, the signals of the signal input end IN, the first clock signal end CK1 and the second clock signal end CK2 are high level signals. The seventh transistor T7 is turned on, and the first transistor T1 and the third transistor T3 are turned off.

[0217] The first transistor T1 is turned off, and the high level signal of the signal input end IN still cannot be written into the first node N1. Under the action of the second capacitor C2, the first node N1 and the third node N3 maintain the low level signal of the last stage, the second transistor T2 is continuously turned on, the high level signal of the second clock signal end CK2 is written into the second node N2, the fifth transistor T5 is turned on, the low level signal of the third clock signal end CK3 is written into the cascade signal output end Carry, the third transistor T3 is turned off, the low level signal of the second power supply end VGL cannot be written into the second node N2, and the fourth transistor T4 and the sixth transistor T6 are turned off. Under the action of the second capacitor C2, the signal of the fourth node N4 is pulled low by the signal of the cascade signal output end Carry, so that the signals of the first node N1 and the third node N3 are low level signals.

[0218] In this stage, the signals of the first node N1, the third node N3 and the fourth node N4 are low level signals, the signal of the second node N2 is a high level signal, and the cascade signal output end Carry outputs a low level signal.

[0219] The fourth stage S4, the signals of the signal input end IN, the first clock signal end CK1, the second clock signal end CK2 and the third clock signal end CK3 are high level signals. The first transistor T1, the third transistor T3 and the seventh transistor T7 are turned off.

[0220] The first transistor T1 is turned off, and the high level signal of the signal input end IN still cannot be written into the first node N1. Under the action of the second capacitor C2, the first node N1 and the third node N3 maintain the low level signal of the last stage, the second transistor T2 is continuously turned on, the high level signal of the second clock signal end CK2 is written into the second node N2, the fifth transistor T5 is turned on, the high level signal of the third clock signal end CK3 is written into the cascade signal output end Carry, the third transistor T3 is turned off, the low level signal of the second power supply end VGL cannot be written into the second node N2, and the fourth transistor T4 and the sixth transistor T6 are turned off.

[0221] In this stage, the signals of the first node N1, the third node N3 and the fourth node N4 are low level signals, the signal of the second node N2 is a high level signal, and the cascade signal output end Carry outputs a high level signal.

[0222] In the fifth stage S5, the signal of the first clock signal terminal CK1 is a low level signal, and the signals of the signal input terminal IN, the second clock signal terminal CK2 and the third clock signal terminal CK3 are high level signals. The first transistor T1 is turned on, and the third transistor T3 and the seventh transistor T7 are turned off.

[0223] The first transistor T1 is turned on, the high level signal of the signal input terminal IN is written into the first node N1, the second transistor T2 is turned off, and the fifth transistor T5 is turned off. Under the action of the first capacitor C1, the second node N2 keeps the high level signal of the previous stage, and the fourth transistor T4 and the sixth transistor T6 are turned off.

[0224] In this stage, the signals of the first node N1, the second node N2 and the third node N3 are low level signals, the signal of the fourth node N4 is a low level signal, and the cascade signal output terminal Carry outputs a high level signal.

[0225] In the sixth stage S6, the signal of the second clock signal terminal CK2 is a low level signal, and the signals of the signal input terminal IN, the first clock signal terminal CK1 and the third clock signal terminal CK3 are high level signals. The third transistor T3 is turned on, and the first transistor T1 and the seventh transistor T7 are turned off.

[0226] The third transistor T3 is turned on, the high level signal of the second power supply terminal VGL is written into the second node N2, the fourth transistor T4 is turned on, and the high level signal of the first power supply terminal VGH is written into the cascade signal output terminal Carry. The sixth transistor T6 is turned on, and the high level signal of the first power supply terminal VGH is written into the fourth node N4. The signals of the first node N1 and the third node N3 keep the high level signal of the previous stage under the action of the second capacitor C2.

[0227] In this stage, the signals of the first node N1, the third node N3 and the fourth node N4 are low level signals, the signal of the second node N2 is a low level signal, and the cascade signal output terminal Carry outputs a high level signal.

[0228] The fifth stage S5 and the sixth stage S6 of the shift register occur cyclically until the signal of the signal input terminal is a low level signal.

[0229] In the exemplary embodiment, when the signal of the cascade signal output terminal Carry of the shift register is a low level signal, the signal of the third clock signal terminal CK3 is a low level signal, the signal of the second node N2 is a high level signal, and the signal of the third node N3 is a low level signal.

[0230] In an example embodiment, FIG. 8 is a timing diagram of the output sub-circuit in the shift register provided in FIG. 6 during a refresh frame. As shown in FIG. 8, when the display substrate is in a refresh frame, the signal at the masking signal terminal MS is a low signal during a first time period. The signal at the first control signal terminal G1 and the signal at the signal input terminal IN are low signals during the first time period.

[0231] The operation of the output sub-circuit in the shift register during a refresh frame includes:

[0232] The signal at the first control signal terminal G1 and the signal at the signal input terminal IN are high signals, and the signal at the masking signal terminal MS is a low signal. The thirteenth transistor T13 and the fourteenth transistor T14 are turned on.

[0233] The thirteenth transistor T13 and the fourteenth transistor T14 are turned on, and the low signal at the masking signal terminal MS is written to the seventh node N7. The eleventh transistor T11 and the twelfth transistor T12 are turned on, the signal at the second node N2 is the same as the signal at the fifth node N5, and the signal at the third node N3 is the same as the signal at the sixth node N6. Therefore, during the operation of the shift register, the operation state of the ninth transistor T9 is the same as the operation state of the fourth transistor T4, the operation state of the tenth transistor T10 is the same as the operation state of the fifth transistor T5, and the signal output at the drive signal output terminal GOUT is the same as the signal output at the cascade signal output terminal Carry.

[0234] The shift register provided in the present disclosure can keep the signal at the drive signal output terminal GOUT the same as the signal output at the cascade signal output terminal Carry during a refresh frame, and can keep the high refresh rate of the display substrate.

[0235] Therefore, when the high refresh rate is required in at least one area of the display substrate, the low signal is input to the masking signal terminal MS, the same signal as the cascade signal output terminal Carry is output at the drive signal output terminal, and the transistors corresponding to the pixel driving circuit in the display substrate are turned on. The data voltage in the display substrate is charged, and the high refresh rate of the area is achieved.

[0236] In an example embodiment, FIG. 9 is a timing diagram of the output sub-circuit in the shift register provided in FIG. 6 during a hold frame. As shown in FIG. 9, when the display substrate is in a hold frame, the signal at the masking signal terminal MS is a high signal during a first time period.

[0237] The operation of the output sub-circuit in the shift register during a hold frame includes:

[0238] The signal at the first control signal terminal G1 and the signal at the signal input terminal IN are high signals, and the signal at the masking signal terminal MS is a high signal. The thirteenth transistor T13 and the fourteenth transistor T14 are turned on.

[0239] The thirteenth transistor T13 and the fourteenth transistor T14 are turned on, the high level signal of the mask signal end MS is written to the seventh node N7, and the eleventh transistor T11 and the twelfth transistor T12 are turned off. The signal of the sixth node N6 is a high level signal, the tenth transistor T10 is turned off, the signal of the fifth node N5 is a low level signal, the ninth transistor T9 is turned on, and the high level signal of the first power supply end VGH is written to the driving signal output end GOUT.

[0240] In the exemplary embodiment, the second control signal end G2 is a low level signal in the part of time after the signal of the cascade signal output end is a low level signal, that is, when the signal of the second control signal end G2 is a low level signal, the signal of the cascade signal output end GOUT is a high level signal. When the signal of the second control signal end G2 is a low level signal, the fifteenth transistor T15 is turned on, the low level signal of the second power supply end VGL is written to the seventh node N7, the eleventh transistor T11 and the twelfth transistor T12 are turned on, the signal of the second node N2 is the same as the signal of the fifth node N5, and the signal of the third node N3 is the same as the signal of the sixth node N6. Therefore, in the working process of the shift register, the working state of the ninth transistor T9 is the same as that of the fourth transistor T4, the working state of the tenth transistor T10 is the same as that of the fifth transistor T5, and the driving signal output end GOUT outputs a high level signal. The setting of the fifteenth transistor T15 can ensure the reliability of the shift register.

[0241] The shift register provided by the present disclosure can continuously output a high level signal from the driving signal output end GOUT when maintaining a frame, and the low refresh rate of the display substrate can be maintained.

[0242] Therefore, when the low refresh rate is required in at least one region of the display substrate, the mask signal end MS is input with a high level signal, the driving signal output end always outputs a high level signal to make the transistors corresponding to the pixel driving circuit in the display substrate be turned off, the data voltage in the display substrate is not charged, the state of the last frame is maintained, and the low refresh rate of the region is realized.

[0243] The present disclosure further provides a driving method of a shift register, configured to drive the shift register provided by any one of the preceding embodiments. The driving method of the shift register can include the following steps:

[0244] Step 100, the shift sub-circuit provides the signal of one of the second power supply terminal and the second clock signal terminal to the second node, provides the signal of the signal input terminal to the third node, and provides the signal of one of the first power supply terminal and the third clock signal terminal to the cascade signal output terminal under the control of the signals of the second node and the third node.

[0245] Step 200, the output sub-circuit provides the signal of one of the first power supply terminal and the third clock signal terminal to the driving signal output terminal under the control of the signals of at least one of the second node, the third node, the first control signal terminal, the second control signal terminal, the signal input terminal and the masking signal terminal.

[0246] The display substrate provided by the embodiments of the present disclosure comprises a display area and a non-display area surrounding at least one side of the display area, and the display substrate comprises a first gate drive circuit located in the non-display area, wherein the first gate drive circuit comprises a plurality of cascaded first shift registers, and the first shift register is the shift register provided by any one of the foregoing embodiments.

[0247] In the example embodiment, the cascade signal output terminals of the nth stage first shift register are respectively electrically connected to the signal input terminals of the (n+X)th stage first shift register and the first control signal terminals of the (n+Y)th stage first shift register, 1≤n≤N, N is the total number of stages of the first shift register, and X<Y. For example, the cascade signal output terminals of the nth stage first shift register can be respectively electrically connected to the signal input terminals of the (n+2)th stage first shift register and the first control signal terminals of the (n+10)th stage first shift register.

[0248] In the example embodiment, FIG. 10 is a structural schematic diagram of the display substrate provided by the embodiments of the present disclosure, and FIG. 11 is a connection schematic diagram of the cross-stage connection lines. As shown in FIG. 10, the display substrate can further comprise a plurality of cross-stage connection lines NL located in the non-display area. FIG. 10 is described by taking four-stage shift registers as the nth stage first shift register GOA(n), the (n+1)th stage first shift register GOA(n+1), the (n+2)th stage first shift register GOA(n+2) and the (n+3)th stage first shift register GOA(n+3) as examples.

[0249] As shown in FIG. 10 and FIG. 11, one of the plurality of cross-stage connection lines NL is respectively electrically connected to the cascade signal output terminal of at least one stage first shift register, the signal input terminal of at least one stage first shift register and the first control signal terminal of at least one stage first shift register.

[0250] In the example embodiment, at least two of the shift register in which the cascade signal output end connected by the cross-stage connection line is located, the shift register in which the signal input end connected is located, and the shift register in which the first control signal end connected is located are different stage shift registers.

[0251] In the example embodiment, as shown in FIGS. 10 and 11, the cross-stage connection line includes a first cross-stage connection portion NL1, a second cross-stage connection portion NL2, and a third cross-stage connection portion NL3, at least one of the first cross-stage connection portion NL1, the second cross-stage connection portion NL2, and the third cross-stage connection portion NL3 extends at least partially along the second direction D2.

[0252] In the example embodiment, as shown in FIGS. 10 and 11, the second cross-stage connection portion NL2 is electrically connected with the first cross-stage connection portion NL1 and the third cross-stage connection portion NL3 respectively, and at least two of the first cross-stage connection portion NL1, the second cross-stage connection portion NL2, and the third cross-stage connection portion NL3 are arranged in different layers.

[0253] In the example embodiment, the at least one stage first shift register includes a first transistor to a fifteenth transistor, a first capacitor to a sixth capacitor. The second capacitor and the third capacitor include a first plate and a second plate. The first electrode of the first transistor and the control electrode of the fourteenth transistor are electrically connected with the signal input end of the first shift register respectively, the control electrode of the thirteenth transistor is electrically connected with the first control signal end of the first shift register, and the second plate of the second capacitor and the second plate of the third capacitor are electrically connected with the cascade signal output end of the first shift register respectively.

[0254] As shown in FIGS. 10 and 11, taking X=2 and Y=10 as an example, for the cross-stage connection line NL(n) electrically connected with the cascade signal output end of the nth stage first shift register, the signal output end of the n+2 stage first shift register, and the first control signal end of the n+10 stage first shift register respectively, the first cross-stage connection portion NL1(n) is electrically connected with the second plate C22(n) of the second capacitor and the second plate C32(n) of the third capacitor of the nth stage first shift register and the second cross-stage connection portion NL2(n) respectively, and the third cross-stage connection portion NL3(n) is electrically connected with the first electrode 13(n+2) of the first transistor and the control electrode 142(n+2) of the fourteenth transistor of the n+2 stage first shift register, the control electrode 132(n+10) of the thirteenth transistor of the n+10 stage first shift register, and the second cross-stage connection portion NL2(n) respectively.

[0255] As shown in FIGS. 10 and 11, the first wire connecting the second plate C22(n) of the second capacitor and the second plate C32(n) of the third capacitor of the first shift register at the n-th stage and the first electrode 13(n+2) of the first transistor and the control electrode 142(n+2) of the fourteenth transistor of the first shift register at the n+2-th stage includes a first inter-stage connection part NL1(n) across the inter-stage connection line NL(n), a second inter-stage connection part NL2(n), and a partial third inter-stage connection part NL3(n), while the second wire connecting the second plate C22(n) of the second capacitor and the second plate C32(n) of the third capacitor of the first shift register at the n-th stage and the control electrode 132(n+10) of the thirteenth transistor of the first shift register at the n+10-th stage is the entire inter-stage connection line NL(n), and the first inter-stage connection part NL1(n), the second inter-stage connection part NL2(n), and the partial third inter-stage connection part NL3(n) in the first wire and the second wire are shared, which realizes the sharing of partial wires in the shift register, saves the space occupied by the shift register, and further realizes the narrow frame of the display substrate.

[0256] In an example embodiment, the display substrate further includes: a substrate and a driving circuit layer disposed on the substrate; the first gate driving circuit is disposed on the driving circuit layer, and the driving circuit layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer which are sequentially stacked on the substrate, and the at least one first shift register includes: at least one transistor and at least one capacitor, the at least one transistor includes: an active pattern, a control electrode, a first electrode, and a second electrode, and the at least one capacitor includes: a first plate and a second plate.

[0257] In an example embodiment, the semiconductor layer includes: the active pattern of the at least one transistor of the at least one first shift register.

[0258] In an example embodiment, the first conductive layer includes: the control electrode of the at least one transistor and the first plate of the at least one capacitor of the at least one first shift register.

[0259] In an example embodiment, the second conductive layer includes: the second plate of the at least one capacitor of the at least one first shift register and a first inter-stage connection part NL1 of at least one inter-stage connection line.

[0260] In an example embodiment, the third conductive layer includes: the first electrode and the second electrode of the at least one transistor of the at least one first shift register and a second inter-stage connection part NL2 of at least one inter-stage connection line.

[0261] In an exemplary embodiment, the fourth conductive layer comprises a third cross-stage connection part NL3 of at least one cross-stage connection line of the plurality of cross-stage connection lines.

[0262] In an exemplary embodiment, as shown in FIG. 11, the second plate of the second capacitor and the second plate of the third capacitor in the at least one stage of the first shift register are the same plate. FIG. 11 is an example of taking the second plate C22(n) of the second capacitor and the second plate C32(n) of the third capacitor in the nth stage of the first shift register as the same plate for illustration. Taking the second plate of the second capacitor and the second plate of the third capacitor in the at least one stage of the first shift register as the same plate can reduce the area occupied by the shift register and narrow the frame.

[0263] In an exemplary embodiment, as shown in FIG. 11, for the cross-stage connection line NL(n) connected to the cascade signal output end of the nth stage of the first shift register, the first cross-stage connection part NL1(n) is in one structure with the second plate C22(n) of the second capacitor in the nth stage of the first shift register.

[0264] In an exemplary embodiment, as shown in FIG. 10, the first cross-stage connection part NL1 in at least one cross-stage connection line of the plurality of cross-stage connection lines at least partially overlaps the first electrode 13 of the first transistor of the at least one stage of the first shift register in the orthographic projection on the substrate.

[0265] In an exemplary embodiment, as shown in FIG. 10, the second cross-stage connection part NL2 in at least one cross-stage connection line of the plurality of cross-stage connection lines at least partially overlaps the control electrode 112 of the eleventh transistor of the at least one stage of the first shift register in the orthographic projection on the substrate.

[0266] In an exemplary embodiment, as shown in FIG. 10, the third cross-stage connection part NL3 in at least one cross-stage connection line of the plurality of cross-stage connection lines at least partially overlaps the control electrode of at least one of the thirteenth transistor and the fourteenth transistor of the at least one stage of the first shift register in the orthographic projection on the substrate. FIG. 10 is an example of taking the third cross-stage connection part NL3 in at least one cross-stage connection line of the plurality of cross-stage connection lines at least partially overlapping the control electrode 132 of the thirteenth transistor and the control electrode 142 of the fourteenth transistor of the at least one stage of the first shift register in the orthographic projection on the substrate for illustration.

[0267] In an example embodiment, FIG. 12 is another schematic view of a display substrate. FIG. 12 is described by taking a first-stage first shift register as an example. The display substrate further includes a clock signal line group located in the non-display area, the clock signal line group is arranged on the driving circuit layer and located in the fourth conductive layer. A plurality of cross-stage connection lines NL are located on the side of the clock signal line group close to the display area.

[0268] As shown in FIG. 12, the clock signal line group includes a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3 and a fourth clock signal line CLK4 arranged in sequence along the side close to the display area, and at least one of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 at least partially extends along the second direction D2.

[0269] The display substrate in the present disclosure includes the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4, which can reduce the load of the clock signal line and further improve the reliability of the display substrate.

[0270] In an example embodiment, the first clock signal end of the 4i-3 stage first shift register is electrically connected with the first clock signal line CLK1, the second clock signal end of the 4i-3 stage first shift register is electrically connected with the second clock signal line CLK2, the third clock signal end of the 4i-3 stage first shift register is electrically connected with the third clock signal line CLK3, the first clock signal end of the 4i-2 stage first shift register is electrically connected with the second clock signal line CLK2, the second clock signal end of the 4i-2 stage first shift register is electrically connected with the third clock signal line CLK3, the third clock signal end of the 4i-2 stage first shift register is electrically connected with the fourth clock signal line CLK4, the first clock signal end of the 4i-1 stage first shift register is electrically connected with the third clock signal line CLK3, the second clock signal end of the 4i-1 stage first shift register is electrically connected with the fourth clock signal line CLK4, the third clock signal end of the 4i-1 stage first shift register is electrically connected with the first clock signal line CLK1, the first clock signal end of the 4i stage first shift register is electrically connected with the fourth clock signal line CLK4, the second clock signal end of the 4i stage first shift register is electrically connected with the first clock signal line CLK1, and the third clock signal end of the 4i stage first shift register is electrically connected with the second clock signal line CLK2.

[0271] In an exemplary embodiment, as shown in FIG. 12, the normal projection of the clock signal line group on the substrate at least partially overlaps with the normal projection of at least one of the first transistor T1, the second transistor T2, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 in the at least one stage of the first shift register on the substrate.

[0272] FIG. 13 is a signal timing diagram of the clock signal lines. As shown in FIG. 13, the time during which the signal of at least two of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, and the fourth clock signal line CLK4 is a low-level signal does not overlap. The length of time during which the signal of at least one of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, and the fourth clock signal line CLK4 is a high-level signal in a cycle is greater than the length of time during which the signal is a low-level signal.

[0273] In an exemplary embodiment, as shown in FIG. 12, the display substrate further includes: a power signal line group and a clock signal line group located in the non-display area, the power signal line group and the clock signal line group being disposed in the driving circuit layer and located in the fourth conductive layer.

[0274] In an exemplary embodiment, as shown in FIG. 12, the power signal line group includes: two first power lines and two second power lines, the first power lines and the second power lines extending at least partially along the second direction D2. The first second power line VGL-1 is located on the side of the clock signal line group away from the display area, the first first power line VGH-1 is located on the side of the clock signal line group close to the display area, the second second power line VGL-2 is located on the side of the first first power line VGH-1 close to the display area, the second first power line VGH-2 is located on the side of the second second power line VGL-2 close to the display area, and the plurality of stage-crossing connection lines NL are located between the second second power line VGL-2 and the second first power line VGH-2.

[0275] In an exemplary embodiment, the first power lines are electrically connected to the first power supply end of the at least one stage of the first shift register, and the second power lines are electrically connected to the second power supply end of the at least one stage of the first shift register.

[0276] In an exemplary embodiment, as shown in FIG. 12, the normal projection of the first first power line VGH-1 on the substrate at least partially overlaps with the normal projection of the fourth transistor T4 and the fifth transistor T5 in the at least one stage of the first shift register on the substrate.

[0277] In an exemplary embodiment, as shown in FIG. 12, the normal projection of the first second power line VGL-1 on the substrate at least partially overlaps with the normal projection of the third transistor T3 in the at least one stage of the first shift register on the substrate.

[0278] In an exemplary embodiment, as shown in FIG. 12, the orthogonal projection of the second first power line VGH-2 on the base at least partially overlaps the orthogonal projection of the ninth transistor T9 and the tenth transistor T10 in the at least one first shift register on the base.

[0279] In an exemplary embodiment, as shown in FIG. 12, the orthogonal projection of the second second power line VGL-2 on the base at least partially overlaps the orthogonal projection of the third capacitor C3 in the at least one first shift register on the base.

[0280] In an exemplary embodiment, as shown in FIG. 12, the display substrate further comprises a scan initial signal line STV located in the non-display area, the scan initial signal line STV is arranged in the driving circuit layer and located in the fourth conductive layer, and the scan initial signal line STV at least partially extends along the second direction D2.

[0281] In an exemplary embodiment, as shown in FIG. 12, the scan initial signal line STV is located between the first second power line VGL-1 and the clock signal line group.

[0282] In an exemplary embodiment, the signal input end of the first stage first shift register and the signal input end of the second stage first shift register are respectively electrically connected with the scan initial signal line;

[0283] In an exemplary embodiment, the orthogonal projection of the scan initial signal line STV on the base at least partially overlaps the orthogonal projection of the second transistor T2 in the at least one first shift register on the base.

[0284] In an exemplary embodiment, as shown in FIG. 12, the power signal line group can further comprise a third power line VSL, and the third power line VSL at least partially extends along the second direction D2.

[0285] In an exemplary embodiment, the display area is provided with light emitting devices, and the third power line VSL is electrically connected with the second electrode of at least one light emitting device;

[0286] In an exemplary embodiment, as shown in FIG. 12, the third power line VSL is located between the first first power line VGH-1 and the second second power line VGL-2.

[0287] In an exemplary embodiment, as shown in FIG. 12, the orthogonal projection of the third power line VSL on the base at least partially overlaps the orthogonal projection of the first capacitor C1 and the second capacitor C2 of the at least one first shift register on the base.

[0288] In an exemplary embodiment, as shown in FIG. 12, the third power supply line VSL has a length along the first direction D1 that is greater than a length of at least one of the first power supply line and the second power supply line along the first direction D1, the first direction and the second direction intersect, and the first direction D1 and the second direction D2 can be perpendicular, for example.

[0289] In an exemplary embodiment, as shown in FIG. 12, the display substrate can further include a mask signal line MSL located in the non-display area, the mask signal line MSL being disposed in the driving circuit layer and located in the fourth conductive layer, and the mask signal line MSL extending at least partially along the second direction D2.

[0290] In an exemplary embodiment, as shown in FIG. 12, the mask signal line MSL is located on a side of the power supply signal line group close to the display area.

[0291] In an exemplary embodiment, the mask signal line MSL is electrically connected to a mask signal terminal of the at least one stage of the first shift register.

[0292] In an exemplary embodiment, as shown in FIG. 12, a projection of the mask signal line MSL on the base at least partially overlaps a projection of the fourth capacitor C2 and the fifth capacitor C5 of the at least one stage of the first shift register on the base.

[0293] In an exemplary embodiment, as shown in FIG. 12, the display substrate can further include a plurality of pixel initial signal lines located in the non-display area. At least one of the plurality of pixel initial signal lines is disposed in the driving circuit layer and located in the fourth conductive layer, and the at least one of the plurality of pixel initial signal lines extends at least partially along the second direction D2. FIG. 12 illustrates an example in which the plurality of pixel initial signal lines includes a first initial signal line INIT1, a second initial signal line INIT2, and a third initial signal line INIT3.

[0294] In an exemplary embodiment, as shown in FIG. 12, the plurality of pixel initial signal lines are located on a side of the mask signal line MSL close to the display area.

[0295] In an exemplary embodiment, as shown in FIG. 12, a projection of one of the plurality of pixel initial signal lines on the base at least partially overlaps a projection of the fourth capacitor C4 and the fifth capacitor C5 of the at least one stage of the first shift register on the base. FIG. 12 illustrates an example in which a projection of the first initial signal line INIT1 on the base at least partially overlaps a projection of the fourth capacitor C4 and the fifth capacitor C5 of the at least one stage of the first shift register on the base.

[0296] The orthogonal projection of one of the plurality of pixel initial signal lines in the present disclosure on the substrate at least partially overlaps the orthogonal projection of the fourth capacitor C4 and the fifth capacitor C5 of the at least one first shift register on the substrate, which can reduce the area occupied by the shift register and achieve a narrow frame of the display substrate.

[0297] In an example embodiment, as shown in FIG. 12, the length of at least one of the plurality of pixel initial signal lines along the first direction D1 is greater than the length of the mask signal line MSL along the first direction D1. The length of at least one of the plurality of pixel initial signal lines along the first direction D1 being greater than the length of the mask signal line MSL along the first direction D1 can reduce the load of at least one of the plurality of pixel initial signal lines.

[0298] In an example embodiment, the display substrate further includes a second gate drive circuit located in the non-display area, and the second gate drive circuit includes a plurality of cascaded second shift registers, and each of the second shift registers includes a light-emitting signal output end.

[0299] In an example embodiment, the at least one first shift register is electrically connected to a write transistor in the at least one row of pixel drive circuits, and the at least one second shift register is electrically connected to a light-emitting transistor in the at least one row of pixel drive circuits.

[0300] In an example embodiment, the second control signal end of the at least one first shift register is electrically connected to the signal output end of the at least one second shift register.

[0301] In an example embodiment, the display substrate further includes a light-emitting structure layer located on the side of the drive circuit layer away from the substrate. The light-emitting structure layer can include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the pixel drive circuit through a via hole. The organic light-emitting layer is connected to the anode. The cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and the cathode.

[0302] In an example embodiment, the display substrate can further include an encapsulation structure layer located on the side of the light-emitting structure layer away from the substrate. The encapsulation structure layer can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer can be made of inorganic materials, and the second encapsulation layer can be made of an organic material. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can prevent external moisture from entering the light-emitting structure layer.

[0303] In the example embodiment, the display substrate can further include a touch structure layer located on the side of the encapsulation structure layer away from the base. The touch structure layer can include a first touch insulating layer disposed on the encapsulation structure layer, a first touch metal layer disposed on the first touch insulating layer, a second touch insulating layer covering the first touch metal layer, a second touch metal layer disposed on the second touch insulating layer, and a touch protection layer covering the second touch metal layer. The first touch metal layer can include a plurality of bridge electrodes. The second touch metal layer can include a plurality of first touch electrodes and second touch electrodes. The first touch electrodes or the second touch electrodes can be connected to the bridge electrodes through vias.

[0304] In the example embodiment, the display substrate of the present disclosure can be applied to a display device with a gate driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED), or quantum dot light-emitting diode display (QDLED), etc., which are not limited by the present disclosure.

[0305] The following is an example description through the preparation process of the display substrate. The "patterning process" of the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist, etc. for metal materials, inorganic materials, or transparent conductive materials, and includes coating organic materials, mask exposure, and development, etc. for organic materials. Deposition can use any one or more of sputtering, evaporation, or chemical vapor deposition, coating can use any one or more of spraying, spin coating, and inkjet printing, and etching can use any one or more of dry etching and wet etching, which are not limited by the present disclosure. "Thin film" refers to a thin film of a certain material made on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process throughout the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" requires a patterning process throughout the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". The "A and B are disposed in the same layer" of the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the example embodiment of the present disclosure, "the orthographic projection of B is located within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0306] (1) forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern can include depositing a semiconductor thin film on the substrate, patterning the semiconductor thin film by a patterning process, and forming the semiconductor layer pattern. As shown in FIG. 14, FIG. 14 is a schematic diagram after the semiconductor layer pattern is formed in FIG. 12.

[0307] In an exemplary embodiment, as shown in FIG. 14, the semiconductor layer pattern can include at least: the active pattern 11 of the first transistor, the active pattern 21 of the second transistor, the active pattern 31 of the third transistor, the active pattern 41 of the fourth transistor, the active pattern 51 of the fifth transistor, the active pattern 61 of the sixth transistor, the active pattern 71 of the seventh transistor, the active pattern 81 of the eighth transistor, the active pattern 91 of the ninth transistor, the active pattern 101 of the tenth transistor, the active pattern 111 of the eleventh transistor, the active pattern 121 of the twelfth transistor, the active pattern 131 of the thirteenth transistor, the active pattern 141 of the fourteenth transistor, and the active pattern 151 of the fifteenth transistor.

[0308] In an exemplary embodiment, as shown in FIG. 14, the active pattern 41 of the fourth transistor, the active pattern 51 of the fifth transistor, the active pattern 61 of the sixth transistor, the active pattern 71 of the seventh transistor, and the active pattern 81 of the eighth transistor are in one structure. The active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor are in one structure. The active pattern 131 of the thirteenth transistor, the active pattern 141 of the fourteenth transistor, and the active pattern 151 of the fifteenth transistor are in one structure. The active pattern 11 of the first transistor, the active pattern 21 of the second transistor, the active pattern 31 of the third transistor, the active pattern 111 of the eleventh transistor, and the active pattern 121 of the twelfth transistor are separately arranged.

[0309] In the exemplary embodiment, as shown in FIG. 14, the active pattern 21 of the second transistor is located on a side of the active pattern 31 of the third transistor close to the display area, the active pattern 11 of the first transistor is located on a side of the active pattern 21 of the second transistor close to the display area, the active pattern 71 of the seventh transistor and the active pattern 81 of the eighth transistor of at least one stage of the first shift register are located on a side of the active pattern 11 of the first transistor close to the next stage of the first shift register, the active pattern 41 of the fourth transistor, the active pattern 51 of the fifth transistor, and the active pattern 61 of the sixth transistor are located on a side of the active pattern 71 of the seventh transistor and the active pattern 11 of the first transistor close to the display area. The active pattern 111 of the eleventh transistor and the active pattern 121 of the twelfth transistor are located on a side of the integrated structure of the active pattern 41 of the fourth transistor, the active pattern 51 of the fifth transistor, the active pattern 61 of the sixth transistor, the active pattern 71 of the seventh transistor, and the active pattern 81 of the eighth transistor close to the display area. The integrated structure of the active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor and the integrated structure of the active pattern 131 of the thirteenth transistor, the active pattern 141 of the fourteenth transistor, and the active pattern 151 of the fifteenth transistor are located on a side of the active pattern 121 of the twelfth transistor close to the display area, and the integrated structure of the active pattern 131 of the thirteenth transistor, the active pattern 141 of the fourteenth transistor, and the active pattern 151 of the fifteenth transistor of at least one stage of the first shift register are located on a side of the integrated structure of the active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor close to the next stage of the first shift register.

[0310] In the exemplary embodiment, the shape of the active pattern 11 of the first transistor of at least one stage of the first shift register is an "n" letter shape with an opening facing the previous stage of the first shift register.

[0311] In the exemplary embodiment, the shape of any one of the active pattern 21 of the second transistor, the active pattern 31 of the third transistor, the active pattern 41 of the fourth transistor, the active pattern 51 of the fifth transistor, the active pattern 61 of the sixth transistor, the active pattern 81 of the eighth transistor, the active pattern 91 of the ninth transistor, and the active pattern 101 of the tenth transistor is a strip shape and extends along the second direction D2.

[0312] In the exemplary embodiment, at least one of the active pattern 71 of the seventh transistor, the active pattern 131 of the thirteenth transistor, the active pattern 141 of the fourteenth transistor, and the active pattern 151 of the fifteenth transistor extends at least partially along the first direction D1.

[0313] In an example embodiment, the active pattern 111 of the eleventh transistor includes a first active portion and a second active portion connected to each other, the first active portion extends along the first direction D1, the second active portion extends along the second direction D2, and the first active portion and the second active portion are arranged at right angles. The first active portion is located on a side of the second active portion away from the display region.

[0314] In an example embodiment, the active pattern 121 of the twelfth transistor includes a third active portion and a fourth active portion connected to each other, the third active portion extends along the first direction D1, the fourth active portion extends along the second direction D2, and the third active portion and the fourth active portion are arranged at right angles. The third active portion is located on a side of the fourth active portion away from the display region. The fourth active portion is located on a side of the second active portion close to the display region, and a straight line extending along the second direction through the fourth active portion passes through the first active portion, and a straight line extending along the second direction through the second active portion passes through the third active portion.

[0315] In an example embodiment, at least one of the active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor has a length along the first direction D1 greater than that of at least one of the active pattern 41 of the fourth transistor and the active pattern 51 of the fifth transistor, so that the ninth transistor and the tenth transistor have stronger driving capability.

[0316] In an example embodiment, the active pattern of each transistor can include a first region, a second region, and a channel region located between the first region and the second region.

[0317] As shown in FIG. 14, the first region 41-1 of the active pattern 41 of the fourth transistor can be as the first region 61-1 of the active pattern 61 of the sixth transistor, the second region 41-2 of the active pattern 41 of the fourth transistor can be as the second region 41-2 of the active pattern 51 of the fifth transistor, the second region 61-2 of the active pattern 61 of the sixth transistor can be as the first region 71-1 of the active pattern 71 of the seventh transistor, the second region 71-2 of the active pattern 71 of the seventh transistor can be as the first region 81-1 of the active pattern 81 of the eighth transistor, the second region 91-2 of the active pattern 91 of the ninth transistor can be as the second region 101-2 of the active pattern 101 of the tenth transistor, the first region 131-1 of the active pattern 131 of the thirteenth transistor can be as the second region 151-2 of the active pattern 151 of the fifteenth transistor, the second region 131-2 of the active pattern 131 of the thirteenth transistor can be as the second region 141-2 of the active pattern 141 of the fourteenth transistor, the first region 11-1 and the second region 11-2 of the active pattern 11 of the first transistor, the first region 21-1 of the active pattern 21 of the second transistor, the first region 31-1 and the second region 31-2 of the active pattern 31 of the third transistor, the first region 51-1 of the active pattern 51 of the fifth transistor, the second region 81-2 of the active pattern 81 of the eighth transistor, the first region 91-1 of the active pattern 91 of the ninth transistor, the first region 101-1 of the active pattern 101 of the tenth transistor, the first region 111-1 and the second region 111-2 of the active pattern 111 of the eleventh transistor, the first region 121-1 and the second region 121-2 of the active pattern 121 of the twelfth transistor, the first region 141-1 of the active pattern 141 of the fourteenth transistor, and the first region 151-1 of the active pattern 151 of the fifteenth transistor are separately provided.

[0318] (2) Forming the first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern can include: depositing a first insulating thin film and a first conductive thin film on the substrate on which the aforementioned patterns are formed, patterning the first conductive thin film by a patterning process, forming a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the first insulating layer, as shown in FIGS. 15 to 16, FIG. 15 is a schematic diagram of the first conductive layer pattern in FIG. 12, and FIG. 16 is a schematic diagram of FIG. 12 after forming the first conductive layer pattern. In an exemplary embodiment, the first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0319] In an exemplary embodiment, as shown in FIGS. 15 and 16, the first conductive layer pattern can include at least: the control electrodes 12 of the first transistor to the control electrodes 152 of the fifteenth transistor in each stage of the first shift register, and the first plate C111 of the first capacitor to the first plate C61 of the sixth capacitor.

[0320] In the example embodiment, the control electrode 12 of the first transistor is separately provided. The control electrode 12 of the first transistor is in a strip shape and extends along the first direction D1. The control electrode 12 of the first transistor overlaps the active pattern of the first transistor in two regions, and thus the first transistor is in a double-gate structure.

[0321] In the example embodiment, the control electrode 22 of the second transistor is separately provided. The control electrode 22 of the second transistor is in a strip shape and extends along the first direction D1.

[0322] In the example embodiment, the control electrode 32 of the third transistor is separately provided. The control electrode 32 of the third transistor is in a broken line shape and extends at least partially along the second direction D2.

[0323] In the example embodiment, the control electrode 42 of the fourth transistor, the control electrode 62 of the sixth transistor, and the first plate C11 of the first capacitor are in an integrated structure. The control electrode 42 of the fourth transistor and the control electrode 62 of the sixth transistor are in a strip shape and extend along the first direction D1, and the main structure of the first plate C11 of the first capacitor is in a rectangular shape. The control electrode 42 of the fourth transistor and the control electrode 62 of the sixth transistor are located on a side of the first plate C11 of the first capacitor away from the display area.

[0324] In the example embodiment, the control electrode 52 of the fifth transistor and the first plate C21 of the second capacitor are in an integrated structure. The control electrode 52 of the fifth transistor includes a plurality of gate lines along the second direction D2, at least one of which extends along the first direction D1. The first plate C21 of the second capacitor is in a block shape, and the plurality of gate lines are electrically connected to the first plate C21 of the second capacitor. The control electrode 52 of the fifth transistor is located on a side of the first plate C21 of the second capacitor away from the display area.

[0325] In the example embodiment, the control electrode 72 of the seventh transistor is separately provided, and the control electrode 72 of the seventh transistor is in a “├” shape.

[0326] In the example embodiment, the control electrode 82 of the eighth transistor is separately provided, and the control electrode 82 of the eighth transistor is in a broken line shape and extends at least partially along the first direction D1.

[0327] In the example embodiment, the control electrode 92 of the ninth transistor and the first plate C41 of the fourth capacitor are in an integrated structure. The control electrode 92 of the ninth transistor is in a strip shape and extends along the first direction D1, and the first plate C41 of the fourth capacitor is in a block shape. The control electrode 92 of the ninth transistor is located on a side of the first plate C41 of the fourth capacitor away from the display area.

[0328] In an example embodiment, the control electrode 102 of the tenth transistor, the first plate C51 of the fifth capacitor, and the first plate C61 of the sixth capacitor are in one structure. The control electrode 102 of the tenth transistor includes: a plurality of gate strips along the second direction D2, at least one of the gate strips extending along the first direction D1, the first plate C51 of the fifth capacitor being in a block shape, and the plurality of gate strips being electrically connected to the first plate C51 of the fifth capacitor, the first plate C61 of the sixth capacitor being in a block shape and being electrically connected to one of the plurality of gate strips, the control electrode 102 of the tenth transistor and the first plate C61 of the sixth capacitor being located on a side of the first plate C51 of the fifth capacitor away from the display region, and the first plate C61 of the sixth capacitor and the first plate C51 of the fifth capacitor being located at both ends of the at least one of the gate strips.

[0329] In an example embodiment, the control electrode 112 of the eleventh transistor and the control electrode 122 of the twelfth transistor are in one structure. The control electrode 112 of the eleventh transistor is in a shape of a broken line with an included angle of 90 degrees and extends at least partially along the second direction D2. The control electrode 122 of the twelfth transistor is in a shape of a broken line with an included angle of 90 degrees and extends at least partially along the first direction D1.

[0330] In an example embodiment, the control electrode 132 of the thirteenth transistor is separately provided. The control electrode 132 of the thirteenth transistor is in a block shape.

[0331] In an example embodiment, the control electrode 142 of the fourteenth transistor is separately provided. The control electrode 142 of the fourteenth transistor is in a shape of a broken line and in a shape of a "┘" character. In FIG. 15, a first part of the control electrode 142(n) of the fourteenth transistor of the nth-stage first shift register and a second part of the control electrode 142(n-1) of the fourteenth transistor of the n-1th-stage first shift register are shown, and the control electrode of the fourteenth transistor of one first shift register is a combination of the first part and the second part in FIG. 15.

[0332] In an example embodiment, the control electrode 152 of the fifteenth transistor is separately provided. The control electrode 152 of the fifteenth transistor is in a shape of a strip and extends along the first direction D1.

[0333] In an example embodiment, the first plate C31 of the third capacitor is separately provided. The main part of the first plate 31 of the third capacitor can be in a rectangular shape.

[0334] In the exemplary embodiment, the control electrode 12 of the first transistor is disposed across the active pattern of the first transistor, the control electrode 22 of the second transistor is disposed across the active pattern of the second transistor, the control electrode 32 of the third transistor is disposed across the active pattern of the third transistor, the control electrode 42 of the fourth transistor (also the control electrode 62 of the sixth transistor and the first electrode plate C11 of the first capacitor) is disposed across the active pattern of the fourth transistor and the active pattern of the sixth transistor, the control electrode 52 of the fifth transistor (also the first electrode plate C21 of the second capacitor) is disposed across the active pattern of the fifth transistor, the control electrode 72 of the seventh transistor is disposed across the active pattern of the seventh transistor, the control electrode 82 of the eighth transistor is disposed across the active pattern of the eighth transistor, the control electrode 92 of the ninth transistor (also the first electrode plate C41 of the fourth capacitor) is disposed across the active pattern of the ninth transistor, the control electrode 102 of the tenth transistor (also the first electrode plate C51 of the fifth capacitor and the first electrode plate C61 of the sixth capacitor) is disposed across the active pattern of the tenth transistor, the control electrode 112 of the eleventh transistor (also the control electrode 122 of the twelfth transistor) is disposed across the active pattern of the eleventh transistor and the active pattern of the twelfth transistor, the control electrode 132 of the thirteenth transistor is disposed across the active pattern of the thirteenth transistor, the control electrode 142 of the fourteenth transistor is disposed across the active pattern of the fourteenth transistor, and the control electrode 152 of the fifteenth transistor is disposed across the active pattern of the fifteenth transistor.

[0335] In the exemplary embodiment, after the first conductive layer pattern is formed, the semiconductor layer can be subjected to a conductorization process using the first conductive layer as a shield, the semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first transistor to the twenty-sixth transistor, and the semiconductor layer in the region not shielded by the first conductive layer is conductorized, i.e., the first region and the second region of the active pattern of any one of the first transistor to the fifteenth transistor are conductorized. As shown in FIG. 16, the second region of the active pattern of the sixth transistor in the disclosure after conductorization (also the first region of the active pattern of the seventh transistor) serves as the second electrode 64 of the sixth transistor (also the first electrode 73 of the seventh transistor), and the second region of the active pattern of the thirteenth transistor (also the second region of the active pattern of the fourteenth transistor) serves as the second electrode 134 of the thirteenth transistor (also the second electrode 144 of the fourteenth transistor).

[0336] (3) forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern can include: on the substrate on which the aforementioned pattern is formed, depositing a second insulating thin film and a second conductive thin film, patterning the second conductive thin film by a patterning process, forming a second insulating layer pattern covering the first conductive layer pattern and a second conductive layer pattern on the second insulating layer pattern, as shown in FIGS. 17 and 18, FIG. 17 is a schematic diagram of the second conductive layer pattern in FIG. 12, and FIG. 18 is a schematic diagram of FIG. 12 after the second conductive layer pattern is formed. In an exemplary embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0337] In an exemplary embodiment, as shown in FIGS. 17 and 18, the second conductive layer pattern can include at least: the second plate C12 of the first capacitor of each stage of the first shift register, the second plate C62 of the sixth capacitor, the first connection electrode L1, and the first inter-stage connection part NL1 of at least one of the plurality of inter-stage connection lines.

[0338] In an exemplary embodiment, the second plate C12 of the first capacitor has an orthographic projection on the substrate that at least partially overlaps the orthographic projection of the first plate of the first capacitor on the substrate. The area of the second plate C12 of the first capacitor is greater than the area of the first plate of the first capacitor. The shape of the second plate C12 of the first capacitor is the same as the shape of the first plate of the first capacitor.

[0339] In an exemplary embodiment, the second plate C22 of the second capacitor and the second plate C32 of the third capacitor are in an integrated structure. The orthographic projection of the integrated structure of the second plate C22 of the second capacitor and the second plate C32 of the third capacitor on the substrate at least partially overlaps the orthographic projection of the first plate of the second capacitor on the substrate, and the second plate C32 of the third capacitor and the second plate C32 of the third capacitor are in an integrated structure. The shape of the integrated structure of the second plate C22 of the second capacitor and the second plate C32 of the third capacitor can be block-shaped.

[0340] In an exemplary embodiment, the second plate C42 of the fourth capacitor has an orthographic projection on the substrate that at least partially overlaps the orthographic projection of the first plate of the fourth capacitor on the substrate. The shape of the second plate C42 of the fourth capacitor is the same as the shape of the first plate of the fourth capacitor, and the area of the second plate C42 of the fourth capacitor is greater than the area of the first plate of the fourth capacitor.

[0341] In an exemplary embodiment, the second plate C52 of the fifth capacitor has an orthographic projection on the substrate that at least partially overlaps the orthographic projection of the first plate of the fifth capacitor on the substrate. The shape of the second plate C52 of the fifth capacitor is the same as the shape of the first plate of the fifth capacitor, and the area of the second plate C52 of the fifth capacitor is greater than the area of the first plate of the fifth capacitor.

[0342] In an example embodiment, the second plate C62 of the sixth capacitor has a shape identical to that of the first plate of the sixth capacitor, and the area of the second plate C62 of the sixth capacitor is greater than that of the first plate of the sixth capacitor.

[0343] In an example embodiment, the first connection line L1 has a shape of a broken line and extends at least partially along the first direction D1.

[0344] In an example embodiment, the first stage connection portion NL1 of at least one connection line of the plurality of stage-crossing connection lines has a shape of a strip and extends at least partially along the second direction D2. The first stage connection portion NL1 of at least one connection line of the plurality of stage-crossing connection lines is in an integral structure with the second plate C22 of the second capacitor of the at least one first shift register.

[0345] (4) Forming a third insulating layer pattern. In an example embodiment, forming the third insulating layer pattern can include: depositing a third insulating thin film on the substrate on which the aforementioned patterns are formed, and patterning the third insulating thin film by a patterning process to form a third insulating layer pattern covering the aforementioned structure, the third insulating layer being provided with a plurality of via patterns, as shown in FIG. 19, which is a schematic diagram after the third insulating layer pattern is formed in FIG. 12.

[0346] In an example embodiment, as shown in FIG. 19, the third insulating layer pattern can include at least: a first via V1 to a forty-second via V42 of each first shift register.

[0347] In an example embodiment, the first via V1 has a normal projection on the substrate within the range of the normal projection on the substrate of the first region of the active pattern of the first transistor, the first insulating layer and the second insulating layer within the first via V1 are etched away to expose the surface of the first region of the active pattern of the first transistor, and the first via V1 is configured to connect the first electrode of the first transistor formed subsequently therethrough with the first region of the active pattern of the first transistor.

[0348] In an example embodiment, the second via V2 has a normal projection on the substrate within the range of the normal projection on the substrate of the second region of the active pattern of the first transistor, the first insulating layer and the second insulating layer within the second via V2 are etched away to expose the surface of the second region of the active pattern of the first transistor, and the second via V2 is configured to connect the second electrode of the first transistor (also the second electrode of the seventh transistor and the first electrode of the eighth transistor) formed subsequently therethrough with the second region of the active pattern of the first transistor.

[0349] In an example embodiment, the third via V3 has a footprint on the substrate within a footprint of the first region of the active pattern of the second transistor on the substrate, the first insulating layer and the second insulating layer within the third via V3 are etched away, exposing a surface of the first region of the active pattern of the second transistor, the third via V3 is configured to enable a first electrode of the second transistor formed subsequently to be connected to the first region of the active pattern of the second transistor through the via.

[0350] In an example embodiment, the fourth via V4 has a footprint on the substrate within a footprint of the second region of the active pattern of the second transistor on the substrate, the first insulating layer and the second insulating layer within the fourth via V4 are etched away, exposing a surface of the second region of the active pattern of the second transistor, the fourth via V4 is configured to enable a second electrode of the second transistor (also a second electrode of the third transistor) formed subsequently to be connected to the second region of the active pattern of the second transistor through the via.

[0351] In an example embodiment, the fifth via V5 has a footprint on the substrate within a footprint of the first region of the active pattern of the third transistor on the substrate, the first insulating layer and the second insulating layer within the fifth via V5 are etched away, exposing a surface of the first region of the active pattern of the third transistor, the fifth via V5 is configured to enable a first electrode of the third transistor formed subsequently to be connected to the first region of the active pattern of the third transistor through the via.

[0352] In an example embodiment, the sixth via V6 has a footprint on the substrate within a footprint of the second region of the active pattern of the third transistor on the substrate, the first insulating layer and the second insulating layer within the sixth via V6 are etched away, exposing a surface of the second region of the active pattern of the third transistor, the sixth via V6 is configured to enable a second electrode of the second transistor (also a second electrode of the third transistor) formed subsequently to be connected to the second region of the active pattern of the third transistor through the via.

[0353] In an example embodiment, the seventh via V7 has a footprint on the substrate within a footprint of the first region of the active pattern of the fourth transistor (also a first region of the active pattern of the sixth transistor) on the substrate, the first insulating layer and the second insulating layer within the seventh via V7 are etched away, exposing a surface of the first region of the active pattern of the fourth transistor (also a first region of the active pattern of the sixth transistor), the seventh via V7 is configured to enable a first electrode of the fourth transistor (also a first electrode of the sixth transistor) formed subsequently to be connected to the first region of the active pattern of the fourth transistor (also a first region of the active pattern of the sixth transistor) through the via.

[0354] In an example embodiment, the eighth via V8 is located within the range of the second region of the active pattern of the fourth transistor (also the second region of the active pattern of the fifth transistor) on the substrate, the first insulating layer and the second insulating layer within the eighth via V8 are etched away to expose the surface of the second region of the active pattern of the fourth transistor (also the second region of the active pattern of the fifth transistor), and the eighth via V8 is configured to connect the second electrode of the fourth transistor (also the second electrode of the fifth transistor) formed subsequently therethrough to the second region of the active pattern of the fourth transistor (also the second region of the active pattern of the fifth transistor).

[0355] In an example embodiment, the ninth via V9 is located within the range of the first region of the active pattern of the fifth transistor on the substrate, the first insulating layer and the second insulating layer within the ninth via V9 are etched away to expose the surface of the second region of the active pattern of the fifth transistor, and the ninth via V9 is configured to connect the first electrode of the fifth transistor (also the first electrode of the tenth transistor) formed subsequently therethrough to the first region of the active pattern of the fifth transistor.

[0356] In an example embodiment, the tenth via V10 is located within the range of the second region of the active pattern of the seventh transistor (also the first region of the active pattern of the eighth transistor) on the substrate, the first insulating layer and the second insulating layer within the tenth via V10 are etched away to expose the surface of the second region of the active pattern of the seventh transistor (also the first region of the active pattern of the eighth transistor), and the tenth via V10 is configured to connect the second electrode of the first transistor (also the second electrode of the seventh transistor and the first electrode of the eighth transistor) formed subsequently therethrough to the second region of the active pattern of the seventh transistor (also the first region of the active pattern of the eighth transistor).

[0357] In an example embodiment, the eleventh via V11 is located within the range of the second region of the active pattern of the eighth transistor on the substrate, the first insulating layer and the second insulating layer within the eleventh via V11 are etched away to expose the surface of the second region of the active pattern of the eighth transistor, and the eleventh via V11 is configured to connect the second electrode of the eighth transistor formed subsequently therethrough to the second region of the active pattern of the eighth transistor.

[0358] In an exemplary embodiment, the orthogonal projection of the twelfth via V12 on the substrate is located within the orthogonal projection on the substrate of the first region of the active pattern of the ninth transistor, the first insulating layer and the second insulating layer within the twelfth via V12 are etched away, exposing the surface of the first region of the active pattern of the ninth transistor, and the twelfth via V12 is configured to enable the first electrode of the ninth transistor formed subsequently to connect with the first region of the active pattern of the ninth transistor through the via.

[0359] In an exemplary embodiment, the orthogonal projection of the thirteenth via V13 on the substrate is located within the orthogonal projection on the substrate of the second region of the active pattern of the ninth transistor (also the second region of the active pattern of the tenth transistor), the first insulating layer and the second insulating layer within the thirteenth via V13 are etched away, exposing the surface of the second region of the active pattern of the ninth transistor (also the second region of the active pattern of the tenth transistor), and the thirteenth via V13 is configured to enable the second electrode of the ninth transistor (also the second electrode of the tenth transistor) formed subsequently to connect with the second region of the active pattern of the ninth transistor (also the second region of the active pattern of the tenth transistor) through the via.

[0360] In an exemplary embodiment, the orthogonal projection of the fourteenth via V14 on the substrate is located within the orthogonal projection on the substrate of the first region of the active pattern of the tenth transistor, the first insulating layer and the second insulating layer within the fourteenth via V14 are etched away, exposing the surface of the first region of the active pattern of the tenth transistor, and the fourteenth via V14 is configured to enable the first electrode of the fifth transistor (also the first electrode of the tenth transistor) formed subsequently to connect with the first region of the active pattern of the tenth transistor through the via.

[0361] In an exemplary embodiment, the orthogonal projection of the fifteenth via V15 on the substrate is located within the orthogonal projection on the substrate of the first region of the active pattern of the eleventh transistor, the first insulating layer and the second insulating layer within the fifteenth via V15 are etched away, exposing the surface of the first region of the active pattern of the eleventh transistor, and the fifteenth via V15 is configured to enable the first electrode of the eleventh transistor formed subsequently to connect with the first region of the active pattern of the eleventh transistor through the via.

[0362] In an exemplary embodiment, the orthogonal projection of the sixteenth via V16 on the substrate is located within the orthogonal projection on the substrate of the second region of the active pattern of the eleventh transistor, the first insulating layer and the second insulating layer within the sixteenth via V16 are etched away, exposing the surface of the second region of the active pattern of the eleventh transistor, and the sixteenth via V16 is configured to enable the second electrode of the eleventh transistor formed subsequently to connect with the second region of the active pattern of the eleventh transistor through the via.

[0363] In an exemplary embodiment, the first insulating layer and the second insulating layer within the seventeenth via V17 are etched away, exposing a surface of the first region of the active pattern of the twelfth transistor, the seventeenth via V17 is configured to connect the first electrode of the twelfth transistor formed subsequently therethrough to the first region of the active pattern of the twelfth transistor.

[0364] In an exemplary embodiment, the first insulating layer and the second insulating layer within the eighteenth via V18 are etched away, exposing a surface of the second region of the active pattern of the twelfth transistor, the eighteenth via V18 is configured to connect the second electrode of the twelfth transistor formed subsequently therethrough to the second region of the active pattern of the twelfth transistor.

[0365] In an exemplary embodiment, the first insulating layer and the second insulating layer within the nineteenth via V19 are etched away, exposing a surface of the first region of the active pattern of the thirteenth transistor (also the second region of the active pattern of the fifteenth transistor), the nineteenth via V19 is configured to connect the first electrode of the thirteenth transistor formed subsequently therethrough to the first region of the active pattern of the thirteenth transistor (also the second region of the active pattern of the fifteenth transistor).

[0366] In an exemplary embodiment, the first insulating layer and the second insulating layer within the twentieth via V20 are etched away, exposing a surface of the first region of the active pattern of the fourteenth transistor, the twentieth via V20 is configured to connect the first electrode of the fourteenth transistor formed subsequently therethrough to the first region of the active pattern of the fourteenth transistor.

[0367] In an exemplary embodiment, the first insulating layer and the second insulating layer within the twenty-first via V21 are etched away, exposing a surface of the first region of the active pattern of the fifteenth transistor, the twenty-first via V21 is configured to connect the first electrode of the fifteenth transistor formed subsequently therethrough to the first region of the active pattern of the fifteenth transistor.

[0368] In an example embodiment, a twenty-second via V22 has a footprint on the substrate within a footprint of the control electrode of the first transistor on the substrate, a second insulating layer within the twenty-second via V22 is etched away to expose a surface of the control electrode of the first transistor, and the twenty-second via V22 is configured to enable a second connection electrode formed subsequently to connect with the control electrode of the first transistor through the via.

[0369] In an example embodiment, a twenty-third via V23 has a footprint on the substrate within a footprint of the control electrode of the second transistor on the substrate, a second insulating layer within the twenty-third via V23 is etched away to expose a surface of the control electrode of the second transistor, and the twenty-third via V23 is configured to enable a second electrode of the first transistor (also a second electrode of the seventh transistor and a first electrode of the eighth transistor) formed subsequently to connect with the control electrode of the second transistor through the via.

[0370] In an example embodiment, a twenty-fourth via V24 has a footprint on the substrate within a footprint of the control electrode of the third transistor on the substrate, a second insulating layer within the twenty-fourth via V24 is etched away to expose a surface of the control electrode of the third transistor, and the twenty-fourth via V24 is configured to enable a first electrode of the second transistor formed subsequently to connect with the control electrode of the third transistor through the via.

[0371] In an example embodiment, a twenty-fifth via V25 has a footprint on the substrate within a footprint of the control electrode of the fourth transistor (also a control electrode of the sixth transistor and a first plate of the first capacitor) on the substrate, a second insulating layer within the twenty-fifth via V25 is etched away to expose a surface of the control electrode of the fourth transistor (also a control electrode of the sixth transistor and a first plate of the first capacitor), and the twenty-fifth via V25 is configured to enable a third connection electrode and a first electrode of the eleventh transistor formed subsequently to connect with the control electrode of the fourth transistor (also a control electrode of the sixth transistor and a first plate of the first capacitor) through the via.

[0372] In an example embodiment, a twenty-sixth via V26 has a footprint on the substrate within a footprint of the control electrode of the fifth transistor (a first plate of the second capacitor) on the substrate, a second insulating layer within the twenty-sixth via V26 is etched away to expose a surface of the control electrode of the fifth transistor (a first plate of the second capacitor), and the twenty-sixth via V26 is configured to enable a second electrode of the eighth transistor and a first electrode of the twelfth transistor formed subsequently to connect with the control electrode of the fifth transistor (a first plate of the second capacitor) through the via.

[0373] In an example embodiment, a twenty-seventh via V27 has a footprint on the substrate within a footprint of a control electrode of the seventh transistor on the substrate, a second insulating layer within the twenty-seventh via V27 is etched away to expose a surface of the control electrode of the seventh transistor, and the twenty-seventh via V27 is configured to connect the fourth connection electrode and the first electrode of the fifth transistor to the control electrode of the seventh transistor through the via.

[0374] In an example embodiment, a twenty-eighth via V28 has a footprint on the substrate within a footprint of a control electrode of the eighth transistor on the substrate, a second insulating layer within the twenty-eighth via V28 is etched away to expose a surface of the control electrode of the eighth transistor, and the twenty-eighth via V28 is configured to connect the fifth connection electrode to the control electrode of the eighth transistor through the via.

[0375] In an example embodiment, a twenty-ninth via V29 has a footprint on the substrate within a footprint of a control electrode of the ninth transistor (also a first electrode plate of the fourth capacitor) on the substrate, a second insulating layer within the twenty-ninth via V29 is etched away to expose a surface of the control electrode of the ninth transistor (also a first electrode plate of the fourth capacitor), and the twenty-ninth via V29 is configured to connect the second electrode of the eleventh transistor to the control electrode of the ninth transistor (also a first electrode plate of the fourth capacitor) through the via.

[0376] In an example embodiment, a thirtieth via V30 has a footprint on the substrate within a footprint of a control electrode of the tenth transistor (also a first electrode plate of the fifth capacitor and a first electrode plate of the sixth capacitor) on the substrate, a second insulating layer within the thirtieth via V30 is etched away to expose a surface of the control electrode of the tenth transistor (also a first electrode plate of the fifth capacitor and a first electrode plate of the sixth capacitor), and the thirtieth via V30 is configured to connect the second electrode of the twelfth transistor to the control electrode of the tenth transistor (also a first electrode plate of the fifth capacitor and a first electrode plate of the sixth capacitor) through the via.

[0377] In an example embodiment, a thirty-first via V31 has a footprint on the substrate within a footprint of a control electrode of the eleventh transistor (also a control electrode of the twelfth transistor) on the substrate, a second insulating layer within the thirty-first via V31 is etched away to expose a surface of the control electrode of the eleventh transistor (also a control electrode of the twelfth transistor), and the thirty-first via V31 is configured to connect the first electrode of the thirteenth transistor (also a second electrode of the fifteenth transistor) to the control electrode of the eleventh transistor (also a control electrode of the twelfth transistor) through the via.

[0378] In an exemplary embodiment, a third thirty-two via V32 has a projection on the substrate within a projection on the substrate of a control electrode of the thirteenth transistor, a second insulating layer within the third thirty-two via V32 is etched away to expose a surface of the control electrode of the thirteenth transistor, and the third thirty-two via V32 is configured to enable a sixth connection electrode formed subsequently to connect to the control electrode of the thirteenth transistor through the via.

[0379] In an exemplary embodiment, a third thirty-three via V33 has a projection on the substrate within a projection on the substrate of a control electrode of the fourteenth transistor, a second insulating layer within the third thirty-three via V33 is etched away to expose a surface of the control electrode of the fourteenth transistor, and the third thirty-three via V33 is configured to enable a seventh connection electrode formed subsequently to connect to the control electrode of the fourteenth transistor through the via.

[0380] In an exemplary embodiment, a third thirty-four via V34 has a projection on the substrate within a projection on the substrate of a control electrode of the fifteenth transistor, a second insulating layer within the third thirty-four via V34 is etched away to expose a surface of the control electrode of the fifteenth transistor, and the third thirty-four via V34 is configured to enable a light emitting connection line formed subsequently to connect to the control electrode of the fifteenth transistor through the via.

[0381] In an exemplary embodiment, a third thirty-five via V35 has a projection on the substrate within a projection on the substrate of a first plate of the third capacitor, a second insulating layer within the third thirty-five via V35 is etched away to expose a surface of the first plate of the third capacitor, and the third thirty-five via V35 is configured to enable a first electrode of the fourth transistor (also a first electrode of the sixth transistor) formed subsequently to connect to the first plate of the third capacitor through the via.

[0382] In an exemplary embodiment, a third thirty-six via V36 has a projection on the substrate within a projection on the substrate of a second plate of the first capacitor, the third thirty-six via V36 exposes a surface of the second plate of the first capacitor, and the third thirty-six via V36 is configured to enable the first electrode of the fourth transistor (also the first electrode of the sixth transistor) formed subsequently to connect to the second plate of the first capacitor through the via.

[0383] In an exemplary embodiment, a third thirty-seven via V37 has a projection on the substrate within a projection on the substrate of a second plate of the second capacitor (also a second plate of the third capacitor), the third thirty-seven via V37 exposes a surface of the second plate of the second capacitor (also the second plate of the third capacitor), and the third thirty-seven via V37 is configured to enable a second electrode of the fourth transistor (also a second electrode of the fifth transistor) formed subsequently to connect to the second plate of the second capacitor (also the second plate of the third capacitor) through the via.

[0384] In an example embodiment, a third eighth via V8 has a footprint on the substrate within a footprint of a second plate of a third capacitor on the substrate, the third eighth via V8 exposes a surface of the second plate of the third capacitor, and the third eighth via V8 is configured to connect a first electrode of a third transistor to be formed later to the second plate of the third capacitor through the via.

[0385] In an example embodiment, a third ninth via V9 has a footprint on the substrate within a footprint of a second plate of a fourth capacitor on the substrate, the third ninth via V9 exposes a surface of the second plate of the fourth capacitor, and the third ninth via V9 is configured to connect a second electrode of a fourth transistor to be formed later to the second plate of the fourth capacitor through the via.

[0386] In an example embodiment, a fourth tenth via V10 has a footprint on the substrate within a footprint of a second plate of a fifth capacitor on the substrate, the fourth tenth via V10 exposes a surface of the second plate of the fifth capacitor, and the fourth tenth via V10 is configured to connect a second electrode of a fifth transistor to be formed later to the second plate of the fifth capacitor through the via.

[0387] In an example embodiment, a fourth eleventh via V11 has a footprint on the substrate within a footprint of a first connection electrode on the substrate, the fourth eleventh via V11 exposes a surface of the first connection electrode, and the fourth eleventh via V11 is configured to connect a second electrode of a second transistor to be formed later and a third connection electrode to the first connection electrode through the via.

[0388] In an example embodiment, a fourth twelfth via V12 has a footprint on the substrate within a footprint of a first inter-stage connection portion of one of the plurality of inter-stage connection lines on the substrate, the fourth twelfth via V12 exposes a surface of the first inter-stage connection portion of the one of the plurality of inter-stage connection lines, and the fourth twelfth via V12 is configured to connect a second inter-stage connection portion of the one of the plurality of inter-stage connection lines to be formed later to the first inter-stage connection portion of the one of the plurality of inter-stage connection lines through the via.

[0389] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a third conductive thin film, patterning the third conductive thin film using a patterning process, forming a third conductive layer disposed on the fifth insulating layer, as shown in FIG. 20 and FIG. 21, FIG. 20 is a schematic diagram of the third conductive layer pattern in FIG. 12, and FIG. 21 is a schematic diagram of FIG. 12 after forming the third conductive layer pattern. In an exemplary embodiment, the third conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0390] In an exemplary embodiment, as shown in FIG. 20 and FIG. 21, the third conductive layer pattern can include at least: the first electrode 13 of the first transistor and the first electrode 153 and the second electrode 154 of the fifteenth transistor in the at least one stage of the first shift register, the second connection electrode L2 to the sixth connection electrode L6, the power connection line VL, the light-emitting connection line EOUTL, and the second stage connection part NL2 of at least one of the plurality of stage connection lines.

[0391] In an exemplary embodiment, the first electrode 13 of the first transistor is separately provided. The first electrode 13 of the first transistor has a strip shape and extends at least partially in the first direction D1. The first electrode 13 of the first transistor is connected to the first region of the active pattern of the first transistor through the first via V.

[0392] In an exemplary embodiment, the second electrode 14 of the first transistor, the second electrode 74 of the seventh transistor, and the first electrode 83 of the eighth transistor are in an integrated structure, and the integrated structure of the second electrode 14 of the first transistor, the second electrode 74 of the seventh transistor, and the first electrode 83 of the eighth transistor has an "n" shape with an opening facing the display area. The second electrode 14 of the first transistor (also the second electrode 74 of the seventh transistor and the first electrode 83 of the eighth transistor) is connected to the second region of the active pattern of the first transistor through the second via, to the second region of the active pattern of the seventh transistor (also the first region of the active pattern of the eighth transistor) through the tenth via, and to the control electrode of the second transistor through the twenty-third via.

[0393] In an exemplary embodiment, the first electrode 23 of the second transistor is separately provided. The first electrode 23 of the second transistor has a "┌" shape. The first electrode 23 of the second transistor is connected to the first region of the active pattern of the second transistor through the third via and to the control electrode of the third transistor through the twenty-fourth via.

[0394] In the example embodiment, the second electrode 24 of the second transistor and the second electrode 34 of the third transistor are in one body structure. The one body structure of the second electrode 24 of the second transistor and the second electrode 34 of the third transistor is in an "L" shape. The second electrode 24 of the second transistor (also the second electrode 34 of the third transistor) is connected to the second region of the active pattern of the second transistor through the fourth via, connected to the second region of the active pattern of the third transistor through the sixth via, and connected to the first connection electrode through the forty-first via.

[0395] In the example embodiment, the first electrode 33 of the third transistor is provided separately. The first electrode 33 of the third transistor is in a strip shape and extends in the second direction D2. The first electrode 33 of the third transistor is connected to the first region of the active pattern of the third transistor through the fifth via.

[0396] In the example embodiment, the first electrode 43 of the fourth transistor and the first electrode 63 of the sixth transistor are in one body structure. The one body structure of the first electrode 43 of the fourth transistor and the first electrode 63 of the sixth transistor is in a zigzag shape and extends at least partially in the first direction D1. The first electrode 43 of the fourth transistor (also the first electrode 63 of the sixth transistor) is connected to the first region of the active pattern of the fourth transistor (also the first region of the active pattern of the sixth transistor) through the seventh via, connected to the first plate of the third capacitor through the thirty-fifth via, and connected to the second plate of the first capacitor through the thirty-sixth via.

[0397] In the example embodiment, the second electrode 44 of the fourth transistor and the second electrode 54 of the fifth transistor are in one body structure. The one body structure of the second electrode 44 of the fourth transistor and the second electrode 54 of the fifth transistor is in a zigzag shape and extends at least partially in the first direction D1. The second electrode 44 of the fourth transistor (also the second electrode 54 of the fifth transistor) is connected to the second region of the active pattern of the fourth transistor (also the second region of the active pattern of the fifth transistor) through the eighth via, and connected to the second plate of the second capacitor (also the second plate of the third capacitor) through the thirty-seventh via.

[0398] In the example embodiment, the first electrode 53 of the fifth transistor and the first electrode 103 of the tenth transistor are in one body structure. The one body structure of the first electrode 53 of the fifth transistor and the first electrode 103 of the tenth transistor is in a zigzag shape and extends at least partially in the first direction D1. The first electrode 53 of the fifth transistor (also the first electrode 103 of the tenth transistor) is connected to the first region of the active pattern of the fifth transistor through the ninth via, connected to the first region of the active pattern of the tenth transistor through the fourteenth via, and connected to the control electrode of the seventh transistor through the twenty-seventh via.

[0399] In the example embodiment, the second electrode 84 of the eighth transistor is provided separately. The second electrode 84 of the eighth transistor has a shape of a bar and extends in the first direction D1. The second electrode 84 of the eighth transistor is connected to the second region of the active pattern of the eighth transistor through the eleventh via, and connected to the control electrode of the fifth transistor (the first plate of the second capacitor) through the twenty-sixth via.

[0400] In the example embodiment, the first electrode 93 of the ninth transistor is provided separately. The first electrode 93 of the ninth transistor has a shape of a bar and extends in the first direction D1. The first electrode 93 of the ninth transistor is connected to the first region of the active pattern of the ninth transistor through the twelfth via, and connected to the second plate of the fourth capacitor through the thirty-eighth via.

[0401] In the example embodiment, the second electrode 94 of the ninth transistor and the first electrode 104 of the tenth transistor are in an integrated structure. The integrated structure of the second electrode 94 of the ninth transistor and the first electrode 104 of the tenth transistor has a shape of an "n" letter type with an opening facing away from the display region. The second electrode 94 of the ninth transistor (also the second electrode 104 of the tenth transistor) is connected to the second region of the active pattern of the ninth transistor (also the second region of the active pattern of the tenth transistor) through the thirteenth via, and connected to the second plate of the fifth capacitor through the thirty-ninth via.

[0402] In the example embodiment, the first electrode 113 of the eleventh transistor is provided separately. The first electrode 113 of the eleventh transistor has a shape of a "┌" letter type. The first electrode 113 of the eleventh transistor is connected to the first region of the active pattern of the eleventh transistor through the fifteenth via, and connected to the control electrode of the fourth transistor (also the control electrode of the sixth transistor and the first plate of the first capacitor) through the twenty-fifth via.

[0403] In the example embodiment, the second electrode 114 of the eleventh transistor is provided separately. The second electrode 114 of the eleventh transistor has a shape of a bar and extends in the first direction D1. The second electrode 114 of the eleventh transistor is connected to the second region of the active pattern of the eleventh transistor through the sixteenth via.

[0404] In the example embodiment, the first electrode 123 of the twelfth transistor is provided separately. The first electrode 123 of the twelfth transistor has a shape of a bar and extends in the first direction D1. The first electrode 123 of the twelfth transistor is connected to the first region of the active pattern of the twelfth transistor through the seventeenth via, and connected to the control electrode of the fifth transistor (the first plate of the second capacitor) through the twenty-sixth via, and connected to the control electrode of the ninth transistor (also the first plate of the fourth capacitor) through the twenty-ninth via.

[0405] In an exemplary embodiment, the second electrode 124 of the twelfth transistor is separately provided. The shape of the second electrode 124 of the twelfth transistor is a strip shape, and extends in the second direction D2. The second electrode 124 of the twelfth transistor is connected to the second region of the active pattern of the twelfth transistor through the eighteenth via, and is connected to the control electrode of the tenth transistor (also the first electrode plate of the fifth capacitor and the first electrode plate of the sixth capacitor) through the thirtieth via.

[0406] In an exemplary embodiment, the first electrode 133 of the thirteenth transistor and the second electrode 154 of the fifteenth transistor are in an integrated structure. The shape of the integrated structure of the first electrode 133 of the thirteenth transistor and the second electrode 154 of the fifteenth transistor is a strip shape, and extends in the first direction D1. The first electrode 133 of the thirteenth transistor (also the second electrode 154 of the fifteenth transistor) is connected to the first region of the active pattern of the thirteenth transistor (also the second region of the active pattern of the fifteenth transistor) through the nineteenth via, is connected to the control electrode of the eleventh transistor (also the control electrode of the twelfth transistor) through the thirty-first via, and is connected to the second electrode plate of the sixth capacitor through the fortieth via.

[0407] In an exemplary embodiment, the first electrode 143 of the fourteenth transistor is separately provided. The shape of the first electrode 143 of the fourteenth transistor is a strip shape, and extends in the first direction D1. The first electrode 143 of the fourteenth transistor is connected to the first region of the active pattern of the fourteenth transistor through the twentieth via.

[0408] In an exemplary embodiment, the first electrode 153 of the fifteenth transistor is separately provided. The shape of the first electrode 153 of the fifteenth transistor is a strip shape, and extends in the first direction D1. The first electrode 153 of the fifteenth transistor is connected to the first region of the active pattern of the fifteenth transistor through the twenty-first via.

[0409] In an exemplary embodiment, the second connection electrode L2 is separately provided. The shape of the second connection electrode L2 is a strip shape, and extends in the first direction D1. The second connection electrode L2 is connected to the control electrode of the first transistor through the twenty-second via.

[0410] In an exemplary embodiment, the third connection electrode L3 is separately provided. The shape of the third connection electrode L3 is a strip shape, and extends in the first direction D1. The third connection electrode L3 is connected to the control electrode of the fourth transistor (also the control electrode of the sixth transistor and the first electrode plate of the first capacitor) through the twenty-fifth via, and is connected to the first connection electrode through the forty-first via.

[0411] In an exemplary embodiment, the fourth connection electrode L4 is separately provided. The shape of the fourth connection electrode L4 is a strip shape, and extends in the first direction D1. The fourth connection electrode L4 is connected to the control electrode of the seventh transistor through the twenty-seventh via.

[0412] In an example embodiment, the fifth connection electrode L5 is provided separately. The fifth connection electrode L5 has a shape of a "┌" character. The fifth connection electrode L5 is connected to the control electrode of the eighth transistor through a twenty-eighth via.

[0413] In an example embodiment, the sixth connection electrode L6 is provided separately. The sixth connection electrode L6 has a shape of a strip and extends along the first direction D1. The sixth connection electrode L6 is connected to the control electrode of the thirteenth transistor through a thirty-second via.

[0414] In an example embodiment, the seventh connection electrode L7 is provided separately. The seventh connection electrode L7 has a shape of a strip and extends along the second direction D2. The seventh connection electrode L7 is connected to the control electrode of the fourteenth transistor through a thirty-third via.

[0415] In an example embodiment, the light emitting connection line EOUTL extends at least partially along the first direction D1. The light emitting connection line EOUTL is connected to the control electrode of the fifteenth transistor through a thirty-fourth via.

[0416] In an example embodiment, the second cross-stage connection part NL2 of one of the plurality of cross-stage connection lines has a shape of a broken line and is bent in a direction away from the display region. The second cross-stage connection part NL2 of one of the plurality of cross-stage connection lines extends at least partially along the second direction D2. The second cross-stage connection part NL2 of one of the plurality of cross-stage connection lines is connected to the first cross-stage connection part through a forty-second via.

[0417] In an example embodiment, the power supply connection line VL extends at least partially along the first direction D1.

[0418] (6) The fourth insulating layer pattern is formed. In an example embodiment, forming the fourth insulating layer pattern can include: on the substrate on which the aforementioned patterns are formed, a fourth insulating thin film is first deposited, then a planar thin film is coated, the fourth insulating thin film and the planar thin film are patterned through a patterning process, a fourth insulating layer covering the aforementioned structure and a planar layer disposed on the fourth insulating layer are formed, and the planar layer is provided with a plurality of via patterns, as shown in FIG. 22, which is a schematic diagram after the planar layer pattern is formed in FIG. 12.

[0419] In an example embodiment, as shown in FIG. 22, the planar layer pattern can at least include: the forty-third via V43 to the fifty-fifth via V55 of the at least one first shift register.

[0420] In an example embodiment, a fourth forty-third via V43 has a footprint on the substrate within a footprint of the second connection electrode on the substrate, a fourth insulating layer within the fourth forty-third via V43 is etched away to expose a surface of the second connection electrode, and the fourth forty-third via V43 is configured to enable one of a group of clock signal lines to be formed subsequently to be connected to the second connection electrode through the via. One of the group of clock signal lines is connected to the control electrode of the first transistor through the second connection electrode.

[0421] In an example embodiment, a fourth forty-fourth via V44 has a footprint on the substrate within a footprint of the first electrode of the first transistor on the substrate, a fourth insulating layer within the fourth forty-fourth via V44 is etched away to expose a surface of the first electrode of the first transistor, and the fourth forty-fourth via V44 is configured to enable at least one of a plurality of cross-level connection lines to be formed subsequently to have a third cross-level connection portion connected to the first electrode of the first transistor through the via.

[0422] In an example embodiment, a fourth forty-fifth via V45 has a footprint on the substrate within a footprint of the first electrode of the second transistor on the substrate, a fourth insulating layer within the fourth forty-fifth via V45 is etched away to expose a surface of the first electrode of the second transistor, and the fourth forty-fifth via V45 is configured to enable one of a group of clock signal lines to be formed subsequently to be connected to the first electrode of the second transistor through the via.

[0423] In an example embodiment, a fourth forty-sixth via V46 has a footprint on the substrate within a footprint of the first electrode of the fourth transistor (also the first electrode of the sixth transistor) on the substrate, a fourth insulating layer within the fourth forty-sixth via V46 is etched away to expose a surface of the first electrode of the fourth transistor (also the first electrode of the sixth transistor), and the fourth forty-sixth via V46 is configured to enable a first power supply line to be formed subsequently to be connected to the first electrode of the fourth transistor (also the first electrode of the sixth transistor) through the via.

[0424] In an example embodiment, a fourth forty-seventh via V47 has a footprint on the substrate within a footprint of the first electrode of the ninth transistor on the substrate, a fourth insulating layer within the fourth forty-seventh via V47 is etched away to expose a surface of the first electrode of the ninth transistor, and the fourth forty-seventh via V47 is configured to enable a second power supply line to be formed subsequently to be connected to the first electrode of the ninth transistor through the via.

[0425] In an example embodiment, a fourth insulating layer in the forty-eighth via V48 is etched away, exposing a surface of the sixth connection electrode, the forty-eighth via V48 is configured to enable a third inter-stage connection part of at least one of the plurality of inter-stage connection lines formed subsequently to pass through the via and electrically connect with the sixth connection electrode. The third inter-stage connection part of at least one of the plurality of inter-stage connection lines is electrically connected with the control electrode of the thirteenth transistor through the sixth connection electrode.

[0426] In an example embodiment, a fourth insulating layer in the forty-ninth via V49 is etched away, exposing a surface of the first electrode of the fourteenth transistor, the forty-ninth via V49 is configured to enable the mask signal line formed subsequently to pass through the via and connect with the first electrode of the fourteenth transistor.

[0427] In an example embodiment, a fourth insulating layer in the fiftieth via V50 is etched away, exposing a surface of the first electrode of the fifteenth transistor, the fiftieth via V50 is configured to enable the second second power line formed subsequently to pass through the via and connect with the first electrode of the fifteenth transistor.

[0428] In an example embodiment, a fourth insulating layer in the fifty-first via V51 is etched away, exposing a surface of the fourth connection electrode, the fifty-first via V51 is configured to enable one of the clock signal line group formed subsequently to pass through the via and connect with the fourth connection electrode. The one of the clock signal line group is electrically connected with the control electrode of the seventh transistor through the fourth connection electrode.

[0429] In an example embodiment, a fourth insulating layer in the fifty-second via V52 is etched away, exposing a surface of the fifth connection electrode, the fifty-second via V52 is configured to enable the first second power line formed subsequently to pass through the via and connect with the fifth connection electrode. The first second power line is electrically connected with the control electrode of the eighth transistor through the fifth connection electrode.

[0430] In an example embodiment, the fifth connection electrode in the n-th stage first shift register and the first electrode of the third transistor in the n+1-th stage first shift register are the same electrode.

[0431] In an exemplary embodiment, the fifth fifty-three via hole V53 is configured such that a third inter-stage connection part of at least one of the plurality of inter-stage connection lines to be formed subsequently is connected to the seventh connection electrode through the via hole. The third inter-stage connection part of at least one of the plurality of inter-stage connection lines is connected to the control electrode of the fourteenth transistor through the seventh connection electrode.

[0432] In an exemplary embodiment, the fifth fifty-four via hole V54 is configured such that a third inter-stage connection part of at least one of the plurality of inter-stage connection lines to be formed subsequently is connected to the second inter-stage connection part of at least one of the plurality of inter-stage connection lines through the via hole.

[0433] In an exemplary embodiment, the fifth fifty-five via hole V55 is configured such that a third power supply line to be formed subsequently is connected to the power supply connection line through the via hole.

[0434] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern can include: depositing a fourth conductive thin film on the substrate on which the aforementioned patterns are formed, and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer disposed on the fourth insulating layer, as shown in FIGS. 23 and 24. FIG. 23 is a schematic view of the fourth insulating layer pattern of FIG. 12, and FIG. 24 is a schematic view of FIG. 12 after the fourth insulating layer pattern is formed. In an exemplary embodiment, the fourth conductive layer can be referred to as a second source-drain metal (SD2) layer.

[0435] In an example embodiment, as shown in FIGS. 22 to 24, the fourth conductive layer pattern can include at least: the initial signal line STV1, the mask signal line MSL, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the first power line VGH-1, the second power line VGH-2, the first second power line VGL-1, the second second power line VGL-2, the third power line VSL, the third sub-stage connection portion NL3 of at least one of the plurality of sub-stage connection lines, the first initial signal line INIT1, the second initial signal line INIT2, and the third initial signal line INIT3.

[0436] In an example embodiment, at least one of the initial signal line STV1, the mask signal line MSL, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the first power line VGH-1, the second power line VGH-2, the first second power line VGL-1, the second second power line VGL-2, the third power line VSL, the third sub-stage connection portion NL3 of at least one of the plurality of sub-stage connection lines, the first initial signal line INIT1, the second initial signal line INIT2, and the third initial signal line INIT3 extends at least partially in the second direction D2.

[0437] In an example embodiment, the first second power line VGL-1, the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the first power line VGH-1, the third power line VSL, the second second power line VGL-2, the second power line VGH-2, the mask signal line MSL, the first initial signal line INIT1, the second initial signal line INIT2, and the third initial signal line INIT3 are arranged in order in a direction close to the display area.

[0438] In an example embodiment, the third sub-stage connection portion NL3 of at least one of the plurality of sub-stage connection lines is located between the second second power line VGL-2 and the second power line VGH-2.

[0439] In an example embodiment, one of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, and the fourth clock signal line CLK4 is connected to the second connection electrode through the forty-third via.

[0440] In an exemplary embodiment, one of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, and the fourth clock signal line CLK4 is connected to the first electrode of the second transistor through the forty-fifth via.

[0441] In an exemplary embodiment, one of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, and the fourth clock signal line CLK4 is connected to the control electrode of the seventh transistor through the fifty-first via.

[0442] In an exemplary embodiment, the third cross-level connection part NL3 of one of the plurality of cross-level connection lines is connected to the first electrode of the first transistor through the forty-fourth via, to the sixth connection electrode through the forty-eighth via, to the seventh connection electrode through the fifty-third via, and to the second cross-level connection part through the fifty-fourth via.

[0443] In an exemplary embodiment, the first power line VGH-1 is connected to the first electrode of the fourth transistor (also the first electrode of the sixth transistor) through the forty-sixth via.

[0444] In an exemplary embodiment, the second power line VGH-2 is connected to the first electrode of the ninth transistor through the forty-seventh via.

[0445] In an exemplary embodiment, the masking signal line MSL is connected to the first electrode of the fourteenth transistor through the forty-ninth via.

[0446] In an exemplary embodiment, the first second power line VGL-1 is connected to the fifth connection electrode through the fifty-second via.

[0447] In an exemplary embodiment, the second second power line VGL-2 is connected to the first electrode of the fifteenth transistor through the fiftieth via.

[0448] In an exemplary embodiment, the third power line VSL is connected to the power supply connection line through the fifty-fifth via.

[0449] In an exemplary embodiment, the first connection part to the seventh connection part can reduce the via depth in the display substrate and improve the reliability of the display substrate.

[0450] In the example embodiment, the initial signal line STV1, the masking signal line MSL, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the first power line VGH-1, the second power line VGH-2, the first second power line VGL-1, the second second power line VGL-2, the third power line VSL, the third inter-stage connection part NL3 of at least one of the plurality of inter-stage connection lines, the first initial signal line INIT1, the second initial signal line INIT2, and the third initial signal line INIT3 can be designed as a length in the first direction with equal edges, or can be designed as a length in the first direction without equal edges, can be a straight line, or can be a broken line, which not only facilitates the layout of the shift register, but also reduces the parasitic capacitance between the signal lines, which is not limited in the disclosure.

[0451] So far, the driving circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the driving circuit layer can include a plurality of shift registers. In a plane perpendicular to the display substrate, the driving circuit layer can be disposed on the substrate.

[0452] In the first display substrate, the driving circuit layer can include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a planar layer, and a fourth conductive layer disposed in sequence on the substrate.

[0453] In the example embodiment, the substrate can be a rigid substrate or a flexible substrate, wherein the rigid substrate can be, but is not limited to, one or more of glass, metal foil; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyaryl acid ester, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers.

[0454] In the example embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The material of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the material of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water-oxygen resistance of the substrate. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer can be amorphous silicon (a-si). In the example embodiment, taking the laminated structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, the preparation process can include: first coating a layer of polyimide on a glass carrier plate, and forming a first flexible (PI1) layer after curing into a film; then depositing a layer of barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating a layer of polyimide on the amorphous silicon layer, and forming a second flexible (PI2) layer after curing into a film; then depositing a layer of barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

[0455] In the example embodiment, the semiconductor layer can be an amorphous silicon layer or a polycrystalline silicon layer, or can be a metal oxide layer. The metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer can be a single layer, or can be a double layer, or can be a multi-layer.

[0456] In the example embodiment, the first, second, third, and fourth conductive layers can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0457] In the example embodiment, the first, second, third, and fourth insulating layers can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer.

[0458] In the exemplary embodiments, after the driving circuit layer is prepared, the light-emitting structure layer is prepared on the driving circuit layer. The preparation process of the light-emitting structure layer can include the following operations.

[0459] On the substrate with the aforementioned pattern, an anode conductive film is deposited, and the anode conductive film is patterned by a patterning process to form an anode conductive layer pattern arranged on the second planar layer. On the substrate with the aforementioned pattern, a pixel definition film is deposited, and the pixel definition film is patterned by a patterning process to form a pixel definition layer pattern exposing the anode conductive layer pattern. On the substrate with the pixel definition layer pattern, an organic light-emitting material is coated, and the organic light-emitting material is patterned by a patterning process to form an organic structure layer pattern. On the substrate with the organic material layer pattern, a cathode conductive film is deposited, and the cathode conductive film is patterned by a patterning process to form a cathode conductive layer.

[0460] At this point, the light-emitting structure layer is prepared on the substrate.

[0461] In the exemplary embodiments, the anode conductive layer includes at least a plurality of anode patterns. The plurality of anode patterns can include an anode of a first light-emitting device, an anode of a second light-emitting device, an anode of a third light-emitting device, and an anode of a fourth light-emitting device. The anode of the first light-emitting device is arranged in a red sub-pixel that emits red light, the anode of the second light-emitting device is arranged in a blue sub-pixel that emits blue light, the anode of the third light-emitting device is arranged in a first green sub-pixel that emits green light, and the anode of the fourth light-emitting device is arranged in a second green sub-pixel that emits green light.

[0462] In the exemplary embodiments, the anode of the first light-emitting device and the anode of the second light-emitting device can be arranged alternately along a first direction, and the anode of the third light-emitting device and the anode of the fourth light-emitting device can be arranged alternately along the first direction. Alternatively, the anode of the first light-emitting device and the anode of the second light-emitting device can be arranged alternately along a second direction, and the anode of the third light-emitting device and the anode of the fourth light-emitting device can be arranged alternately along the second direction.

[0463] In the exemplary embodiments, the anode shapes and areas of the four sub-pixels in one pixel unit can be the same or different.

[0464] In the exemplary embodiments, the anode conductive layer can be a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a multi-layer composite structure, such as ITO / Ag / ITO.

[0465] In the exemplary embodiments, the organic structure layer can include at least an organic light-emitting layer of a light-emitting device.

[0466] In an exemplary embodiment, the cathode conductive layer can at least include a cathode of a plurality of light emitting devices.

[0467] In an exemplary embodiment, the cathode layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an electrically conductive alloy material, such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Exemplarily, the fourth conductive layer can be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0468] The display substrate provided by the embodiments of the present disclosure can be applied to any resolution display product.

[0469] In an exemplary embodiment, the subsequent preparation process can include forming an encapsulation structure layer on the cathode conductive layer, and the encapsulation structure layer can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer can be made of an inorganic material, and the second encapsulation layer can be made of an organic material, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, so as to prevent external water vapor from entering the light emitting structure layer.

[0470] The embodiments of the present disclosure also provide a display device, which can include a display substrate.

[0471] The display substrate is the display substrate provided by any one of the preceding embodiments, and has similar implementation principles and effects, which will not be described here again.

[0472] In an exemplary embodiment, the display device can be any product or component with a display function, such as a wearable device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0473] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0474] For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and size of a layer or microstructure are exaggerated. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly” on or under the other element, or there can be an intermediate element.

[0475] Although the disclosed embodiments have been fully described above with reference to the attachments, figures, and the accompanying drawings, other embodiments can be utilized and changes can be made without departing from the scope of the disclosure, which is not to be limited by the above-described embodiments. Accordingly, various modifications and changes can be made to the embodiments without departing from the scope of the disclosure as set forth in the claims below. The disclosure is not to be limited to the embodiments set forth herein for the purpose of the practice of the present disclosure.

Claims

1. A shift register comprising: The shift sub-circuit and the output sub-circuit; The shift sub-circuit is electrically connected with the signal input end, the first clock signal end, the second clock signal end, the third clock signal end, the first power supply end, the second power supply end, the cascade signal output end, the second node and the third node respectively, and is configured to provide the signal of one of the second power supply end and the second clock signal end to the second node, provide the signal of the signal input end to the third node, and provide the signal of one of the first power supply end and the third clock signal end to the cascade signal output end under the control of the signals of at least one of the signal input end, the first clock signal end, the second clock signal end and the third clock signal end; The output sub-circuit is electrically connected with the second node, the third node, the signal input end, the first control signal end, the second control signal end, the masking signal end, the third clock signal end, the first power supply end, the second power supply end and the driving signal output end respectively, and is configured to provide the signal of one of the first power supply end and the third clock signal end to the driving signal output end under the control of the signals of at least one of the second node, the third node, the first control signal end, the second control signal end, the signal input end and the masking signal end.

2. The shift register of claim 1, wherein, The number of the shift registers is multiple, and the multiple shift registers are cascaded; The cascade signal output end of at least one level of shift registers is electrically connected with the signal input end of at least one level of shift registers and the first control signal end of at least one level of shift registers respectively; The shift register, in which the signal input end connected with the cascade signal output end is located, is different from the shift register, in which the first control signal end connected with the cascade signal output end is located.

3. The shift register of claim 1 or 2, wherein, The shift sub-circuit comprises first to eighth transistors and first to third capacitors, and at least one of the first to third capacitors comprises a first plate and a second plate; The control electrode of the first transistor is electrically connected with the first clock signal end, the first electrode of the first transistor is electrically connected with the signal input end, and the second electrode of the first transistor is electrically connected with the first node; The control electrode of the second transistor is electrically connected with the first node, the first electrode of the second transistor is electrically connected with the second clock signal end, and the second electrode of the second transistor is electrically connected with the second node; The control electrode of the third transistor is electrically connected with the second clock signal end, the first electrode of the third transistor is electrically connected with the second power supply end, and the second electrode of the third transistor is electrically connected with the second node; The control electrode of the fourth transistor is electrically connected with the second node, the first electrode of the fourth transistor is electrically connected with the first power supply end, and the second electrode of the fourth transistor is electrically connected with the cascade signal output end; The control electrode of the fifth transistor is electrically connected with the third node, the first electrode of the fifth transistor is electrically connected with the third clock signal end, and the second electrode of the fifth transistor is electrically connected with the cascade signal output end; The control electrode of the sixth transistor is electrically connected with the second node, the first electrode of the sixth transistor is electrically connected with the first power supply end, and the second electrode of the sixth transistor is electrically connected with the fourth node; A control electrode of the seventh transistor is electrically connected with the third clock signal terminal, a first electrode of the seventh transistor is electrically connected with the fourth node, and a second electrode of the seventh transistor is electrically connected with the first node; A control electrode of the eighth transistor is electrically connected with the second power supply terminal, a first electrode of the eighth transistor is electrically connected with the first node, and a second electrode of the eighth transistor is electrically connected with the third node; A first electrode plate of the first capacitor is electrically connected with the second node, and a second electrode plate of the first capacitor is electrically connected with the first power supply terminal; A first electrode plate of the second capacitor is electrically connected with the third node, and a second electrode plate of the second capacitor is electrically connected with the cascade signal output terminal; A first electrode plate of the third capacitor is electrically connected with the first power supply terminal, and a second electrode plate of the third capacitor is electrically connected with the cascade signal output terminal.

4. The shift register of claim 1, wherein, The output sub-circuit comprises a node control sub-circuit and an output control sub-circuit; The node control sub-circuit is electrically connected with the second node, the third node, the fifth node, the sixth node, the signal input terminal, the masking signal terminal, the first control signal terminal, the second control signal terminal and the second power supply terminal respectively, and is configured to provide the signal of the second node to the fifth node and provide the signal of the third node to the sixth node under the control of the signals of at least one of the first control signal terminal, the second control signal terminal, the signal input terminal, the masking signal terminal and the second power supply terminal. The output control sub-circuit is electrically connected with the fifth node, the sixth node, the first power supply terminal, the third clock signal terminal and the driving signal output terminal respectively, and is configured to provide the signal of the first power supply terminal to the driving signal output terminal under the control of the signal of the fifth node and provide the signal of the third clock signal terminal to the driving signal output terminal under the control of the signal of the sixth node.

5. The shift register of claim 4, wherein, The output control sub-circuit comprises a ninth transistor, a tenth transistor, a fourth capacitor, a fifth capacitor and a sixth capacitor, and at least one capacitor of the fourth capacitor to the sixth capacitor comprises a first electrode plate and a second electrode plate; A control electrode of the ninth transistor is electrically connected with the fifth node, a first electrode of the ninth transistor is electrically connected with the first power supply terminal, and a second electrode of the ninth transistor is electrically connected with the driving signal output terminal; A control electrode of the tenth transistor is electrically connected with the sixth node, a first electrode of the tenth transistor is electrically connected with the third clock signal terminal, and a second electrode of the tenth transistor is electrically connected with the driving signal output terminal; A first electrode plate of the fourth capacitor is electrically connected with the fifth node, and a second electrode plate of the fourth capacitor is electrically connected with the first power supply terminal; A first electrode plate of the fifth capacitor is electrically connected with the sixth node, and a second electrode plate of the fifth capacitor is electrically connected with the driving signal output terminal; A first electrode plate of the sixth capacitor is electrically connected with the sixth node, and a second electrode plate of the sixth capacitor is electrically connected with the seventh node.

6. The shift register of claim 4, wherein, The node control sub-circuit comprises an eleventh transistor to a fifteenth transistor; A control electrode of the eleventh transistor is electrically connected with the seventh node, a first electrode of the eleventh transistor is electrically connected with the second node, and a second electrode of the eleventh transistor is electrically connected with the fifth node; A control electrode of the twelfth transistor is electrically connected with the seventh node, a first electrode of the twelfth transistor is electrically connected with the third node, and a second electrode of the twelfth transistor is electrically connected with the sixth node; The control electrode of the thirteenth transistor is electrically connected with the first control signal end, the first electrode of the thirteenth transistor is electrically connected with the seventh node, and the second electrode of the thirteenth transistor is electrically connected with the eighth node; The control electrode of the fourteenth transistor is electrically connected with the signal input end, the first electrode of the fourteenth transistor is electrically connected with the masking signal end, and the second electrode of the fourteenth transistor is electrically connected with the eighth node; The control electrode of the fifteenth transistor is electrically connected with the second control signal end, the first electrode of the fifteenth transistor is electrically connected with the second power supply end, and the second electrode of the fifteenth transistor is electrically connected with the seventh node.

7. A display substrate, comprising: The display substrate comprises a first gate drive circuit located in the non-display area, and the first gate drive circuit comprises a plurality of cascaded first shift registers, and the first shift register is the shift register according to any one of claims 1 to 6. 8.The display substrate of claim 7, wherein, The at least one first shift register comprises a second capacitor and a third capacitor, and the second capacitor and the third capacitor comprise a first electrode plate and a second electrode plate. The second electrode plate of the second capacitor and the second electrode plate of the third capacitor in the at least one first shift register are the same electrode plate. 9.The display substrate of claim 7, wherein, The cascade signal output end of the nth first shift register is electrically connected with the signal input end of the n+X first shift register and the first control signal end of the n+Y first shift register, respectively, 1≤n≤N, N is the total number of stages of the first shift register, and X<Y. 10.The display substrate of claim 9, further comprising: A plurality of cross-stage connection lines are located in the non-display area. One of the plurality of cross-stage connection lines is electrically connected with the cascade signal output end of the at least one first shift register, the signal input end of the at least one shift register, and the first control signal end of the at least one first shift register, respectively. At least two shift registers of the shift register where the cascade signal output end connected by the same cross-stage connection line is located, the shift register where the signal input end connected is located, and the shift register where the first control signal end connected is located are different stage shift registers. 11.The display substrate of claim 10, wherein, The cross-stage connection line comprises a first cross-stage connection part, a second cross-stage connection part, and a third cross-stage connection part, and at least one of the first cross-stage connection part, the second cross-stage connection part, and the third cross-stage connection part extends at least partially along the second direction. The second cross-stage connection part is electrically connected with the first cross-stage connection part and the third cross-stage connection part, respectively, and at least two of the first cross-stage connection part, the second cross-stage connection part, and the third cross-stage connection part are arranged in different layers. 12.The display substrate of claim 11, wherein, The at least one first shift register comprises a first transistor, a thirteenth transistor, a fourteenth transistor, a second capacitor and a third capacitor, the second capacitor and the third capacitor comprise a first plate and a second plate, wherein the first pole of the first transistor and the control pole of the fourteenth transistor are electrically connected with the signal input end of the first shift register respectively, the control pole of the thirteenth transistor is electrically connected with the first control signal end of the first shift register, and the second plate of the second capacitor and the second plate of the third capacitor are electrically connected with the cascade signal output end of the first shift register respectively; For the cross-stage connection line electrically connected with the cascade signal output end of the nth first shift register, the signal output end of the n+Xth first shift register and the first control signal end of the n+Yth first shift register, the first cross-stage connection part is electrically connected with the second plate of the second capacitor and the second plate of the third capacitor of the nth first shift register respectively, and the third cross-stage connection part is electrically connected with the first pole of the first transistor and the control pole of the fourteenth transistor of the n+Xth first shift register, the control pole of the thirteenth transistor of the n+Yth first shift register and the second cross-stage connection part respectively. 13.The display substrate according to claim 11 or 12, wherein, The at least one first shift register in the plurality of cascaded first shift registers comprises a second capacitor, and the second capacitor comprises a first plate and a second plate. For the cross-stage connection line electrically connected with the cascade signal output end of the nth first shift register, the first cross-stage connection part is an integral structure with the second plate of the second capacitor in the nth first shift register.

14. The display substrate of claim 11, further comprising: A substrate and a driving circuit layer arranged on the substrate; The first gate drive circuit is arranged on the driving circuit layer, and the driving circuit layer comprises a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer which are sequentially stacked on the substrate, the at least one first shift register comprises at least one transistor and at least one capacitor, the at least one transistor comprises an active pattern, a control pole, a first pole and a second pole, and the at least one capacitor comprises a first plate and a second plate; The semiconductor layer comprises the active pattern of the at least one transistor of the at least one first shift register; The first conductive layer comprises the control pole of the at least one transistor and the first plate of the at least one capacitor of the at least one first shift register; The second conductive layer comprises the second plate of the at least one capacitor of the at least one first shift register and the first cross-stage connection part of at least one cross-stage connection line; The third conductive layer comprises the first pole and the second pole of the at least one transistor of the at least one first shift register and the second cross-stage connection part of at least one cross-stage connection line; The fourth conductive layer comprises the third cross-stage connection part of at least one cross-stage connection line. 15.The display substrate of claim 14, wherein, The at least one first shift register comprises a first transistor, an eleventh transistor, a fourteenth transistor and a fifteenth transistor; A first cross-stage connection portion in at least one of the plurality of cross-stage connection lines at least partially overlaps a first projection of a first transistor of the at least one stage first shift register on the substrate; A second cross-stage connection portion in at least one of the plurality of cross-stage connection lines at least partially overlaps a control electrode projection of an eleventh transistor of the at least one stage first shift register on the substrate; A third cross-stage connection portion in at least one of the plurality of cross-stage connection lines at least partially overlaps a control electrode projection of at least one of a thirteenth transistor and a fourteenth transistor of the at least one stage first shift register on the substrate.

16. The display substrate of claim 14, further comprising: A clock signal line group located in the non-display area is arranged on the driving circuit layer and located in the fourth conductive layer; The plurality of cross-stage connection lines are located on a side of the clock signal line group close to the display area; The clock signal line group comprises a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line arranged in sequence close to the display area, and at least one of the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line at least partially extends along the second direction. 17.The display substrate of claim 16, wherein, The first clock signal end of the 4i-3 stage first shift register is electrically connected to the first clock signal line, the second clock signal end of the 4i-3 stage first shift register is electrically connected to the second clock signal line, the third clock signal end of the 4i-3 stage first shift register is electrically connected to the third clock signal line, the first clock signal end of the 4i-2 stage first shift register is electrically connected to the second clock signal line, the second clock signal end of the 4i-2 stage first shift register is electrically connected to the third clock signal line, the third clock signal end of the 4i-2 stage first shift register is electrically connected to the fourth clock signal line, the first clock signal end of the 4i-1 stage first shift register is electrically connected to the third clock signal line, the second clock signal end of the 4i-1 stage first shift register is electrically connected to the fourth clock signal line, the third clock signal end of the 4i-1 stage first shift register is electrically connected to the first clock signal line, the first clock signal end of the 4i stage first shift register is electrically connected to the fourth clock signal line, the second clock signal end of the 4i stage first shift register is electrically connected to the first clock signal line, and the third clock signal end of the 4i stage first shift register is electrically connected to the second clock signal line.

18. The display plate of claim 16, wherein, The at least one stage first shift register comprises a first transistor, a second transistor, a sixth transistor, a seventh transistor and an eighth transistor. The clock signal line group at least partially overlaps at least one of the first transistor, the second transistor, the sixth transistor, the seventh transistor and the eighth transistor of the at least one stage first shift register on the substrate.

19. The display substrate of claim 14, further comprising: A power signal line group and a clock signal line group located in the non-display region, the power signal line group and the clock signal line group being arranged in the driving circuit layer and located in the fourth conductive layer; The power signal line group comprises two first power lines and two second power lines, the first power lines and the second power lines extending at least partially along the second direction; The first second power line is located on the side of the clock signal line group away from the display region, the first first power line is located on the side of the clock signal line group close to the display region, the second second power line is located on the side of the first first power line close to the display region, the second first power line is located on the side of the second second power line close to the display region, and the plurality of cross-stage connection lines are located between the second second power line and the second first power line; The first power lines are electrically connected to the first power supply ends of the at least one first shift register, and the second power lines are electrically connected to the second power supply ends of the at least one first shift register. 20.The display substrate of claim 19, wherein, The at least one first shift register comprises a third transistor, a fourth transistor, a fifth transistor, a ninth transistor, a tenth transistor, and a third capacitor; The first first power line is at least partially overlapped with the fourth transistor and the fifth transistor in the at least one first shift register in the orthographic projection on the substrate, the first second power line is at least partially overlapped with the third transistor in the at least one first shift register in the orthographic projection on the substrate, the second first power line is at least partially overlapped with the ninth transistor and the tenth transistor in the at least one first shift register in the orthographic projection on the substrate, and the second second power line is at least partially overlapped with the third capacitor in the at least one first shift register in the orthographic projection on the substrate.

21. The display substrate of claim 19, further comprising: A scan initial signal line located in the non-display region, the scan initial signal line being arranged in the driving circuit layer and located in the fourth conductive layer, and extending at least partially along the second direction; The scan initial signal line is located between the first second power line and the clock signal line group; The signal input ends of the first-stage first shift register and the second-stage first shift register are respectively electrically connected to the scan initial signal line; The at least one first shift register comprises a second transistor; The scan initial signal line is at least partially overlapped with the second transistor in the at least one first shift register in the orthographic projection on the substrate.

22. The display substrate of claim 19, wherein, The power signal line group further comprises a third power line, the third power line extending at least partially along the second direction; The third power line is located between the first first power line and the second second power line; The display region is provided with light emitting devices, and the third power line is electrically connected to the second poles of the at least one light emitting device; The at least one first shift register comprises a first capacitor and a second capacitor; A third power line, a projection of the third power line on the substrate at least partially overlaps with a projection of the first capacitor and the second capacitor of the at least one stage of the first shift register on the substrate; A length of the third power line along the first direction is greater than a length of at least one of the first power line and the second power line along the first direction.

23. The display substrate of claim 19, further comprising: A mask signal line located in the non-display region, the mask signal line is arranged in the driving circuit layer and located in the fourth conductive layer, the mask signal line at least partially extends along the second direction; The mask signal line is located on a side of the power signal line group close to the display region; The mask signal line is electrically connected with a mask signal terminal of the at least one stage of the first shift register; The at least one stage of the first shift register comprises a fourth capacitor and a fifth capacitor; A projection of the mask signal line on the substrate at least partially overlaps with a projection of the fourth capacitor and the fifth capacitor of the at least one stage of the first shift register on the substrate.

24. The display substrate of claim 23, further comprising: A plurality of pixel initial signal lines located in the non-display region; At least one of the plurality of pixel initial signal lines is arranged in the driving circuit layer and located in the fourth conductive layer, at least one of the plurality of pixel initial signal lines at least partially extends along the second direction; The plurality of pixel initial signal lines are located on a side of the mask signal line close to the display region; A projection of at least one of the plurality of pixel initial signal lines on the substrate at least partially overlaps with a projection of the fourth capacitor and the fifth capacitor of the at least one stage of the first shift register on the substrate; A length of at least one of the plurality of pixel initial signal lines along the first direction is greater than a length of the mask signal line along the first direction.

25. The display substrate of claim 7, further comprising: A second gate drive circuit located in the non-display region, the second gate drive circuit comprises a plurality of cascaded second shift registers, the second shift register comprises a light-emitting signal output terminal; The display region is provided with a plurality of pixel drive circuits, the pixel drive circuit comprises a light-emitting transistor and a write transistor; At least one stage of the first shift register is electrically connected with the write transistor in at least one row of pixel drive circuits, and at least one stage of the second shift register is electrically connected with the light-emitting transistor in at least one row of pixel drive circuits; A second control signal terminal of at least one stage of the first shift register is electrically connected with a light-emitting signal output terminal of at least one stage of the second shift register.

26. A display device comprising: The display substrate of any one of claims 7 to 25.

27. A driving method of a shift register configured to drive the shift register of any one of claims 1 to 6, the method comprising: The shift sub-circuit provides the signal of the second power terminal and one of the second clock signal terminals to the second node, provides the signal of the signal input terminal to the third node, and provides the signal of one of the first power terminal and the third clock signal terminal to the cascaded signal output terminal under the control of the signals of the second node and the third node. The output sub-circuit provides a signal of one of the first power supply terminal and the third clock signal terminal to the driving signal output terminal under control of a signal of at least one of the second node, the third node, the first control signal terminal, the second control signal terminal, the signal input terminal and the masking signal terminal.

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