Shift register and driving method thereof, gate driving circuit and display device

Abstract

A shift register and a driving method thereof, a gate driving circuit and a display device, the shift register can include: a control sub-circuit and an output sub-circuit; the control sub-circuit is electrically connected with a signal input end, a first clock signal end, a first node and a second node respectively, and is configured to provide a signal to the first node or the second node under the control of signals of the signal input end and the first clock signal end; the output sub-circuit is electrically connected with the first node, the second node, at least one power signal end and at least one output signal end respectively, and is configured to provide a signal to the at least one output signal end under the control of signals of the first node, the second node and the at least one power signal end.

Description

Shift register and driving method thereof, gate driving circuit and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, display technology, in particular to a shift register and driving method thereof, a gate driving circuit and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-luminous, wide viewing angle, high contrast, low power consumption, extremely high response speed, light and thin, bendable and low cost. With the continuous development of display technology, flexible display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, an embodiment of the present disclosure provides a shift register, comprising: a control sub-circuit and an output sub-circuit;

[0006] The control sub-circuit is electrically connected with a signal input end, a first clock signal end, a first node and a second node respectively, and is configured to provide a signal to the first node or the second node under the control of signals at the signal input end and the first clock signal end;

[0007] The output sub-circuit is electrically connected with the first node, the second node, at least one power signal end and at least one output signal end respectively, and is configured to provide a signal to the at least one output signal end under the control of signals at the first node, the second node and the at least one power signal end.

[0008] In some possible implementations, the control sub-circuit comprises a first control sub-circuit, and the first control sub-circuit is further electrically connected with a first power end and a second power end;

[0009] Alternatively,

[0010] The control sub-circuit comprises a second control sub-circuit, and the second control sub-circuit is further electrically connected with the first power end, the second power end and a third power end;

[0011] Alternatively,

[0012] The control sub-circuit comprises a third control sub-circuit, and the third control sub-circuit is further electrically connected with the first power supply end.

[0013] In some possible implementation manners, the first control sub-circuit comprises a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a third capacitor.

[0014] The control electrode of the third transistor is electrically connected with the first clock signal end, the first electrode of the third transistor is electrically connected with the signal input end, and the second electrode of the third transistor is electrically connected with the second node.

[0015] The control electrode of the fifth transistor is electrically connected with the third node, the first electrode of the fifth transistor is electrically connected with the second power supply end, and the second electrode of the fifth transistor is electrically connected with the fourth node.

[0016] The control electrode of the sixth transistor is electrically connected with the signal input end, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power supply end.

[0017] The control electrode of the seventh transistor is electrically connected with the signal input end, the first electrode of the seventh transistor is electrically connected with the third node, and the second electrode of the seventh transistor is electrically connected with the first power supply end.

[0018] The control electrode of the eighth transistor is electrically connected with the first clock signal end, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node.

[0019] The third capacitor comprises a first plate and a second plate, the first plate of the third capacitor is electrically connected with the first clock signal end, and the second plate of the third capacitor is electrically connected with the third node.

[0020] In some possible implementation manners, the first control sub-circuit comprises a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor.

[0021] The control electrode of the third transistor is electrically connected with the first clock signal end, the first electrode of the third transistor is electrically connected with the signal input end, and the second electrode of the third transistor is electrically connected with the second node.

[0022] The control electrode of the fifth transistor is electrically connected with the fifth node, the first electrode of the fifth transistor is electrically connected with the second power supply end, and the second electrode of the fifth transistor is electrically connected with the fourth node.

[0023] The control electrode of the sixth transistor is electrically connected with the signal input end, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power supply end.

[0024] The control electrode of the seventh transistor is electrically connected with the signal input end, the first electrode of the seventh transistor is electrically connected with the sixth node, and the second electrode of the seventh transistor is electrically connected with the first power supply end;

[0025] The control electrode of the eighth transistor is electrically connected with the first clock signal end, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node;

[0026] The control electrode of the ninth transistor is electrically connected with the first clock signal end, the first electrode of the ninth transistor is electrically connected with the fifth node, and the second electrode of the ninth transistor is electrically connected with the sixth node.

[0027] In some possible implementation manners, the third control sub-circuit includes a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a third capacitor.

[0028] The control electrode of the third transistor is electrically connected with the first clock signal end, the first electrode of the third transistor is electrically connected with the signal input end, and the second electrode of the third transistor is electrically connected with the second node;

[0029] The control electrode of the fifth transistor is electrically connected with the third node, the first electrode of the fifth transistor is electrically connected with the first clock signal end, and the second electrode of the fifth transistor is electrically connected with the fourth node;

[0030] The control electrode of the sixth transistor is electrically connected with the signal input end, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power supply end;

[0031] The control electrode of the seventh transistor is electrically connected with the signal input end, the first electrode of the seventh transistor is electrically connected with the third node, and the second electrode of the seventh transistor is electrically connected with the first power supply end;

[0032] The control electrode of the eighth transistor is electrically connected with the first clock signal end, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node;

[0033] The third capacitor includes a first plate and a second plate, the first plate of the third capacitor is electrically connected with the first clock signal end, and the second plate of the third capacitor is electrically connected with the third node.

[0034] In some possible implementation manners, the third control sub-circuit includes a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor.

[0035] The control electrode of the third transistor is electrically connected with the first clock signal end, the first electrode of the third transistor is electrically connected with the signal input end, and the second electrode of the third transistor is electrically connected with the second node;

[0036] The control electrode of the fifth transistor is electrically connected with the fifth node, the first electrode of the fifth transistor is electrically connected with the first clock signal end, and the second electrode of the fifth transistor is electrically connected with the fourth node.

[0037] The control electrode of the sixth transistor is electrically connected with the signal input end, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power supply end.

[0038] The control electrode of the seventh transistor is electrically connected with the signal input end, the first electrode of the seventh transistor is electrically connected with the sixth node, and the second electrode of the seventh transistor is electrically connected with the first power supply end.

[0039] The control electrode of the eighth transistor is electrically connected with the first clock signal end, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node.

[0040] The control electrode of the ninth transistor is electrically connected with the first clock signal end, the first electrode of the ninth transistor is electrically connected with the fifth node, and the second electrode of the ninth transistor is electrically connected with the sixth node.

[0041] In some possible implementation manners, the first control sub-circuit comprises a third transistor, a fifth transistor, a sixth transistor, a seventh transistor and a third capacitor.

[0042] The control electrode of the third transistor is electrically connected with the first clock signal end, the first electrode of the third transistor is electrically connected with the signal input end, and the second electrode of the third transistor is electrically connected with the second node.

[0043] The control electrode of the fifth transistor is electrically connected with the third node, the first electrode of the fifth transistor is electrically connected with the second power supply end, and the second electrode of the fifth transistor is electrically connected with the first node.

[0044] The control electrode of the sixth transistor is electrically connected with the second node, the first electrode of the sixth transistor is electrically connected with the first node, and the second electrode of the sixth transistor is electrically connected with the first power supply end.

[0045] The control electrode of the seventh transistor is electrically connected with the signal input end, the first electrode of the seventh transistor is electrically connected with the third node, and the second electrode of the seventh transistor is electrically connected with the first power supply end.

[0046] The third capacitor comprises a first plate and a second plate, the first plate of the third capacitor is electrically connected with the first clock signal end, and the second plate of the third capacitor is electrically connected with the third node.

[0047] In some possible implementation manners, the fifth transistor is a P-type transistor.

[0048] In some possible implementation manners, the first control sub-circuit comprises a third transistor, a fifth transistor, a sixth transistor and an eighth transistor.

[0049] The control electrode of the third transistor is electrically connected with the first clock signal end, the first electrode of the third transistor is electrically connected with the signal input end, and the second electrode of the third transistor is electrically connected with the second node;

[0050] The control electrode of the fifth transistor is electrically connected with the signal input end, the first electrode of the fifth transistor is electrically connected with the second power supply end, and the second electrode of the fifth transistor is electrically connected with the fourth node;

[0051] The control electrode of the sixth transistor is electrically connected with the signal input end, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power supply end;

[0052] The control electrode of the eighth transistor is electrically connected with the first clock signal end, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node.

[0053] In some possible implementation manners, the second control sub-circuit includes: a third transistor, a fifth transistor, a sixth transistor and an eighth transistor, the fifth transistor is a double-gate transistor, and includes a first control electrode and a second control electrode;

[0054] The control electrode of the third transistor is electrically connected with the first clock signal end, the first electrode of the third transistor is electrically connected with the signal input end, and the second electrode of the third transistor is electrically connected with the second node;

[0055] The first control electrode of the fifth transistor is electrically connected with the signal input end, the second control electrode of the fifth transistor is electrically connected with the third power supply end, the first electrode of the fifth transistor is electrically connected with the second power supply end, and the second electrode of the fifth transistor is electrically connected with the fourth node;

[0056] The control electrode of the sixth transistor is electrically connected with the signal input end, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power supply end;

[0057] The control electrode of the eighth transistor is electrically connected with the first clock signal end, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node.

[0058] In some possible implementation manners, the signals of the second power supply end and the third power supply end are low-level signals, and the voltage value of the third power supply end is less than or equal to the voltage value of the second power supply end.

[0059] In some possible implementation manners, the fifth transistor is an N-type transistor.

[0060] In some possible implementation manners, the control sub-circuit is further electrically connected with the second clock signal terminal and the first power supply terminal, and is configured to provide a signal of the first power supply terminal to the second node under control of signals of the first node and the second clock signal terminal.

[0061] In some possible implementation manners, the control sub-circuit further includes a tenth transistor and an eleventh transistor.

[0062] The control electrode of the tenth transistor is electrically connected with the first node, the first electrode of the tenth transistor is electrically connected with the first power supply terminal, and the second electrode of the tenth transistor is electrically connected with the seventh node.

[0063] The control electrode of the eleventh transistor is electrically connected with the second clock signal terminal, the first electrode of the eleventh transistor is electrically connected with the seventh node, and the second electrode of the eleventh transistor is electrically connected with the second node.

[0064] In some possible implementation manners, the at least one power supply signal terminal includes a fourth power supply terminal and a fifth power supply terminal, and the at least one output signal terminal includes a signal output terminal.

[0065] The output sub-circuit is further electrically connected with the second clock signal terminal, and is configured to provide a signal of the fourth power supply terminal or the second clock signal terminal to the signal output terminal under control of signals of the first node and the second node.

[0066] In some possible implementation manners, the output sub-circuit includes a first transistor, a second transistor, a fourth transistor, a first capacitor and a second capacitor.

[0067] The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fourth power supply terminal, and the second electrode of the first transistor is electrically connected with the signal output terminal.

[0068] The control electrode of the second transistor is electrically connected with the eighth node, the first electrode of the second transistor is electrically connected with the signal output terminal, and the second electrode of the second transistor is electrically connected with the second clock signal terminal.

[0069] The control electrode of the fourth transistor is electrically connected with the fifth power supply terminal, the first electrode of the fourth transistor is electrically connected with the second node, and the second electrode of the fourth transistor is electrically connected with the eighth node.

[0070] The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the eighth node, and the second plate of the first capacitor is electrically connected with the signal output terminal.

[0071] The second capacitor includes a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with the fourth power supply terminal.

[0072] In some possible implementation manners, the at least one power signal terminal includes a fourth power terminal, a fifth power terminal and a sixth power terminal, and the at least one output signal terminal includes a signal output terminal and a cascade output terminal.

[0073] The output sub-circuit is further electrically connected with a second clock signal terminal and a third clock signal terminal, and is configured to provide, under control of signals of the first node and the second node, a signal of the sixth power terminal or the third clock signal terminal to the signal output terminal, and provide a signal of the fourth power terminal or the second clock signal terminal to the cascade output terminal.

[0074] In some possible implementation manners, the output sub-circuit includes a first transistor, a second transistor, a fourth transistor, a twelfth transistor, a thirteenth transistor, a first capacitor and a second capacitor.

[0075] The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fourth power terminal, and the second electrode of the first transistor is electrically connected with the cascade output terminal.

[0076] The control electrode of the second transistor is electrically connected with the eighth node, the first electrode of the second transistor is electrically connected with the cascade output terminal, and the second electrode of the second transistor is electrically connected with the second clock signal terminal.

[0077] The control electrode of the fourth transistor is electrically connected with the fifth power terminal, the first electrode of the fourth transistor is electrically connected with the second node, and the second electrode of the fourth transistor is electrically connected with the eighth node.

[0078] The control electrode of the twelfth transistor is electrically connected with the first node, the first electrode of the twelfth transistor is electrically connected with the sixth power terminal, and the second electrode of the twelfth transistor is electrically connected with the signal output terminal.

[0079] The control electrode of the thirteenth transistor is electrically connected with the eighth node, the first electrode of the thirteenth transistor is electrically connected with the signal output terminal, and the second electrode of the thirteenth transistor is electrically connected with the third clock signal terminal.

[0080] The first capacitor includes a first plate and a second plate, the first plate of the first capacitor is electrically connected with the eighth node, and the second plate of the first capacitor is electrically connected with the cascade output terminal.

[0081] The second capacitor includes a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with the fourth power terminal.

[0082] In some possible implementation manners, the at least one power signal terminal includes a fourth power terminal, a fifth power terminal and a sixth power terminal, and the at least one output signal terminal includes a signal output terminal and a cascade output terminal.

[0083] The output sub-circuit is further electrically connected with a third clock signal terminal, and is configured to provide a signal of the sixth power supply terminal or the third clock signal terminal to the signal output terminal and provide a signal of the fourth power supply terminal or the fifth power supply terminal to the cascade output terminal under control of signals of the first node and the second node.

[0084] In some possible implementation manners, the output sub-circuit comprises a first transistor, a second transistor, a fourth transistor, a twelfth transistor, a thirteenth transistor, a first capacitor and a second capacitor.

[0085] The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fourth power supply terminal, and the second electrode of the first transistor is electrically connected with the cascade output terminal.

[0086] The control electrode of the second transistor is electrically connected with the eighth node, the first electrode of the second transistor is electrically connected with the cascade output terminal, and the second electrode of the second transistor is electrically connected with the fifth power supply terminal.

[0087] The control electrode of the fourth transistor is electrically connected with the fifth power supply terminal, the first electrode of the fourth transistor is electrically connected with the second node, and the second electrode of the fourth transistor is electrically connected with the eighth node.

[0088] The control electrode of the twelfth transistor is electrically connected with the first node, the first electrode of the twelfth transistor is electrically connected with the sixth power supply terminal, and the second electrode of the twelfth transistor is electrically connected with the signal output terminal.

[0089] The control electrode of the thirteenth transistor is electrically connected with the eighth node, the first electrode of the thirteenth transistor is electrically connected with the signal output terminal, and the second electrode of the thirteenth transistor is electrically connected with the third clock signal terminal.

[0090] The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the eighth node, and the second plate of the first capacitor is electrically connected with the cascade output terminal.

[0091] The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with the fourth power supply terminal.

[0092] In a second aspect, the embodiments of the present disclosure provide a gate drive circuit, comprising: a plurality of cascaded shift registers as described in any of the embodiments of the first aspect, at least one output signal terminal of at least one shift register comprises: a signal output terminal.

[0093] The signal output terminal of the i-th shift register is electrically connected with the signal input terminal of the i+L-th shift register, 1≤i≤M-L, M is the total number of stages of the shift registers, M≥1, and L is a positive integer greater than or equal to 1.

[0094] In a third aspect, the embodiments of the present disclosure provide a display device, comprising a display area and a non-display area, the display area is provided with pixel driving circuits arranged in an array, and the non-display area is provided with the gate driving circuit according to any one of the embodiments of the second aspect, the pixel driving circuit comprises a write transistor.

[0095] The at least one stage of shift registers in the gate driving circuit is electrically connected with the write transistor of the at least one row of pixel driving circuits.

[0096] In some possible implementation manners, the control sub-circuit is electrically connected with the signal input end, the first clock signal end and the second clock signal end respectively, and the display device further comprises an initial signal line, a first clock signal line and a second clock signal line.

[0097] The signal input end of the at least one stage of shift registers is electrically connected with the initial signal line, the first clock signal end is electrically connected with one of the first clock signal line and the second clock signal line, the second clock signal end is electrically connected with the other of the first clock signal line and the second clock signal line, the signal line connected with the first clock signal end of the adjacent shift register is different, and the signal line connected with the second clock signal end of the adjacent shift register is different.

[0098] In some possible implementation manners, the control sub-circuit is electrically connected with the signal input end, the first clock signal end and the second clock signal end respectively, and the display device further comprises an initial signal line, a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line.

[0099] The signal input end of the at least one stage of shift registers is electrically connected with the initial signal line.

[0100] The first clock signal end of the 4M-3 stage shift register is electrically connected with the first clock signal line, and the second clock signal end is electrically connected with the third clock signal line.

[0101] The first clock signal end of the 4M-2 stage shift register is electrically connected with the second clock signal line, and the second clock signal end is electrically connected with the fourth clock signal line.

[0102] The first clock signal end of the 4M-1 stage shift register is electrically connected with the third clock signal line, and the second clock signal end is electrically connected with the first clock signal line.

[0103] The first clock signal end of the 4M stage shift register is electrically connected with the fourth clock signal line, and the second clock signal end is electrically connected with the second clock signal line.

[0104] Wherein, M is the total number of stages of shift registers, and M≥1.

[0105] In a fourth aspect, the embodiments of the present disclosure provide a driving method of a shift register, configured to drive the shift register of any of the embodiments of the first aspect, and the method comprises:

[0106] The control sub-circuit provides a signal to the first node or the second node under the control of signals at the signal input end and the first clock signal end;

[0107] The output sub-circuit provides a signal to the at least one output signal end under the control of signals at the first node, the second node and the at least one power signal end.

[0108] Other aspects can be apparent after reading and understanding the accompanying drawings and detailed description.

[0109] SUMMARY

[0110] The accompanying drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0111] FIG. 1 is a structural schematic diagram of a shift register provided by an example embodiment of the present disclosure;

[0112] FIG. 2 is an equivalent circuit diagram of a control sub-circuit provided by an example embodiment;

[0113] FIG. 3 is an equivalent circuit diagram of a control sub-circuit provided by an example embodiment;

[0114] FIG. 4 is an equivalent circuit diagram of a control sub-circuit provided by an example embodiment;

[0115] FIG. 5 is an equivalent circuit diagram of a control sub-circuit provided by an example embodiment;

[0116] FIG. 6 is an equivalent circuit diagram of a control sub-circuit provided by an example embodiment;

[0117] FIG. 7 is an equivalent circuit diagram of a control sub-circuit provided by an example embodiment;

[0118] FIG. 8 is an equivalent circuit diagram of a control sub-circuit provided by an example embodiment;

[0119] FIG. 9 is an equivalent circuit diagram of a control sub-circuit provided by an example embodiment;

[0120] FIG. 10 is an equivalent circuit diagram of an output sub-circuit provided by an example embodiment;

[0121] FIG. 11 is an equivalent circuit diagram of an output sub-circuit provided by an example embodiment;

[0122] Figure 12 is an equivalent circuit diagram of an output sub-circuit according to an example embodiment;

[0123] Figure 13 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0124] Figure 14 is a timing diagram of the operation of the shift register of Figure 13 according to an example embodiment;

[0125] Figure 15 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0126] Figure 16 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0127] Figure 17 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0128] Figure 18 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0129] Figure 19 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0130] Figure 20 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0131] Figure 21 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0132] Figure 22 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0133] Figure 23 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0134] Figure 24 is a structural circuit diagram of a display device according to an example embodiment;

[0135] Figure 25 is an output timing diagram of a multi-stage shift register according to an example embodiment;

[0136] Figure 26 is a structural circuit diagram of a display device according to an example embodiment;

[0137] Figure 27 is an output timing diagram of a multi-stage shift register according to an example embodiment.

[0138] DETAILED DESCRIPTION

[0139] For the purpose of making the objects, technical solutions and advantages of the present disclosure clearer, the following will describe the embodiments of the present disclosure in detail with reference to the drawings. Note that the embodiments can be implemented in a variety of different forms. It should be understood by those skilled in the art that the embodiments and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and brief, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed

[0140] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0141] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided to avoid confusion of components, and are not intended to be limiting in terms of number.

[0142] In the present specification, for the purpose of convenience, words indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, only for the purpose of facilitating the description of the present specification and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0143] In the present specification, unless otherwise explicitly specified and limited, the terms "mount", "connect", "connection" should be interpreted broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0144] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0145] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In the case of using a transistor having opposite polarity or in the case of changing the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other.

[0146] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0147] In this specification, "parallel" means a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0148] In this specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be changed into "a conductive film". Similarly, "an insulating film" can be changed into "an insulating layer".

[0149] In this specification, "disposed in the same layer" means that two (or more) structures are formed by patterning at the same time, and the materials thereof can be the same or different. For example, the materials of precursors used for forming the two (or more) structures in the same layer are the same, and the materials of the formed structures can be the same or different.

[0150] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, but can be an approximately triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can have some small deformation due to a tolerance, can have a rounded corner, a rounded side, or deformation.

[0151] In the present disclosure, "about" means not strictly limited to the boundary, allowing values within the range of process and measurement errors.

[0152] The current display device uses a cascade driving circuit to generate a scanning signal, but the current cascade driving circuit output mode is relatively single and cannot meet the display requirements.

[0153] Figure 1 is a structural schematic diagram of a shift register provided by an example embodiment of the present disclosure, as shown in Figure 1, the shift register can include: a control sub-circuit and an output sub-circuit.

[0154] The control sub-circuit is electrically connected with the signal input end IN, the first clock signal end CLK1, the first node N1 and the second node N2 respectively, and is configured to provide a signal to the first node N1 or the second node N2 under the control of signals of the signal input end IN and the first clock signal end CLK1.

[0155] The output sub-circuit is electrically connected with the first node N1, the second node N2, at least one power signal end Vn and at least one output signal end Gn respectively, and is configured to provide a signal to the at least one output signal end Gn under the control of signals of the first node N1, the second node N2 and the at least one power signal end Vn.

[0156] In an example embodiment, the signal of the first clock signal end CLK1 can be a periodic pulse signal.

[0157] In the embodiment of the present disclosure, the control sub-circuit can provide a signal to the first node or the second node under the control of signals of the signal input end and the first clock signal end, and the output sub-circuit can provide a signal to the at least one output signal end under the control of signals of the first node, the second node and the at least one power signal end. By providing a signal to the at least one output signal end under the control of signals of the signal input end and the first clock signal end, the signal output of the shift register is realized, and the positive and negative of the pulse of the signal on the signal input end can determine the positive and negative of the pulse of the output signal of the shift register.

[0158] In an example embodiment, the control sub-circuit can include: a first control sub-circuit, and the first control sub-circuit is further electrically connected with a first power end V1 and a second power end V2.

[0159] Figure 2 is an equivalent circuit diagram of a control sub-circuit provided by an example embodiment, as shown in Figure 2, the first control sub-circuit is further electrically connected with the first power end V1 and the second power end V2, and the first control sub-circuit can include: a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a third capacitor C3.

[0160] In an example embodiment, as shown in FIG. 2, the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is electrically connected to the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control electrode of the seventh transistor T7 is electrically connected to the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected to the first clock signal terminal CLK1, and the second plate C32 of the third capacitor is electrically connected to the third node N3.

[0161] In an example embodiment, as shown in FIG. 2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are P-type transistors.

[0162] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal, and the signal of the second power supply terminal V2 is a low-level signal.

[0163] An example structure of the control sub-circuit is shown in FIG. 2. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited to this.

[0164] FIG. 3 is an equivalent circuit diagram of the control sub-circuit provided in an example embodiment. As shown in FIG. 3, the first control sub-circuit is further electrically connected to the first power supply terminal V1 and the second power supply terminal V2, and the first control sub-circuit can include: the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9.

[0165] In an example embodiment, as shown in FIG. 3, the control electrode of the third transistor T3 is electrically connected with the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected with the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply terminal V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected with the sixth node N6, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; and the control electrode of the ninth transistor T9 is electrically connected with the first clock signal terminal CLK1, the first electrode of the ninth transistor T9 is electrically connected with the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected with the sixth node N6.

[0166] In an example embodiment, as shown in FIG. 3, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are P-type transistors.

[0167] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal, and the signal of the second power supply terminal V2 is a low-level signal.

[0168] An example structure of the control sub-circuit is shown in FIG. 3. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited to this.

[0169] In an example embodiment, the control sub-circuit can further include a third control sub-circuit, and the third control sub-circuit is also electrically connected with the first power supply terminal V1.

[0170] An equivalent circuit diagram of the control sub-circuit provided by an example embodiment is shown in FIG. 4. As shown in FIG. 4, the third control sub-circuit is also electrically connected with the first power supply terminal V1, and the control sub-circuit can include the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the third capacitor C3.

[0171] In an example embodiment, as shown in FIG. 4, the control electrode of the third transistor T3 is electrically connected with the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the third node N3, the first electrode of the fifth transistor T5 is electrically connected with the first clock signal terminal CLK1, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply terminal V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal terminal CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3.

[0172] In an example embodiment, as shown in FIG. 4, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are P-type transistors.

[0173] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal.

[0174] An example structure of the control sub-circuit is shown in FIG. 4. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited to this.

[0175] An equivalent circuit diagram of the control sub-circuit provided in an example embodiment is shown in FIG. 5. As shown in FIG. 5, the third control sub-circuit is also electrically connected with the first power supply terminal V1, and the third control sub-circuit can include: the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9.

[0176] In an example embodiment, as shown in FIG. 5, the control electrode of the third transistor T3 is electrically connected with the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected with the first clock signal terminal CLK1, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply terminal V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected with the sixth node N6, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the ninth transistor T9 is electrically connected with the first clock signal terminal CLK1, the first electrode of the ninth transistor T9 is electrically connected with the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected with the sixth node N6.

[0177] In an example embodiment, as shown in FIG. 5, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are P-type transistors.

[0178] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal.

[0179] An example structure of the control sub-circuit is shown in FIG. 5. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited to this.

[0180] FIG. 6 is an equivalent circuit diagram of the control sub-circuit provided in an example embodiment. As shown in FIG. 6, the first control sub-circuit is further electrically connected with the first power supply terminal V1 and the second power supply terminal V2, and the first control sub-circuit comprises the third transistor T3, the fifth transistor T5, the sixth transistor T6 and the eighth transistor T8.

[0181] In an example embodiment, as shown in FIG. 6, the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the signal input terminal IN, the first electrode of the fifth transistor T5 is electrically connected to the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1.

[0182] In an example embodiment, as shown in FIG. 6, the fifth transistor T5 is an N-type transistor, and the third transistor T3, the sixth transistor T6, and the eighth transistor T8 are P-type transistors.

[0183] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal, and the signal of the second power supply terminal V2 is a low-level signal.

[0184] An example structure of the control sub-circuit is shown in FIG. 6. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited to this.

[0185] In an example embodiment, the control sub-circuit can include a second control sub-circuit, and the second control sub-circuit is also electrically connected to the first power supply terminal V1, the second power supply terminal V2, and the third power supply terminal V3.

[0186] FIG. 7 is an equivalent circuit diagram of the control sub-circuit provided by an example embodiment. As shown in FIG. 7, the second control sub-circuit is also electrically connected to the first power supply terminal V1, the second power supply terminal V2, and the third power supply terminal V3, and the second control sub-circuit includes: the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8, the fifth transistor T5 is a double-gate transistor, and includes a first control electrode and a second control electrode.

[0187] In an example embodiment, as shown in FIG. 7, the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the first control electrode of the fifth transistor T5 is electrically connected to the signal input terminal IN, the second control electrode of the fifth transistor T5 is electrically connected to the third power supply terminal V3, the first electrode of the fifth transistor T5 is electrically connected to the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1.

[0188] In an example embodiment, as shown in FIG. 7, the fifth transistor T5 is an N-type transistor, and the third transistor T3, the sixth transistor T6, and the eighth transistor T8 are P-type transistors.

[0189] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal, the signal of the second power supply terminal V2 is a low-level signal, and the signal of the third power supply terminal V3 is a low-level signal.

[0190] In an example embodiment, the voltage value of the third power supply terminal V3 is less than or equal to the voltage value of the second power supply terminal V2.

[0191] An example structure of the control sub-circuit is shown in FIG. 7. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited to this.

[0192] FIG. 8 is an equivalent circuit diagram of the control sub-circuit provided in an example embodiment. As shown in FIG. 8, the control sub-circuit is also electrically connected to the first power supply terminal V1 and the second power supply terminal V2, and the first control sub-circuit can include the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the third capacitor C3.

[0193] In an example embodiment, as shown in FIG. 8, the control electrode of the third transistor T3 is electrically connected with the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the third node N3, the first electrode of the fifth transistor T5 is electrically connected with the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected with the first node N1; the control electrode of the sixth transistor T6 is electrically connected with the second node N2, the first electrode of the sixth transistor T6 is electrically connected with the first node N1, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply terminal V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply terminal V1; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal terminal CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3.

[0194] In an example embodiment, as shown in FIG. 8, the third transistor T3, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are P-type transistors.

[0195] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal, and the signal of the second power supply terminal V2 is a low-level signal.

[0196] An example structure of the control sub-circuit is shown in FIG. 8. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited to this.

[0197] In an example embodiment, the control sub-circuit is further electrically connected with the second clock signal terminal CLK2 and the first power supply terminal V1, and is configured to provide the signal of the first power supply terminal V1 to the second node N2 under the control of the first node N1 and the signal of the second clock signal terminal CLK2.

[0198] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal.

[0199] In the embodiments of the present disclosure, the control sub-circuit can provide the signal of the first power supply terminal V1 to the second node N2 under the control of the first node N1 and the signal of the second clock signal terminal CLK2, thereby increasing the anti-noise capability of the second node N2.

[0200] FIG. 9 is an equivalent circuit diagram of the control sub-circuit provided by an example embodiment, as shown in FIG. 9, the control sub-circuit can further include a tenth transistor T10 and an eleventh transistor T11.

[0201] In an example embodiment, as shown in FIG. 9, the control electrode of the tenth transistor T10 is electrically connected with the first node N1, the first electrode of the tenth transistor T10 is electrically connected with the first power supply end V1, and the second electrode of the tenth transistor T10 is electrically connected with the seventh node N7; the control electrode of the eleventh transistor T11 is electrically connected with the second clock signal end CLK2, the first electrode of the eleventh transistor T11 is electrically connected with the seventh node N7, and the second electrode of the eleventh transistor T11 is electrically connected with the second node N2.

[0202] In an example embodiment, as shown in FIG. 9, the tenth transistor T10 and the eleventh transistor T11 are P-type transistors.

[0203] In the embodiments of the present disclosure, the tenth transistor T10 and the eleventh transistor T11 form the anti-noise circuit, and the anti-noise capability of the second node N2 is increased.

[0204] In the embodiments of the present disclosure, only the anti-noise circuit formed by the tenth transistor T10 and the eleventh transistor T11 based on the control sub-circuit shown in FIG. 2 is exemplified, and the implementation manners of the anti-noise circuit formed by the tenth transistor T10 and the eleventh transistor T11 based on the control sub-circuits shown in FIGS. 3 to 8 are the same as or similar to those, and the embodiments of the present disclosure are not limited and elaborated herein.

[0205] An example structure of the control sub-circuit is shown in FIG. 9. It is easy for those skilled in the art to understand that the implementation manner of the control sub-circuit is not limited thereto.

[0206] In an example embodiment, the at least one power supply signal end can include a fourth power supply end V4 and a fifth power supply end V5, and the at least one output signal end can include a signal output end OUT; an output sub-circuit is also electrically connected with the second clock signal end CLK2 and is configured to provide the signal of the fourth power supply end V4 or the second clock signal end CLK2 to the signal output end OUT under the control of the signals of the first node N1 and the second node N2.

[0207] In an example embodiment, the signal of the fourth power supply end V4 is a high-level signal, and the signal of the fifth power supply end V5 is a low-level signal.

[0208] In an example embodiment, the fourth power supply end V4 and the first power supply end V1 can be the same signal end, and the fifth power supply end V5 and the second power supply end V2 can be the same signal end.

[0209] FIG. 10 is an equivalent circuit diagram of an output sub-circuit provided by an example embodiment, as shown in FIG. 10, the output sub-circuit can include a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1 and a second capacitor C2.

[0210] In an example embodiment, as shown in FIG. 10, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply terminal V4, and the second electrode of the first transistor T1 is electrically connected with the signal output terminal OUT; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the signal output terminal OUT, and the second electrode of the second transistor T2 is electrically connected with the second clock signal terminal CLK2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply terminal V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the signal output terminal OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the first power supply terminal V1.

[0211] In an example embodiment, as shown in FIG. 10, the first transistor T1, the second transistor T2, and the fourth transistor T4 are P-type transistors.

[0212] An example structure of the output sub-circuit is shown in FIG. 10. It is easy for those skilled in the art to understand that the implementation of the output sub-circuit is not limited to this.

[0213] In an example embodiment, the at least one power supply signal terminal includes the fourth power supply terminal V4, the fifth power supply terminal V5, and the sixth power supply terminal V6, the at least one output signal terminal includes the signal output terminal OUT and the cascade output terminal CR, and the output sub-circuit is further electrically connected with the second clock signal terminal CLK2 and the third clock signal terminal CLK3, and is configured to provide the signal of the sixth power supply terminal V6 or the third clock signal terminal CLK3 to the signal output terminal OUT and provide the signal of the fourth power supply terminal V4 or the second clock signal terminal CLK2 to the cascade output terminal CR under the control of the signals of the first node N1 and the second node N2.

[0214] In an example embodiment, the signal of the fourth power supply terminal V4 is a high-level signal, the signal of the fifth power supply terminal V5 is a low-level signal, and the signal of the sixth power supply terminal V6 is a high-level signal.

[0215] In an example embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0216] Fig. 11 is an equivalent circuit diagram of an output sub-circuit according to an example embodiment. As shown in Fig. 11, the output sub-circuit can include a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1 and a second capacitor C2.

[0217] In an example embodiment, as shown in Fig. 11, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the second clock signal end CLK2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the twelfth transistor T12 is electrically connected with the first node N1, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the eighth node N8, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the third clock signal end CLK3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4.

[0218] In an example embodiment, as shown in Fig. 11, the first transistor T1, the second transistor T2, the fourth transistor T4, the twelfth transistor T12 and the thirteenth transistor T13 are P-type transistors.

[0219] An example structure of the output sub-circuit is shown in Fig. 11. It is easily understood by those skilled in the art that the implementation of the output sub-circuit is not limited to this.

[0220] In an example embodiment, the at least one power signal terminal includes a fourth power terminal V4, a fifth power terminal V5, and a sixth power terminal V6, the at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, and the output sub-circuit is electrically connected to a third clock signal terminal CLK3 and configured to provide the signal of the sixth power terminal V6 or the third clock signal terminal CLK3 to the signal output terminal OUT and provide the signal of the fourth power terminal V4 or the fifth power terminal V5 to the cascade output terminal CR under the control of the signals of the first node N1 and the second node N2.

[0221] In an example embodiment, the signal of the fourth power terminal V4 is a high-level signal, the signal of the fifth power terminal V5 is a low-level signal, and the signal of the sixth power terminal V6 is a high-level signal.

[0222] In an example embodiment, the fourth power terminal V4 and the first power terminal V1 can be the same signal terminal, and the fifth power terminal V5 and the second power terminal V2 can be the same signal terminal.

[0223] FIG. 12 is an equivalent circuit diagram of an output sub-circuit provided by an example embodiment, as shown in FIG. 12, the output sub-circuit can include a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2.

[0224] In an example embodiment, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second electrode of the first transistor T1 is electrically connected to the cascade output terminal CR; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first electrode of the second transistor T2 is electrically connected to the cascade output terminal CR, and the second electrode of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the fourth transistor T4 is electrically connected to the fifth power supply terminal V5, the first electrode of the fourth transistor T4 is electrically connected to the second node N2, and the second electrode of the fourth transistor T4 is electrically connected to the eighth node N8; the control electrode of the twelfth transistor T12 is electrically connected to the first node N1, the first electrode of the twelfth transistor T12 is electrically connected to the sixth power supply terminal V6, and the second electrode of the twelfth transistor T12 is electrically connected to the signal output terminal OUT; the control electrode of the thirteenth transistor T13 is electrically connected to the eighth node N8, the first electrode of the thirteenth transistor T13 is electrically connected to the signal output terminal OUT, and the second electrode of the thirteenth transistor T13 is electrically connected to the third clock signal terminal CLK3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the cascade output terminal CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the fourth power supply terminal V4.

[0225] In an example embodiment, as shown in FIG. 12, the first transistor T1, the second transistor T2, the fourth transistor T4, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0226] An example structure of the output sub-circuit is shown in FIG. 12. It is easy for those skilled in the art to understand that the implementation of the output sub-circuit is not limited thereto.

[0227] FIG. 13 is an equivalent circuit diagram of a shift register provided in an example embodiment. As shown in FIG. 13, the at least one power supply signal terminal includes a fourth power supply terminal V4 and a fifth power supply terminal V5, the at least one output signal terminal includes a signal output terminal OUT, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a third capacitor C3, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1, and a second capacitor C2.

[0228] In an example embodiment, a control electrode of the first transistor T1 is electrically connected to the first node N1, a first electrode of the first transistor T1 is electrically connected to the fourth power supply end V4, and a second electrode of the first transistor T1 is electrically connected to the signal output end OUT; a control electrode of the second transistor T2 is electrically connected to the eighth node N8, a first electrode of the second transistor T2 is electrically connected to the signal output end OUT, and a second electrode of the second transistor T2 is electrically connected to the second clock signal end CLK2; a control electrode of the third transistor T3 is electrically connected to the first clock signal end CLK1, a first electrode of the third transistor T3 is electrically connected to the signal input end IN, and a second electrode of the third transistor T3 is electrically connected to the second node N2; a control electrode of the fourth transistor T4 is electrically connected to the fifth power supply end V5, a first electrode of the fourth transistor T4 is electrically connected to the second node N2, and a second electrode of the fourth transistor T4 is electrically connected to the eighth node N8; a control electrode of the fifth transistor T5 is electrically connected to the third node N3, a first electrode of the fifth transistor T5 is electrically connected to the first clock signal end CLK1 or the second power supply end V2, and a second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; a control electrode of the sixth transistor T6 is electrically connected to the signal input end IN, a first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and a second electrode of the sixth transistor T6 is electrically connected to the first power supply end V1; a control electrode of the seventh transistor T7 is electrically connected to the signal input end IN, a first electrode of the seventh transistor T7 is electrically connected to the third node N3, and a second electrode of the seventh transistor T7 is electrically connected to the first power supply end V1; a control electrode of the eighth transistor T8 is electrically connected to the first clock signal end CLK1, a first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and a second electrode of the eighth transistor T8 is electrically connected to the first node N1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the signal output end OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the fourth power supply end V4; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected to the first clock signal end CLK1, and the second plate C32 of the third capacitor is electrically connected to the third node N3.

[0229] In an example embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are P-type transistors.

[0230] In an example embodiment, a signal of the first power supply end V1 is a high-level signal, and a signal of the second power supply end V2 is a low-level signal.

[0231] In an example embodiment, the signal of the fourth power supply end V4 is a high level signal, and the signal of the fifth power supply end V5 is a low level signal.

[0232] In an example embodiment, the fourth power supply end V4 and the first power supply end V1 can be the same signal end, and the fifth power supply end V5 and the second power supply end V2 can be the same signal end.

[0233] An example structure of the shift register is shown in FIG. 13. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0234] FIG. 14 is a working timing diagram of the shift register provided in FIG. 13. The working process of the first stage shift register exemplified by FIG. 13 is described below. The signal of the signal input end IN is the signal of the initial signal line STV. The working process of the shift register can include:

[0235] In the first stage P1, the signal of the signal input end IN is a low level signal. The seventh transistor T7 and the sixth transistor T6 are turned on respectively. The signal of the first power supply end V1 is written to the third node N3 and charges the third capacitor C3. The signal of the first power supply end V1 is written to the fourth node N4. Since the first power supply end V1 is a high level signal, the signals of the third node N3 and the fourth node N4 are high level signals respectively. The signal of the first clock signal end CLK1 is a high level signal. The eighth transistor T8 is disconnected. Under the action of the second capacitor C2, the first node N1 maintains a low level signal. The first transistor T1 is turned on. The high level signal of the fourth power supply end V4 is written to the signal output end OUT. The signal output end OUT outputs a high level signal.

[0236] In the second stage P2, i.e. the input stage, the signal of the signal input end IN is a low level signal. The sixth transistor T6 and the seventh transistor T7 are turned on. The signals of the third node N3 and the fourth node N4 remain high level signals respectively. The signal of the first clock signal end CLK1 is a low level signal. The eighth transistor T8 is turned on. The high level signal of the fourth node N4 is written to the first node N1. The first node N1 changes from a low level signal to a high level signal. The first transistor T1 is disconnected. The third transistor T3 is turned on. Since the fifth power supply end V5 is a low level signal, the fourth transistor T4 is turned on. The low level signal of the signal input end IN is written to the second node N2 and the eighth node N8 respectively. The eighth node N8 is a low level signal. The second transistor T2 is turned on. The signal of the second clock signal end CLK2 is written to the signal output end OUT. Since the second clock signal end CLK2 is a high level signal, the signal output end OUT outputs a high level signal.

[0237] The third phase P3 is an output phase. The signal of the signal input terminal IN is a low level signal. The sixth transistor T6 and the seventh transistor T7 are turned on. The signals of the third node N3 and the fourth node N4 are kept as high level signals respectively. The signal of the first clock signal terminal CLK1 is a high level signal. The third transistor T3 and the eighth transistor T8 are turned off. The second node N2 and the eighth node N8 are kept as low level signals due to the voltage stabilizing effect of the first capacitor C1 and the second capacitor C2. The first node N1 is kept as a high level signal. The eighth node N8 is a low level signal. The second transistor T2 is turned on. The signal of the second clock signal terminal CLK2 is written into the signal output terminal OUT. The signal output terminal OUT outputs a low level signal due to the low level signal of the second clock signal terminal CLK2.

[0238] The fourth phase P4 is that the signal of the signal input terminal IN is a low level signal. The signal of the second clock signal terminal CLK2 is a high level signal. The signal of the first clock signal terminal CLK1 is a low level signal. The signals of the third node N3 and the fourth node N4 are kept as high level signals respectively. The signal of the eighth node N8 is pulled down by the voltage change of the signal output terminal OUT due to the coupling effect of the first capacitor C1. The voltage of the second node N2 is pulled down by a smaller amplitude than the first node N1 due to the voltage limiting effect of the fourth transistor T4. At this time, the voltage of the signal output terminal OUT changes from a high level signal to a low level signal.

[0239] The fifth phase P5 is that the signal of the signal input terminal IN is a high level signal. The signal of the first clock signal terminal CLK1 is a high level signal. The signals of the third node N3 and the fourth node N4 are kept as high level signals. The signals of the second node N2 and the eighth node N8 are kept as low level signals. The signal output by the signal output terminal OUT is consistent with the signal of the second clock signal terminal CLK2.

[0240] The sixth phase P6 is that the signal of the signal input terminal IN is a high level signal. The signal of the first clock signal terminal CLK1 is a low level signal. The signals of the third node N3 and the fourth node N4 change from high level signals to low level signals. The signals of the second node N2 and the eighth node N8 change from low level signals to high level signals. The second transistor T2 is turned off. The first transistor T1 is turned on. The signal output terminal OUT outputs a high level signal of the fourth power supply terminal V4.

[0241] The working processes of the shift registers in the following embodiments are similar to the above embodiment. The following embodiments will not be described in detail.

[0242] Fig. 15 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment, as shown in Fig. 15, at least one power signal terminal includes: a fourth power terminal V4 and a fifth power terminal V5, at least one output signal terminal includes: a signal output terminal OUT, the control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9, the output sub-circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1 and a second capacitor C2.

[0243] In an example embodiment, as shown in FIG. 15, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected to the signal output end OUT; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first electrode of the second transistor T2 is electrically connected to the signal output end OUT, and the second electrode of the second transistor T2 is electrically connected to the second clock signal end CLK2; the control electrode of the third transistor T3 is electrically connected to the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input end IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected to the second node N2, and the second electrode of the fourth transistor T4 is electrically connected to the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected to the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected to the first clock signal end CLK1 or the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected to the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected to the sixth node N6, and the second electrode of the seventh transistor T7 is electrically connected to the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected to the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1; the control electrode of the ninth transistor T9 is electrically connected to the first clock signal end CLK1, the first electrode of the ninth transistor T9 is electrically connected to the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected to the sixth node N6; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the signal output end OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the fourth power supply end V4.

[0244] In an example embodiment, as shown in FIG. 15, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are P-type transistors.

[0245] In an example embodiment, the signal of the first power supply end V1 is a high-level signal, and the signal of the second power supply end V2 is a low-level signal.

[0246] In an example embodiment, the signal of the fourth power supply terminal V4 is a high level signal, and the signal of the fifth power supply terminal V5 is a low level signal.

[0247] In an example embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0248] An example structure of the shift register is shown in FIG. 15. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0249] FIG. 16 is an equivalent circuit diagram of the shift register provided by an example embodiment. As shown in FIG. 16, the at least one power supply signal terminal includes a fourth power supply terminal V4, a fifth power supply terminal V5, and a sixth power supply terminal V6, the at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a third capacitor C3, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2.

[0250] In an example embodiment, as shown in FIG. 16, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the second clock signal end CLK2 or the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the third node N3, the first electrode of the fifth transistor T5 is electrically connected with the first clock signal end CLK1 or the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the twelfth transistor T12 is electrically connected with the first node N1, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the eighth node N8, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the third clock signal end CLK3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal end CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3.

[0251] In an example embodiment, as shown in FIG. 16, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0252] In an example embodiment, the signal of the first power terminal V1 is a high-level signal, and the signal of the second power terminal V2 is a low-level signal.

[0253] In an example embodiment, the signal of the fourth power terminal V4 is a high-level signal, the signal of the fifth power terminal V5 is a low-level signal, and the signal of the sixth power terminal V6 is a high-level signal.

[0254] In an example embodiment, the fourth power terminal V4 and the first power terminal V1 can be the same signal terminal, and the fifth power terminal V5 and the second power terminal V2 can be the same signal terminal.

[0255] An example structure of the shift register is shown in FIG. 16. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0256] FIG. 17 is an equivalent circuit diagram of the shift register provided in an example embodiment. As shown in FIG. 17, at least one power signal terminal includes a fourth power terminal V4, a fifth power terminal V5, and a sixth power terminal V6, at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, a control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9, and an output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2.

[0257] In an example embodiment, as shown in FIG. 17, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the second clock signal end CLK2 or the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected with the first clock signal end CLK1 or the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T4 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the sixth node N6, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the ninth transistor T9 is electrically connected with the first clock signal end CLK1, the first electrode of the ninth transistor T9 is electrically connected with the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected with the sixth node N6; the control electrode of the twelfth transistor T12 is electrically connected with the first node N1, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the eighth node N8, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the third clock signal end CLK3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4.

[0258] In an example embodiment, as shown in FIG. 17, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12 and the thirteenth transistor T13 are P-type transistors.

[0259] In an example embodiment, the signal of the first power terminal V1 is a high level signal, and the signal of the second power terminal V2 is a low level signal.

[0260] In an example embodiment, the signal of the fourth power terminal V4 is a high level signal, the signal of the fifth power terminal V5 is a low level signal, and the signal of the sixth power terminal V6 is a high level signal.

[0261] In an example embodiment, the fourth power terminal V4 and the first power terminal V1 can be the same signal terminal, and the fifth power terminal V5 and the second power terminal V2 can be the same signal terminal.

[0262] An example structure of the shift register is shown in FIG. 17. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0263] FIG. 18 is an equivalent circuit diagram of the shift register provided in an example embodiment. As shown in FIG. 18, the at least one power signal terminal includes the fourth power terminal V4 and the fifth power terminal V5, the at least one output signal terminal includes the signal output terminal OUT, the control sub-circuit includes the third transistor T3, the fifth transistor T5, the sixth transistor T6 and the eighth transistor T8, and the output sub-circuit includes the first transistor T1, the second transistor T2, the fourth transistor T4, the first capacitor C1 and the second capacitor C2.

[0264] In an example embodiment, as shown in FIG. 18, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply terminal V4, and the second electrode of the first transistor T1 is electrically connected with the signal output terminal OUT; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the signal output terminal OUT, and the second electrode of the second transistor T2 is electrically connected with the second clock signal terminal CLK2; the control electrode of the third transistor T3 is electrically connected with the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply terminal V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the signal input terminal IN, the first electrode of the fifth transistor T5 is electrically connected with the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the signal output terminal OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate of the second capacitor is electrically connected with the first node N1, and the second plate of the second capacitor is electrically connected with the fourth power supply terminal V4.

[0265] In an example embodiment, as shown in FIG. 18, the fifth transistor T5 is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are P-type transistors.

[0266] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal, and the signal of the second power supply terminal V2 is a low-level signal.

[0267] In an example embodiment, the signal of the fourth power supply terminal V4 is a high-level signal, and the signal of the fifth power supply terminal V5 is a low-level signal.

[0268] An example structure of the shift register is shown in FIG. 18. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0269] Figure 19 is an equivalent circuit diagram of a shift register according to an example embodiment. As shown in Figure 19, the at least one power signal terminal includes a fourth power terminal V4 and a fifth power terminal V5, the at least one output signal terminal includes a signal output terminal OUT, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, and an eighth transistor T8, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1, and a second capacitor C2.

[0270] In an example embodiment, as shown in Figure 19, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power terminal V4, and the second electrode of the first transistor T1 is electrically connected to the signal output terminal OUT; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first electrode of the second transistor T2 is electrically connected to the signal output terminal OUT, and the second electrode of the second transistor T2 is electrically connected to the second clock signal terminal CLK2; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the fifth power terminal V5, the first electrode of the fourth transistor T4 is electrically connected to the second node N2, and the second electrode of the fourth transistor T4 is electrically connected to the eighth node N8; the fifth transistor T5 is a double-gate transistor and includes a first control electrode and a second control electrode, the first control electrode of the fifth transistor T5 is electrically connected to the signal input terminal IN, the second control electrode of the fifth transistor T5 is electrically connected to the third power terminal V3, the first electrode of the fifth transistor T5 is electrically connected to the second power terminal V2, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first power terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate of the second capacitor is electrically connected to the first node N1, and the second plate of the second capacitor is electrically connected to the fourth power terminal V4.

[0271] In an example embodiment, as shown in FIG. 18, the fifth transistor T5 is an N-type transistor, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the eighth transistor T8 are P-type transistors.

[0272] In an example embodiment, the signal of the first power supply end V1 is a high-level signal, the signal of the second power supply end V2 is a low-level signal, and the signal of the third power supply end V3 is a low-level signal.

[0273] In an example embodiment, the voltage value of the third power supply end V3 is less than or equal to the voltage value of the second power supply end V2.

[0274] In an example embodiment, the signal of the fourth power supply end V4 is a high-level signal, and the signal of the fifth power supply end V5 is a low-level signal.

[0275] In an example embodiment, the fourth power supply end V4 and the first power supply end V1 can be the same signal end, and the fifth power supply end V5 and the second power supply end V2 can be the same signal end.

[0276] An example structure of the shift register is shown in FIG. 19. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0277] FIG. 20 is an equivalent circuit diagram of the shift register provided by an example embodiment. As shown in FIG. 20, the at least one power supply signal end includes a fourth power supply end V4, a fifth power supply end V5 and a sixth power supply end V6, the at least one output signal end includes a signal output end OUT and a cascade output end CR, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6 and an eighth transistor T8, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1 and a second capacitor C2.

[0278] In an example embodiment, as shown in FIG. 20, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the second clock signal end CLK2 or the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the signal input end IN, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the twelfth transistor T12 is electrically connected with the first node N1, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the eighth node N8, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the third clock signal end CLK3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4.

[0279] In an example embodiment, as shown in FIG. 20, the fifth transistor is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0280] In an example embodiment, the signal of the first power supply terminal V1 is a high level signal, and the signal of the second power supply terminal V2 is a low level signal.

[0281] In an example embodiment, the signal of the fourth power supply terminal V4 is a high level signal, and the signal of the fifth power supply terminal V5 is a low level signal.

[0282] In an example embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0283] An example structure of the shift register is shown in FIG. 20. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0284] FIG. 21 is an equivalent circuit diagram of the shift register provided by an example embodiment. As shown in FIG. 21, the at least one power supply signal terminal includes a fourth power supply terminal V4, a fifth power supply terminal V5, and a sixth power supply terminal V6, the at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, and an eighth transistor T8, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2.

[0285] In an example embodiment, as shown in FIG. 21, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the second clock signal end CLK2 or the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the fifth transistor T5 is a double-gate transistor, the first control electrode of the fifth transistor T5 is electrically connected with the signal input end IN, the second control electrode of the fifth transistor T5 is electrically connected with the third power supply end V3, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the twelfth transistor T12 is electrically connected with the first node N1, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the eighth node N8, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the third clock signal end CLK3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4.

[0286] In an example embodiment, as shown in FIG. 20, the fifth transistor is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0287] In an example embodiment, the signal of the first power terminal V1 is a high level signal, the signal of the second power terminal V2 is a low level signal, and the signal of the third power terminal V3 is a low level signal.

[0288] In an example embodiment, the voltage of the third power terminal V3 is less than or equal to the voltage of the second power terminal V2.

[0289] In an example embodiment, the signal of the fourth power terminal V4 is a high level signal, and the signal of the fifth power terminal V5 is a low level signal.

[0290] In an example embodiment, the fourth power terminal V4 and the first power terminal V1 can be the same signal terminal, and the fifth power terminal V5 and the second power terminal V2 can be the same signal terminal.

[0291] An example structure of the shift register is shown in FIG. 21. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0292] FIG. 22 is an equivalent circuit diagram of the shift register according to an example embodiment. As shown in FIG. 22, the at least one power signal terminal includes a fourth power terminal V4 and a fifth power terminal V5, the at least one output signal terminal includes a signal output terminal OUT, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a third capacitor C3, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1, and a second capacitor C2.

[0293] In an example embodiment, as shown in FIG. 22, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the signal output end OUT; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the signal output end OUT, and the second electrode of the second transistor T2 is electrically connected with the second clock signal end CLK2; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the third node N3, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the first node N1; the control electrode of the sixth transistor T6 is electrically connected with the second node N2, the first electrode of the sixth transistor T6 is electrically connected with the first node N1, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the signal output end OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal end CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3.

[0294] In an example embodiment, as shown in FIG. 22, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are P-type transistors.

[0295] In an example embodiment, the signal of the first power supply end V1 is a high-level signal, and the signal of the second power supply end V2 is a low-level signal.

[0296] In an example embodiment, the signal of the fourth power supply end V4 is a high-level signal, and the signal of the fifth power supply end V5 is a low-level signal.

[0297] In an example embodiment, the fourth power supply end V4 and the first power supply end V1 can be the same signal end, and the fifth power supply end V5 and the second power supply end V2 can be the same signal end.

[0298] An example structure of the shift register is shown in FIG. 22. It is easily understood by those skilled in the art that the implementation of the shift register is not limited to this.

[0299] An equivalent circuit diagram of the shift register provided by an example embodiment is shown in FIG. 23. As shown in FIG. 23, the at least one power supply signal end includes a fourth power supply end V4, a fifth power supply end V5, and a sixth power supply end V6, the at least one output signal end includes a signal output end OUT and a cascade output end CR, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a third capacitor C3, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2.

[0300] In an example embodiment, as shown in FIG. 23, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the second clock signal end CLK2 or the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the third node N3, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the first node N1; the control electrode of the sixth transistor T6 is electrically connected with the second node N2, the first electrode of the sixth transistor T6 is electrically connected with the first node N1, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the control electrode of the twelfth transistor T12 is electrically connected with the first node N1, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the eighth node N8, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the third clock signal end CLK3; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4;

[0301] The third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal end, and the second plate C32 of the third capacitor is electrically connected with the third node.

[0302] In an example embodiment, as shown in FIG. 23, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0303] In an example embodiment, the signal of the first power supply end V1 is a high-level signal, and the signal of the second power supply end V2 is a low-level signal.

[0304] In an example embodiment, the signal of the fourth power supply end V4 is a high-level signal, and the signal of the fifth power supply end V5 is a low-level signal.

[0305] In an example embodiment, the fourth power supply end V4 and the first power supply end V1 can be the same signal end, and the fifth power supply end V5 and the second power supply end V2 can be the same signal end.

[0306] An example structure of the shift register is shown in FIG. 23. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0307] The disclosure embodiments also provide a gate drive circuit, comprising: a plurality of cascaded shift registers, at least one output signal end of at least one stage of shift registers comprising: a signal output end;

[0308] The signal output end of the i-th stage of shift registers is electrically connected to the signal input end of the i+L-th stage of shift registers, 1≤i≤M-L, M is the total number of stages of the shift registers, M≥1, and L is a positive integer greater than or equal to 1.

[0309] The shift register is the shift register provided by any one of the foregoing embodiments, and has similar implementation principles and effects, which will not be described here again.

[0310] The disclosure embodiments also provide a display device, comprising a display area and a non-display area, the display area being provided with pixel drive circuits arranged in an array, and the non-display area being provided with a gate drive circuit, the pixel drive circuit comprising: a write transistor; at least one stage of shift registers in the gate drive circuit is electrically connected to the write transistor of at least one row of pixel drive circuits.

[0311] The gate drive circuit is the gate drive circuit provided by any one of the foregoing embodiments, and has similar implementation principles and effects, which will not be described here again.

[0312] Fig. 24 is a structural circuit diagram of a display device according to an example embodiment. As shown in Fig. 24, the control sub-circuit is electrically connected to the signal input end IN, the first clock signal end CLK1 and the second clock signal end CLK2 respectively. The display device further comprises an initial signal line STV, a first clock signal line CK1 and a second clock signal line CK2. The signal input end IN of the at least one stage of shift register is electrically connected to the initial signal line STV. The first clock signal end CLK1 is electrically connected to one of the first clock signal line CK1 and the second clock signal line CK2. The second clock signal end CLK2 is electrically connected to the other one of the first clock signal line CK1 and the second clock signal line CK2. The first clock signal end CLK1 of the adjacent shift register is connected to different signal lines. The second clock signal end CLK2 of the adjacent shift register is connected to different signal lines.

[0313] Fig. 25 is an output timing diagram of a multi-stage shift register according to an example embodiment. As shown in Fig. 25, the signal input end IN of the first stage of shift register is electrically connected to the initial signal line STV. The signal output end of the i-th stage of shift register is electrically connected to the signal input end of the i+1-th stage of shift register. The first clock signal end CLK1 of the at least one stage of shift register is electrically connected to one of the first clock signal line CK1 and the second clock signal line CK2. The second clock signal end CLK2 is electrically connected to the other one of the first clock signal line CK1 and the second clock signal line CK2. The timing diagram shown in Fig. 25 can be outputted, and the shift of the negative pulse output signal is realized.

[0314] Fig. 26 is a structural circuit diagram of a display device according to an example embodiment. As shown in Fig. 26, the control sub-circuit is electrically connected to the signal input end IN, the first clock signal end CLK1 and the second clock signal end CLK2 respectively. The display device further comprises an initial signal line STV, a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CK3 and a fourth clock signal line CK4. The signal input end IN of the at least one stage of shift register is electrically connected to the initial signal line STV. The first clock signal end CLK1 of the 4M-3-th stage of shift register is electrically connected to the first clock signal line CK1. The second clock signal end CLK2 is electrically connected to the third clock signal line CK3. The first clock signal end CLK1 of the 4M-2-th stage of shift register is electrically connected to the second clock signal line CK2. The second clock signal end is electrically connected to the fourth clock signal line CK4. The first clock signal end CLK1 of the 4M-1-th stage of shift register is electrically connected to the third clock signal line CK3. The second clock signal end is electrically connected to the first clock signal line CK1. The first clock signal end CLK1 of the 4M-th stage of shift register is electrically connected to the fourth clock signal line CK4. The second clock signal end is electrically connected to the second clock signal line CK2. Wherein, M is the total number of stages of shift register, and M≥1.

[0315] Fig. 27 is an output timing diagram of a multi-stage shift register according to an example embodiment. As shown in Fig. 27, the signal input end IN of the first-stage shift register is electrically connected to the initial signal line STV, the signal output end of the i-th stage shift register is electrically connected to the signal input end of the i+2-th stage shift register, the first clock signal end CLK1 of the 4M-3-th stage shift register is electrically connected to the first clock signal line CK1, and the second clock signal end CLK2 is electrically connected to the third clock signal line CK3; the first clock signal end CLK1 of the 4M-2-th stage shift register is electrically connected to the second clock signal line CK2, and the second clock signal end is electrically connected to the fourth clock signal line CK4; the first clock signal end CLK1 of the 4M-1-th stage shift register is electrically connected to the third clock signal line CK3, and the second clock signal end is electrically connected to the first clock signal line CK1; the first clock signal end CLK1 of the 4M-th stage shift register is electrically connected to the fourth clock signal line CK4, and the second clock signal end is electrically connected to the second clock signal line CK2, so as to output the timing diagram shown in Fig. 27 and realize the shift of the negative pulse output signal.

[0316] The disclosure also provides a driving method of a shift register, configured to drive the shift register. The driving method of the shift register can include:

[0317] The control sub-circuit provides a signal to the first node or the second node under the control of the signals at the signal input end and the first clock signal end;

[0318] The output sub-circuit provides a signal to the at least one output signal end under the control of the signals at the first node, the second node and the at least one power signal end.

[0319] The shift register is the shift register provided by any one of the preceding embodiments, and has similar implementation principles and effects, which will not be described here.

[0320] The drawings in the disclosure only relate to the structures involved in the embodiments of the disclosure, and other structures can be referred to the general design.

[0321] For the sake of clarity, the thickness and size of a layer or microstructure are exaggerated in the drawings used to describe embodiments of the disclosure. It can be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intermediate element.

[0322] Although the disclosed embodiments have been fully described above with reference to the attachments, figures, and the accompanying drawings, other embodiments can be utilized and changes can be made without departing from the scope of the disclosure, which is not to be limited by the above-described embodiments. Accordingly, various modifications and changes can be made to the embodiments without departing from the scope of the disclosure as set forth in the claims below. The disclosure is not to be limited to the embodiments set forth herein for the purpose of the practice of the present disclosure.

Claims

A shift register comprising: The control sub-circuit and the output sub-circuit; The control sub-circuit is electrically connected with the signal input end, the first clock signal end, the first node and the second node respectively, and is configured to provide a signal to the first node or the second node under the control of signals of the signal input end and the first clock signal end; The output sub-circuit is electrically connected with the first node, the second node, at least one power signal end and at least one output signal end respectively, and is configured to provide a signal to the at least one output signal end under the control of signals of the first node, the second node and the at least one power signal end. The shift register according to claim 1, wherein The control sub-circuit comprises a first control sub-circuit, and the first control sub-circuit is further electrically connected with the first power end and the second power end; Alternatively, The control sub-circuit comprises a second control sub-circuit, and the second control sub-circuit is further electrically connected with the first power end, the second power end and the third power end. The shift register according to claim 2, wherein The first control sub-circuit comprises a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a third capacitor; The control electrode of the third transistor is electrically connected with the first clock signal end, the first electrode of the third transistor is electrically connected with the signal input end, and the second electrode of the third transistor is electrically connected with the second node; The control electrode of the fifth transistor is electrically connected with the third node, the first electrode of the fifth transistor is electrically connected with the second power end, and the second electrode of the fifth transistor is electrically connected with the fourth node; The control electrode of the sixth transistor is electrically connected with the signal input end, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power end; The control electrode of the seventh transistor is electrically connected with the signal input end, the first electrode of the seventh transistor is electrically connected with the third node, and the second electrode of the seventh transistor is electrically connected with the first power end; The control electrode of the eighth transistor is electrically connected with the first clock signal end, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node; The third capacitor comprises a first plate and a second plate, the first plate of the third capacitor is electrically connected with the first clock signal end, and the second plate of the third capacitor is electrically connected with the third node. The shift register according to claim 2, wherein The first control sub-circuit comprises a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor; The control electrode of the third transistor is electrically connected with the first clock signal end, the first electrode of the third transistor is electrically connected with the signal input end, and the second electrode of the third transistor is electrically connected with the second node; The control electrode of the fifth transistor is electrically connected with the fifth node, the first electrode of the fifth transistor is electrically connected with the second power end, and the second electrode of the fifth transistor is electrically connected with the fourth node; The control electrode of the sixth transistor is electrically connected with the signal input end, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power end; The control electrode of the seventh transistor is electrically connected with the signal input end, the first electrode of the seventh transistor is electrically connected with the sixth node, and the second electrode of the seventh transistor is electrically connected with the first power end; The control electrode of the eighth transistor is electrically connected with the first clock signal end, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node; The control electrode of the ninth transistor is electrically connected with the first clock signal terminal, the first electrode of the ninth transistor is electrically connected with the fifth node, and the second electrode of the ninth transistor is connected with the sixth node. The shift register according to claim 2, wherein The first control sub-circuit comprises a third transistor, a fifth transistor, a sixth transistor, a seventh transistor and a third capacitor. The control electrode of the third transistor is electrically connected with the first clock signal terminal, the first electrode of the third transistor is electrically connected with the signal input terminal, and the second electrode of the third transistor is electrically connected with the second node. The control electrode of the fifth transistor is electrically connected with the third node, the first electrode of the fifth transistor is electrically connected with the second power supply terminal, and the second electrode of the fifth transistor is electrically connected with the first node. The control electrode of the sixth transistor is electrically connected with the second node, the first electrode of the sixth transistor is electrically connected with the first node, and the second electrode of the sixth transistor is electrically connected with the first power supply terminal. The control electrode of the seventh transistor is electrically connected with the signal input terminal, the first electrode of the seventh transistor is electrically connected with the third node, and the second electrode of the seventh transistor is electrically connected with the first power supply terminal. The third capacitor comprises a first plate and a second plate, the first plate of the third capacitor is electrically connected with the first clock signal terminal, and the second plate of the third capacitor is electrically connected with the third node. The shift register according to any one of claims 3 to 5, wherein The fifth transistor is a P-type transistor. The shift register according to claim 2, wherein The first control sub-circuit comprises a third transistor, a fifth transistor, a sixth transistor and an eighth transistor. The control electrode of the third transistor is electrically connected with the first clock signal terminal, the first electrode of the third transistor is electrically connected with the signal input terminal, and the second electrode of the third transistor is electrically connected with the second node. The control electrode of the fifth transistor is electrically connected with the signal input terminal, the first electrode of the fifth transistor is electrically connected with the second power supply terminal, and the second electrode of the fifth transistor is electrically connected with the fourth node. The control electrode of the sixth transistor is electrically connected with the signal input terminal, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power supply terminal. The control electrode of the eighth transistor is electrically connected with the first clock signal terminal, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node. The shift register according to claim 2, wherein The second control sub-circuit comprises a third transistor, a fifth transistor, a sixth transistor and an eighth transistor, the fifth transistor is a double-gate transistor and comprises a first control electrode and a second control electrode. The control electrode of the third transistor is electrically connected with the first clock signal terminal, the first electrode of the third transistor is electrically connected with the signal input terminal, and the second electrode of the third transistor is electrically connected with the second node. The first control electrode of the fifth transistor is electrically connected with the signal input terminal, the second control electrode of the fifth transistor is electrically connected with the third power supply terminal, the first electrode of the fifth transistor is electrically connected with the second power supply terminal, and the second electrode of the fifth transistor is electrically connected with the fourth node. The control electrode of the sixth transistor is electrically connected with the signal input terminal, the first electrode of the sixth transistor is electrically connected with the fourth node, and the second electrode of the sixth transistor is electrically connected with the first power supply terminal. The control electrode of the eighth transistor is electrically connected with the first clock signal terminal, the first electrode of the eighth transistor is electrically connected with the fourth node, and the second electrode of the eighth transistor is electrically connected with the first node. The shift register according to claim 8, wherein The signals of the second power supply end and the third power supply end are low level signals, and the voltage value of the third power supply end is less than or equal to the voltage value of the second power supply end. The shift register according to claim 7 or 8, wherein The fifth transistor is an N-type transistor. The shift register according to claim 1, wherein The control sub-circuit is further electrically connected with the second clock signal end and the first power supply end, and is configured to provide the signal of the first power supply end to the second node under the control of the signals of the first node and the second clock signal end. The control sub-circuit further comprises a tenth transistor and an eleventh transistor. The shift register according to claim 11, wherein The control electrode of the tenth transistor is electrically connected with the first node, the first electrode of the tenth transistor is electrically connected with the first power supply end, and the second electrode of the tenth transistor is electrically connected with the seventh node. The control electrode of the eleventh transistor is electrically connected with the second clock signal end, the first electrode of the eleventh transistor is electrically connected with the seventh node, and the second electrode of the eleventh transistor is electrically connected with the second node. The at least one power supply signal end comprises a fourth power supply end and a fifth power supply end, and the at least one output signal end comprises a signal output end. The shift register according to claim 1, wherein The output sub-circuit is further electrically connected with the second clock signal end, and is configured to provide the signal of the fourth power supply end or the second clock signal end to the signal output end under the control of the signals of the first node and the second node. The output sub-circuit comprises a first transistor, a second transistor, a fourth transistor, a first capacitor and a second capacitor. The shift register according to claim 13, wherein The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fourth power supply end, and the second electrode of the first transistor is electrically connected with the signal output end. The control electrode of the second transistor is electrically connected with the eighth node, the first electrode of the second transistor is electrically connected with the signal output end, and the second electrode of the second transistor is electrically connected with the second clock signal end. The control electrode of the fourth transistor is electrically connected with the fifth power supply end, the first electrode of the fourth transistor is electrically connected with the second node, and the second electrode of the fourth transistor is electrically connected with the eighth node. The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the eighth node, and the second plate of the first capacitor is electrically connected with the signal output end. The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with the fourth power supply end. The at least one power supply signal end comprises a fourth power supply end, a fifth power supply end and a sixth power supply end, and the at least one output signal end comprises a signal output end and a cascade output end. The shift register according to claim 1, wherein The output sub-circuit is further electrically connected with the second clock signal end and the third clock signal end, and is configured to provide the signal of the sixth power supply end or the third clock signal end to the signal output end under the control of the signals of the first node and the second node, and provide the signal of the fourth power supply end or the second clock signal end to the cascade output end. The output sub-circuit comprises a first transistor, a second transistor, a fourth transistor, a twelfth transistor, a thirteenth transistor, a first capacitor and a second capacitor. The shift register of claim 15, wherein, The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fourth power supply end, and the second electrode of the first transistor is electrically connected with the cascade output end. ​ The control electrode of the second transistor is electrically connected with the eighth node, the first electrode of the second transistor is electrically connected with the cascade output end, and the second electrode of the second transistor is electrically connected with the second clock signal end; The control electrode of the fourth transistor is electrically connected with the fifth power supply end, the first electrode of the fourth transistor is electrically connected with the second node, and the second electrode of the fourth transistor is electrically connected with the eighth node; The control electrode of the twelfth transistor is electrically connected with the first node, the first electrode of the twelfth transistor is electrically connected with the sixth power supply end, and the second electrode of the twelfth transistor is electrically connected with the signal output end; The control electrode of the thirteenth transistor is electrically connected with the eighth node, the first electrode of the thirteenth transistor is electrically connected with the signal output end, and the second electrode of the thirteenth transistor is electrically connected with the third clock signal end; The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the eighth node, and the second plate of the first capacitor is electrically connected with the cascade output end; The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with the fourth power supply end. The shift register according to claim 1, wherein The at least one power signal end comprises a fourth power supply end, a fifth power supply end and a sixth power supply end, and the at least one output signal end comprises a signal output end and a cascade output end; The output sub-circuit is further electrically connected with the third clock signal end and is configured to provide the signal of the sixth power supply end or the third clock signal end to the signal output end and provide the signal of the fourth power supply end or the fifth power supply end to the cascade output end under the control of the signals of the first node and the second node. The shift register of claim 17, wherein The output sub-circuit comprises a first transistor, a second transistor, a fourth transistor, a twelfth transistor, a thirteenth transistor, a first capacitor and a second capacitor; The control electrode of the first transistor is electrically connected with the first node, the first electrode of the first transistor is electrically connected with the fourth power supply end, and the second electrode of the first transistor is electrically connected with the cascade output end; The control electrode of the second transistor is electrically connected with the eighth node, the first electrode of the second transistor is electrically connected with the cascade output end, The second electrode of the second transistor is electrically connected with the fifth power supply end; The control electrode of the fourth transistor is electrically connected with the fifth power supply end, the first electrode of the fourth transistor is electrically connected with the second node, and the second electrode of the fourth transistor is electrically connected with the eighth node; The control electrode of the twelfth transistor is electrically connected with the first node, the first electrode of the twelfth transistor is electrically connected with the sixth power supply end, and the second electrode of the twelfth transistor is electrically connected with the signal output end; The control electrode of the thirteenth transistor is electrically connected with the eighth node, the first electrode of the thirteenth transistor is electrically connected with the signal output end, and the second electrode of the thirteenth transistor is electrically connected with the third clock signal end; The first capacitor comprises a first plate and a second plate, the first plate of the first capacitor is electrically connected with the eighth node, and the second plate of the first capacitor is electrically connected with the cascade output end; The second capacitor comprises a first plate and a second plate, the first plate of the second capacitor is electrically connected with the first node, and the second plate of the second capacitor is electrically connected with the fourth power supply end. A gate drive circuit, comprising: The plurality of cascaded shift registers as claimed in any one of claims 1 to 18, and the at least one output signal end of the at least one shift register comprises a signal output end. The signal output end of the i-th stage shift register is electrically connected with the signal input end of the i+L-th stage shift register, 1≤i≤M-L, M is the total stage number of the shift register, M≥1, and L is a positive integer greater than or equal to 1. A display device comprising a display area and a non-display area, the display area being provided with pixel driving circuits arranged in an array, the non-display area being provided with the gate driving circuit as claimed in claim 19, the pixel driving circuit comprising: A write transistor; At least one stage shift register in the gate drive circuit is electrically connected with the write transistor of the pixel drive circuit of at least one row. The display device according to claim 20, wherein The control sub-circuit is electrically connected with the signal input end, the first clock signal end and the second clock signal end respectively, and the display device further comprises an initial signal line, a first clock signal line and a second clock signal line. The signal input end of at least one stage shift register is electrically connected with the initial signal line, the first clock signal end is electrically connected with one of the first clock signal line and the second clock signal line, the second clock signal end is electrically connected with the other of the first clock signal line and the second clock signal line, the signal line connected with the first clock signal end of the adjacent shift register is different, and the signal line connected with the second clock signal end of the adjacent shift register is different. The display device according to claim 21, wherein The control sub-circuit is electrically connected with the signal input end, the first clock signal end and the second clock signal end respectively, and the display device further comprises an initial signal line, a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line. The signal input end of at least one stage shift register is electrically connected with the initial signal line. The first clock signal end of the 4M-3-th stage shift register is electrically connected with the first clock signal line, and the second clock signal end is electrically connected with the third clock signal line. The first clock signal end of the 4M-2-th stage shift register is electrically connected with the second clock signal line, and the second clock signal end is electrically connected with the fourth clock signal line. The first clock signal end of the 4M-1-th stage shift register is electrically connected with the third clock signal line, and the second clock signal end is electrically connected with the first clock signal line. The first clock signal end of the 4M-th stage shift register is electrically connected with the fourth clock signal line, and the second clock signal end is electrically connected with the second clock signal line. M is the total stage number of the shift register, and M≥1. A driving method of a shift register configured to drive the shift register according to any one of claims 1 to 19, the method comprising: The control sub-circuit provides a signal to the first node or the second node under the control of signals at the signal input end and the first clock signal end; The output sub-circuit provides a signal to the at least one output signal end under the control of signals at the first node, the second node and the at least one power signal end.

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