Multi-step micro-nano structure and preparation method thereof

Abstract

The present application relates to the field of micro-nano device processing, and particularly relates to a multi-step micro-nano structure and a preparation method thereof. The method comprises the following steps: forming a mask layer on a substrate surface, the mask layer having a plurality of openings with different sizes for exposing the substrate; and performing single etching on the substrate with the mask layer as a mask to obtain the multi-step micro-nano structure on the substrate. The present application realizes the multi-step by designing openings with different sizes to obtain the multi-step through single etching. The complex process flow of traditional multiple exposures and multiple etchings is compressed into one exposure and one etching, which fundamentally eliminates the problems of cumulative error, long production cycle and high cost caused by multiple process cycles. The strict overlay alignment requirement between multiple photolithographies is avoided, the manufacturing precision and yield are greatly improved, the present application is easy to integrate into the existing semiconductor production line, and the present application paves the way for the large-scale and low-cost manufacturing of multi-step devices.

Description

Technical Field

[0001] This invention relates to the field of micro-nano device fabrication, and in particular to a multi-step micro-nano structure and its fabrication method. Background Technology

[0002] Multi-step micro / nano structures are widely used in microfluidics, biomimetic functional device surfaces, MEMS devices, micro-optical lens arrays, and other fields.

[0003] However, traditional micro / nano fabrication processes often employ the following methods: 1) To determine the number of steps of varying heights (e.g., 3), photomasks of different heights (e.g., 3) are needed for etching multiple times. Grayscale exposure is used to obtain masks of varying thicknesses in different areas. In subsequent etching processes, the masks are consumed, with thinner masks consuming light first and thicker masks consuming light later, thus creating different step heights. These methods have the following problems: 1) Multiple exposures complicate the process flow, such as alignment accuracy; after the steps are formed, there are issues with inconsistent new resist thickness and step coverage; 2) Grayscale exposure presents challenges, such as difficulty in pattern stitching when the area is large; 3) The process time is often long (e.g., multiple exposures and etchings result in a longer process flow; grayscale exposure requires a longer single-stage writing time than a single mask exposure), which is not conducive to mass production.

[0004] Therefore, existing technologies need to be improved. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a multi-step micro / nano structure and its preparation method, aiming to solve the technical problems of complex, inefficient and difficult-to-mass-produce multi-step micro / nano structures.

[0006] The technical solution of the present invention is as follows: In a first aspect, the present invention provides a method for fabricating multi-step micro / nano structures, comprising the following steps: S1. Provide a substrate, and form a mask layer on the surface of the substrate, the mask layer having a plurality of openings of different sizes to expose the substrate; The size of the opening is set according to the target etching depth, so that under the same etching conditions, opening areas of different sizes can obtain different etching depths. S2. Using the mask layer as a shield, the substrate is exposed and etched to obtain the multi-step micro / nano structure on the substrate.

[0007] Optionally, the opening can be a square hole, a round hole, a diamond-shaped hole, or a grating.

[0008] Optionally, the distance between two adjacent openings is 50-500 nm.

[0009] Optionally, the short side length of the opening is 1.61-21.43 μm, and the target etching depth is 20.00-35.00 μm.

[0010] Optionally, the target etching depth increases with the increase of the short side length of the opening.

[0011] Optionally, the relationship between the short side length of the opening and the target etching depth is as follows: D = 0.6164 * W + 22.60, where D is the target etching depth and W is the length of the short side of the opening.

[0012] Optionally, during a single etching in step S2, when the etching depth is 0-30 μm, the etching rate is between 1.4-1.6 μm / min and increases rapidly; when the etching depth is 30-45 μm, the etching rate is between 1.6-0.6 μm / min and decreases rapidly.

[0013] Optionally, during the single etching in step S2, the substrate sidewall next to the mask opening is etched using tilt etching, thereby forming a multi-step micro / nano structure with at least two steps of different depths and a continuous surface on the substrate in one step.

[0014] Secondly, the present invention provides a multi-step micro / nano structure prepared by the method described above.

[0015] Beneficial Effects: This invention provides a multi-step micro / nano structure and its fabrication method. By defining the relationship between the "mask opening size" and the "target etching depth," multi-step structures can be achieved in a single etching operation by designing mask openings of different sizes. This invention compresses the complex traditional process requiring multiple exposures and etchings into a single patterning (exposure) and etching operation, fundamentally eliminating the problems of accumulated errors, long production cycles, and high costs caused by multiple process cycles. Single exposure avoids the strict alignment requirements between multiple lithography operations, significantly improving manufacturing accuracy and yield, and is particularly suitable for substrates with high aspect ratios or existing topologies. The process is identical to conventional single-layer patterning, making it easily integrated into existing semiconductor or MEMS production lines, paving the way for the large-scale, low-cost manufacturing of multi-step devices. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating the fabrication of multi-step micro / nano structures in Example 1.

[0017] Figure 2 This is a schematic diagram of the substrate and mask layer during the fabrication of multi-step micro / nano structures.

[0018] Figure 3This is a schematic diagram of the exposure and etching process during the fabrication of multi-step micro / nano structures.

[0019] Figure 4 This is a schematic diagram of a multi-step micro / nano structure prepared according to one embodiment.

[0020] Figure 5 This is a diagram showing the relationship between the short side dimension of the opening and the etching depth in Example 1.

[0021] Figure 6 This is a graph showing the relationship between etching depth and etching rate in Example 1.

[0022] Figure 7 This is a scanning electron microscope image of the etching depth in Example 1. Detailed Implementation

[0023] This invention provides a multi-step micro / nano structure and a method for fabricating it using a single exposure and single etching process. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention is further described in detail below. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of the invention.

[0024] Traditional micro / nano fabrication methods have the following problems: 1) Multiple exposures lead to complex processes, such as alignment accuracy; uneven thickness of new adhesive coatings after step formation and step coverage issues; 2) In grayscale exposures, large areas present challenges in pattern stitching; 3) Processes are often time-consuming (e.g., multiple exposures and etchings result in a longer process flow; grayscale exposures require longer single-stage writing time than a single mask exposure), which is not conducive to mass production.

[0025] Based on this, this embodiment provides a method for fabricating multi-step micro / nano structures, such as... Figure 1 As shown, it includes the following steps: S1. Provide a substrate 1 (where the substrate can be silicon, quartz, InP, etc.), and form a mask layer 2 on the surface of the substrate (where the material of the mask layer can be photoresist or a hard mask, such as SiO2, SiN, metal, etc.). The mask layer has multiple openings 2-1 of different sizes to expose the substrate. Figure 2 As shown; The size of the opening is set according to the target etching depth, so that under the same etching conditions, opening areas of different sizes can obtain different etching depths. S2. Using the mask layer as a shield, expose and etch the substrate (e.g., ...). Figure 3 As shown), the multi-step micro / nano structure is obtained on the substrate 1, such as... Figure 4 As shown.

[0026] The etching depth is related to the aperture size. Generally, apertures with larger apertures will be etched deeper than those with smaller apertures. The reasons are as follows: a) Plasma has difficulty reaching the bottom and continuing to react with the substrate; b) Reaction products at the bottom of the aperture are difficult to extract and remain there, affecting the presence of lateral etching.

[0027] During the etching process, downward etching is the main etching direction, but lateral etching, which is perpendicular to the main etching direction, will also produce lateral etching. At the end of the etching process, the gap pattern between two adjacent openings is consumed by lateral etching.

[0028] This embodiment defines the causal relationship between the "mask opening size" and the "target etching depth." This is the fundamental difference between this invention and existing technologies (multiple etching or grayscale exposure). Multi-step etching can be achieved in a single etching operation by designing mask patterns of different sizes. This embodiment compresses the complex process flow that traditionally requires multiple exposures and etchings into a single patterning (exposure) and etching operation, fundamentally eliminating the problems of accumulated errors, long production cycles, and high costs caused by multiple process cycles. Single exposure avoids the strict alignment requirements between multiple lithography operations, significantly improving manufacturing accuracy and yield, especially suitable for substrates with high aspect ratios or existing topologies. The process is no different from conventional single-layer patterning, making it easily integrated into existing semiconductor or MEMS production lines, paving the way for the large-scale, low-cost manufacturing of multi-step devices.

[0029] It should be noted that exposure and etching are mature processes. In this embodiment, the substrate includes a base material layer 1-1 (such as a silicon wafer, glass, or quartz) and a photoresist layer 1-2. Exposure transfers the pattern on the mask layer to the photoresist layer, specifically by irradiating the mask layer with a light source of a specific wavelength (such as ultraviolet light, deep ultraviolet light, or an electron beam). The light-transmitting and opaque areas on the mask layer determine which areas of the photoresist are exposed. After exposure, the chemical properties of the photoresist change. Subsequent development treatment dissolves the photoresist in the exposed (or unexposed, depending on the type of photoresist) areas, thus "opening" a window in the photoresist layer, exposing the underlying base material layer and forming a temporary relief pattern corresponding to the mask layer. At this point, the pattern is only on the photoresist. Etching uses the pattern on the photoresist layer as a mask to permanently transfer the pattern to the underlying base material layer, forming micro / nano structures, including but not limited to grooves, holes, or three-dimensional structures. This process includes wet etching and dry etching (such as reactive ion etching). The area protected by the photoresist layer is preserved, while the exposed areas are etched away to a certain depth, thus forming a permanent three-dimensional structure on the substrate material layer. Finally, the residual photoresist is removed (resist removal). Conventionally, one pattern corresponds to one etching depth. As shown in the figure, with N depths, N different patterns need to be designed, and N cycles need to be performed. Using the method of this invention, N depths can be mapped to a small opening of a specific size, allowing the target pattern to be obtained with a single exposure and etching operation.

[0030] In some embodiments, the opening is a square hole, a round hole, a diamond-shaped hole, or a grating.

[0031] In some implementations, the distance between two adjacent openings is 50-500 nm. Preferably, it can be 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 200 nm, 300 nm, 400 nm or 500 nm, depending on the specific situation. If the total etching time is long, it can be wider; if the etching process formula has a large lateral variation, it can be narrower.

[0032] It should be noted that the appropriate distance between adjacent openings ensures that the material is completely consumed by the lateral expansion of the etching process in step S2, resulting in a continuous multi-step structure surface without residual mask gaps. In dry etching, a controllable lateral etching component can be introduced by adjusting process parameters (such as increasing pressure or a specific gas ratio). This lateral etching simultaneously advances from the sidewalls of adjacent openings towards the central region. This solution critically solves the problem of how to form a continuous, smooth stepped surface from a discrete patterned cell array, ensuring the mechanical integrity and functional surface consistency of the final device. It avoids residual small mask pillars or "fence" structures, which could become defect sources or stress concentration points in subsequent processes or device use.

[0033] In some embodiments, when the opening is a square hole, the length of the short side of the opening is 1.61-21.43 μm, such as 1.61 μm, 2.85 μm, 3.92 μm, 5.91 μm, 10.90 μm, 11.33 μm, or 21.43 μm, and the target etching depth is 20.00-35.00 μm.

[0034] Taking silicon etching as an example: the etching equipment is an ICP plasma etching machine, with a process pressure of 30 mt, an SF6 gas flow rate of 90 sccm, an O2 gas flow rate of 40 sccm, a source power of 600 W, a bias power source of 30 W, and an etching time of 10 min. The mask material can be a 3-4 μm thick photoresist. The substrate material is silicon. In this embodiment, etching may stop prematurely when the short side is less than the lower limit; when it is greater than the upper limit, the depth approaches saturation, and the sensitivity of size control decreases. This invention provides a verified and reliable parameter range, reducing the uncertainty and trial-and-error costs in process development.

[0035] In one embodiment, the target etching depth increases with the increase of the short side length of the opening.

[0036] In one specific embodiment, the relationship between the short side length of the opening and the target etching depth is as follows: D = 0.6164 * W + 22.60, where D is the target etching depth and W is the length of the short side of the opening.

[0037] In one embodiment, during a single etching step S2, when the etching depth is 0-30 μm, the etching rate is between 1.4-1.6 μm / min and increases rapidly; when the etching depth is 30-45 μm, the etching rate is between 1.6-0.6 μm / min and decreases rapidly.

[0038] In this embodiment, when etching to the bottom of the pattern, the aspect ratio of the etched hole affects: 1. Plasma has difficulty reaching the bottom and continuing to react with the substrate; 2. The reaction products at the bottom of the hole are difficult to be extracted and remain at the bottom, affecting the etching.

[0039] In one embodiment, during the single etching in step S2, the substrate sidewall next to the mask opening is etched using tilt etching, thereby forming a multi-step micro / nano structure with at least two steps of different depths and a continuous surface on the substrate in one step.

[0040] It should be noted that the "tilted etching" described in this embodiment actually refers to controllable lateral etching achieved through process control. In dry etching, by increasing the non-vertical component of physical bombardment or enhancing the isotropic nature of chemical reactions, etching can be performed not only in the vertical direction but also in the horizontal direction, thereby forming a multi-step micro / nano structure with at least two steps of different depths and a continuous surface on the substrate in one step.

[0041] Secondly, the present invention provides a multi-step micro / nano structure prepared by the method described above.

[0042] The present invention will be further described below through specific embodiments.

[0043] Example 1 A method for fabricating multi-step micro / nano structures includes the following steps: S1. Provide a substrate (silicon), and form a mask layer (photoresist with a thickness of 8 μm) on the surface of the substrate. The mask layer has multiple openings of different sizes that expose the substrate (the size information of the openings is as follows). Figure 5 (as shown) The size of the opening is set according to the target etching depth, so that under the same etching conditions, opening areas of different sizes can obtain different etching depths. S2. Using the mask layer as a shield, the substrate is subjected to a single exposure and etching to obtain the multi-step micro / nano structure on the substrate.

[0044] The opening described in this embodiment is a square hole.

[0045] In this embodiment, the distance between two adjacent openings is approximately 400 nm. This embodiment can completely etch an interval of approximately 400 nm between two adjacent openings; if the interval is too large, it cannot be completely etched.

[0046] like Figure 5 As shown, the short side lengths of the openings in this embodiment are 1.61μm, 2.85μm, 3.92μm, 5.91μm, 10.90μm, 11.33μm, and 21.43μm, respectively, and the target etching depths are 21.65μm, 23.04μm, 25.62μm, 27.45μm, 30.88μm, 31.26μm, and 34.00μm, respectively.

[0047] The relationship between the shorter side length of the opening and the target etching depth is as follows: D = 0.6164 * W + 22.60, where D is the target etching depth and W is the length of the short side of the opening.

[0048] like Figure 6As shown, during a single etching step S2, when the etching depth is 0-30 μm, the etching rate increases linearly between 1.4-1.6 μm / min; when the etching depth is 30-45 μm, the etching rate decreases linearly between 1.6-0.6 μm / min. The results are as follows... Figure 7 As shown, from Figure 7 As can be seen, the method of this invention can obtain multi-step micro / nano structures with a single exposure and a single etching.

[0049] In summary, this invention provides a multi-step micro / nano structure and its fabrication method using a single exposure and single etching. By defining the causal relationship between the "mask opening size" and the "target etching depth," this invention allows for the creation of multi-step structures through a single etching process by designing mask patterns of different sizes. This invention compresses the complex traditional process requiring multiple exposures and etchings into a single patterning (exposure) and etching step, fundamentally eliminating the problems of accumulated errors, long production cycles, and high costs associated with multiple process cycles. Single exposure avoids the stringent alignment requirements between multiple lithography steps, significantly improving manufacturing accuracy and yield, and is particularly suitable for substrates with high aspect ratios or existing topologies. The process is identical to conventional single-layer patterning, making it easily integrated into existing semiconductor or MEMS production lines, paving the way for the large-scale, low-cost manufacturing of multi-step devices.

[0050] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method for fabricating multi-step micro / nano structures, characterized in that, Includes the following steps: S1. Provide a substrate and form a mask layer on the surface of the substrate, the mask layer having a plurality of openings of different sizes for exposing the substrate; The size of the opening is set according to the target etching depth, so that under the same etching conditions, opening areas of different sizes can obtain different etching depths. S2. Using the mask layer as a shield, the substrate is exposed and etched to obtain the multi-step micro / nano structure on the substrate.

2. The method for fabricating a multi-step micro / nano structure according to claim 1, characterized in that, The opening can be a square hole, a round hole, a diamond-shaped hole, or a grating.

3. The method for fabricating a multi-step micro / nano structure according to claim 1, characterized in that, The distance between two adjacent openings is 50-500 nm.

4. The method for fabricating a multi-step micro / nano structure according to claim 1, characterized in that, The short side length of the opening is 1.61-21.43 μm, and the target etching depth is 20.00-35.00 μm.

5. The method for fabricating a multi-step micro / nano structure according to claim 4, characterized in that, The target etching depth increases with the increase of the short side length of the opening.

6. The method for fabricating a multi-step micro / nano structure according to claim 5, characterized in that, The relationship between the shorter side length of the opening and the target etching depth is as follows: D = 0.6164 * W + 22.60, where D is the target etching depth and W is the length of the short side of the opening.

7. The method for fabricating a multi-step micro / nano structure according to claim 1, characterized in that, During a single etching operation in step S2, when the etching depth is 0-30 μm, the etching rate is between 1.4-1.6 μm / min and increases rapidly; when the etching depth is 30-45 μm, the etching rate is between 1.6-0.6 μm / min and decreases rapidly.

8. The method for fabricating a multi-step micro / nano structure according to claim 1, characterized in that, In step S2, during a single etching operation, tilted etching is used to etch the substrate sidewall next to the mask opening, thereby forming a multi-step micro / nano structure with at least two steps of different depths and a continuous surface on the substrate in one operation.

9. A multi-step micro / nano structure, characterized in that, Prepared by the method described in any one of claims 1-8.

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