A test method for zero-voltage gate voltage off of a planar SiC MOSFET

Abstract

The application discloses a kind of plane SiC MOSFET zero-volt gate voltage off test methods, method includes: S1, plane SiC MOSFET device is assembled to test circuit;S2, in test circuit, the drive opening and closing voltage of active tube Q1, resistance Rgon1, resistance Rgoff1 Adjustable;For the drive opening and closing voltage of active tube Q1, the adjustment range of opening voltage signal is set as +12V to +20V, and the off voltage signal is 0V;S3, the test process of zero-volt gate voltage off of to-be-tested tube Q2 is carried out using test circuit.The zero-volt gate voltage off critical resistance value of plane SiC MOSFET is obtained by the way of zero-volt gate voltage off test.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a test method for zero-volt gate voltage turn-off of a planar SiC MOSFET. Background Technology

[0002] In existing wafer fabrication processes, the design of planar SiC MOSFETs faces a significant physical and technological contradiction: the strong coupling and constraint between the threshold voltage Vth and the specific on-resistance Rsp. To provide extremely low on-resistance (RDS(on)) in a competitive market, semiconductor manufacturers often need to enhance channel conductivity by optimizing channel doping concentration and gate oxide thickness. In planar structures, this optimization path inevitably leads to a reduction in the device threshold voltage. Currently, the mainstream planar 1200V SiC MOSFETs on the market typically have nominal threshold voltages in the lower range of 2.0V to 3.0V (some specific models even as low as 1.8V). This extremely fast switching speed (i.e., extremely high voltage change rate dv / dt and current change rate di / dt) combined with a relatively low inherent threshold voltage, in bridge commutation topologies represented by half-bridge or full-bridge, introduces highly destructive parasitic conduction risks and severe drive control challenges.

[0003] To suppress the Miller crosstalk and parasitic conduction risks caused by high-frequency switching transients, the industry and major semiconductor manufacturers have long adopted a standardized technical solution: employing an asymmetric bipolar negative gate voltage turn-off drive strategy. While the traditional negative gate voltage turn-off scheme is technically mature, it still has many limitations in practical applications. 1. High complexity of the drive circuit: Negative gate voltage turn-off requires an additional negative power supply module, increasing the size, weight, and cost of the drive circuit. In high-density integrated power electronic systems, the presence of the negative power supply occupies valuable installation space, preventing further increases in the power density of power electronic devices; simultaneously, a negative gate voltage generation circuit requires an additional transformer, leading to increased device costs, such as... Figure 1 As shown; 2. Gate oxide layer reliability risk: There is a high interface state density between the gate oxide layer and the SiC substrate of SiC MOSFETs. A negative gate voltage will generate a large electric field strength in the gate oxide layer. Under long-term operation under negative gate voltage conditions, the interface states are prone to trapping charge, leading to threshold voltage drift, and in severe cases, even gate oxide layer breakdown, shortening the device lifespan. 3. Increased body diode voltage drop: Bridge circuits require a dead time for simultaneous turn-off of both upper and lower transistors to prevent bridge arm shoot-through. During the dead time, the body diode is needed for freewheeling to achieve soft turn-on or soft turn-off. The forward voltage drop of the body diode is significantly greater under negative gate voltage turn-off and under high-voltage zero gate voltage turn-off, leading to increased freewheeling losses during the dead time and reduced system efficiency. Figure 2 As shown. Summary of the Invention

[0004] Technical Objective: To address the numerous drawbacks of existing technologies, such as high BOM costs, difficult PCB layout, and serious reliability risks due to negative bias temperature instability (NBTI), this invention provides a test method for zero-volt gate turn-off of planar SiC MOSFETs. The zero-volt gate turn-off critical resistance value of the planar SiC MOSFET is obtained by testing the zero-volt gate turn-off method.

[0005] Technical solution: To achieve the above technical objectives, the present invention adopts the following technical solution.

[0006] A test method for zero-volt gate turn-off of a planar SiC MOSFET, comprising the following steps: S1. Assemble the planar SiC MOSFET device into the test circuit; S2. In the test circuit, the drive turn-on and turn-off voltages of the active transistor Q1, resistor Rgon1, and resistor Rgoff1 are adjustable. For the drive turn-on and turn-off voltages of the active transistor Q1, the adjustment range of the turn-on voltage signal is set to +12V to +20V, and the turn-off voltage signal is 0V. S3. The process of using a test circuit to perform a zero-volt gate voltage turn-off test on the transistor Q2 under test.

[0007] Beneficial effects: 1. This invention establishes a scientific and systematic evaluation method. By testing the zero-gate voltage turn-off method, the critical resistance value of the planar SiC MOSFET is obtained, which accurately determines the feasibility of the planar SiC MOSFET to achieve reliable turn-off at zero gate voltage, and provides a theoretical basis for simplifying the design of the drive circuit.

[0008] 2. Promote the application of zero-volt gate voltage turn-off technology in practical engineering, simplify the drive circuit architecture, reduce system cost and energy consumption, and improve the reliability and integration of power electronic systems.

[0009] 3. The present invention also includes an aging test circuit to verify the zero gate voltage turn-off critical resistance value of the test tube Q2 under test. Attached Figure Description

[0010] Figure 1A schematic diagram of the negative voltage circuit that can be omitted in the existing technology using 0V shutdown; Figure 2 This is a schematic diagram comparing the voltage drop of 0V and negative voltage turn-off diodes in the prior art; Figure 3 This is a schematic diagram of the 0V shutdown double-pulse test and evaluation circuit in this invention; Figure 4 This is a schematic diagram of the driving circuit principle; Figure 5 A flowchart for the testing and evaluation process; Figure 6 This is a schematic diagram of the aging process of the 0V shutdown synchronous Boost circuit of the present invention. Figure 7 This is a schematic diagram of the test results of device A under operating condition 1; Figure 8 This is a schematic diagram of the test results of device A under operating condition 2. Detailed Implementation

[0011] The present invention will be further explained and described below with reference to the accompanying drawings and embodiments.

[0012] The embodiments are for illustrative purposes only and do not constitute a limitation on the scope of the claims. Other alternative means that can be conceived by those skilled in the art are all within the scope of the claims of this invention.

[0013] Furthermore, in the description of this invention, it should be noted that the terms "central," "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0014] Example: As attached Figure 3 To be continued Figure 8 As shown in this embodiment, a test method for zero-volt gate voltage turn-off of a planar SiC MOSFET includes the following steps: S1. Assemble the planar SiC MOSFET device into the test circuit; the planar SiC MOSFET device is a packaged device with Kelvin source pins, such as TOLL, QDPAK or TO247-4, etc.

[0015] As attached Figure 3As shown, the test circuit includes a DC power supply VDC, a first turn-off voltage source, a second turn-off voltage source, an inductor L, an active transistor Q1, a transistor under test Q2, resistors Rgon1, Rgoff1, and Rgoff2. The active transistor Q1 and the transistor under test Q2 are planar SiC MOSFETs of the same type. The drive turn-on and turn-off voltages of the active transistor Q1 are adjustable, that is, the turn-on adjustment range of the first turn-off voltage source is +12V to +20V, and the turn-off voltage adjustment range is -5V to 0V. The second turn-off voltage source is a DC power supply with a voltage range of -5V to 1V. In other words, the operating mode of the transistor under test Q2 is the off state, and the turn-off voltage range is adjustable from -5V to +1V. The turn-off resistor Rgoff2 is also adjustable.

[0016] The positive terminal of the DC power supply VDC is connected to the drain of the active transistor Q1. Resistors Rgon1 and Rgoff1 are connected in parallel, with one end connected to the gate of the active transistor Q1 and the other end connected to the source of the active transistor Q1 and the drain of the transistor under test Q2 through the first turn-off voltage source. One end of resistor Rgoff2 is connected to the gate of the transistor under test Q2 and the other end connected to the source of the transistor under test Q2 through the second turn-off voltage source. The source of the transistor under test Q2 is connected to the drain of the transistor under test Q2 and the source of the active transistor Q1 through the inductor L. The source of the transistor under test Q2 is connected to the negative terminal of the DC power supply.

[0017] As attached Figure 4 As shown, the circuit structure of the first turn-off voltage source includes a driver chip; the driver chip model is UCC5350 or NSi6601; the Vdd2 pin of the driver chip is connected to the turn-on voltage signal; the GND2 pin of the driver chip is connected to the turn-off voltage signal; the IN+ pin of the driver chip is connected to a double pulse signal; the OUTH pin of the driver chip is connected to one end of resistor Rgon; the OUTL pin of the driver chip is connected to one end of resistor Rgoff; the other ends of resistors Rgon and Rgoff are connected to the gate of the active transistor Q1; resistors Rgon and Rgoff correspond to the test circuit, i.e. Figure 3 The resistors are Rgon1 and Rgoff1.

[0018] S2. In the test circuit, the drive turn-on and turn-off voltage of the active transistor Q1, resistor Rgon1, and resistor Rgoff1 are adjustable. Specifically, for the drive turn-on and turn-off voltages of the active transistor Q1, i.e., the first turn-off voltage source, the adjustment range of the turn-on voltage signal is set to +12V to +20V, and the turn-off voltage signal is 0V; resistor Rgon1 is the turn-on resistor of the active transistor Q1, and resistor Rgoff1 is the turn-off resistor of the active transistor Q1. Both the turn-on resistor Rgon1 and the turn-off resistor Rgoff1 can be adjusted separately to freely and flexibly adjust the switching speed; the test circuit may also include a device heating device to adjust the case temperature of the device under test by heating the resistor.

[0019] S3. The test circuit is used to perform a zero-volt gate voltage turn-off test on the transistor Q2 under test, obtaining the zero-gate voltage turn-off critical resistance value of Q2; as shown in the attached diagram. Figure 5 As shown, it includes the following steps: S31. Set the working mode of the tube under test Q2 to the off state and set the off voltage signal, that is, the voltage signal output by the second off voltage source is 0V, and the resistor Rgoff2 is used as the off resistor and is adjustable. S32. Obtain the first operating voltage and current conditions that need to be tested for the transistor Q2 under test. The first operating voltage and current conditions include bus voltage test, turn-off current test, drain-source voltage change rate dv / dt test and operating temperature test, and obtain the candidate zero gate voltage turn-off critical resistance value. As attached Figure 5 As shown, the test process for the first operating voltage and current condition in S32 includes: S321. By adjusting the drive turn-on and turn-off voltage of the active transistor Q1, resistor Rgon1, and resistor Rgoff1, the drain-source voltage change rate dv / dt under the first working voltage and current condition is tested. S322. Set the turn-off resistor Rgoff2 of the transistor Q2 under test to 0Ω and the turn-off voltage to 0V; apply a dual-pulse drive signal to the active transistor Q1, and adjust the turn-off current of the first pulse and the turn-on current of the second pulse to the first working voltage and current condition by adjusting the width of pulse 1, and perform a turn-off current test; test the reverse recovery current waveform and the gate-source voltage waveform of the transistor Q2 under test; wherein, the switching frequency of the drive signal is selected between 50-100kHz, and the upper and lower bridge drive signals are complementary switches.

[0020] S323. Integrate the measured reverse recovery current waveform over time to obtain the reverse recovery charge Qrr*. S324. Repeatedly increase the turn-off resistance Rgoff2 of the transistor Q2 under test, obtain the reverse recovery current and the corresponding reverse recovery charge Qrr after increasing Rgoff2; compare the current reverse recovery charge with the previous reverse recovery charge, and stop when the current reverse recovery charge is greater than 1.2 times the previous reverse recovery charge. At this time, the turn-off resistance Rgoff2 corresponding to the first working voltage and current condition is used as the candidate zero gate voltage turn-off critical resistance value.

[0021] S325. Complete the bus voltage test and operating temperature test processes under the first operating voltage and current conditions; S33. Obtain other operating voltage and current conditions that need to be tested for the transistor Q2 under test, and perform the tests according to the process in S32 to obtain the corresponding candidate zero gate voltage turn-off critical resistance values. Select the minimum value from all candidate zero gate voltage turn-off critical resistance values ​​as the final zero gate voltage turn-off critical resistance value.

[0022] Different operating voltage and current conditions refer to different bus voltage, shutdown current, and operating temperature.

[0023] This invention can select the minimum value of Rgoff2 based on the critical value under different operating voltage and current conditions, thereby satisfying the reliable turn-off of planar SiC MOSFETs at zero volt gate voltage under different operating conditions.

[0024] As attached Figure 7 and attached Figure 8 As shown, different zero-gate voltage turn-off critical resistance values ​​obtained by testing the same transistor under different operating voltage and current conditions are presented.

[0025] This invention also includes an aging test circuit, as shown in the attached diagram. Figure 6 As shown, the aging test circuit in this invention is a continuous power test circuit based on boost topology to verify whether the device's characteristics change after long-term operation. The test circuit includes a DC power supply, a load resistor Rload, a first turn-off voltage source, a second turn-off voltage source, an inductor L, an active transistor Q1, a transistor under test Q2, resistors Rgon1, Rgon2, Rgoff1, Rgoff2, and a voltage source; the active transistor Q1 and the transistor under test Q2 are planar SiC MOSFETs of the same type; A load resistor Rload is connected to both ends of a DC power supply. The two ends of the load resistor are connected to the drain of the active transistor Q1 and the source of the transistor under test Q2, respectively. Resistors Rgon1 and Rgoff1 are connected in parallel, with one end connected to the gate of the active transistor Q1 and the other end connected to the source of the active transistor Q1 and the drain of the transistor under test Q2 through a first turn-off voltage source. Resistors Rgon2 and Rgoff2 are connected in parallel, with one end connected to the gate of the transistor under test Q2 and the other end connected to the source of the transistor under test Q2 through a second turn-off voltage source. The drain of the transistor under test Q2 is connected to the positive terminal of the voltage source through an inductor L, and the negative terminal of the voltage source is connected to the source of the transistor under test Q2. Resistor Rgoff2 is set as the zero-gate voltage turn-off threshold resistance value for the transistor under test Q2.

[0026] Among them, the turn-on and turn-off voltages of Q1 and Q2 are adjustable, that is, the turn-on adjustment range of the first turn-off voltage source and the second turn-off voltage source is +12V to +20V, and the turn-off voltage is 0V; the aging test method is as follows: 1. Select appropriate operating voltage, operating current, and drain-source voltage change rate according to different SiC MOSFET models, i.e., the transistor under test Q2; 2. Before aging, test the threshold voltage, on-resistance, gate-source leakage current, and drain-source leakage current parameters of the transistor Q2 under test; 3. Choose different heat dissipation methods according to the power rating, such as natural heat dissipation by attaching a heat sink, air cooling, water cooling, etc. 4. The switching frequency of the drive signal is selected between 50-100kHz, and the upper and lower bridge drive signals are switched complementaryly. 5. Test the gate-source (GS) waveform and drain-source voltage waveform of the upper and lower transistors, namely the active transistor Q1 and the transistor under test Q2; 6. Perform continuous power aging with zero-volt gate voltage turn-off for several hours in this manner; 7. After aging, remove the active transistor Q1 and the transistor under test Q2, and test their threshold voltage, on-resistance, gate-source leakage current, and drain-source leakage current parameters respectively. The parameter drift before and after aging should be less than 10%, then the aging test is considered passed.

[0027] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A test method for zero-volt gate turn-off of a planar SiC MOSFET, characterized in that, The method includes the following steps: S1. Assemble the planar SiC MOSFET device into the test circuit; S2. In the test circuit, the drive turn-on and turn-off voltages of the active transistor Q1, resistor Rgon1, and resistor Rgoff1 are adjustable. For the drive turn-on and turn-off voltages of the active transistor Q1, the adjustment range of the turn-on voltage signal is set to +12V to +20V, and the turn-off voltage signal is 0V. S3. Use the test circuit to perform a zero-volt gate voltage turn-off test on the transistor Q2 under test, and obtain the zero-gate voltage turn-off critical resistance value of the transistor Q2 under test.

2. The test method for zero-volt gate turn-off of a planar SiC MOSFET according to claim 1, characterized in that: Planar SiC MOSFET devices are devices with Kelvin source pins in their package.

3. The test method for zero-volt gate voltage turn-off of a planar SiC MOSFET according to claim 1, characterized in that: The test circuit includes a DC power supply VDC, a first turn-off voltage source, a second turn-off voltage source, an inductor L, an active transistor Q1, a transistor under test Q2, resistors Rgon1, Rgoff1, and Rgoff2; the active transistor Q1 and the transistor under test Q2 are planar SiC MOSFETs of the same type. The positive terminal of the DC power supply VDC is connected to the drain of the active transistor Q1. Resistors Rgon1 and Rgoff1 are connected in parallel, with one end connected to the gate of the active transistor Q1 and the other end connected to the source of the active transistor Q1 and the drain of the transistor Q2 under test through the first turn-off voltage source. One end of resistor Rgoff2 is connected to the gate of the transistor Q2 under test, and the other end is connected to the source of the transistor Q2 under test through the second turn-off voltage source. The source of the transistor Q2 under test is connected to the drain of the transistor Q2 under test through the inductor L. The source of the transistor Q2 under test is connected to the negative terminal of the DC power supply.

4. The test method for zero-volt gate voltage turn-off of a planar SiC MOSFET according to claim 3, characterized in that: The circuit structure of the first turn-off voltage source includes a driver chip; the Vdd2 pin of the driver chip is connected to the turn-on voltage signal; the GND2 pin of the driver chip is connected to the turn-off voltage signal; the IN+ pin of the driver chip is connected to a dual-pulse signal; the OUTH pin of the driver chip is connected to one end of the resistor Rgon; the OUTL pin of the driver chip is connected to one end of the resistor Rgoff; and the other ends of the resistors Rgon and Rgoff are connected to the gate of the transistor Q2 under test.

5. The test method for zero-volt gate voltage turn-off of a planar SiC MOSFET according to claim 4, characterized in that: The driver chip model is either UCC5350 or NSi6601.

6. The test method for zero-volt gate turn-off of a planar SiC MOSFET according to claim 1, characterized in that: The testing process includes the following steps: S31. Set the working mode of the tube under test Q2 to the off state and set the off voltage signal to 0V. S32. Obtain the first operating voltage and current conditions that need to be tested for the transistor Q2 under test. The first operating voltage and current conditions include bus voltage test, turn-off current test, drain-source voltage change rate dv / dt test and operating temperature test, and obtain the candidate zero gate voltage turn-off critical resistance value. S33. Obtain other operating voltage and current conditions that need to be tested for the transistor Q2 under test, and perform the tests according to the process in S32 to obtain the corresponding candidate zero gate voltage turn-off critical resistance values. Select the minimum value from all candidate zero gate voltage turn-off critical resistance values ​​as the final zero gate voltage turn-off critical resistance value.

7. The test method for zero-volt gate turn-off of a planar SiC MOSFET according to claim 6, characterized in that: The test procedure for the first operating voltage and current condition in S32 includes: S321. By adjusting the drive turn-on and turn-off voltage of the active transistor Q1, resistor Rgon1, and resistor Rgoff1, the drain-source voltage change rate dv / dt under the first working voltage and current condition is tested. S322. Set the turn-off resistor Rgoff2 of the transistor Q2 under test to 0Ω and the turn-off voltage to 0V; apply a double-pulse drive signal to the active transistor Q1, and adjust the turn-off current of the first pulse and the turn-on current of the second pulse to the first working voltage and current condition by adjusting the width of pulse 1, and perform a turn-off current test; test the reverse recovery current waveform and the gate-source voltage waveform of the transistor Q2 under test. S323. Integrate the measured reverse recovery current waveform over time to obtain the reverse recovery charge; S324. Repeatedly increase the turn-off resistance Rgoff2 of the transistor Q2 under test, obtain the reverse recovery current and the corresponding reverse recovery charge after increasing Rgoff2; compare the current reverse recovery charge with the previous reverse recovery charge, and stop when the current reverse recovery charge is greater than 1.2 times the previous reverse recovery charge. At this time, the turn-off resistance Rgoff2 corresponding to the first working voltage and current condition is used as the candidate zero gate voltage turn-off critical resistance value. S325. Complete the bus voltage test and operating temperature test processes under the first operating voltage and current conditions.

8. The test method for zero-volt gate voltage turn-off of a planar SiC MOSFET according to claim 1, characterized in that: After the test is completed, the results are verified by an aging test circuit, which includes a DC power supply, a load resistor Rload, a first turn-off voltage source, a second turn-off voltage source, an inductor L, an active transistor Q1, a transistor under test Q2, resistors Rgon1, Rgon2, Rgoff1, Rgoff2, and voltage sources; the active transistor Q1 and the transistor under test Q2 are planar SiC MOSFETs of the same model; the turn-on and turn-off voltages of the active transistor Q1 and the transistor under test Q2 are adjustable, that is, the turn-on adjustment range of the first turn-off voltage source and the second turn-off voltage source is +12V to +20V, and the turn-off voltage is 0V; A load resistor Rload is connected to both ends of a DC power supply. The two ends of the load resistor are connected to the drain of the active transistor Q1 and the source of the transistor under test Q2, respectively. Resistors Rgon1 and Rgoff1 are connected in parallel, with one end connected to the gate of the active transistor Q1 and the other end connected to the source of the active transistor Q1 and the drain of the transistor under test Q2 through a first turn-off voltage source. Resistors Rgon2 and Rgoff2 are connected in parallel, with one end connected to the gate of the transistor under test Q2 and the other end connected to the source of the transistor under test Q2 through a second turn-off voltage source. The drain of the transistor under test Q2 is connected to the positive terminal of the voltage source through an inductor L, and the negative terminal of the voltage source is connected to the source of the transistor under test Q2. Among them, resistor Rgoff2 is set as the zero gate voltage turn-off critical resistance value of the transistor under test Q2.

9. The test method for zero-volt gate voltage turn-off of a planar SiC MOSFET according to claim 8, characterized in that: Aging test methods include: (1) Select appropriate operating voltage, operating current and drain-source voltage change rate according to different models of the test tube Q2; (2) Test the threshold voltage, on-resistance, gate-source leakage current, and drain-source leakage current parameters of the test tube Q2 before aging; (3) Select different heat dissipation methods according to the power level; (4) The switching frequency of the drive signal is selected between 50-100kHz, and the upper and lower bridge drive signals are switched complementaryly. (5) Test the GS waveform and drain-source voltage waveform of the upper and lower transistors, namely the active transistor Q1 and the transistor under test Q2; (6) Perform zero-volt gate voltage turn-off continuous power aging for several hours in this manner; (7) After aging, remove the active transistor Q1 and the transistor under test Q2, and test their threshold voltage, on-resistance, gate-source leakage current and drain-source leakage current parameters respectively. If the parameter drift before and after aging is less than 10%, the aging test is deemed to have passed.

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