A memory out-of-bounds detection method, device, medium and program product

Abstract

This invention relates to the field of chip technology and discloses a method, device, medium, and program product for memory out-of-bounds detection. The method includes: obtaining the operator semantics and input parameters corresponding to a target operator, and generating initial address attribute entries based on the operator semantics and input parameters; obtaining the computing core corresponding to the target operator, and storing each initial address attribute entry in a fine-grained memory protection unit corresponding to the computing core; and performing memory out-of-bounds detection on memory access requests of the computing core based on each initial address attribute entry to obtain the detection result. By pre-deriving the address attribute entries corresponding to the target operator based on the operator semantics and input parameters, adding a fine-grained memory protection unit for storing the address attribute entries, and implementing real-time memory out-of-bounds detection of memory access requests based on the address attribute entries, efficient and accurate memory out-of-bounds detection under a memory pool mechanism can be achieved, ensuring memory data security.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a method, device, medium, and program product for detecting memory out-of-bounds access. Background Technology

[0002] In the underlying implementation of deep learning and artificial intelligence frameworks, operator execution is typically routed to kernel functions on heterogeneous computing hardware. During operator development and execution, memory out-of-bounds detection is a necessary process to ensure the normal execution of operators.

[0003] Currently, existing memory out-of-bounds detection methods typically rely on system-level or driver-level memory allocation boundary verification. However, to avoid frequent system calls and memory fragmentation, AI frameworks generally employ memory pooling mechanisms. This involves requesting a large block of memory from the hardware all at once and then internally partitioning and allocating it. This memory pooling mechanism can lead to situations where an operator experiences a memory out-of-bounds error, potentially crossing only its logical allocation boundary but still falling within the physical memory block allocated by the memory pool. Existing detection methods are ineffective in handling this type of memory out-of-bounds scenario, resulting in missed detections and compromising memory data security. Summary of the Invention

[0004] This invention provides a memory out-of-bounds detection method, device, medium, and program product, which can achieve efficient and accurate memory out-of-bounds detection under the memory pool mechanism and ensure memory data security.

[0005] According to one aspect of the present invention, a memory out-of-bounds detection method is provided, comprising: Obtain the operator semantics and input parameters corresponding to the target operator, and generate each initial address attribute entry corresponding to the target operator based on the operator semantics and the input parameters; Obtain the computing core corresponding to the target operator, and store each initial address attribute entry into the fine-grained memory protection unit corresponding to the computing core; Based on the initial address attribute entries in the fine-grained memory protection unit, memory access requests from the computing core are checked for out-of-bounds access in order to obtain the detection results.

[0006] According to another aspect of the present invention, a memory out-of-bounds detection device is provided, comprising: The entry generation module is used to obtain the operator semantics and input parameters corresponding to the target operator, and generate each initial address attribute entry corresponding to the target operator based on the operator semantics and the input parameters. An entry storage module is used to obtain the computing core corresponding to the target operator and store each initial address attribute entry into the fine-grained memory protection unit corresponding to the computing core. The out-of-bounds detection module is used to perform memory out-of-bounds detection on the memory access requests of the computing core based on the initial address attribute entries in the fine-grained memory protection unit, so as to obtain the detection results.

[0007] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the memory out-of-bounds detection method according to any embodiment of the present invention.

[0008] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing a computer program configured to cause a processor to execute and implement the memory out-of-bounds detection method according to any embodiment of the present invention.

[0009] According to another aspect of the present invention, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the memory out-of-bounds detection method described in any embodiment of the present invention.

[0010] The technical solution of this invention involves obtaining the operator semantics and input parameters corresponding to the target operator, and generating initial address attribute entries corresponding to the target operator based on the operator semantics and input parameters; obtaining the computing core corresponding to the target operator, and storing each initial address attribute entry in a fine-grained memory protection unit corresponding to the computing core; performing memory out-of-bounds detection on memory access requests of the computing core based on each initial address attribute entry in the fine-grained memory protection unit to obtain the detection result; by pre-deriving the address attribute entries corresponding to the target operator based on the operator semantics and input parameters, adding a fine-grained memory protection unit for storing address attribute entries, and implementing real-time memory out-of-bounds detection of memory access requests based on address attribute entries, efficient and accurate memory out-of-bounds detection under the memory pool mechanism can be achieved, ensuring memory data security.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a flowchart of a memory out-of-bounds detection method provided in Embodiment 1 of the present invention; Figure 2 This is a flowchart of a memory out-of-bounds detection method provided in Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of a memory out-of-bounds detection device according to Embodiment 3 of the present invention; Figure 4 This is a schematic diagram of the structure of an electronic device that implements the memory out-of-bounds detection method of this invention. Detailed Implementation

[0014] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0015] It should be noted that the terms "first," "second," "target," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0016] Example 1 Figure 1This is a flowchart of a memory out-of-bounds detection method provided in Embodiment 1 of the present invention. This embodiment is applicable to the case of fine-grained memory access out-of-bounds detection for operator execution in an artificial intelligence framework. This method can be executed by a memory out-of-bounds detection device, which can be implemented in hardware and / or software. Typically, this memory out-of-bounds detection device can be configured in electronic devices, such as computer equipment, servers, etc. Figure 1 As shown, the method includes: S110. Obtain the operator semantics and input parameters corresponding to the target operator, and generate each initial address attribute entry corresponding to the target operator based on the operator semantics and the input parameters.

[0017] In this embodiment, the memory out-of-bounds detection method can be applied to a memory out-of-bounds detection system composed of a host and a chip, which can be installed in an electronic device. The host can be a main control chip with deployed operator software, primarily used for configuring and distributing operator tasks. The chip can be an artificial intelligence chip for executing computational tasks, and may include multiple computing cores.

[0018] The target operator can be the operator that needs to be called and executed during the software compilation or runtime phase. Specifically, firstly, the host extracts the corresponding operator semantics and input parameters from the target operator's configuration information. Operator semantics refers to a precise description of the operator's functional definition, behavioral rules, and logical constraints, including information such as computational purpose, input / output specifications, computational logic, and data read / write requirements. Input parameters refer to the parameter information required for operator execution. Taking a two-dimensional convolution operator as an example, input parameters may include input tensors, weight tensors, tensor shapes, data types, and starting memory addresses. Then, operator execution simulation can be performed based on the operator semantics and input parameters to derive the starting memory address, memory size, and read / write permission requirements corresponding to each memory block. The starting memory address, memory size, and read / write permission requirements are then combined to obtain the initial address attribute entries.

[0019] Optionally, after generating the initial address attribute entries, the host can add each initial address attribute entry to the task descriptor of the target operator and send it along with the binary instructions of the target operator to the hardware task scheduler on the chip.

[0020] Optionally, generating initial address attribute entries corresponding to the target operator based on the operator semantics and the input parameters may include: Based on the operator semantics, the initial read / write permission requirements corresponding to each initial memory block are obtained, and based on the input parameters, the initial memory address range corresponding to each initial memory block is obtained; Based on the initial read / write permission requirements and the initial memory address range, generate the initial address attribute entries corresponding to each initial memory block.

[0021] Each initial memory block represents a memory space required during the execution of the target operator. For example, when the target operator is a two-dimensional convolution operator, the initial memory block may include an input tensor memory block, a weight tensor memory block, an output tensor memory block, and a temporary workspace memory block, etc.

[0022] In this embodiment, a unique initial address attribute entry can be generated for each initial memory block. Specifically, firstly, the operator semantics are parsed to obtain the current operation semantic type corresponding to each initial memory block. Based on the preset correspondence between operation semantic types and read / write permissions, and the current operation semantic type, the initial read / write permission requirements for each initial memory block are obtained. Next, the starting memory address and memory size corresponding to each initial memory block can be extracted from the input parameters. Combining the starting memory address and memory size, the initial memory address range corresponding to each initial memory block is determined. The memory address range can correspond to the byte level. Finally, the initial read / write permission requirements and the initial memory address range can be combined to obtain the initial address attribute entry corresponding to each initial memory block.

[0023] The process of obtaining the initial memory address range corresponding to each initial memory block based on the input parameters may include: Based on the input parameters, the starting memory address, tensor shape, and data type of each initial memory block are obtained, and the memory size of each initial memory block is calculated based on the tensor shape and the data type. Based on the starting memory address and the memory size, obtain the initial memory address range corresponding to each initial memory block.

[0024] Specifically, when calculating the initial memory address range, firstly, the starting memory address, tensor shape, and data type corresponding to each initial memory block are extracted from the input parameters. Data types can include integer and floating-point types, etc. Next, based on the tensor shape, the number of elements is calculated. Then, based on the current data type and the preset correspondence between data types and byte counts, the number of bytes corresponding to each element is obtained. The number of elements is then multiplied by the number of bytes to obtain the memory size. Finally, the starting memory address is added to the memory size to obtain the sum, which serves as the cutoff memory address. The starting and cutoff memory addresses are used as address boundaries to obtain the initial memory address range.

[0025] In a specific example, the target operator is a two-dimensional convolution operator. The input parameters include: an input tensor with shape [N,C,H,W], data type float16 (2 bytes per element), and starting memory address Addr_In; a weight tensor with shape [K,C,R,S], data type float16, and starting memory address Addr_Wt; an output tensor with shape [N,K,P,Q], data type float16, and starting memory address Addr_Out; and a workspace, a temporary workspace required by the algorithm, with a memory size of Workspace_Size bytes and starting memory address Addr_Ws.

[0026] The initial address attribute entries generated based on the above input parameters can be: Entry 1 (Input Feature Map): Base (Starting Memory Address) = Addr_In, Size (Memory Size) = N C H W 2 bytes, Permission (read / write permission requirement) = Read-Only (RO, read-only); Item 2 (convolution kernel weights): Base = Addr_Wt, Size = K C R S 2 bytes, Permission = Read-Only (RO); Entry 3 (Output Feature Map): Base = Addr_Out, Size = N K P Q 2 bytes, Permission=Write-Only (WO, write only) (or configured as RW according to the cumulative semantics); Entry 4 (temporary workspace): Base=Addr_Ws, Size=Workspace_Size bytes, Permission=Read-Write (RW, read and write).

[0027] S120. Obtain the computing core corresponding to the target operator, and store each initial address attribute entry into the fine-grained memory protection unit corresponding to the computing core.

[0028] Specifically, the hardware task scheduler on the chip can allocate corresponding computing cores to the target operator based on load balancing methods, extract the initial address attribute entries corresponding to the target operator from the task descriptor, and then load the extracted initial address attribute entries into the fine-grained memory protection unit corresponding to the computing core. Alternatively, if the hardware task scheduler does not support parsing extended fields, a special boot code can be inserted into the header of the kernel function instruction sequence of the target operator. This boot code is used to proactively configure the address attribute entries into the fine-grained memory protection unit corresponding to the computing core through specific system-level instructions (such as writing special register instructions) before the operator core logic is executed.

[0029] The fine-grained memory protection unit can be deployed inside the computing core or bypassed by the cache controller, corresponding one-to-one with the computing core. In this embodiment, a fine-grained memory protection unit can be added in the Load / StoreUnit (LSU) inside the computing core, or bypassed by the Level 1 / Level 2 cache controller. When the fine-grained memory protection unit is directly integrated into the LSU, verification can be completed during the instruction issue phase, resulting in minimal latency. When the fine-grained memory protection unit is integrated by bypassing the cache controller, all memory access requests, whether missed or hit, can be centrally filtered. Optionally, a "fine-grained check channel" can be added as a fine-grained memory protection unit, bypassing the traditional page table-based memory management unit. When the page table cache is hit, an additional byte-level verification based on the range register is added to achieve memory out-of-bounds detection.

[0030] Fine-grained memory protection units can include a set of dedicated range registers for storing address attribute entries. For example, each entry can contain three dimensions of metadata: starting memory address, memory size, and read / write permission requirements. Read / write permission requirements include read-only, write-only, and read-write. It's important to note that the registers in the fine-grained memory protection unit are strongly bound to the hardware execution context to ensure that boundary checks between different concurrently executing operators or threads on the chip do not interfere with each other.

[0031] S130. Based on the initial address attribute entries in the fine-grained memory protection unit, perform memory out-of-bounds detection on the memory access requests of the computing core to obtain the detection results.

[0032] Specifically, during the execution of the target operator by the computing core, internal threads can initiate memory access requests to the memory system as needed. At this time, the computing core first retrieves the initial address attribute entry matching the current memory access request from the fine-grained memory protection unit. Then, based on the starting memory address and memory size in the initial address attribute entry, it performs an address validity check on the memory access request, that is, it determines whether the memory address corresponding to the memory access request is within the memory address range formed by the starting memory address and the memory size. If the check passes, the memory out-of-bounds detection result is determined to be a pass; otherwise, if the check fails, the detection result is determined to be a fail.

[0033] The technical solution of this invention involves obtaining the operator semantics and input parameters corresponding to the target operator, and generating initial address attribute entries corresponding to the target operator based on the operator semantics and input parameters; obtaining the computing core corresponding to the target operator, and storing each initial address attribute entry in a fine-grained memory protection unit corresponding to the computing core; performing memory out-of-bounds detection on memory access requests of the computing core based on each initial address attribute entry in the fine-grained memory protection unit to obtain the detection result; by pre-deriving the address attribute entries corresponding to the target operator based on the operator semantics and input parameters, adding a fine-grained memory protection unit for storing address attribute entries, and implementing real-time memory out-of-bounds detection of memory access requests based on address attribute entries, efficient and accurate memory out-of-bounds detection under the memory pool mechanism can be achieved, ensuring memory data security.

[0034] Example 2 Figure 2 This is a flowchart of a memory out-of-bounds detection method provided in Embodiment 2 of the present invention. This embodiment is a further refinement of the above technical solution, and the technical solution in this embodiment can be combined with one or more of the above implementation methods. Figure 2 As shown, the method includes: S210. Obtain the operator semantics and input parameters corresponding to the target operator, and generate each initial address attribute entry corresponding to the target operator based on the operator semantics and the input parameters.

[0035] S220. Obtain the computing core corresponding to the target operator, and store each initial address attribute entry into the fine-grained memory protection unit corresponding to the computing core.

[0036] S230. When a memory access request for a target memory block is detected by the computing core, the memory access address, access operation type, and target address attribute entries corresponding to the memory access request are obtained.

[0037] Specifically, during the execution of the target operator, if the current thread needs to read or write to the target memory block, it can generate a memory access request and send it to the memory system. The memory system can parse the memory access request to obtain the corresponding memory address and access operation type. Simultaneously, it can determine the target address attribute entry corresponding to the target memory block based on the correspondence between memory blocks and address attribute entries. The access memory address is the memory address that needs to be read or written. The access operation type is the type of read / write operation that needs to be performed.

[0038] S240. Read the target address attribute entry from the fine-grained memory protection unit, and perform memory out-of-bounds detection on the memory access request based on the access memory address, the access operation type and the target address attribute entry, so as to obtain the detection result.

[0039] Next, the range register of the fine-grained memory protection unit reads the target address attribute entry and extracts the target memory address range and target read / write permission requirements from it. Finally, based on the target memory address range and target read / write permission requirements, address validity and permission checks are performed on the accessed memory address and access operation type, respectively. If both checks pass, the detection result is considered passed; otherwise, if either check fails, the detection result is considered failed. Memory access requests that pass the checks can be directly allowed, while memory access requests that fail the checks can trigger hardware anomalies, such as precise interception or error reporting.

[0040] It should be noted that this embodiment does not impose a specific limitation on the execution order of permission verification and address validity verification. Address validity verification can be performed first, or permission verification can be performed first.

[0041] The process of performing memory out-of-bounds detection on the memory access request based on the accessed memory address, the access operation type, and the target address attribute entry to obtain the detection result may include: Based on the target address attribute entries, obtain the target read / write permission requirements and the target memory address range; If the access operation type is detected to be successfully matched with the target read / write permission requirement, it is determined whether the accessed memory address is within the range of the target memory address. If so, the detection result is determined to be a successful detection.

[0042] In this embodiment, when performing memory out-of-bounds detection, firstly, it is determined whether the access operation type matches the target read / write permission requirement. If so, for example, if the access operation type is read and the target read / write permission requirement is read-only, then the two can be determined to be successfully matched. Further, it is determined whether the accessed memory address is within the target memory address range. If so, the detection result is finally determined to be successful. For example, if the accessed memory address is Request_Address, the starting memory address is Base_Address, and the memory size is Size, then a pure byte-level arithmetic comparison can be used, i.e., by determining whether Base_Address <= Request_Address < (Base_Address + Size) is true, to determine whether the accessed memory address is within the target memory address range.

[0043] Optionally, after obtaining the target read / write permission requirements and the target memory address range based on the target address attribute entries, the process may further include: If the access operation type fails to match the target read / write permission requirement, and / or the accessed memory address is not within the target memory address range, the detection result is determined to be a failure, and memory out-of-bounds description information is generated and stored in the target buffer.

[0044] In another scenario, if either the permission check or the address validity check fails, the detection result is determined to be a failure. In this case, detailed information about the out-of-bounds violation can be collected and integrated, including the out-of-bounds address, violation type, program counter value that triggered the violation, thread identifier, etc., to generate a memory out-of-bounds description, which is then stored in the target buffer.

[0045] Taking the aforementioned two-dimensional convolution operator as an example, if a defect in the index calculation within the target operator causes a thread to attempt to write data to the memory region where Addr_In resides, the fine-grained memory protection unit will immediately intercept the request due to "permission violation (writing to the RO region)". Similarly, if a thread requests to read Addr_In+(N... C H W 2) The fine-grained memory protection unit will precisely intercept the request for the memory address "address out of bounds (out of the Size range)" even if the out-of-bounds address is still in a large block of memory in the framework's memory pool.

[0046] In this embodiment, after determining that the detection result is a failure, exception handling can be triggered based on a preset exception handling mechanism. This mechanism includes a hard interrupt mode and a soft interrupt / debugging mode. In hard interrupt mode (interception mode), once an out-of-bounds memory access is detected, the memory access request is discarded, an interrupt signal is sent to the host, and the execution of the operator on the current computing core is terminated, suitable for strict protection in production environments. In soft interrupt / debugging mode (recording mode), detecting an out-of-bounds memory access does not terminate operator execution; instead, detailed information about the out-of-bounds access is recorded in a dedicated debug circular buffer on the chip. For out-of-bounds write requests, the chip can choose to silently discard them to prevent damage to other data while allowing the operator to continue running. This mode greatly facilitates post-event troubleshooting and performance profiling for operator developers.

[0047] The beneficial effects of the technical solution of this invention can include: (1) breaking the memory pool blind zone, completely solving the failure problem of traditional memory management unit page-level checks and allocator boundary checks under the memory pool mechanism of artificial intelligence framework, and realizing 100% accurate interception of logical out-of-bounds; (2) byte-level precise protection, by introducing fine-grained memory protection units and range registers, getting rid of the coarse-grained limitation of traditional memory management units based on 4 kilobytes / 2 megabytes physical pages, and realizing byte-level fine-grained checks that perfectly match the actual size of the tensor; (3) zero software performance overhead, by packaging configuration information into task descriptors and automatically loading it by the hardware scheduler, eliminating the overhead of configuring registers in software startup code, and ensuring extremely high calling efficiency of artificial intelligence operators; (4) high concurrency security, based on the register design of computing unit context binding, perfectly supporting the scenario of high concurrency and multi-task mixed deployment of modern artificial intelligence chips, and realizing mutual non-interference.

[0048] The technical solution of this invention, when a memory access request for a target memory block is detected by the computing core, obtains the memory access address, access operation type, and target address attribute entry corresponding to the memory access request; reads the target address attribute entry from the fine-grained memory protection unit, and performs memory out-of-bounds detection on the memory access request based on the memory access address, access operation type, and target address attribute entry to obtain the detection result; by implementing memory out-of-bounds detection based on the memory access address, access operation type, and target address attribute entry, the accuracy of memory out-of-bounds detection can be improved.

[0049] Example 3 Figure 3 This is a schematic diagram of a memory out-of-bounds detection device provided in Embodiment 3 of the present invention. Figure 3 As shown, the device includes: an entry generation module 310, an entry storage module 320, and an out-of-bounds detection module 330; wherein, The entry generation module 310 is used to obtain the operator semantics and input parameters corresponding to the target operator, and generate each initial address attribute entry corresponding to the target operator according to the operator semantics and the input parameters. Entry storage module 320 is used to obtain the computing core corresponding to the target operator and store each initial address attribute entry into the fine-grained memory protection unit corresponding to the computing core; The out-of-bounds detection module 330 is used to perform memory out-of-bounds detection on the memory access requests of the computing core based on the initial address attribute entries in the fine-grained memory protection unit, so as to obtain the detection results.

[0050] The technical solution of this invention involves obtaining the operator semantics and input parameters corresponding to the target operator, and generating initial address attribute entries corresponding to the target operator based on the operator semantics and input parameters; obtaining the computing core corresponding to the target operator, and storing each initial address attribute entry in a fine-grained memory protection unit corresponding to the computing core; performing memory out-of-bounds detection on memory access requests of the computing core based on each initial address attribute entry in the fine-grained memory protection unit to obtain the detection result; by pre-deriving the address attribute entries corresponding to the target operator based on the operator semantics and input parameters, adding a fine-grained memory protection unit for storing address attribute entries, and implementing real-time memory out-of-bounds detection of memory access requests based on address attribute entries, efficient and accurate memory out-of-bounds detection under the memory pool mechanism can be achieved, ensuring memory data security.

[0051] Optionally, the entry generation module 310 includes: The address range acquisition unit is used to acquire the initial read / write permission requirements corresponding to each initial memory block according to the operator semantics, and to acquire the initial memory address range corresponding to each initial memory block according to the input parameters. The entry generation unit is used to generate the initial address attribute entry corresponding to each initial memory block according to the initial read / write permission requirements and the initial memory address range.

[0052] Optionally, the address range acquisition unit is specifically used to acquire the starting memory address, tensor shape and data type corresponding to each initial memory block according to the input parameters, and to calculate the memory size corresponding to each initial memory block according to the tensor shape and the data type; Based on the starting memory address and the memory size, obtain the initial memory address range corresponding to each initial memory block.

[0053] Optionally, the boundary detection module 330 includes: The request detection unit is used to obtain the memory access address, access operation type and target address attribute entries corresponding to the memory access request when a memory access request for a target memory block is detected by the computing core. The out-of-bounds detection unit is used to read the target address attribute entry from the fine-grained memory protection unit, and perform memory out-of-bounds detection on the memory access request based on the access memory address, the access operation type and the target address attribute entry, so as to obtain the detection result.

[0054] Optionally, the out-of-bounds detection unit is specifically used to obtain the target read / write permission requirements and the target memory address range based on the target address attribute entries; If the access operation type is detected to be successfully matched with the target read / write permission requirement, it is determined whether the accessed memory address is within the range of the target memory address. If so, the detection result is determined to be a successful detection.

[0055] Optionally, the out-of-bounds detection unit is further configured to determine the detection result as a failure if it detects that the access operation type fails to match the target read / write permission requirement, and / or the accessed memory address is not within the range of the target memory address, and generate memory out-of-bounds description information and store it in the target buffer.

[0056] Optionally, fine-grained memory protection units can be deployed inside the compute core or bypassed by the cache controller.

[0057] The memory out-of-bounds detection device provided in this embodiment of the invention can execute the memory out-of-bounds detection method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the method.

[0058] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0059] Example 4 Figure 4 A schematic diagram of an electronic device 40 that can be used to implement embodiments of the present invention is shown. The electronic device 40 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0060] like Figure 4As shown, the electronic device 40 includes at least one processor 41 and a memory, such as a read-only memory (ROM) 42 or a random access memory (RAM) 43, communicatively connected to the at least one processor 41. The memory stores computer programs executable by the at least one processor. The processor 41 can perform various appropriate actions and processes based on the computer program stored in the read-only memory 42 or loaded from the storage unit 48 into the random access memory 43. The RAM 43 can also store various programs and data required for the operation of the electronic device 40. The processor 41, ROM 42, and RAM 43 are interconnected via a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.

[0061] Multiple components in electronic device 40 are connected to I / O interface 45, including: input unit 46, such as keyboard, mouse, etc.; output unit 47, such as various types of monitors, speakers, etc.; storage unit 48, such as disk, optical disk, etc.; and communication unit 49, such as network card, modem, wireless transceiver, etc. Communication unit 49 allows electronic device 40 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0062] Processor 41 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 41 include, but are not limited to, central processing units, graphics processing units, various special-purpose artificial intelligence computing chips, various processors running machine learning model algorithms, digital signal processors, and any suitable processor, controller, microcontroller, etc. Processor 41 performs the various methods and processes described above, such as memory out-of-bounds detection methods.

[0063] In some embodiments, the memory out-of-bounds detection method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 48. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 40 via ROM 42 and / or communication unit 49. When the computer program is loaded into RAM 43 and executed by processor 41, one or more steps of the memory out-of-bounds detection method described above may be performed. Alternatively, in other embodiments, processor 41 may be configured to perform the memory out-of-bounds detection method by any other suitable means (e.g., by means of firmware).

[0064] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays, application-specific integrated circuits (ASICs), application-specific standard products (ASICs), system-on-a-chip (SoCs), complex programmable logic devices, computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0065] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0066] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory, read-only memory, erasable programmable read-only memory, optical fibers, portable compact disk read-only memory, optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0067] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device 40, which includes: a display device (e.g., a cathode ray tube or liquid crystal display) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device 40. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0068] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0069] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact via a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server.

[0070] This embodiment may also include a computer program product, which includes a computer program that, when executed by a processor, implements the memory out-of-bounds detection method provided in any embodiment of the present invention.

[0071] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0072] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for detecting memory out-of-bounds access, characterized in that, include: Obtain the operator semantics and input parameters corresponding to the target operator, and generate each initial address attribute entry corresponding to the target operator based on the operator semantics and the input parameters; Obtain the computing core corresponding to the target operator, and store each initial address attribute entry into the fine-grained memory protection unit corresponding to the computing core; Based on the initial address attribute entries in the fine-grained memory protection unit, memory access requests from the computing core are checked for out-of-bounds access in order to obtain the detection results.

2. The method according to claim 1, characterized in that, Based on the operator semantics and the input parameters, generate initial address attribute entries corresponding to the target operator, including: Based on the operator semantics, the initial read / write permission requirements corresponding to each initial memory block are obtained, and based on the input parameters, the initial memory address range corresponding to each initial memory block is obtained; Based on the initial read / write permission requirements and the initial memory address range, generate the initial address attribute entries corresponding to each initial memory block.

3. The method according to claim 2, characterized in that, Based on the input parameters, obtain the initial memory address range corresponding to each initial memory block, including: Based on the input parameters, the starting memory address, tensor shape, and data type of each initial memory block are obtained, and the memory size of each initial memory block is calculated based on the tensor shape and the data type. Based on the starting memory address and the memory size, obtain the initial memory address range corresponding to each initial memory block.

4. The method according to claim 1, characterized in that, Based on the initial address attribute entries in the fine-grained memory protection unit, memory access requests from the computing core are subjected to memory out-of-bounds detection to obtain detection results, including: When a memory access request for a target memory block is detected by the computing core, the memory access address, access operation type, and target address attribute entries corresponding to the memory access request are obtained. The target address attribute entry is read from the fine-grained memory protection unit, and memory out-of-bounds detection is performed on the memory access request based on the access memory address, the access operation type, and the target address attribute entry to obtain the detection result.

5. The method according to claim 4, characterized in that, Based on the accessed memory address, the access operation type, and the target address attribute entry, a memory out-of-bounds detection is performed on the memory access request to obtain the detection result, including: Based on the target address attribute entries, obtain the target read / write permission requirements and the target memory address range; If the access operation type is detected to be successfully matched with the target read / write permission requirement, it is determined whether the accessed memory address is within the range of the target memory address. If so, the detection result is determined to be a successful detection.

6. The method according to claim 5, characterized in that, After obtaining the target read / write permission requirements and the target memory address range based on the target address attribute entries, the process also includes: If the access operation type fails to match the target read / write permission requirement, and / or the accessed memory address is not within the target memory address range, the detection result is determined to be a failure, and memory out-of-bounds description information is generated and stored in the target buffer.

7. The method according to any one of claims 1-6, characterized in that, Fine-grained memory protection units are deployed inside the computing core or bypassed by the cache controller.

8. An electronic device, characterized in that, The electronic device includes: At least one processor, and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the memory out-of-bounds detection method according to any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that enables a processor to implement the memory out-of-bounds detection method according to any one of claims 1-7 when executed.

10. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the memory out-of-bounds detection method according to any one of claims 1-7.

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