Single bus debugging circuit and chip

Abstract

The application discloses a single bus debugging circuit and a chip, and belongs to the technical field of communication. The single bus debugging circuit comprises a single bus interface, a signal conversion module, and a debugging transmission module. The single bus interface is used for establishing a single line connection with an external debugger. The signal conversion module is configured to convert a first single line signal received by the single bus interface into a first JTAG signal in a RISC-V standard. The debugging transmission module is connected with the signal conversion module and is configured to perform a debugging operation on a to-be-debugged module in a RISC-V chip based on the converted first JTAG signal in the RISC-V standard. A single line connection is established between the single bus debugging circuit and the external debugger, and the debugging function of the RISC-V chip can be completed through one pin, the function of the pin is maximized, and the debugging cost of the circuit limited by the pin is reduced.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a single-bus debugging circuit and chip. Background Technology

[0002] In the field of communication technology, modules within electronic devices often require debugging. A host computer-based debugging module is used to locate and repair problems, thereby improving performance stability. These modules may be, for example, processors or memory. The process of using a host computer-based debugging module involves the host computer sending signals to a debugging circuit, which then uses these signals to debug the modules within the electronic device.

[0003] However, the debugging circuitry within electronic devices cannot communicate directly with the host computer. A debugger is typically used to connect the debugging circuitry and the host computer, facilitating signal transmission between them. For example, after receiving a signal from the host computer, the debugger sends a signal back to the debugging circuitry. Summary of the Invention

[0004] This application provides a single-bus debugging circuit and chip for receiving signals sent by a debugger, and for debugging modules requiring debugging based on the received signals. The technical solution is as follows: In a first aspect, embodiments of this application provide a single-bus debug circuit based on a RISC-V architecture, comprising: A single-bus interface is used to establish a single-wire connection with an external debugger; The signal conversion module is configured to convert the first single-wire signal received by the single-bus interface into the first Joint Test Action Group (JTAG) signal of the RISC-V standard. The debug transmission module is connected to the signal conversion module and is configured to perform debug operations on the module to be debugged inside the RISC-V chip based on the first JTAG signal of the converted RISC-V standard.

[0005] In one possible implementation, the debug transmission module is further configured to send a second JTAG signal output from inside the RISC-V chip to the signal conversion module, the second JTAG signal being used to describe the debugging result of the module to be debugged; The signal conversion module is configured to convert the second JTAG signal into a second single-wire signal and send it to the external debugger through the single-bus interface.

[0006] In one possible implementation, the first single-wire signal includes multiple clock levels, at least two of which correspond to a data bit in the first JTAG signal.

[0007] In one possible implementation, the multiple clock levels included in the first single-wire signal are divided into multiple level groups, each level group including at least two clock levels, and different level groups include the same number of clock levels. There is a mapping relationship between the level value distribution of the level group and the data bits in the first JTAG signal.

[0008] In one possible implementation, the level group includes eight clock levels; When the distribution of the eight clock levels is two first levels and six second levels, there is a mapping relationship between the distribution of the level values ​​and the data bits that take the first value; Alternatively, if the distribution of the eight clock levels is six first levels and two second levels, there is a mapping relationship between the distribution of the level values ​​and the data bits that take the second value.

[0009] In one possible implementation, the first JTAG signal carries verification information, and the signal conversion module is further configured to verify whether the first JTAG signal has a transmission anomaly based on the verification information.

[0010] In one possible implementation, the first JTAG signal is a status signal or a debug signal, and the status signal is used to control whether the signal conversion module activates the debug function. The debugging signal is used to perform debugging operations on the module to be debugged when the debugging function of the signal conversion module has been activated.

[0011] In one possible implementation, the debug signal includes a command packet and a data packet, the command packet indicating a debug operation to be performed on the module to be debugged, and the data packet providing data related to performing the debug operation on the module to be debugged.

[0012] In one possible implementation, the command packet includes a data field, and the debug transmission module performs the debug operation on the module to be debugged based on the address register; The data field indicates the length of the data packet and the address register.

[0013] Secondly, a RISC-V chip is provided, which integrates a single-bus debug circuit as described in the first aspect or any possible implementation of the first aspect.

[0014] Thirdly, an electronic device is provided, the electronic device being configured with a single-bus debugging circuit and a module to be debugged as shown in the first aspect or any possible implementation of the first aspect.

[0015] Fourthly, a debugger is provided, the debugger including a first interface and a conversion module, wherein the first interface establishes a single-wire connection with the single-bus interface of a single-bus debug circuit; The conversion module is used to convert the first JTAG signal into a first single-wire signal, wherein the first JTAG signal indicates that the single-bus debugging circuit debugs the module to be debugged inside the RISC-V chip. The first interface is used to send the first single-wire signal to the single-bus interface.

[0016] Fifthly, a debugging system is provided, which includes a host computer, a debugger, and a single-bus debugging circuit, wherein the debugger is connected to the host computer and the single-bus debugging circuit respectively.

[0017] The technical solution provided in this application brings at least the following beneficial effects: A single-wire connection is established between the single-bus debug circuit and the external debugger, enabling debugging of the RISC-V chip through a single pin. This maximizes the use of pin functionality and reduces the debugging cost of pin-limited circuits. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a single-bus debugging circuit provided in an embodiment of this application; Figure 2 This is a connection diagram of an electronic device provided in an embodiment of this application; Figure 3 This is a schematic diagram of a single-wire signal provided in an embodiment of this application; Figure 4 This is a schematic diagram of the state switching of a signal conversion module provided in an embodiment of this application; Figure 5 This is a schematic diagram of a first single-wire signal provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a command package provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a data packet provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of a debugging result provided in an embodiment of this application; Figure 9This is a schematic diagram of another debugging circuit provided in an embodiment of this application; Figure 10 This is a schematic diagram of the connection of a debugger provided in an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0021] In the field of communication technology, it is common to use a host computer to debug modules within electronic devices. This allows for rapid location and repair of problems in the modules, thereby improving their performance. For example, the host computer can be any device configured with debugging software, such as a terminal or server, while the electronic device can be any device with debugging requirements, such as a terminal, server, gateway, or switch.

[0022] The terminal mentioned in this application embodiment can be any electronic product capable of human-computer interaction with the user through one or more methods such as a keyboard, touchpad, touchscreen, remote control, voice interaction, or handwriting device. When the terminal acts as a host computer, it can be, for example, a PC (Personal Computer), mobile phone, smartphone, PDA (Personal Digital Assistant), PPC (Pocket PC), tablet computer, etc. When the terminal acts as a device to be debugged, it can be, for example, a PC, mobile phone, smartphone, PDA, PPC, tablet computer, wearable device, PPC (Pocket PC), tablet computer, smart car system, smart TV, smart speaker, etc. The server can be, for example, a single server, a server cluster consisting of multiple servers, or a cloud computing service center.

[0023] Furthermore, the host computer can be a standalone device or a component within a device, such as a transceiver, processor, or chip. A processor could be a graphics processing unit (GPU) or a neural network processing unit (NPU). Modules within an electronic device that require debugging include processors, memory, or transceivers; these modules will be referred to as "modules to be debugged" below.

[0024] For example, the module to be debugged is connected to a debugging circuit within the electronic device. This debugging circuit is used to debug the module based on signals sent by a host computer. However, in some cases, there may be a mismatch between the host computer and the debugging circuit, preventing direct communication between them. For instance, the host computer may have a USB (Universal Serial Bus) interface, while the debugging circuit may not have a USB interface. The debugging circuit's interface could be an SPI (Serial Peripheral Interface) or I2C (Inter-Integrated Circuit) interface, making direct connection impossible. Furthermore, the host computer may send signals in the format of data packets encapsulated based on the USB protocol, while the debugging circuit can only handle UART (Universal Asynchronous Receiver / Transmitter) serial data streams or data streams transmitted via the toggling of levels on GPIO (General Purpose Input / Output) pins.

[0025] Therefore, the debugging circuit and the host computer are connected via a debugger. The debugger converts the signals sent by the host computer into a format that the debugging circuit can process, and then sends the converted signals to the debugging circuit. Alternatively, it receives signals sent by the debugging circuit, converts the received signals into a format that the host computer can process, and then sends the converted signals to the host computer.

[0026] Based on the examples above, it is clear that there is a signal transmission requirement between the debugging circuit and the debugger. The transmission direction can be either the debugging circuit sending signals to the debugger or the debugger sending signals to the debugging circuit. Furthermore, if the debugger also transmits a clock signal during signal transmission with the debugging circuit, it must ensure synchronization between the two. Since the clock signal and the signals used for debugging are transmitted through different channels, the debugging circuit and the debugger must be connected through at least two interfaces.

[0027] When an electronic device is designed using the RISC-V (Reduced Instruction Set Computing-V) instruction set, the debug circuitry communicates with the debugger via JTAG (Joint Test Action Group). Devices designed using the RISC-V instruction set refer to electronic devices that include a chip using a RISC-V CPU. Examples of devices designed using the RISC-V instruction set include medical wearable devices and personal electronic products. JTAG is a standardized chip test and debug interface technology.

[0028] As devices designed using the RISC-V instruction set become increasingly miniaturized, especially medical probes where size requirements are higher, the size and pin count of JTAG integrated circuits (ICs) within these devices are limited. Specifically, the JTAG IC corresponds to the debug circuit, and due to the size limitations of the debug circuit, the number of channels established between the debug circuit and the debugger is also limited.

[0029] Based on this, embodiments of this application provide a single-bus debugging circuit, which enables data communication with the debugger using only a single bus. The RISC-V JTAG-based debugging technology provided in this application, which requires only a single wire, can be called Unitary JTAG (uJTAG, single-bus JTAG).

[0030] See Figure 1 The debugging circuit includes a single-bus interface 01, a signal conversion module 02, and a debugging transmission module 03. The single-bus interface 01 is used to establish a single-wire connection with an external debugger. An external debugger refers to a debugger that is not integrated into the debugging circuit. This application does not limit whether the external debugger and the debugging circuit are integrated into the same device.

[0031] In some cases, the single-bus interface 01 is used to transmit single-wire signals between the signal conversion module 02 and the debugger. A single-wire signal includes multiple clock levels, with each clock level corresponding to one clock cycle. At least two of the multiple clock levels in the single-wire signal correspond to a data bit in the JTAG signal. The JTAG signal contains data involved in the debugging process of the module to be debugged, and is data that the signal conversion module 02 supports processing under the JTAG communication protocol.

[0032] Optionally, the JTAG signal transmitted between the signal conversion module 02 and the debugger within the debugging circuit can be a JTAG signal sent from the debugger to the signal conversion module 02, or a JTAG signal sent from the signal conversion module 02 to the debugger. See [link to relevant documentation] Figure 2 Electronic device 23 is equipped with a debugging circuit and a module to be debugged, while debugger 21 establishes communication connections with host computer 22 and electronic device 23 respectively. Figure 2 For the time being, we will take the establishment of a communication connection between the debugger 21 and the host computer 22 via USB as an example. The debugger 21 and the electronic device 23 are connected only through a single bus.

[0033] Figure 2 In this configuration, the debugging function of the host computer 22 is implemented through OpenOCD (Open On-Chip Debugger), which has single-bus debugging capabilities. The debugger 21 receives external data sent by the host computer 22, converts the data into JTAG signals and sends them to the debugging circuit in the electronic device 23. Alternatively, the debugging circuit in the electronic device 23 sends JTAG signals to the debugger 21, which then converts the JTAG signals into external data and sends them to the host computer 22.

[0034] Regardless of the direction of the JTAG signal transmitted between the debug circuit and the debugger, the transmission process is similar. Since the debug circuit and the debugger are connected via a single bus, clock signals and JTAG signals cannot be transmitted in parallel. In this case, JTAG signal transmission is achieved through a single-wire signal. This single-wire signal is obtained by converting the JTAG signal, and at least two of the multiple clock levels included in the single-wire signal correspond to one data bit in the JTAG signal, with one clock level equal to one clock cycle.

[0035] Figure 3 The clock signal indicates the clock signal, with 1 and 0 indicating different data bits. The clock signal consists of eight clock cycles, numbered 0 to 7. A clock cycle refers to the time it takes for the clock signal to complete one level transition. Figure 3 Both 1 and 0 correspond to 8 clock levels. The duration of each clock level is one clock cycle, and the level is stable within the clock cycle. The clock cycle can be called the system clock, and the clock level can also be called the system clock level.

[0036] In one possible implementation, the multiple clock levels of a single-wire signal are divided into multiple level groups, each level group including at least two clock levels, and different level groups include the same number of clock levels. For example, as shown in the above embodiment, a level group includes eight clock levels, corresponding to eight clock cycles.

[0037] In some cases, JTAG signals include multiple data bits. There is a mapping relationship between the level distribution of a level group and the data bits. For example, a data bit is a binary data element in the JTAG signal. A binary data element, also called a binary bit, can be understood as having two possible values: 0 and 1. In this case, the level group will also have two level distributions, with one distribution corresponding to one value of the data bit.

[0038] For example, the level group includes eight clock levels. When the level values ​​of the eight clock levels are distributed as two first levels and six second levels, there is a mapping relationship between the level value distribution and the data bits that take the first value. The first and second levels can be arbitrarily different values; for example, the first level can be low and the second level can be high. See also... Figure 3 The second line shows a level group consisting of two low levels, six high levels, and a first value of 1.

[0039] Alternatively, if the eight clock levels are distributed as six first levels and two second levels, there is a mapping relationship between the level distribution and the data bits that take the second value. Here, the first and second values ​​can be any different values, and the first value is used as the basis for further mapping. Figure 3 For example, the second value is 0, as shown in the example of 1. See the level group shown in the third row, which includes six low levels and two high levels.

[0040] It should be understood that Figure 3 This is intended to illustrate the mapping relationship between level groups and data bits, and is not intended to be limiting. A level group may include eight clock levels, or it may include other numbers of clock levels, and the number and order of the first and second levels within a level group may also be different. Figure 3 The differences are shown.

[0041] Regardless of the mapping relationship between data bits and level groups, the conversion between single-wire signals and JTAG signals can be achieved based on this mapping relationship. This conversion can be performed by the signal conversion module 02 or by the debugger; the following sections will explain the different scenarios.

[0042] Case 1: Single-line signals include the first single-line signal, and JTAG signals include the first JTAG signal.

[0043] In the following case, the signal conversion module 02 is configured to convert the first single-wire signal received by the single-bus interface 01 into the first JTAG signal of the RISC-V standard, so as to perform debugging operations on the module to be debugged based on the first JTAG signal.

[0044] In some cases, the debugger connects to a host computer to receive external data sent by the host computer. The debugger can convert the external data into a first single-wire signal based on a mapping relationship and send this signal to the single-bus interface 01 of the debug circuit. Due to a mismatch between the host computer and the debug circuit—meaning the debug circuit cannot directly process the external data sent by the host computer—the debugger will also convert the external data format to data that the debug circuit can process, i.e., the first JTAG signal, if conversion is required. The content of the first JTAG signal is the same as the external data sent by the host computer, but the format differs, for example, due to different protocols.

[0045] After receiving the first single-wire signal based on the single-bus interface 01, the signal conversion module 02 splits the first single-wire signal into multiple level groups, where eight clock levels form one level group. Based on the level distribution of each level group, the module converts the level group into data bits and concatenates the data bits to obtain the first JTAG signal. For example, the first level group is converted to 1, the second level group to 0, the third level group to 0, and so on. Concatenating the converted data bits yields the first JTAG signal 100…

[0046] Optionally, the first JTAG signal is either a status signal or a debug signal. The status signal is used to control whether the signal conversion module 02 activates the debug function, while the debug signal is used to perform debug operations on the module to be debugged when the signal conversion module 02 has activated the debug function. The conversion process of the status signal and the debug signal will be described below.

[0047] For example, the uJTAG function in signal conversion module 02 is normally inactive, and debugging of the module to be debugged can only be performed when signal conversion module 02 is active. Therefore, the host computer will send a status signal to activate the debugging function before debugging the module to be debugged. This status signal can be a specific activation sequence, including 0xA5. Optionally, there is no need to convert the status signal because the status signal is the signal that wakes up the uJTAG function of signal conversion module 02, and is not an inherent signal defined by the JTAG standard. Therefore, even without protocol conversion of the status signal, signal conversion module 02 can process the status signal normally, that is, it can treat the status signal as a JTAG signal that signal conversion module 02 supports processing.

[0048] Based on this, the debugger parses the external data sent by the host computer, extracts the status signal from the external data, converts the status signal into a first single-wire signal, and then sends the first single-wire signal to the debug circuit.

[0049] Figure 4 The state transition process of signal conversion module 02 is shown. Figure 4The debugging state includes an off state and an active state. The active sequence corresponds to the state signal. The signal conversion module 02 can switch the debugging state from off to active through the active sequence.

[0050] 0xA5 is converted to binary data as 10100101, which consists of eight data bits. Since eight clock levels represent one data bit, 0xA5 will be represented by 64 clock levels. In some cases, the first single-line signal obtained based on the activation sequence includes not only the 64 clock levels corresponding to 0xA5, but also other clock levels. For example, the first single-line signal includes 16 low-level clock levels and the 64 clock levels corresponding to 0xA5, for a total of 80 clock levels.

[0051] See Figure 5 The first single-wire signal used to convert the status signal consists of 80 clock levels. By sending 16 low-level clock levels, the state machine inside the signal conversion module 02 performs an internal state switch after counting 16 clock levels. For example, after counting 16 low levels, it is determined that there is a need to switch to the debug state, and the subsequent clock levels are counted. After completing the counting of 80 clock levels, the switch to debug state is determined to activate the debug function.

[0052] In addition to activating the debugging function of signal conversion module 02, the status signal can also be used to deactivate the debugging function, for example... Figure 4 The signal conversion module 02 can also switch the debugging state from active to off via a reset signal. This means the status signal includes not only the activation sequence but also a reset signal. Therefore, the first single-wire signal used to obtain the reset signal also includes 80 clock levels, all of which are low. In other words, the host computer can reset the debugging function of the signal conversion module 02 by inputting 80 low-level system clock signals. Figure 5 It can be seen that the distribution of level values ​​in the level group of the first single-line signal received by the signal conversion module 02 may be neither the first value nor the second value. In this case, the signal conversion module 02 can count based on the level group.

[0053] When the debugging function of the signal conversion module 02 is active, the host computer will also send a debugging signal to debug the module to be debugged. During the sending of the debugging signal, the debugging function of the signal conversion module 02 remains active. Since the signal conversion module 02 needs to transmit the debugging signal to the debugging transmission module 03 when performing debugging operations on the module to be debugged based on the debugging signal, there is a conversion requirement for the debugging signal. That is, the debugger will convert the debugging signal format, for example, converting the debugging signal from the USB data packet format to TMS (Test Mode Select), TCK (Test Clock), and TDI (Test Data In), which belong to the JTAG signal, and forming a serial data stream based on TMS, TCK, and TDI.

[0054] For example, debug signals include command packets and data packets. Command packets indicate the debug operations to be performed on the module to be debugged, and data packets provide the data involved in performing the debug operations on the module to be debugged. Debug operations may include, for example, reading registers or setting breakpoints, and the data involved in the debug operations may include, for example, program code and configuration parameters, the address of the TAP register to be accessed, and the values ​​of the corresponding TAP registers to be read or written.

[0055] In some cases, the host computer sends debug signals in the order of sending command packets first, followed by data packets. Since the data packets transmitted by the host computer are of variable length each time—for example, the length of a data packet containing program code differs from that of a data packet containing configuration parameters—the command packet, in addition to instructing the debug transmission module 03 to perform the operation, also includes a data field. This data field carries information indicating the length of the data packet transmitted after the command packet.

[0056] Figure 6 This is a schematic diagram of the structure of a command packet provided in an embodiment of this application, which belongs to the underlying data of the command packet sent by the host computer. Figure 6 The Command field is a data field, and the data it carries includes 0x10 or 0x11. When the data field is 0x10, the data in subsequent data packets is 32 bits; when the data field is 0x11, the data in subsequent data packets is 41 bits.

[0057] In one possible implementation, the debug signal may only include command packets. For example, when the debug transmission module 03 executes the debug operation indicated by the command packet, it does not depend on other data. Therefore, the host computer does not need to send data packets to the debug circuit. In this case, the data fields within the command packet can also indicate whether subsequent data packets exist. For example... Figure 6As shown in the third command packet, the data carried by the Command field in this command packet is different from that in 0x10 and 0x11, indicating that there are no subsequent data packets in this command packet.

[0058] In one possible implementation, when the debug transmission module 03 performs debug operations on the module to be debugged based on the address register, the data field, in addition to indicating the length of the data packet, also indicates the address register. Taking the module to be debugged as a processor within a RISC-V chip, and the debug operation as setting a breakpoint as an example, setting a breakpoint means that the processor automatically pauses when it executes a specific instruction, so that the debugger can view the processor status. In this case, the data packet is the target address of the specific instruction, and the address register is used to store the target address to provide a basis for pausing the processor.

[0059] For debugging operations that rely on address registers, the data carried in the data field of the command packet can be understood as register addresses to indicate the address register to be used for debugging. Furthermore, the length of the data field in the command packet is consistent with the length and width of the address register. Taking the address register bits as the TAP (Test Access Port) address register, if the length of the TAP address register is 5 bits, the length of the data field in the command packet is 5 bits.

[0060] The TAP address register includes register dtmcs (Debug Transport Module Control and Status) and register dmi (Debug Module Interface). Register dtmcs has an address of 0x10, and register dmi has an address of 0x11. Therefore, when the data field of the command packet carries 0x10, the indicated address register is register dtmcs in the DTM TAP Register; when the data field of the command packet carries 0x11, the indicated address register is register dmi in the DTM TAP Register.

[0061] In one possible implementation, the command packet includes not only data fields but also other fields. For example, command packets transmitted on a single bus are in frame format, and each frame of the command packet is as follows: Figure 6 The message consists of four parts: a one-bit Header, N bits of transmitted data, a one-bit Parity bit, and a one-bit Acknowledge signal.

[0062] The value of Header is set according to the data transmission direction. When the data transmission direction is from the host computer to the debugging circuit, this value is as follows: Figure 6 The value is set to 1 when the data transmission direction is from the debug circuit back to the host computer, and this value is set to 0. The length of the N-bit data sent is defined according to the scenario, with the least significant bit first and the most significant bit last. Parity is calculated using an odd parity algorithm based on the Data value in the command packet. The Acknowledge bit is sent by the data receiver. If the host computer received data sent by the debug circuit before sending the command packet, this Acknowledge bit indicates whether the previously received data was correctly received. If the transmitted data was correctly received, the Acknowledge bit is 0; if the transmitted data had an error, the Acknowledge bit is 1.

[0063] Taking data packets as an example again, and Figure 6 The command packages shown have similar structures. Figure 7 The data packet shown also includes Header, Data, Parity, and Acknowledge; for the meaning of each field, please refer to [link / reference needed]. Figure 6 The difference between the command packets shown is that the Data field is used to carry data related to the execution of debugging operations, such as the target address of a specific instruction used as a breakpoint in the above embodiment.

[0064] In one possible implementation, regardless of the nature of the first JTAG signal, the first JTAG signal always carries verification information. Therefore, after the signal conversion module 02 converts the first JTAG signal based on the first single-wire signal, it will also verify whether the first JTAG signal has any transmission anomalies based on the verification information. This verification information could be, for example,... Figure 6 The Parity signal conversion module 02 can use an odd parity algorithm to calculate the Data field in the first JTAG signal and determine whether the calculation result is consistent with the data carried in the Parity field, for example, whether they are both 0.

[0065] If the calculation result is consistent with the data carried in the Parity field, for example, both are 0, it indicates that there is no transmission abnormality in the first JTAG signal. The signal conversion module 02 can perform debugging operations based on the information carried in the data field of the first JTAG signal. For example, the first JTAG signal is sent to the debugging transmission module 03, and the debugging transmission module 03 performs debugging operations on the module to be debugged inside the RISC-V chip based on the converted RISC-V standard first JTAG signal.

[0066] If the calculation result is inconsistent with the data carried in the Parity field, it indicates that there is an anomaly in the transmission process of the command packet. The signal conversion module 02 sends the abnormal data to the debugger. The transmission process of the abnormal data can be referred to in Case 2, which will not be repeated here.

[0067] Based on the above examples, it can be seen that the first single-line signal received by the signal conversion module 02 always starts with a low level. For example, the first single-line signal modulated based on the first JTAG signal, whether corresponding to 1 or 0, always starts with a low level, and different values ​​are represented by the length of the high and low levels. Each bit transmitted on the uJTAG single bus adopts a return-to-zero code design, that is, the signal level is forced to return to zero at the end of each bit cycle. Since the single bus is at a high level when it is idle, the return-to-zero code here means that after the transmission ends, the level switches to a high level, waiting for the level on the bus to be pulled low, indicating the start of a transmission.

[0068] Case 2: Single-line signals include second single-line signals, and JTAG signals include second JTAG signals.

[0069] In the second scenario, the debug transmission module 03 is also configured to send the second JTAG signal output from the RISC-V chip to the signal conversion module 02. The second JTAG signal is used to describe the debugging result of the module to be debugged. The signal conversion module 02 is configured to convert the second JTAG signal into a second single-wire signal and send it to the external debugger signal through the single-bus interface 01. At least two of the multiple clock levels included in the second single-wire signal correspond to a data bit in the second JTAG signal.

[0070] Next, combine Figure 9 This describes the process of a SoC chip performing debugging operations as a debugging circuit. The SoC chip includes a uJTAG pin, which is a single-bus interface for connecting to a debugger. The uJTAG pin and the debugger are connected via a single bus. The SoC chip also includes a uJTAG module as a signal conversion module 02, responsible for converting the first single-wire signal received by the uJTAG pin into a first JTAG signal. When the first JTAG signal is a status signal, such as the activation sequence in the above embodiment, the uJTAG module will activate the uJTAG function. When the first JTAG signal is a debugging signal, the debugging signal obtained by the uJTAG module from the first single-wire signal includes a RISC-V standard JTAG multi-wire JTAG signal. This multi-wire JTAG signal corresponds to the first JTAG signal in the above embodiment, and the multi-wire JTAG signal corresponds to... Figure 9 TMS, TCK, and TDI.

[0071] TMS controls the transitions in the JTAG state machine, TCK synchronizes all operations on the JTAG bus, and TDI sends debug commands (such as reading registers and writing memory) into the chip. Figure 9In the process of uJTAG module conversion, the Clock and nRST (active low reset) signals are also referenced. Clock is the operating clock of uJTAG module, ensuring internal logic synchronization. nRST is used to initialize uJTAG module or the entire debug link.

[0072] The uJTAG module sends multi-line signals to the DTM, which acts as the debug transmission module 03. Upon receiving the multi-line signals, the DTM parses them into an instruction format recognizable by the Debug Module. The Debug Module and the DTM are connected via the Debug Module Interface, which defines the communication protocol and data format between them.

[0073] The Debug Module serves as the debugging function module for the RISC-V core, supporting debugging operations such as setting breakpoints, single-stepping, register reading / writing, and memory access. The RISC-V Core, as the core computing unit of the electronic device, is the module to be debugged. Continuing with the example of setting breakpoints, the debugging result is the outcome after the RISC-V core is interrupted. For example, after executing a specific instruction, the RISC-V core will pause normal program execution, and during the pause, the program counter within the RISC-V core will point to the address of the next instruction to be executed, while the state of its internal registers is saved.

[0074] Optionally, the module to be debugged and the debug circuit can be integrated on a single chip, for example... Figure 10 The RISC-V core configuration shown in the CPU can also integrate the module to be debugged and the debugging circuit on different chips. Furthermore, the module to be debugged can be other modules besides the processor, such as memory. This application does not limit this.

[0075] Regardless of the condition of the module to be debugged, the signal conversion module 02 will always receive the debugging results of the module to be debugged sent by the debugging transmission module 03, for example... Figure 9 The Debug Module returns the debugging results to the DTM. The DTM sends a second JTAG signal describing the debugging results to the uJTAG module through the TDO (TestData Out) interface. The debugging results may be, for example, register values ​​or execution results.

[0076] After receiving the second JTAG signal, the signal conversion module 02 converts it into a second single-wire signal. For example, the signal conversion module 02 can convert each data bit in the second JTAG signal into a second single-wire signal including multiple clock levels according to the mapping relationship, either from low to high or from high to low. For instance, if the second JTAG signal includes 1000010, the 1 is converted to... Figure 3 The second row of level groups shown converts 0 to... Figure 3 The third row of level groups is shown.

[0077] This method of converting data bits into level groups is called PLM (Pulse Width Modulation). After the signal conversion module 02 obtains the second single-wire signal, it sends the second single-wire signal to the debugger through the single-bus interface 01. The debugger converts the second single-wire signal into a second JTAG signal and then into a data format that the host computer can understand. Furthermore, the second JTAG signal can also include verification information, and the debugger will perform verification on the second JTAG signal based on this verification information.

[0078] Unlike the first JTAG signal, which may have a different data packet length, the second JTAG signal has a fixed length. Figure 8 The diagram shows the structure of the debugging results, which is data obtained by the debugger based on the second JTAG signal for protocol conversion. Figure 8 It can be seen that the data length is 35 bits, of which the message header, Parity, and Ack are each 1 bit, and the data field is 32 bits.

[0079] In some cases, the connection between the signal conversion module 02 and the single-bus interface 01 can use an open-drain circuit with an internal pull-up resistor, for example... Figure 9 As shown. Under this connection, the bus connected to the single-bus interface 01 will remain high when idle. If there is a single-wire signal that needs to be transmitted on the bus, the data initiator will pull the bus low.

[0080] Furthermore, the examples above are intended to illustrate the operation of the debugging circuit, not to limit the configuration relationship between the debugging circuit and the debugger. The debugging circuit and the debugger can be located in different devices, for example... Figure 2 As shown, the debugging circuit is configured within electronic device 23, while the debugger 21 is independent of electronic device 23 and is connected to the debugging circuit within the electronic device via a bus. The debugger and debugging circuit can also be integrated into the electronic device; see [reference needed]. Figure 10 The debugger is configured in the SoC chip inside the electronic device. The SoC chip has built-in physical pins and is connected to the host computer via a USB cable. The SoC chip provides two buses: one bus is used to connect to GND (ground), and the other bus is used to connect to the debugging circuit inside the electronic device.

[0081] In summary, the debugging circuit provided in this application establishes a single-wire connection between the single-bus debugging circuit and the external debugger, enabling debugging of the RISC-V chip through a single pin. This maximizes the utilization of pin functionality and reduces the debugging cost of pin-limited circuits. Furthermore, since at least two clock levels correspond to one data bit, data transmission can be achieved when the periodic blocks corresponding to the data bits are synchronized between the debugging circuit and the debugger. The periodic block corresponding to the data bit consists of at least two clock cycles corresponding to at least two clock levels. Compared to single-clock-cycle synchronization, periodic block synchronization has a higher tolerance for synchronization deviations, and JTAG signal transmission can be achieved even without transmitting clock signals.

[0082] This application embodiment also provides a debugger, which includes a first interface and a conversion module. The first interface establishes a single-wire connection with the single-bus interface of the single-bus debug circuit. The conversion module is used to convert a first JTAG signal into a first single-wire signal. The first JTAG signal indicates that the debug circuit is debugging the module to be debugged inside the RISC-V chip. The first interface is used to send the first single-wire signal to the single-bus interface.

[0083] In some cases, the debugger also includes a second interface that connects to the host computer. For details on the functions of the debugger, please refer to the relevant descriptions in the above embodiments, which will not be repeated here.

[0084] This application also provides a RISC-V chip, which integrates the debugging circuit shown in the above embodiments.

[0085] This application also provides an electronic device, which is configured with the debugging circuit and the module to be debugged as described in the above embodiments, such as a processor or a memory.

[0086] This application also provides a debugging system, which includes a host computer, a debugger, and a single-bus debugging circuit. The debugger is connected to both the host computer and the debugging circuit.

[0087] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application have been authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the first single-wire signals involved in this application were all obtained under fully authorized conditions.

[0088] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0089] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A single-bus debug circuit based on RISC-V architecture, characterized in that, include: A single-bus interface is used to establish a single-wire connection with an external debugger; The signal conversion module is configured to convert the first single-wire signal received by the single-bus interface into the first Joint Test Action Group (JTAG) signal of the RISC-V standard. The debug transmission module is connected to the signal conversion module and is configured to perform debug operations on the module to be debugged inside the RISC-V chip based on the first JTAG signal of the converted RISC-V standard.

2. The circuit according to claim 1, characterized in that, The debug transmission module is also configured to send a second JTAG signal output from the RISC-V chip to the signal conversion module. The second JTAG signal is used to describe the debugging result of the module to be debugged. The signal conversion module is configured to convert the second JTAG signal into a second single-wire signal and send it to the external debugger through the single-bus interface.

3. The circuit according to claim 1, characterized in that, The first single-wire signal includes multiple clock levels, and at least two of the multiple clock levels correspond to a data bit in the first JTAG signal.

4. The circuit according to claim 3, characterized in that, The first single-wire signal includes multiple clock levels, which are divided into multiple level groups. Each level group includes at least two clock levels, and different level groups include the same number of clock levels. There is a mapping relationship between the level value distribution of the level group and the data bits in the first JTAG signal.

5. The circuit according to claim 3, characterized in that, The level group includes eight clock levels; When the distribution of the eight clock levels is two first levels and six second levels, there is a mapping relationship between the distribution of the level values ​​and the data bits that take the first value; Alternatively, if the distribution of the eight clock levels is six first levels and two second levels, there is a mapping relationship between the distribution of the level values ​​and the data bits that take the second value.

6. The circuit according to any one of claims 1-5, characterized in that, The first JTAG signal carries verification information, and the signal conversion module is further configured to verify whether the first JTAG signal has a transmission abnormality based on the verification information.

7. The circuit according to any one of claims 1-5, characterized in that, The first JTAG signal is a status signal or a debug signal, and the status signal is used to control whether the signal conversion module activates the debug function; The debugging signal is used to perform debugging operations on the module to be debugged when the debugging function of the signal conversion module has been activated.

8. The circuit according to claim 7, characterized in that, The debugging signal includes a command packet and a data packet. The command packet indicates the debugging operation to be performed on the module to be debugged, and the data packet is used to provide data related to performing the debugging operation on the module to be debugged.

9. The circuit according to claim 8, characterized in that, The command package includes a data field, and the debug transmission module performs the debug operation on the module to be debugged based on the address register. The data field indicates the length of the data packet and the address register.

10. A RISC-V chip, characterized in that, It integrates a single-bus debugging circuit as described in any one of claims 1-9.

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