A method and apparatus for improving yield in an integrated circuit manufacturing facility

Abstract

This invention relates to the field of integrated circuit design and manufacturing, and particularly to a method and apparatus for improving yield in integrated circuit manufacturing. The method involves collecting full-process manufacturing data at the integrated circuit manufacturing end and generating a wafer defect map based on this data. The manufacturing end then extracts graphic features of manufacturing weaknesses from the wafer defect map, constructing a weakness graphic database. This database is then transmitted to the integrated circuit design end, enabling the design end to adjust routing strategies and graphics during the chip physical design routing stage. This avoids weak point graphics in the layout that match the graphic features in the database, resulting in an adjusted routing layout. This invention avoids layout structures prone to manufacturing defects from the design stage, thereby expanding the process window and significantly improving finished product yield.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design and manufacturing, and in particular to a method and apparatus for improving the yield of integrated circuit manufacturing, a method and apparatus for improving the yield of integrated circuit design, and a device for improving the yield of integrated circuits. Background Technology

[0002] In the physical design process of integrated circuit chips, existing technologies typically do not incorporate manufacturing weaknesses (hereinafter referred to as weaknesses) from the wafer fabrication stage into the design considerations. However, in actual mass production of integrated circuits, these weaknesses directly narrow the process window and become a core bottleneck restricting chip production yield.

[0003] As integrated circuit process nodes continue to evolve towards advanced processes, the graphic complexity and wiring density of chip layouts have increased significantly, and the number of weak points has grown exponentially. Relying solely on manufacturing process optimization is no longer sufficient to overcome and resolve these weak points. Current technologies typically employ resolution enhancement techniques (RET) to optimize layout graphics and mitigate yield losses caused by weak points. However, with the continuous increase in layout graphic density, full-chip-level graphic optimization has gradually reached a technological bottleneck and cannot fundamentally solve the problem of the disconnect between design and manufacturing.

[0004] Therefore, how to further reduce the weaknesses generated in the wafer manufacturing process and improve the yield of finished chips is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a method and apparatus for improving the yield of integrated circuit manufacturing, a method and apparatus for improving the yield of integrated circuit design, and an integrated circuit yield improvement device, so as to solve the problem of multiple weak points and low yield of finished chips in the existing wafer manufacturing process.

[0006] To address the aforementioned technical problems, this invention provides a method for improving the yield of integrated circuit manufacturing, comprising:

[0007] The integrated circuit manufacturing end collects manufacturing data throughout the entire production process and generates a wafer defect map based on the manufacturing data.

[0008] The integrated circuit manufacturing end extracts the graphic features of manufacturing weak points based on the wafer defect map and constructs a weak point graphic database.

[0009] The integrated circuit manufacturing end transmits the weak point graphic database to the integrated circuit design end, enabling the integrated circuit design end to adjust the routing strategy and graphic based on the weak point graphic database during the routing stage of chip physical design. This avoids weak point graphics in the layout that match the graphic features in the weak point graphic database, resulting in a routing adjustment layout.

[0010] Optionally, in the method for improving yield in integrated circuit manufacturing, the full-process manufacturing data includes online inspection data in the wafer manufacturing process, wafer acceptance test (WAT) data, yield statistics data, and chip failure analysis data.

[0011] And / or, the wafer defect map includes the location information of the defects, the corresponding defect type, and the corresponding defect graphic structure information.

[0012] Optionally, in the method for improving yield in integrated circuit manufacturing, the graphic features stored in the weak point graphic database include defect type, graphic structure corresponding to the defect, process window influence parameters, adapted process node, lithography process type, and mask attribute information.

[0013] A method for improving yield at the integrated circuit design stage, which corresponds to the aforementioned method for improving yield at the integrated circuit manufacturing stage, includes:

[0014] The integrated circuit design end receives a vulnerability graph database from the integrated circuit manufacturing end;

[0015] Based on the weak point graphic database, the integrated circuit design end performs routing strategy adjustments and graphic adjustments during the routing stage of chip physical design to avoid weak point graphics in the layout that match the graphic features in the weak point graphic database, thus obtaining a routing adjustment layout.

[0016] Optionally, in the yield improvement method at the integrated circuit design end, the integrated circuit design end, based on the weak point graphic database, performs routing strategy adjustment and graphic adjustment during the routing stage of chip physical design to avoid weak point graphics in the layout that match the graphic features in the weak point graphic database, including:

[0017] During the automatic routing process, the integrated circuit design end periodically acquires the original pattern in the routing front area and the planned routing pattern in the routing front area.

[0018] The planned wiring diagram is combined with the original diagram to obtain the planned layout diagram;

[0019] Determine whether the graphic features of the planned layout graphic match the weak point graphic database;

[0020] When the graphic features of the planned layout graphic match the weak point graphic database, the planned wiring graphic in the wiring forward area is replanned so that the planned wiring graphic bypasses the original graphic;

[0021] And / or, when the graphic features of the planned layout graphic match the weak point graphic database, redundant wires or programmable fuses are set in the corresponding area of ​​the planned wiring graphic.

[0022] Optionally, in the method for improving yield in the integrated circuit design stage, after obtaining the routing adjustment layout, the method further includes:

[0023] The integrated circuit design end re-examines the routing adjustment layout based on the weak point graphic database to determine whether there are potential problem graphics in the routing adjustment layout that match the graphic features in the weak point graphic database;

[0024] When a potential problem graphic appears in the routing adjustment layout that matches the graphic features in the vulnerability graphic database, the potential problem graphic is readjusted so that the graphic features of the readjusted potential problem graphic no longer match the vulnerability graphic database, resulting in a routing re-screening layout.

[0025] Optionally, in the yield improvement method at the integrated circuit design end, the potential problem pattern is readjusted so that the graphic features of the readjusted potential problem pattern no longer match the weak point graphic database, including:

[0026] Identify the metal bridging weak points and metal necking weak points in the potential problem diagrams;

[0027] Increase the spacing between the metal bridging weak point graphics and / or reduce the line width of the metal bridging weak point graphics;

[0028] Reduce the spacing between the metal necking weak point patterns and / or increase the line width of the metal bridging weak point patterns.

[0029] An integrated circuit manufacturing yield improvement device includes:

[0030] The defect collection module is used to enable the integrated circuit manufacturing end to collect full-process manufacturing data during the production process and generate a wafer defect map based on the full-process manufacturing data.

[0031] The database construction module is used to enable the integrated circuit manufacturing end to extract the graphical features of manufacturing weak points based on the wafer defect map and construct a weak point graphical database.

[0032] The transmission module is used to enable the integrated circuit manufacturing end to transmit the weak point graphic database to the integrated circuit design end, so that the integrated circuit design end can adjust the routing strategy and graphic based on the weak point graphic database during the routing stage of chip physical design, avoid the appearance of weak point graphics in the layout that match the graphic features in the weak point graphic database, and obtain the routing adjusted layout.

[0033] An integrated circuit design-side yield improvement device, corresponding to the aforementioned integrated circuit manufacturing-side yield improvement device, includes:

[0034] The receiving module is used to enable the integrated circuit design end to receive a vulnerability graph database from the integrated circuit manufacturing end.

[0035] The routing adjustment module is used by the integrated circuit design end to adjust the routing strategy and pattern based on the weak point pattern database during the routing stage of chip physical design, so as to avoid the appearance of weak point patterns in the layout that match the pattern features in the weak point pattern database, and obtain the routing adjustment layout.

[0036] An integrated circuit yield improvement device, comprising:

[0037] Memory, used to store computer programs;

[0038] A processor, configured to implement the steps of the above-described integrated circuit manufacturing yield improvement method and / or the steps of the above-described integrated circuit design yield improvement method when executing the computer program.

[0039] The integrated circuit manufacturing yield improvement method provided by this invention involves collecting full-process manufacturing data at the integrated circuit manufacturing end and generating a wafer defect map based on the full-process manufacturing data; the integrated circuit manufacturing end extracts graphic features of manufacturing weak points based on the wafer defect map and constructs a weak point graphic database; the integrated circuit manufacturing end transmits the weak point graphic database to the integrated circuit design end, enabling the integrated circuit design end to adjust the routing strategy and graphic features during the routing stage of chip physical design based on the weak point graphic database, avoiding the appearance of weak point graphics in the layout that match the graphic features in the weak point graphic database, and obtaining a routing adjustment layout.

[0040] This invention constructs a weak point graphical database based on defect data from actual mass production. It fully considers the graphical characteristics of weak points in the manufacturing process during the chip design stage, achieving cooperation between the manufacturing and design ends. Weak point avoidance strategies are integrated into the entire chip physical design process, avoiding layout structures prone to manufacturing defects from the design stage. This reduces the pressure on process optimization in manufacturing, expands the process window, and significantly improves the yield of integrated circuit chips in mass production. This invention also provides a yield improvement device for integrated circuit manufacturing, a yield improvement method and device for integrated circuit design, and an integrated circuit yield improvement equipment, all possessing the aforementioned beneficial effects. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 A flowchart illustrating a specific implementation of the method for improving the yield of integrated circuit manufacturing provided by the present invention;

[0043] Figure 2 A schematic diagram of a specific embodiment of the yield improvement device for integrated circuit manufacturing provided by the present invention;

[0044] Figure 3 A flowchart illustrating a specific implementation of the method for improving the yield of integrated circuit design provided by the present invention;

[0045] Figure 4 A partial flowchart illustrating another specific implementation of the method for improving the yield of integrated circuit design provided by the present invention;

[0046] Figure 5 This is a schematic diagram of a specific embodiment of the yield improvement device for integrated circuit design provided by the present invention.

[0047] Figure label:

[0048] 110 - Defect collection module; 120 - Database construction module; 130 - Transmission module; 210 - Receiving module; 220 - Wiring adjustment module. Detailed Implementation

[0049] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] The core of this invention is to provide a method for improving the yield of integrated circuit manufacturing, and a flowchart of one specific implementation is shown below. Figure 1 As shown, this is referred to as Specific Implementation Method One, which includes:

[0051] S101: The integrated circuit manufacturing end collects full-process manufacturing data during the production process and generates a wafer defect map based on the full-process manufacturing data.

[0052] Furthermore, the full-process manufacturing data includes online inspection data during the wafer manufacturing process, wafer acceptance test (WAT) data, yield statistics, and chip failure analysis data;

[0053] And / or, the wafer defect map includes the location information of the defects, the corresponding defect type, and the corresponding defect graphic structure information.

[0054] By further refining and disclosing the data types contained in the full-process manufacturing data and the wafer defect map, this invention further enhances its versatility and also improves the effectiveness and accuracy of subsequent layout improvements in integrated circuit design.

[0055] The following example illustrates the situation in actual production. In a specific production embodiment, the integrated circuit manufacturing end (wafer fab) collects the full-process manufacturing data of 100 consecutive batches of wafers at the 5nm process node. In this embodiment, the full-process manufacturing data includes online inspection data of each wafer manufacturing process (including overlay error and topography inspection data of the photolithography process, and linewidth deviation inspection data of the etching process), wafer acceptance test (WAT) data (including electrical parameter test data such as sheet resistance, contact hole resistance, and threshold voltage), chip yield statistics, and chip failure analysis data.

[0056] Based on the collected full-process manufacturing data, through defect location and coordinate mapping, all defect information is mapped to the coordinate system of the corresponding wafer to generate a wafer defect map. In this embodiment, the wafer defect map also includes the location information of each defect in the wafer and chip layout, the defect type corresponding to the defect (this embodiment focuses on marking two core defects: metal bridging defects and metal necking defects), the layout graphic structure information corresponding to the defect, and the degree of impact of the defect on the process window.

[0057] S102: The integrated circuit manufacturing end extracts the graphic features of manufacturing weak points based on the wafer defect map and constructs a weak point graphic database.

[0058] Following the previous example, in this step, the integrated circuit manufacturing end performs cluster analysis on the graphic structure corresponding to all defects based on the wafer defect map generated in the previous step, extracts the common graphic features of various manufacturing weak points, and constructs a standardized weak point graphic database after classification and statistics.

[0059] As one specific implementation, the graphic features stored in the weak point graphic database include defect types, corresponding graphic structures, process window influence parameters, compatible process nodes (5nm in this example), lithography process types (including positive development PTD and negative development NTD), and mask attribute information (including clear and dark types). Further detailed disclosure of the graphic features stored in the weak point graphic database can enhance the guidance for subsequent integrated circuit design routing strategy adjustments, address various process conditions, improve adjustment effectiveness, and further reduce weak points in the layout.

[0060] Preferably, the integrated circuit manufacturing end iteratively updates the weak point graph database every certain period of time (e.g., monthly) based on newly added mass production wafer data, supplements newly discovered weak point graphs, optimizes the feature parameters and optimization guidelines of existing graphs, and ensures real-time matching between the database and the actual process characteristics of the production line.

[0061] S103: The integrated circuit manufacturing end transmits the weak point graphic database to the integrated circuit design end, so that the integrated circuit design end can adjust the routing strategy and graphic based on the weak point graphic database during the routing stage of chip physical design, avoid the appearance of weak point graphics in the layout that match the graphic features in the weak point graphic database, and obtain the routing adjustment layout.

[0062] In this step, the integrated circuit manufacturing end transmits the iteratively updated vulnerability graph database to the integrated circuit design end through an encrypted standardized data interface. At the same time, it provides adaptation plugins for the database and mainstream EDA tools, enabling the integrated circuit design end to directly call the database in the routing tool. This guides the integrated circuit design end to adjust the routing strategy and graph during the routing stage of chip physical design, avoiding the appearance of vulnerability graphs in the layout that match the graph features in the database, and finally obtaining a routing adjustment layout that meets manufacturing requirements.

[0063] The integrated circuit manufacturing yield improvement method provided by this invention involves collecting full-process manufacturing data at the integrated circuit manufacturing end and generating a wafer defect map based on the full-process manufacturing data. The integrated circuit manufacturing end extracts graphic features of manufacturing weaknesses based on the wafer defect map, constructing a weakness graphic database. The integrated circuit manufacturing end transmits the weakness graphic database to the integrated circuit design end, enabling the integrated circuit design end to adjust routing strategies and graphics during the routing stage of chip physical design based on the weakness graphic database. This avoids weak point graphics in the layout that match the graphic features in the weakness graphic database, resulting in a routing adjustment layout. This invention constructs a weakness graphic database based on actual mass production defect data, fully considering the weak point graphic features of the manufacturing process during the chip design stage. This achieves mutual cooperation between the manufacturing and design ends, integrating weakness avoidance strategies throughout the entire chip physical design process. From the design stage, it avoids layout structures that easily cause manufacturing defects, thereby reducing the process optimization pressure on the manufacturing end, expanding the process window, and significantly improving the yield of integrated circuit chips in mass production.

[0064] The following describes the yield improvement device for integrated circuit manufacturing provided in the embodiments of the present invention. The yield improvement device for integrated circuit manufacturing described below and the yield improvement method for integrated circuit manufacturing described above can be referred to in correspondence.

[0065] Figure 2 The structural block diagram of the integrated circuit manufacturing yield improvement device provided in this embodiment of the invention is referred to as Specific Embodiment Two, and is referred to as... Figure 2 Integrated circuit manufacturing yield improvement devices may include:

[0066] The defect collection module 110 is used to enable the integrated circuit manufacturing end to collect full-process manufacturing data during the production process and generate a wafer defect map based on the full-process manufacturing data.

[0067] The database construction module 120 is used to enable the integrated circuit manufacturing end to extract the graphic features of manufacturing weak points based on the wafer defect map and construct a weak point graphic database.

[0068] The transmission module 130 is used to enable the integrated circuit manufacturing end to transmit the weak point graphic database to the integrated circuit design end, so that the integrated circuit design end can adjust the routing strategy and graphic based on the weak point graphic database during the routing stage of chip physical design, avoid the appearance of weak point graphics in the layout that match the graphic features in the weak point graphic database, and obtain the routing adjustment layout.

[0069] The integrated circuit manufacturing yield improvement device provided by this invention includes a defect collection module 110, used to enable the integrated circuit manufacturing end to collect full-process manufacturing data during the production process and generate a wafer defect map based on the full-process manufacturing data; a database construction module 120, used to enable the integrated circuit manufacturing end to extract graphic features of manufacturing weak points based on the wafer defect map and construct a weak point graphic database; and a transmission module 130, used to enable the integrated circuit manufacturing end to transmit the weak point graphic database to the integrated circuit design end, so that the integrated circuit design end can adjust the routing strategy and graphic adjustment during the routing stage of chip physical design based on the weak point graphic database, avoid the appearance of weak point graphics in the layout that match the graphic features in the weak point graphic database, and obtain a routing adjustment layout. This invention constructs a weak point graphical database based on defect data from actual mass production. It fully considers the weak point graphical features of the manufacturing process during the chip design stage, realizing mutual cooperation between the manufacturing and design ends. It integrates weak point avoidance strategies into the entire process of chip physical design, avoiding layout structures that are prone to manufacturing defects from the design stage. This reduces the process optimization pressure on the manufacturing end, expands the process window, and significantly improves the yield of integrated circuit chips in mass production.

[0070] The integrated circuit manufacturing yield improvement device of this embodiment is used to implement the aforementioned integrated circuit manufacturing yield improvement method. Therefore, the specific implementation of the integrated circuit manufacturing yield improvement device can be found in the embodiment section of the integrated circuit manufacturing yield improvement method above. For example, the defect collection module 110, the database construction module 120, and the transmission module 130 are respectively used to implement steps S101, S103, and S103 in the aforementioned integrated circuit manufacturing yield improvement method. Therefore, the specific implementation can be referred to the description of the corresponding embodiments, which will not be repeated here.

[0071] This invention also provides a method for improving yield in integrated circuit design, and a flowchart of one specific implementation is shown below. Figure 3 As shown, referred to as Specific Implementation Method Three, the yield improvement method at the integrated circuit design end corresponds to any of the aforementioned yield improvement methods at the integrated circuit manufacturing end, and includes:

[0072] S201: The integrated circuit design end receives a vulnerability graph database from the integrated circuit manufacturing end.

[0073] The yield improvement method for integrated circuit design in this invention corresponds to the yield improvement method for integrated circuit manufacturing described above. They can be considered as the same method described from different perspectives.

[0074] Corresponding to the specific embodiments mentioned above, in this step, the integrated circuit design end receives the weak point graph database corresponding to the 5nm process node from the integrated circuit manufacturing end mentioned above through a standardized data interface, and embeds the database into the EDA automatic routing tool through an adapter plug-in to complete the configuration and preparation for calling the database.

[0075] S202: Based on the weak point graphic database, the integrated circuit design end performs routing strategy adjustment and graphic adjustment during the routing stage of chip physical design to avoid weak point graphics in the layout that match the graphic features in the weak point graphic database, and obtains the routing adjustment layout.

[0076] In this step, the integrated circuit design team, based on the received vulnerability graph database, performs real-time routing strategy and graph adjustments during the routing phase of the 5nm SoC chip physical design. The core is to predict and avoid vulnerability graphs in advance during the routing process. The specific process is as follows: Figure 4 As shown, it includes:

[0077] A1: During the automatic routing process, the integrated circuit design end periodically acquires the original pattern in the routing advance area and the planned routing pattern in the routing advance area.

[0078] Following the previous example, this step presets a sliding routing advance area. In this embodiment, the routing advance area can be set as a 100μm×100μm routing window, which advances synchronously with the progress of automatic routing. During the automatic routing process, after each smallest routing unit is laid out, the original pattern in the current routing advance area (i.e., the layout pattern of metal traces, vias, etc. that have been laid out in the window) and the planned routing pattern that the routing tool will lay out in the window are obtained once.

[0079] A2: Combine the planned wiring diagram with the original diagram to obtain the planned layout diagram.

[0080] In this step, the obtained planned wiring graphic is combined with the original graphic to obtain the planned layout graphic in the window, which completely restores the complete layout structure of the area after the wiring is completed.

[0081] A3: Determine whether the graphic features of the planned layout graphic match the weak point graphic database.

[0082] The graphic matching algorithm compares the graphic features of the planned layout graphic with the graphic features in the vulnerability graphic database. For example, a similarity threshold of 80% can be preset. That is, if the similarity exceeds 80%, the planned layout graphic is determined to match the vulnerability graphic database and belongs to a high-risk vulnerability graphic.

[0083] A4: When the graphic features of the planned layout graphic match the weak point graphic database, the planned wiring graphic in the wiring forward area is replanned so that the planned wiring graphic bypasses the original graphic.

[0084] A5: When the graphic features of the planned layout graphic match the weak point graphic database, redundant wires or programmable fuses are set in the corresponding area of ​​the planned wiring graphic.

[0085] Of course, steps A4 and A5 are not sequential and can be performed simultaneously, or one can be performed depending on the actual situation. This invention does not impose any restrictions on this.

[0086] When a match is determined, the integrated circuit design end will perform corresponding optimization operations. Specifically, it will prioritize replanning the planned routing pattern in the routing area before routing, adjusting the routing path so that the planned routing pattern bypasses the original pattern, avoiding the formation of high-risk weak point patterns after combination. If the routing path of critical signal traces cannot be adjusted, redundant wires or programmable fuses will be laid around the corresponding area of ​​the planned routing pattern to improve the defect tolerance of the layout and avoid single defects causing chip function failure.

[0087] Through the above steps, weak points are predicted and avoided in real time during the routing process. After the full chip routing is completed, the routing adjustment layout is obtained.

[0088] In a preferred embodiment, after obtaining the wiring adjustment layout, the method further includes:

[0089] B1: The integrated circuit design end re-examines the routing adjustment layout based on the weak point graphic database to determine whether there are potential problem graphics in the routing adjustment layout that match the graphic features in the weak point graphic database.

[0090] In this step, the integrated circuit design end performs a full-chip global graphic re-inspection of the wiring adjustment layout based on the weak point graphic database. Through the graphic matching algorithm, the similarity of all layout graphics of the whole chip is compared with the graphic features in the database. In this embodiment, the preset similarity threshold can be set to 75%, that is, if the similarity exceeds 75%, it is determined to be a potential problem graphic.

[0091] B2: When a potential problem graphic appears in the routing adjustment layout that matches the graphic features in the weak point graphic database, the potential problem graphic is readjusted so that the graphic features of the readjusted potential problem graphic no longer match the weak point graphic database, resulting in a routing re-screening layout.

[0092] Once a potential problem pattern is identified, it is re-adjusted to ensure its features no longer match the vulnerability pattern database. This results in a final routing re-screening layout, completing the entire layout optimization process. Theoretically, the routing re-screening layout at this point no longer contains any patterns recorded in the vulnerability pattern database, meaning there are no known patterns that could cause vulnerabilities, thus reducing the probability of vulnerabilities occurring during integrated circuit manufacturing.

[0093] As a preferred embodiment, the potential problem graphs are readjusted so that the graphical features of the readjusted potential problem graphs no longer match the vulnerability graph database, including:

[0094] C1: Identify the metal bridging weak points and metal necking weak points in the potential problem diagrams.

[0095] In this step, the first step is to identify the type of potential problem patterns, distinguishing them into metal bridging weak point patterns and metal necking weak point patterns.

[0096] C2: Increase the graphic spacing of the metal bridging weak point graphic, and / or reduce the graphic line width of the metal bridging weak point graphic.

[0097] For weak points in metal bridging patterns (i.e., defective patterns where two parallel traces are prone to short circuits), and when the mask of the corresponding trace layer is of the clear type and the photolithography process is PTD process, optimization is achieved by increasing the pattern spacing between the two traces or reducing the pattern linewidth of the traces. Following the previous example, the trace spacing is preferentially increased from the minimum design rule of 28nm to 32nm. If the spacing cannot be adjusted, the trace linewidth is reduced from 22nm to 20nm.

[0098] C3: Reduce the graphic spacing of the metal necking weak point graphic, and / or increase the graphic line width of the metal bridging weak point graphic.

[0099] For metal necking weak point patterns (i.e., defective patterns where the middle trace of three parallel traces is prone to necking and breakage), and when the mask of the corresponding trace layer is of type clear and the photolithography process is PTD process, optimization is carried out by reducing the pattern spacing of the traces or increasing the pattern linewidth of the traces; in this embodiment, the trace linewidth is preferentially increased from 22nm to 24nm. If the linewidth cannot be adjusted, the trace spacing is reduced from 28nm to 26nm.

[0100] For trace layers with a dark mask, a reverse adjustment rule is adopted: weak points in metal bridging are optimized by reducing the pattern spacing or increasing the pattern line width, and weak points in metal necking are optimized by increasing the pattern spacing or decreasing the pattern line width.

[0101] After the above readjustment is completed, the final wiring rescreening layout is delivered to the manufacturing end for tape-out. In this embodiment, the chip optimized by the above method has a significantly improved mass production yield compared with the traditional design scheme, and the process window is further expanded.

[0102] The integrated circuit design-side yield improvement method provided by this invention involves the integrated circuit design end receiving a vulnerability graph database from the integrated circuit manufacturing end. Based on this database, the integrated circuit design end adjusts routing strategies and graphs during the routing stage of chip physical design to avoid vulnerability graphs in the layout that match the graph features in the database, resulting in an adjusted routing layout. This invention constructs a vulnerability graph database based on actual mass production defect data, fully considering the vulnerability graph features of the manufacturing process during the chip design stage. This achieves mutual cooperation between the manufacturing and design ends, integrating vulnerability avoidance strategies throughout the entire chip physical design process. By avoiding layout structures prone to manufacturing defects from the design stage, it reduces the process optimization pressure on the manufacturing end, expands the process window, and significantly improves the yield of integrated circuit chips in mass production.

[0103] The following describes the yield improvement device for integrated circuit design provided in the embodiments of the present invention. The yield improvement device for integrated circuit design described below and the yield improvement method for integrated circuit design described above can be referred to in correspondence.

[0104] Figure 5 The structural block diagram of the integrated circuit design end yield improvement device provided in the embodiment of the present invention is shown below. Figure 5 The yield improvement device at the integrated circuit design end corresponds to the yield improvement device at the integrated circuit manufacturing end described above, and includes:

[0105] Receiver module 210 is used to enable the integrated circuit design end to receive a weak point graphic database from the integrated circuit manufacturing end;

[0106] The routing adjustment module 220 is used by the integrated circuit design end to adjust the routing strategy and the pattern based on the weak point pattern database during the routing stage of chip physical design, so as to avoid the appearance of weak point patterns in the layout that match the pattern features in the weak point pattern database, and obtain the routing adjustment layout.

[0107] In one specific implementation, the wiring adjustment module 220 includes:

[0108] The forward area detection unit is used to periodically acquire the original pattern in the forward area of ​​the wiring and the planned wiring pattern in the forward area of ​​the wiring during the automatic wiring process of the integrated circuit design end.

[0109] The planning and assembly unit is used to combine the planned wiring pattern with the original pattern to obtain the planned layout pattern;

[0110] The planning layout unit is used to determine whether the graphic features of the planning layout graphic match the weak point graphic database;

[0111] The planning detour unit is used to replan the planned wiring pattern in the wiring forward area when the graphic features of the planned layout graphic match the weak point graphic database, so that the planned wiring pattern detours around the original graphic.

[0112] And / or, a planning addition unit is configured to set redundant wires or programmable fuses in the corresponding area of ​​the planned wiring pattern when the graphic features of the planned layout pattern match the weak point graphic database.

[0113] In one specific implementation, the wiring adjustment module 220 further includes:

[0114] The re-inspection unit is used by the integrated circuit design end to re-inspect the routing adjustment layout according to the weak point graphic database, and to determine whether there are potential problem graphics in the routing adjustment layout that match the graphic features in the weak point graphic database.

[0115] The readjustment unit is used to readjust the potential problem pattern when a potential problem pattern that matches the graphic features in the vulnerability graphic database appears in the wiring adjustment layout, so that the graphic features of the readjusted potential problem pattern no longer match the vulnerability graphic database, thereby obtaining a wiring rescreening layout.

[0116] In one specific implementation, the wiring adjustment module 220 includes:

[0117] A linear weak point determination unit is used to determine the metal bridging weak point pattern and the metal necking weak point pattern in the potential problem pattern.

[0118] A bridging processing unit is used to increase the graphic spacing of the metal bridging weak point graphic and / or reduce the graphic line width of the metal bridging weak point graphic.

[0119] The necking processing unit is used to reduce the pattern spacing of the metal necking weak point pattern and / or increase the pattern line width of the metal bridging weak point pattern.

[0120] The integrated circuit design-side yield improvement device provided by this invention includes a receiving module 210 for receiving a vulnerability graph database from the integrated circuit manufacturing end; and a routing adjustment module 220 for adjusting routing strategies and graphs during the routing stage of chip physical design based on the vulnerability graph database, avoiding vulnerability graphs in the layout that match the graph features in the vulnerability graph database, and obtaining a routing adjusted layout. This invention constructs a vulnerability graph database based on actual mass production defect data, fully considering the vulnerability graph features of the manufacturing process during the chip design stage, achieving mutual cooperation between the manufacturing and design ends, and integrating vulnerability avoidance strategies throughout the entire chip physical design process. This avoids layout structures that easily cause manufacturing defects from the design stage, thereby reducing the process optimization pressure on the manufacturing end, expanding the process window, and significantly improving the yield of integrated circuit chips in mass production.

[0121] The yield improvement device for the integrated circuit design end in this embodiment is used to implement the aforementioned yield improvement method for the integrated circuit design end. Therefore, the specific implementation of the yield improvement device for the integrated circuit design end can be found in the embodiment section of the yield improvement method for the integrated circuit design end mentioned above. For example, the receiving module 210 and the routing adjustment module 220 are used to implement steps S201 and S202 in the aforementioned yield improvement method for the integrated circuit design end, respectively. Therefore, the specific implementation can be referred to the description of the corresponding embodiments, and will not be repeated here.

[0122] The present invention also provides an integrated circuit yield improvement device, comprising:

[0123] Memory, used to store computer programs;

[0124] A processor is configured to execute the computer program to implement the steps of the aforementioned integrated circuit manufacturing yield improvement method and / or the steps of the aforementioned integrated circuit design yield improvement method. The integrated circuit manufacturing yield improvement method provided by this invention involves collecting full-process manufacturing data during the production process at the integrated circuit manufacturing end and generating a wafer defect map based on the full-process manufacturing data; the integrated circuit manufacturing end extracts graphic features of manufacturing weaknesses based on the wafer defect map to construct a weakness graphic database; the integrated circuit manufacturing end transmits the weakness graphic database to the integrated circuit design end, enabling the integrated circuit design end to adjust routing strategies and graphics during the routing stage of chip physical design based on the weakness graphic database, avoiding the appearance of weakness graphic patterns in the layout that match the graphic features in the weakness graphic database, thus obtaining a routing adjustment layout. This invention constructs a weak point graphical database based on defect data from actual mass production. It fully considers the weak point graphical features of the manufacturing process during the chip design stage, realizing mutual cooperation between the manufacturing and design ends. It integrates weak point avoidance strategies into the entire process of chip physical design, avoiding layout structures that are prone to manufacturing defects from the design stage. This reduces the process optimization pressure on the manufacturing end, expands the process window, and significantly improves the yield of integrated circuit chips in mass production.

[0125] This invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the above-described methods for improving yield at the integrated circuit manufacturing end and / or at the integrated circuit design end. The integrated circuit manufacturing end yield improvement method provided by this invention involves collecting full-process manufacturing data at the integrated circuit manufacturing end and generating a wafer defect map based on the full-process manufacturing data; the integrated circuit manufacturing end extracting graphic features of manufacturing weaknesses based on the wafer defect map to construct a weakness graphic database; the integrated circuit manufacturing end transmitting the weakness graphic database to the integrated circuit design end, enabling the integrated circuit design end to adjust routing strategies and graphics during the routing stage of chip physical design based on the weakness graphic database, avoiding the appearance of weakness graphic patterns in the layout that match the graphic features in the weakness graphic database, and obtaining a routing adjustment layout. This invention constructs a weak point graphical database based on defect data from actual mass production. It fully considers the weak point graphical features of the manufacturing process during the chip design stage, realizing mutual cooperation between the manufacturing and design ends. It integrates weak point avoidance strategies into the entire process of chip physical design, avoiding layout structures that are prone to manufacturing defects from the design stage. This reduces the process optimization pressure on the manufacturing end, expands the process window, and significantly improves the yield of integrated circuit chips in mass production.

[0126] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0127] It should be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0128] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0129] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0130] The above provides a detailed description of a method and apparatus for improving the yield of integrated circuit manufacturing, a method and apparatus for improving the yield of integrated circuit design, and a device for improving the yield of integrated circuits. Specific examples have been used to illustrate the principles and implementation methods of the invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of the invention. It should be noted that those skilled in the art can make various improvements and modifications to the invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the invention.

Claims

1. A method for improving yield in integrated circuit manufacturing, characterized in that, include: The integrated circuit manufacturing end collects manufacturing data throughout the entire production process and generates a wafer defect map based on the manufacturing data. The integrated circuit manufacturing end extracts the graphic features of manufacturing weak points based on the wafer defect map and constructs a weak point graphic database. The integrated circuit manufacturing end transmits the weak point graphic database to the integrated circuit design end, so that the integrated circuit design end can adjust the routing strategy and graphic based on the weak point graphic database during the routing stage of chip physical design, avoid the appearance of weak point graphics in the layout that match the graphic features in the weak point graphic database, and obtain the routing adjusted layout. The full-process manufacturing data includes online inspection data in the wafer manufacturing process, wafer acceptance test (WAT) data, yield statistics, and chip failure analysis data. And / or, the wafer defect map includes the location information of the defects, the corresponding defect type, and the corresponding defect graphic structure information.

2. The method for improving yield in integrated circuit manufacturing as described in claim 1, characterized in that, The graphic features stored in the weak point graphic database include defect type, graphic structure corresponding to the defect, process window influence parameters, adapted process node, lithography process type, and mask attribute information.

3. A method for improving yield in integrated circuit design, characterized in that, The yield improvement method for integrated circuit design corresponds to the yield improvement method for integrated circuit manufacturing according to any one of claims 1 to 2, including: The integrated circuit design end receives a vulnerability graph database from the integrated circuit manufacturing end; Based on the weak point graphic database, the integrated circuit design end performs routing strategy adjustments and graphic adjustments during the routing stage of chip physical design to avoid weak point graphics in the layout that match the graphic features in the weak point graphic database, thus obtaining a routing adjustment layout.

4. The method for improving yield in integrated circuit design as described in claim 3, characterized in that, Based on the vulnerability graph database, the integrated circuit design end adjusts the routing strategy and graph during the routing stage of chip physical design to avoid vulnerability graphs in the layout that match the graph features in the vulnerability graph database, including: During the automatic routing process, the integrated circuit design end periodically acquires the original pattern in the routing front area and the planned routing pattern in the routing front area. The planned wiring diagram is combined with the original diagram to obtain the planned layout diagram; Determine whether the graphic features of the planned layout graphic match the weak point graphic database; When the graphic features of the planned layout graphic match the weak point graphic database, the planned wiring graphic in the wiring forward area is replanned so that the planned wiring graphic bypasses the original graphic; And / or, when the graphic features of the planned layout graphic match the weak point graphic database, redundant wires or programmable fuses are set in the corresponding area of ​​the planned wiring graphic.

5. The method for improving yield in integrated circuit design as described in claim 3, characterized in that, After obtaining the wiring adjustment layout, the following is also included: The integrated circuit design end re-examines the routing adjustment layout based on the weak point graphic database to determine whether there are potential problem graphics in the routing adjustment layout that match the graphic features in the weak point graphic database; When a potential problem graphic appears in the routing adjustment layout that matches the graphic features in the vulnerability graphic database, the potential problem graphic is readjusted so that the graphic features of the readjusted potential problem graphic no longer match the vulnerability graphic database, resulting in a routing re-screening layout.

6. The method for improving yield in integrated circuit design as described in claim 5, characterized in that, The potential problem graphs are readjusted so that their graphical features no longer match the vulnerability graph database, including: Identify the metal bridging weak points and metal necking weak points in the potential problem diagrams; Increase the spacing between the metal bridging weak point graphics and / or reduce the line width of the metal bridging weak point graphics; Reduce the spacing between the metal necking weak point patterns and / or increase the line width of the metal bridging weak point patterns.

7. A yield improvement device for integrated circuit manufacturing, characterized in that, include: The defect collection module is used to enable the integrated circuit manufacturing end to collect full-process manufacturing data during the production process and generate a wafer defect map based on the full-process manufacturing data. The database construction module is used to enable the integrated circuit manufacturing end to extract the graphical features of manufacturing weak points based on the wafer defect map and construct a weak point graphical database. The transmission module is used to enable the integrated circuit manufacturing end to transmit the weak point graphic database to the integrated circuit design end, so that the integrated circuit design end can adjust the routing strategy and graphic based on the weak point graphic database during the routing stage of chip physical design, avoid the appearance of weak point graphics in the layout that match the graphic features in the weak point graphic database, and obtain the routing adjusted layout. The full-process manufacturing data includes online inspection data in the wafer manufacturing process, wafer acceptance test (WAT) data, yield statistics, and chip failure analysis data. And / or, the wafer defect map includes the location information of the defects, the corresponding defect type, and the corresponding defect graphic structure information.

8. A yield improvement device for integrated circuit design, characterized in that, The yield improvement device at the integrated circuit design end corresponds to the yield improvement device at the integrated circuit manufacturing end as described in claim 7, and includes: The receiving module is used to enable the integrated circuit design end to receive a vulnerability graph database from the integrated circuit manufacturing end. The routing adjustment module is used by the integrated circuit design end to adjust the routing strategy and pattern based on the weak point pattern database during the routing stage of chip physical design, so as to avoid the appearance of weak point patterns in the layout that match the pattern features in the weak point pattern database, and obtain the routing adjustment layout.

9. A yield improvement device for integrated circuits, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the integrated circuit manufacturing yield improvement method as described in any one of claims 1 to 2, and / or the steps of the integrated circuit design yield improvement method as described in any one of claims 3 to 6, when executing the computer program.

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