Light emitting diode driving chip, fault detection method and sealing device

Abstract

This application relates to the field of integrated circuit and LED driver technology, and provides a light-emitting diode driver chip, a fault detection method, and a packaging device. The light-emitting diode driver chip includes: at least one signal input terminal, at least one fault detection terminal, at least one switch output terminal, a switch module, and a fault detection module. The first terminal of the fault detection terminal is connected to the anode of the load; the second terminal of the fault detection terminal is connected to the fault detection module through the switch module; the switch output terminal is connected to the cathode of the load; the fault detection module is used to detect the fault state of the driver chip through the fault detection terminal in response to a detection timing signal, and generate a fault flag signal. This driver chip can immediately turn off the corresponding switch when it detects faults such as leakage at the switch output terminal, fault in the circuit where the switch transistor is located, or open / short circuit in the load, thereby preventing abnormal brightness in the display screen with this driver chip and achieving hardware-level protection and fault isolation.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit and LED driver technology, and particularly relates to a light-emitting diode driver chip, a fault detection method and a sealing device. Background Technology

[0002] Currently, leakage, open circuit, short circuit, or switching transistor failure at the output port of traditional LED driver chips can cause abnormal brightness issues in displays (such as "dim brightness" or "constant brightness"). The root causes of such leakage failures are diverse, including but not limited to ESD failure of the chip port electrostatic discharge protection diode, parasitic diode, switching transistor, output transistor failure, defects in the packaging wire bonding process, and poor soldering during the production process.

[0003] Especially in advanced processes that combine traditional LED driver chips with RGB light-emitting chips in a single package (ARGB), the problem of leakage current is even more prominent. Because the single-package process highly integrates the traditional LED driver chip with the LED, any tiny packaging defect can easily create a leakage path internally. However, production process control is limited. Once leakage failure occurs, it often manifests as widespread product malfunctions at the customer's end, which cannot be remedied by conventional methods. Ultimately, the entire batch must be scrapped, resulting in huge economic losses and reduced product cost-effectiveness.

[0004] Traditional LED driver chips lack effective built-in detection and real-time protection mechanisms, making it impossible to promptly identify and isolate faults such as leakage, open circuit, short circuit, or switching tube failure during power-on or operation. This has become a long-standing technical bottleneck for the industry. Summary of the Invention

[0005] This application provides a light-emitting diode driver chip, a fault detection method, and a sealing device, which can solve the problem of abnormal display screen brightness caused by leakage, open circuit, short circuit, or switching transistor failure in existing LED driver chips.

[0006] In a first aspect, embodiments of this application provide a light-emitting diode (LED) driver chip, the LED driver chip comprising:

[0007] It includes at least one signal input terminal, at least one fault detection terminal, at least one switch output terminal, a switch module, and a fault detection module; The first end of the fault detection terminal is connected to the positive end of the load; The second end of the fault detection terminal is connected to the fault detection module through the switch module; The switch output terminal is connected to the cathode end of the load; The fault detection module is used to detect the fault status of the LED driver chip through the fault detection terminal in response to the detection timing signal, and generate a fault flag signal; wherein, the detection timing signal is used to coordinate and control the start-up, execution sequence and timing relationship of multiple fault status detections; the fault detection terminal has the functions of fault status detection and providing power to the load.

[0008] In one possible implementation of the first aspect, the fault detection module includes a leakage current fault detection module and a circuit fault detection module where the switching transistor is located; the switching module includes a first switching transistor, a second switching transistor, and an output transistor module; wherein, The second switching transistor is connected between the fault detection terminal and the power supply to form the main power supply path; The first switching transistor is connected between the fault detection terminal and the leakage fault detection module to form a leakage detection path; The output tube module is connected between the switch output terminal and ground, and is connected in series with the load to form a current loop; The leakage fault detection module is connected to the first switch and the power supply respectively. It is used to collect the analog current signal flowing through the leakage detection path, obtain the first sampled voltage value, compare the first sampled voltage value with the first preset reference voltage value, and generate a leakage fault flag signal that characterizes the leakage fault state of the switch output terminal. The fault detection module for the circuit where the switching transistor is located is connected to the second switching transistor and the fault detection terminal, respectively. It is used to collect the voltage of the fault detection terminal, obtain a second sampled voltage value, and compare the second sampled voltage value with a second preset reference voltage value to generate a fault flag signal for the circuit where the switching transistor is located, which represents the fault status of the circuit where the first switching transistor and the second switching transistor are located.

[0009] In one possible implementation of the first aspect, the leakage fault detection module includes a current detection module and a leakage detection comparison module; wherein, The current detection module is connected between the first switching transistor and the power supply, and is used to convert the analog current signal flowing through the leakage current detection path into the first sampling voltage value. The leakage current detection comparison module is connected to the current detection module and is used to compare the first sampled voltage value output by the current detection module with the first preset reference voltage value to generate the leakage current fault flag signal.

[0010] In one possible implementation of the first aspect, the fault detection module further includes an open-circuit detection comparison module and a short-circuit detection comparison module; wherein, The open circuit detection comparison module is connected between the switch output terminal and the load. It is used to collect the voltage at the switch output terminal, obtain the open circuit sampling voltage value, compare the open circuit sampling voltage value with the preset open circuit reference voltage value, and generate an open circuit fault flag signal that represents the open circuit fault state of the load. The short-circuit detection comparison module is connected between the switch output terminal and the load. It is used to collect the voltage at the switch output terminal, obtain the short-circuit sampled voltage value, compare the short-circuit sampled voltage value with the preset short-circuit reference voltage value, and generate a short-circuit fault flag signal that characterizes the short-circuit fault state of the load.

[0011] In one possible implementation of the first aspect, the LED driver chip further includes a detection result latching module and a logic judgment module; wherein, The detection result latching module is connected to the leakage current detection comparison module, the fault detection module of the circuit where the switch is located, the open circuit detection comparison module, and the short circuit detection comparison module, respectively. It is used to latch the leakage current fault flag signal, the fault flag signal of the circuit where the switch is located, the open circuit fault flag signal, and the short circuit fault flag signal according to their states, to obtain a global fault status signal, and output the global fault status signal to the logic judgment module. The logic judgment module is connected to the detection result latching module, the second switch, and the output module, respectively. It is used to receive the global fault status signal output by the detection result latching module and generate a corresponding execution signal based on the global fault status signal, so as to control the second switch and the output module to be turned on or off according to the execution signal.

[0012] In one possible implementation of the first aspect, the LED driver chip further includes: a parallel-to-serial conversion module and a feedback control logic module; The feedback control logic module is connected to the detection result latching module through the parallel-to-serial conversion module. In response to the readback status command sent through the bidirectional input / output port, it switches the bidirectional input / output port from the input state to the output state and turns on the parallel-to-serial conversion module so that the global fault status signal read from the detection result latching module through the parallel-to-serial conversion module is output to the external controller in serial data form through the bidirectional input / output port.

[0013] Secondly, embodiments of this application provide a fault detection method for a light-emitting diode (LED) driver chip, applied to the LED driver chip described in any of the first aspects above, the method comprising: In response to a detection control command, a detection timing signal is generated; wherein the detection control command is a power-on reset signal or an external fault detection command, and the detection timing signal is used to coordinate and control the start-up, execution sequence and timing relationship of multiple fault state detections; According to the detection timing signal, the corresponding fault state detection is performed to generate a fault flag signal corresponding to the fault state detection; wherein, the fault state detection includes at least one of the following: leakage fault state detection at the switch output terminal, open / short circuit fault state detection at the load, and fault state detection at the circuit where the switch tube is located; Based on the fault flag signal, an execution signal corresponding to the fault flag signal is generated.

[0014] In one possible implementation of the second aspect, the fault indicator signal includes: a leakage fault indicator signal, a fault indicator signal for the circuit where the switching transistor is located, an open circuit fault indicator signal, and a short circuit fault indicator signal; The step of performing corresponding fault state detection based on the detection timing signal and generating a fault flag signal corresponding to the fault state detection includes: When the detection timing signal indicates that the leakage fault state detection at the switch output terminal is valid, the leakage fault state at the switch output terminal is detected by enabling and conducting the first switch transistor, the current detection module, and the leakage detection comparison module, and by enabling and disabling the second switch transistor, the fault detection module of the path where the switch transistor is located, the output transistor module, the open circuit detection comparison module, and the short circuit detection comparison module, thereby obtaining the leakage fault flag signal. When the detection timing signal indicates that the fault status detection of the path where the switch is located is valid, the fault detection module of the path where the switch is located is enabled and turned on, and the first switch, the second switch, the output tube module, the current detection module, the leakage current detection comparison module, the open circuit detection comparison module and the short circuit detection comparison module are turned off, so as to detect the fault status of the path where the first switch and the second switch are located and obtain the fault flag signal of the path where the switch is located. When the detection timing signal indicates that the load open / short circuit fault state detection is valid, the first switch, the fault detection module of the path where the switch is located, the current detection module, the leakage current detection comparison module, and the output tube module are turned off by enabling the second switch. Then, the open circuit detection comparison module and the short circuit detection comparison module are turned on in sequence to detect the open circuit fault state and the short circuit fault state of the load, respectively, and obtain the open circuit fault flag signal and the short circuit fault flag signal.

[0015] In one possible implementation of the second aspect, the execution signal includes a first execution signal and a second execution signal; wherein the first execution signal is used to enable and turn on the second switch and the output transistor module; and the second execution signal is used to enable and turn off the second switch and the output transistor module. When the detection control command is the power-on reset signal, the method includes: If the detection timing signal indicates that the leakage fault status detection at the switch output terminal is valid, the leakage fault status detection at the switch output terminal is executed, and the leakage fault flag signal is generated. If the leakage fault flag signal is valid, the second execution signal is generated, and a response action is performed according to the second execution signal to stop fault detection; If the leakage fault flag signal is invalid, then if the detection timing signal indicates that the fault status detection of the circuit where the switch is located is valid, the fault status detection of the circuit where the switch is located is executed, and the fault flag signal of the circuit where the switch is located is generated. If the fault flag signal of the path where the switch is located is valid, the second execution signal is generated, and a response action is performed according to the second execution signal and the fault detection is stopped; If the fault flag signal of the path where the switch tube is located is invalid, then according to the detection timing signal, the load open-short circuit fault state detection is valid, the load open-short circuit fault state detection is executed, and the short-circuit fault flag signal and the open-circuit fault flag signal are generated. If the short-circuit fault flag signal is valid or the open-circuit fault flag signal is valid, then the second execution signal is generated, and a response action is performed according to the second execution signal and the fault detection is stopped. If both the short-circuit fault indicator signal and the open-circuit fault indicator signal are invalid, the first execution signal is generated, and a response action is performed according to the first execution signal, and the system enters the normal working mode.

[0016] Thirdly, embodiments of this application provide a packaging device for a light-emitting diode driver chip, including a light-emitting diode (LED) driver chip as described in any of the first aspects above, and at least one LED; The LED driver chip and at least one of the LEDs are packaged on a main packaging substrate; The first end of at least one fault detection terminal of the LED driver chip is connected to the anode of at least one LED, the second end of the fault detection terminal is connected to the leakage fault detection module in the LED driver chip, and at least one switch output terminal of the LED driver chip is connected to the cathode of at least one LED; wherein, the fault detection terminal has the functions of fault state detection and providing power to the LED.

[0017] The beneficial effects of the embodiments in this application compared with the prior art are: This application provides a light-emitting diode (LED) driver chip, including: at least one signal input terminal, at least one fault detection terminal, at least one switch output terminal, a switch module, and a fault detection module. The first terminal of the fault detection terminal is connected to the anode of the load. The second terminal of the fault detection terminal is connected to the fault detection module via the switch module. The switch output terminal is connected to the cathode of the load. The fault detection module is used to detect the fault state of the LED driver chip through the fault detection terminal in response to a detection timing signal, and generate a fault flag signal; wherein, the detection timing signal is used to coordinate and control the start-up, execution sequence, and timing relationship of multiple fault state detections; the fault detection terminal has the function of fault state detection and the function of providing power to the load. This LED driver chip has the ability to detect leakage current at the switch output terminal, open / short circuits in the load, and faults in the path of the switching transistor. It can immediately shut down the corresponding switching transistor when a fault occurs in the LED driver chip, avoiding abnormal brightness in the display screen with this LED driver chip, and achieving hardware-level protection and fault isolation. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the application circuit of a traditional LED driver chip in the existing technology; Figure 2 This is a schematic diagram of potential leakage current paths in the application circuits of traditional LED driver chips in existing technologies. Figure 3 This is a schematic diagram of the internal circuit of a light-emitting diode driver chip provided in an embodiment of this application; Figure 4 This is a timing diagram of the on / off state of each switch tube during the fault state detection at the switch output terminal and the fault state detection of the path where the switch tube is located, provided by another embodiment of this application; Figure 5 This is a schematic diagram of the structure of a leakage current detection comparison module and a fault detection module for the circuit where the switching transistor is located, provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of an open-circuit detection comparison module and a short-circuit detection comparison module provided in an embodiment of this application; Figure 7 This is a timing diagram illustrating the on / off state of each switch transistor during load open / short circuit fault detection, provided by an embodiment of this application. Figure 8 This is a schematic diagram of the structure of a detection result latching module and a logic judgment module provided in an embodiment of this application; Figure 9 This is a schematic diagram of the structure of a parallel-to-serial conversion module and a return control logic module provided in an embodiment of this application; Figure 10 This is a flowchart illustrating a fault detection method for a light-emitting diode driver chip according to an embodiment of this application; Figure 11 This is a flowchart illustrating a method for detecting faults in an LED driver chip during power-on reset, provided in one embodiment of this application. Figure 12 This is a circuit diagram of a cascaded driving system for a light-emitting diode driver chip provided in one embodiment of this application; Figure 13 This is a schematic diagram of an RGB sealing device in the prior art; Figure 14 This is a schematic diagram of the structure of a light-emitting diode encapsulation device provided in an embodiment of this application. Detailed Implementation

[0020] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0021] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0022] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0023] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0024] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0025] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0026] In existing technologies, leakage current at the output port of LED driver chips is a core issue that causes abnormal "dim" or "constantly bright" displays. The root causes of this type of leakage failure are diverse, including but not limited to failure of ESD protection devices at the chip port, parasitic diodes, switching transistors, output transistor malfunctions, defects in the packaging wire bonding process, and poor soldering during the manufacturing process.

[0027] Especially in the process of co-packaging chips with LED RGB (ARGB), poor control of the packaging wire bonding process can lead to chip port failure, a long-standing problem for manufacturers. Co-packaging highly integrates the driver chip and the LED chip, making even the smallest packaging defect highly susceptible to creating internal leakage paths. However, production process control is limited. Once leakage failure occurs, it often manifests as a noticeable bright spot at the customer's end, an unrecoverable product malfunction that cannot be fixed by conventional methods, ultimately requiring the entire batch to be scrapped, resulting in significant economic losses and reduced product cost-effectiveness. Figure 1 As shown, Figure 1This is a schematic diagram of the application circuit of a traditional LED driver chip in the existing technology. Figure 1 In this diagram, VDD represents the power supply, DIN represents the data signal input, and IOUT represents the switch output. DIN is connected to the data input of traditional LED driver chip #a, the data output of traditional LED driver chip #a is connected to the data input of traditional LED driver chip #b, the data output of traditional LED driver chip #b is connected to the data input of traditional LED driver chip #c, and so on, forming a chain structure for data transmission. Each traditional LED driver chip has a corresponding LED connected to its switch output (IOUT), and each traditional LED driver chip controls the on / off state, brightness, and color of its connected LED. The driving circuit of this traditional LED driver chip lacks an effective detection and remediation mechanism for the aforementioned leakage current problem, becoming a long-standing technical bottleneck for industry users.

[0028] To more clearly reveal the shortcomings of existing technologies, the following explanation combines the internal structure of traditional LED driver chips, such as... Figure 2 As shown, Figure 2 This diagram illustrates a potential leakage current path in the application circuit of a conventional LED driver chip in existing technology. In a typical application, the anodes of the R, G, and B LEDs are connected to the power supply VDD, while their cathodes are connected to the corresponding output terminals of the conventional LED driver chip. Figure 2 As can be seen from this, there are three main potential leakage current paths, namely: Path 1: After the output tube itself fails, The circuit is as follows: Current starts from the power supply VDD, flows through the LED, and then through the output transistor inside the traditional LED driver chip to ground (GND ground terminal) to form a loop, making the LED exceptionally bright.

[0029] Pathway 2: After the parasitic diode fails, The circuit is as follows: Current starts from the power supply VDD, flows through the LED, and then through the parasitic diode inside the traditional LED driver chip to ground (GND ground terminal), forming a loop, making the LED unusually bright.

[0030] Pathway 3: After other circuit modules fail, The current flows from the power supply VDD, through the LED, and then through other circuit modules inside the traditional LED driver chip to ground (GND), forming a loop, making the LED exceptionally bright.

[0031] If any of the three paths mentioned above experiences a leakage current (e.g., due to parasitic diode failure, output transistor malfunction, or other circuit module failure), an unexpected minute current will be generated after the traditional LED driver chip is powered on. This current is sufficient to drive the LED to produce a visible abnormal brightness phenomenon such as "constantly lit" or "dimmed." For end users, it is acceptable for the LED to be completely off due to a fault, but this uncontrolled abnormal lighting indicates a product quality defect, which is unacceptable. Therefore, the lack of effective built-in port leakage current detection and real-time protection mechanisms in traditional LED driver chips, which cannot promptly identify and isolate leakage current and other faults during power-on or operation, has become a long-standing technical bottleneck in the industry.

[0032] The present application aims to overcome the shortcomings of the prior art and provide a highly integrated LED driver chip and fault detection method with real-time self-diagnosis capability. It constructs a multi-functional circuit architecture with the fault detection terminal (VD) as the core node, enabling the fault detection port to simultaneously perform the dual functions of leakage current detection and power supply to the load. It can effectively detect and lock the abnormal brightness of the LED caused by leakage current, open circuit, short circuit and switching tube failure, and completely cut off the fault path from the hardware to prevent the abnormal lighting of the LED.

[0033] Please see Figure 3 , Figure 3 This is a schematic diagram of the internal circuit of a light-emitting diode (LED) driver chip according to an embodiment of this application. The LED driver chip 100 includes: It includes at least one signal input terminal, at least one fault detection terminal VD, at least one switch output terminal OUT, a switch module, and a fault detection module.

[0034] The first terminal of the fault detection terminal VD is connected to the positive terminal of the load 200.

[0035] The second terminal of the fault detection terminal VD is connected to the fault detection module via a switch module.

[0036] The switch output terminal OUT is connected to the cathode end of the load 200.

[0037] The fault detection module, in response to the detection timing signal, detects the fault state of the LED driver chip 100 through the fault detection terminal VD and generates a fault flag signal. The detection timing signal coordinates and controls the start-up, execution sequence, and timing relationship of multiple fault state detections; the fault detection terminal VD has both fault state detection and power supply functions for the load 200.

[0038] It should be noted that the LED driver chip 100 is an integrated circuit chip used to drive light-emitting diodes (LEDs) to work. It can control and manage the connected load 200 (such as LEDs, resistors, etc.), for example, by providing appropriate current and voltage, and performing fault detection and corresponding processing. The load 200 is an external device connected to the LED driver chip 100. The load 200 can be a single LED, an LED string, or a resistor, etc.

[0039] The LED driver chip 100 includes multiple ports, such as at least one signal input terminal, at least one fault detection terminal VD, and at least one switch output terminal OUT. The signal input terminal is used to receive external input signals and is a crucial port for information exchange between the LED driver chip 100 and the external environment. These input signals can come from a control system or other related circuits and are used to control the operating mode, on / off function, etc., of the LED driver chip 100. The fault detection terminal VD is used to detect the state of the load 200. One end of the fault detection terminal VD (i.e., the first end) is connected to the anode of the load 200, providing voltage to the anode of the driven load 200. Relevant electrical parameter information of the load 200 can be obtained through the fault detection terminal VD. The switch output terminal OUT is used to output current to the load 200. This switch output terminal OUT is connected to the cathode of the load 200, forming an independent and controllable light-emitting branch. The output current is controlled by the OUT switch to drive and control the load 200. For example, if the load 200 is an LED, the brightness of the LED can be adjusted via the OUT switch. Figure 3 As shown, the fault detection terminal VD of the LED driver chip 100 is connected to the positive terminal of the load 200, and the switching output terminal OUT of the LED driver chip 100 is connected to the negative terminal of the load 200, thus forming an independent and controllable light-emitting branch.

[0040] The LED driver chip 100 includes a switching module and a fault detection module, capable of detecting leakage current in the load path, open / short circuits in the load, and internal switching transistor faults. The other end (i.e., the second end) of the fault detection terminal VD is connected to the fault detection module via the switching module. The fault detection module, in response to a detection timing signal, detects the fault state of the LED driver chip 100 through the fault detection terminal VD to obtain a fault flag signal, enabling subsequent corresponding response actions based on the fault flag signal. The switching module is a switching network composed of a first switching transistor, a second switching transistor, and an output switching transistor. The switching transistors can be selected from semiconductor switching devices such as metal-oxide-semiconductor field-effect transistors (MOS transistors, such as P-type MOS transistors used for high-voltage side switching), transistors (such as NPN or PNP bipolar junction transistors), or insulated-gate bipolar transistors (IGBTs).

[0041] The detection timing signal is a signal generated by the LED driver chip 100 after responding to the detection control command. It is used to perform fault state detection on the LED driver chip 100 according to a specific time sequence and logic. This detection timing signal can be used to coordinate and control the start-up, execution sequence, and timing relationship of each fault state detection during the detection process, such as the time sequence of each step, the order of signal transmission and reception, etc., to ensure that the detection work can be carried out accurately and orderly. The detection control command is the instruction for the LED driver chip 100 to perform fault state detection. This instruction can be a specific electrical signal, digital code, or specific control sequence. After receiving the detection control command, the LED driver chip 100 can execute the corresponding fault detection process. In this embodiment, the detection control command can be the power-on reset signal of the driver chip 100. That is, when the driver chip 100 is powered on and reset, the chip is initialized and the fault detection process is automatically performed according to the generated power-on reset signal. This fault detection process includes the entire detection process of leakage fault state detection at the switch output terminal, open / short circuit fault state detection at the load, and fault state detection at the path where the switching transistor is located. The detection control command can also be an external detection command for the driver chip 100, that is, a detection command sent by an external device received by the signal input terminal. The corresponding fault detection process is performed according to the content of the external detection command. In other words, it can be used when it is necessary to actively detect LED driver chip faults. For example, when the content of the external detection command is to detect the leakage fault status of the switch output terminal, the LED driver chip 100 only needs to perform the detection process of the leakage fault status of the switch output terminal.

[0042] The fault flag signal is generated by the LED driver chip 100 after performing fault detection based on the detection timing signal. This signal reflects whether the LED driver chip 100 has a fault and the type of fault. The fault status signal can be high level to indicate normal operation and low level to indicate a fault. The fault type can be leakage fault at the switch output terminal, open / short circuit fault in the load, or fault in the circuit where the switching transistor is located. Executing corresponding response actions based on the fault flag signal refers to a series of operations performed by the LED driver chip 100 based on the generated fault status signal. These response actions are designed to address detected fault conditions to protect the LED driver chip 100 and the load 200, ensuring stable system operation. For example, when an open / short circuit fault in the load is detected, the response action can be to cut off the current output of the power supply switch terminal and the switch output terminal OUT to prevent excessive current from damaging the load 200 or to avoid abnormal brightness of the LED display screen.

[0043] During the fault detection phase, this embodiment can achieve leakage fault detection at the switch output port OUT by using a detection timing signal through internal timing control of the switch module and the fault detection module. When a leakage fault is detected, a fault flag signal is output, immediately shutting off the power supply path corresponding to the switch module, thereby completely cutting off the LED load and effectively preventing uncontrolled phenomena such as constant or dim LED illumination. It should be understood that this embodiment can improve the fault self-diagnosis capability of the LED driver chip, avoid customer application problems, increase product usability, and reduce the risk of product failure caused by port leakage.

[0044] It should be noted that the LED driver chip provided in this embodiment can be applied to application scenarios such as RGB displays, transparent screens, ARGB LED modules, and driver chips in the lighting field, which have high reliability requirements, to avoid problems such as abnormal brightness of the display screen (such as "dim brightness" or "constant brightness").

[0045] It is understood that the LED driver chip provided in this embodiment includes: at least one signal input terminal, at least one fault detection terminal, at least one switch output terminal, a switch module, and a fault detection module. The first terminal of the fault detection terminal is connected to the anode of the load. The second terminal of the fault detection terminal is connected to the fault detection module via the switch module. The switch output terminal is connected to the cathode of the load. The fault detection module is used to detect the fault state of the LED driver chip through the fault detection terminal in response to a detection timing signal, and generate a fault flag signal; wherein, the detection timing signal is used to coordinate and control the start-up, execution sequence, and timing relationship of multiple fault state detections; the fault detection terminal has the function of fault state detection and the function of providing power to the load. This LED driver chip has the ability to detect leakage current at the switch output terminal, open / short circuits in the load, and faults in the path where the switch transistor is located. It can immediately shut down the corresponding switch transistor when the LED driver chip malfunctions, avoiding abnormal brightness in the display screen with this LED driver chip, and achieving hardware-level protection and fault isolation.

[0046] In one possible implementation, the fault detection module includes a leakage fault detection module 10 and a circuit fault detection module 20 where the switching transistor is located. The switching module includes a first switching transistor 1, a second switching transistor 2, and an output transistor module 3.

[0047] The second switch 2 is connected between the fault detection terminal VD and the power supply VDD to form the main power supply path.

[0048] The first switch tube 1 is connected between the fault detection terminal VD and the leakage fault detection module 10 to form a leakage detection path.

[0049] Output module 3 is connected between the switch output terminal OUT and ground GND, and is connected in series with load 200 to form a current loop.

[0050] The leakage fault detection module 10 is connected to the first switch tube 1 and the power supply VDD, respectively. It is used to collect the analog current signal flowing through the leakage detection path, obtain the first sampled voltage value, compare the first sampled voltage value with the first preset reference voltage value, and generate a leakage fault flag signal Leakage_Fault_out that represents the leakage fault state of the switch output terminal.

[0051] The fault detection module 20 for the circuit where the switching transistor is located is connected to the second switching transistor 2 and the fault detection terminal VD respectively. It is used to collect the voltage of the fault detection terminal VD, obtain the second sampled voltage value, and compare the second sampled voltage value with the second preset reference voltage value to generate a fault flag signal SW2_Fen_out for the circuit where the first switching transistor 1 and the second switching transistor 2 are located, representing the fault status of the circuit.

[0052] like Figure 3 As shown, the second switch 2 is located between the fault detection terminal VD and the power supply VDD, forming the main power supply path and controlling the current flow from the power supply VDD to the fault detection terminal VD. When the second switch 2 is turned on, the power supply VDD supplies power to the fault detection terminal VD through the second switch 2, and the main circuit operates; when the second switch 2 is turned off, the power supply VDD is disconnected from the fault detection terminal VD, and the main circuit is de-energized.

[0053] The first switch 1 is located between the fault detection terminal VD and the leakage current fault detection module 10, forming a leakage current detection path and controlling the current flow from the fault detection terminal VD to the leakage current fault detection module 10. When the first switch 1 is turned on, the leakage current detection is allowed. The current flows through the leakage fault detection module 10; when the first switch tube 1 is turned off, the leakage detection path is blocked.

[0054] Output transistor module 3 is located between the switch output terminal OUT and ground GND, forming a current loop with load 200 to control the current flow through load 200. When output transistor module 3 is turned on, load 200 is energized, and the current flowing through load 200 is... When output tube module 3 is disconnected, load 200 is de-energized.

[0055] The leakage fault detection module 10 is connected to the power supply VDD and the first switching transistor 1. When the leakage fault detection module 10 is working, it can generate a leakage fault flag signal Leakage_Fault_out (e.g., a high level indicates leakage, and a low level indicates normal operation). Specifically, the leakage fault detection module 10 can collect the analog current signal flowing through the leakage detection path, convert the analog current signal into a first sampling voltage value, and then compare the first sampling voltage value with a first preset reference voltage value to generate the leakage fault flag signal Leakage_Fault_out (if the first sampling voltage value is higher than the first preset reference value, the leakage fault flag signal Leakage_Fault_out is at a high level).

[0056] The fault detection module 20 for the circuit containing the switching transistor is connected to the second switching transistor 2 and the fault detection terminal VD. It can detect the fault status of the main power supply path formed by the power supply VDD, the second switching transistor 2, and the fault detection terminal VD, and it can also detect the fault status of the first switching transistor 1, thereby generating a fault flag signal SW2_Fen_out for the circuit containing the switching transistor (e.g., high level indicates leakage, low level indicates normal). Specifically, when the enable signal SW2_Fen_EN of the fault detection module 20 for the circuit containing the switching transistor is valid, the fault detection module 20 for the circuit containing the switching transistor operates, can collect the voltage of the fault detection terminal VD to obtain a second sampled voltage value, and then compare the second sampled voltage value with a second preset reference voltage value to generate the fault flag signal SW2_Fen_out for the circuit containing the switching transistor.

[0057] In one possible implementation, the leakage fault detection module 10 includes a current detection module 101 and a leakage detection comparison module 102.

[0058] The current detection module 101 is connected between the first switching transistor 1 and the power supply VDD, and is used to convert the analog current signal flowing through the leakage current detection path into a first sampling voltage value.

[0059] The leakage current detection comparison module 102 is connected to the current detection module 101 and is used to compare the first sampled voltage value output by the current detection module 101 with the first preset reference voltage value to generate a leakage fault flag signal Leakage_Fault_out.

[0060] like Figure 3 As shown, the leakage fault detection module 10 includes a current detection module 101 and a leakage detection comparison module 102. The current detection module 101 is connected in series between the first switching transistor 1 and the power supply VDD, forming a key link in the leakage detection path. When the enable signal SW1_Fen_EN is valid, the current detection module 101 operates, converting the analog current signal flowing through the leakage detection path into a first sampled voltage value. The input terminal of the leakage detection comparison module 102 is connected to the output terminal of the current detection module 101. When the enable signal Leakage_Fault_EN is valid, the leakage detection comparison module 102 operates, receiving the first sampled voltage value output by the current detection module 101, then comparing the first sampled voltage value with a first preset reference voltage value to generate a leakage fault flag signal Leakage_Fault_out, which is output from the output terminal of the leakage detection comparison module 102.

[0061] like Figure 4 As shown, Figure 4This is a timing diagram illustrating the on / off state of each switch transistor during fault state detection at the switch output terminal and fault state detection in the path where the switch transistor is located, provided by an embodiment of this application. Figure 4 In the process of detecting leakage fault status at the switch output terminal, the first switch transistor 1 is turned on (i.e., the enable signal SW1_EN is valid), the second switch transistor 2 is turned off (i.e., the enable signal SW2_EN is invalid), and the output transistor module 3 is turned off (i.e., the enable signal SW3_EN is invalid). Then, the control activates the current detection module 101 and the leakage detection comparison module 102 to sample the current at the switch output terminal OUT to determine whether there is an abnormal leakage current. During the fault detection phase of the circuit where the switching transistor is located, the first switching transistor 1 is turned off, the second switching transistor 2 is turned off, and the output transistor module 3 is turned off. Then, by controlling and activating the fault detection module 20 of the circuit where the switching transistor is located, the voltage at the VD terminal is sampled to obtain the second sampled voltage value, so as to determine whether the main power supply circuit where the second switching transistor 2 is located and the first switching transistor 1 have a fault based on the second sampled voltage value.

[0062] like Figure 5 As shown, Figure 5 This is a schematic diagram of the structure of a leakage current detection comparison module and a fault detection module for the circuit where the switching transistor is located, provided in an embodiment of this application. Figure 5 The specific circuit configuration and working principle of the current detection module 101, the leakage current detection comparison module 102, and the fault detection module 20 for the circuit containing the switching transistor are as follows. The core of this configuration lies in using a comparator and a reference voltage source architecture to digitally determine the sampled signal. Specifically, the leakage current detection comparison module 102 includes a first comparator C1 and a first reference voltage source LV1. Its input receives and samples the abnormal leakage current. Proportional sampling voltage signal That is, the first sampled voltage value. The signal directly reflects the total current flowing through the detection port (VD) and is mainly used to characterize leakage current in detection mode. The non-inverting input of the first comparator C1 receives the processed sampled voltage signal. The first sampled voltage value is connected to the first reference voltage source LV1 (i.e., receiving the first preset reference voltage value). The voltage value of the first reference voltage source LV1 is set to the corresponding threshold voltage (i.e., the first preset reference voltage value). When the module enable signal SW1_Fen_EN of the current detection module 101 is valid, the current detection module 101 starts to work. If the actual leakage current exceeds the allowable value, the first sampled voltage value will exceed the first preset reference voltage value, causing the output state of the first comparator C1 to flip, thereby outputting a valid digital fault signal, i.e., a valid leakage fault flag signal Leakage_Fault_out, indicating that a leakage abnormality has been detected, which is then used for signal filtering to improve anti-interference capability. If no leakage current is collected, the first sampled voltage value is less than the first preset reference voltage value, and the first comparator C1 outputs an invalid digital fault signal, i.e., an invalid leakage fault flag signal Leakage_Fault_out, indicating that the detection is normal.

[0063] Similarly, the fault detection module 20 for the switching transistor's path also includes a second comparator C2 and a second reference voltage source FV1. This fault detection module 20 is primarily used to monitor the voltage at critical nodes, especially the voltage V related to the state of the second switching transistor 2. Fen Its sampling point is set on the circuit where the OUT port is located. Its second comparator C2 will sample the node voltage V. Fen The second sampled voltage value is compared with the threshold value set by the second reference voltage source FV1 (i.e., the second preset reference voltage value). When the enable signal SW2_Fen_EN of the fault detection module 20 for the circuit where the switch is located is valid, the fault detection module 20 for the circuit where the switch is located is activated. If the voltage at the monitored point is abnormal, for example, when the second switch 2 is turned off and the first switch 1 is turned off, there should be no current flowing through them, but there is voltage across the terminals of the second switch 2 and the first switch 1 when they are turned off, indicating that current is forced to flow (i.e., the state of the second switch 2 is abnormal or the state of the first switch 1 is abnormal), causing the second sampled voltage to be lowered. If the value reaches or exceeds the threshold set by FV1 (the second preset reference voltage value), the second comparator C2 will activate and output a valid fault flag signal, namely, the valid fault flag signal SW2_Fen_out for the circuit where the switch is located; if no current flows through the second switch 2 and the first switch 1 when they are turned off, that is, the second switch 2 and the first switch 1 are in normal condition, and the second sampled voltage value is less than the threshold set by FV1 (the second preset reference voltage value), the second comparator C2 will output an invalid fault flag signal, namely, the invalid fault flag signal SW2_Fen_out for the circuit where the switch is located.

[0064] In one possible implementation, the fault detection module further includes an open-circuit detection comparison module 30 and a short-circuit detection comparison module 40.

[0065] The open-circuit detection comparison module 30 is connected between the switch output terminal OUT and the load 200. It is used to collect the voltage of the switch output terminal OUT, obtain the open-circuit sampling voltage value, compare the open-circuit sampling voltage value with the preset open-circuit reference voltage value, and generate an open-circuit fault flag signal Open_Fen_out that represents the open-circuit fault state of the load.

[0066] The short-circuit detection comparison module 40 is connected between the switch output terminal OUT and the load 200. It is used to collect the voltage of the switch output terminal OUT, obtain the short-circuit sampled voltage value, compare the short-circuit sampled voltage value with the preset short-circuit reference voltage value, and generate a short-circuit fault flag signal Short_Fen_out that represents the short-circuit fault state of the load.

[0067] like Figure 6 As shown, Figure 6 This is a schematic diagram of the structure of an open-circuit detection comparison module and a short-circuit detection comparison module provided in an embodiment of this application. Figure 6 In this chip, the open-circuit detection comparison module and the short-circuit detection comparison module are integrated within a single LED driver chip 100. Its architecture uses the detection port (VD) and output port (OUT) as key nodes. Through the collaboration of the internal switching module and multiple dedicated detection modules, it achieves accurate diagnosis of the load path status (open circuit, short circuit). Specifically, when the second switch 2 is turned on, voltage is applied to the fault detection terminal VD through the second switch 2, and the voltage at the switch output terminal OUT is... ,in, This indicates the voltage of the power supply VDD. This indicates the voltage of the second switch transistor 2. This indicates a load voltage of 200. If... Under normal circumstances The voltage drop of the second switch transistor 2 is 0.5V, that is... So, under normal circumstances, If the voltage at the OUT terminal near When this occurs, it indicates that a short circuit fault has occurred in load 200; if the voltage at the OUT terminal... near When this occurs, it indicates that load 200 has an open circuit fault.

[0068] Based on the above principles, it is possible to effectively determine whether an LED is open-circuited or short-circuited by measuring the voltage at the OUT terminal. For example... Figure 7 As shown, Figure 7This is a timing diagram illustrating the on / off state of various switching transistors during load open / short circuit fault detection, provided by an embodiment of this application. Figure 7 As shown, the load open / short circuit fault state detection is triggered by the system power-on reset signal POR. During the detection phase, the first switch 1 and output module 3 are first ensured to be turned off. Simultaneously, the second switch 2 is turned on, thereby connecting the fault detection terminal VD to the internal detection path. The detection phase is further divided into two sub-phases. The first is the open-circuit fault state detection phase. At this time, the control signal Open_Fault_EN of the open-circuit detection comparison module 30 is valid, enabling the open-circuit detection comparison module 30, while Short_Fault_EN is invalid, disabling the short-circuit detection comparison module 40. The open-circuit detection comparison module 30 samples and analyzes the voltage at the OUT port. If the load 200 (such as an LED) is in an open-circuit state, the detection loop cannot be formed, and the voltage at the OUT port will show an abnormally low level. Figure 6 As shown, the open-circuit detection module includes an open-circuit detection comparator C3 and a third reference voltage source OV1. During the period when Open_Fault_EN is active, the open-circuit detection comparator C3 is activated to compare the voltage at the sampling points. The open-circuit sampling voltage value is compared with a preset open-circuit judgment threshold voltage (i.e., the preset open-circuit reference voltage value, OV1 in the figure). When the open-circuit sampling voltage value is lower than the preset open-circuit reference voltage value, the output of the open-circuit detection comparator C3 flips to indicate the open-circuit state. At this time, the open-circuit detection comparison module 30 outputs a valid open-circuit fault flag signal Open_Fen_out.

[0069] After completing the open-circuit fault state detection, the short-circuit fault state detection stage begins. At this time, the control signal Open_Fault_EN of the open-circuit detection comparison module 30 is turned off, and the control signal Short_Fault_EN of the short-circuit detection comparison module 40 is turned on, activating the independent short-circuit detection comparison module 40. Under specific detection conditions, the short-circuit detection comparison module 40 determines whether the load 200 is short-circuited. If the load 200 is short-circuited, the loop impedance is extremely low, and the OUT port voltage will exhibit abnormal characteristics, such as… Figure 6 As shown, the short-circuit detection comparison module 40 includes a short-circuit detection comparator C4 and a fourth reference voltage source SV1. During short-circuit fault state detection, the short-circuit detection comparison module 40 is activated to compare the voltage at the sampling point. The short-circuit sampling voltage value is compared with a preset short-circuit judgment threshold voltage (i.e., the preset short-circuit reference voltage value, SV1 in the figure). When the short-circuit sampling voltage value is higher than the preset short-circuit reference voltage value, the output of the short-circuit detection comparator C4 flips to indicate the short-circuit state. At this time, the short-circuit detection comparison module 40 outputs a valid short-circuit fault flag signal Short_Fen_out.

[0070] It should be understood that the embodiments of this application construct a multi-dimensional, high-precision fault perception network by additionally designing independent open-circuit detection comparison modules and short-circuit detection comparison modules, and combining them with leakage fault detection modules for switch port leakage and circuit fault detection modules for the switch transistor. Through carefully designed pure hardware decision and protection logic, fast, reliable, and adaptive isolation and protection against various faults are achieved, significantly improving the robustness and reliability of the LED driver system.

[0071] In one possible implementation, the LED driver chip 100 also includes a detection result latching module 50 and a logic judgment module.

[0072] The detection result latching module 50 is connected to the leakage current detection comparison module 102, the fault detection module 20 for the circuit where the switch is located, the open circuit detection comparison module 30, and the short circuit detection comparison module 40, respectively. It is used to latch the leakage current fault flag signal Leakage_Fault_out, the fault flag signal SW2_Fen_out for the circuit where the switch is located, the open circuit fault flag signal Open_Fen_out, and the short circuit fault flag signal Short_Fen_out according to their status, to obtain a global fault status signal, and then output the global fault status signal to the logic judgment module.

[0073] The logic judgment module is connected to the detection result latch module 50, the second switch 2, and the output module 3 respectively. It is used to receive the global fault status signal output by the detection result latch module 50 and generate the corresponding execution signal according to the global fault status signal, so as to control the second switch 2 and the output module 3 to be turned on or off according to the execution signal.

[0074] like Figure 8 As shown, Figure 8 This is a schematic diagram of the structure of a detection result latching module and a logic judgment module provided in an embodiment of this application. Figure 8 In this application, the embodiment focuses on the most critical result retention and execution link in the fault detection system. Its core is that it includes a detection result latching module 50 and a logic judgment module for controlling the hardware. It can ensure that any identified fault flag signal can be reliably memorized and immediately converted into a shutdown command for the switching transistor, thereby achieving deterministic hardware-level protection.

[0075] The detection result latching module 50 serves as the decision and memory center for the entire fault detection system. It receives real-time fault flag signals from various front-end detection modules (leakage detection comparison module 102, switch-path fault detection module 20, open-circuit detection comparison module 30, and short-circuit detection comparison module 40). Specifically, these input signals include: the leakage fault flag signal Leakage_Fault_out generated by the leakage detection comparison module 102; the switch-path fault flag signal SW2_Fen_out, which may be generated by the switch-path fault detection module 20 after processing; and the open-circuit fault flag signals Open_Fen_out and Short-circuit fault flag signals Short_Fen_out, respectively generated by the independent open-circuit detection comparison module 30 and short-circuit detection comparison module 40. When these flag signals are valid under the control of the detection timing, they indicate the occurrence of the corresponding type of fault.

[0076] The core function of the detection result latch module 50 is that when any fault flag signal is valid, its corresponding internal latch (such as a D flip-flop or SR latch) is triggered, capturing and locking the fault state. Figure 8 As shown, after latching, the detection result latching module 50 can output a stable global fault status signal, including Leakage, SW2_Fen (fault of the second switch 2), Open, and Short. This latching mechanism is crucial, as it ensures that brief fault pulses can be persistently recorded, avoiding protection failures due to signal jitter, and providing stable status information for system queries.

[0077] The output of the detection result latch module 50 does not directly drive high-power devices, but is instead sent to the subsequent logic judgment module (i.e., hardware combinational logic circuit) to generate the final execution signal. The logic judgment module includes NOR gates, OR gates, and AND gates. For example... Figure 8 As shown, the latched global fault status signals (including Leakage, SW2_Fem, Open, Short, etc.) are sent to a NOR gate logic. The logic function of this NOR gate logic is: as long as any one of the input signals is high (i.e., any type of fault is latched), the output of the NOR gate logic becomes low. At this time, this low-level signal represents "comprehensive fault exists," which is the root cause of triggering the system protection action. This "comprehensive fault" signal is simultaneously fed to the control path of the second switch 2 and the output module 3 to achieve coordinated protection.

[0078] Specifically, the control of the second switch transistor 2: such as Figure 8As shown, the generation logic of the enable signal SW2_EN for the second switch 2 integrates a fault signal output by a NOR gate logic. Under normal circumstances, the enable signal SW2_EN for the second switch 2 is controlled by the upstream circuit and is used to power on the second switch 2. Once the NOR gate logic where the fault signal is located outputs a low-level fault signal, this low-level fault signal will force the enable signal SW2_EN for the second switch 2 to an invalid level through an AND gate logic &, thereby commanding the second switch 2 to unconditionally turn off, that is, immediately cutting off the main power supply to the fault detection terminal VD.

[0079] Control of output tube module 3: such as Figure 8 As shown, the fault signal output by the NOR gate also affects the control logic of output transistor module 3. Under normal circumstances, the enable signal SW3_EN of output transistor module 3 is controlled by the upstream circuit. It, together with the load pulse width modulation signal PWM signal, controls output transistor module 3. Once the NOR gate outputs a low-level fault signal, this low-level fault signal will force the signal output by the OR gate composed of the enable signal SW3_EN of output transistor module 3 and the PWM signal to an invalid level through the AND gate &. That is, when the fault signal output by the NOR gate is valid, it will immediately invalidate the corresponding input of the AND gate &, causing the enable signal SW3_EN of output transistor module 3 and the PWM signal to be disabled, thereby turning off output transistor module 3 and achieving output isolation.

[0080] Through the above mechanism, as long as any of the following faults—leakage, fault in the circuit where the switching transistor is located, open circuit, or short circuit—is detected and latched, the system will immediately and synchronously shut down the second switching transistor 2 and the output transistor module 3. This action completely cuts off the power supply and return current of the faulty load 200, achieving complete electrical isolation. Since all logic is implemented by hardware circuits, the delay from fault identification to switching transistor shutdown will be very short, the response speed is extremely fast, and it does not depend on the execution of software programs. This protection state will be maintained until the fault memory in the detection result latching module 50 is cleared.

[0081] It should be understood that the embodiments of this application achieve reliable memory of fault states through a detection result latching module, and construct a robust, automatically executed protection barrier through subsequent logic judgment modules controlling the path. This ensures that the LED driver chip provided in the embodiments of this application has the ability to autonomously, quickly, and unavoidably enter a safe state when facing various potential faults, greatly improving the overall reliability of the system.

[0082] In one possible implementation, the LED driver chip 100 further includes: a parallel-to-serial conversion module 70 and a feedback control logic module 80.

[0083] The feedback control logic module 80 is connected to the detection result latch module 50 via the parallel-to-serial conversion module 70. In response to the readback status command sent through the bidirectional input / output port DATA, the bidirectional input / output port DATA is switched from the input state to the output state, and the parallel-to-serial conversion module 70 is turned on. This allows the global fault status signal read from the detection result latch module 50 through the parallel-to-serial conversion module 70 to be output to the external controller in serial data form via the bidirectional input / output port DATA.

[0084] like Figure 9 As shown, Figure 9 This is a schematic diagram illustrating the structure of a parallel-to-serial conversion module and a feedback control logic module according to an embodiment of this application. In this embodiment, the LED driver chip 100 also has a function of reading back fault status. Figure 9 In this context, DATA stands for Bidirectional Input / Output Port. The Bidirectional Input / Output Port DATA is a communication port with both input and output functions. The operating state of the Bidirectional Input / Output Port DATA is managed by the feedback control logic module. Specifically, under default conditions or when receiving input commands, the port is configured as an input; when it needs to report status to an external controller, it can be dynamically switched to an output state to drive the bus. The parallel-to-serial converter 70 can convert the parallel global fault status signal (such as a 4-bit binary code) output by the detection result latching module 50 into a serial data stream, which is then output to an external controller (such as an MCU) through the Bidirectional Input / Output Port DATA. The feedback control logic module 80 can respond to the external controller's read-back status command, dynamically switching the port direction of the Bidirectional Input / Output Port DATA (i.e., from input to output state), and controlling the start and stop of the parallel-to-serial converter 70 to achieve serial feedback of the global fault status signal.

[0085] Specifically, after sending a readback status command through the bidirectional input / output port DATA, the signal processing of the feedback control logic module 80 first changes the input state of the bidirectional input / output port DATA from input to output. Then, the parallel-to-serial conversion module 70 is activated, and the fault data, such as the global fault status signal read from the detection result latch module 50, is converted into serial data by the parallel-to-serial conversion module 70 and output to the bidirectional input / output port DATA. The serial data is then returned to the external controller through the bidirectional input / output port DATA. Figure 9 In this context, the OSC is the internal data oscillator that provides the digital unit.

[0086] It should be understood that by utilizing the bidirectional input / output communication port, the function of reliably reading back the internal diagnostic status of the chip under the trigger of external commands is realized, providing a solid foundation for system-level fault monitoring and maintenance.

[0087] In one possible implementation, the LED driver chip 100 further includes a cascaded communication interface (not shown in the figure).

[0088] The LED driver chip 100 is connected to at least one upstream LED driver chip or at least one downstream LED driver chip through a cascaded communication interface, so that the LED driver chip can receive control data and forward the control data to the downstream LED driver chip through the cascaded communication interface, send the fault status signal of the LED driver chip to the upstream LED driver chip or an external controller, and receive and forward the fault status signal of the downstream LED driver chip.

[0089] In some examples, the LED driver chip 100 has a cascade communication interface, which enables data interaction with other chips. The cascade communication interface is the interface in the LED driver chip 100 used for data communication with other LED driver chips. This interface supports cascading connections between chips, allowing multiple chips to be connected in series to form a long-chain communication network. The upstream LED driver chip is the chip located upstream of the current LED driver chip 100 in the cascade communication network. The downstream LED driver chip is the chip located downstream of the current LED driver chip 100 in the cascade communication network. The external controller is the control center of the entire cascade communication network system, responsible for generating and sending control data to achieve control functions for each LED in the system.

[0090] Through this cascaded communication interface, the current LED driver chip can receive control data from the upstream LED driver chip, forward it to the downstream LED driver chip, and simultaneously send its own fault status signal to the upstream LED driver chip or external controller. It also receives and forwards fault status signals reported by the downstream LED driver chip. Upon receiving the fault status signal, the external controller displays the fault location and type on the monitoring interface, can send control commands to shut down the LED driver chips in the faulty area to prevent the fault from escalating, and simultaneously notify maintenance personnel for repair.

[0091] Please see Figure 10 , Figure 10 This is a flowchart illustrating a fault detection method for a light-emitting diode (LED) driver chip according to an embodiment of this application. The method can be applied to the LED driver chip described in the first aspect above, and includes: S11. In response to the detection control command, generate a detection timing signal; wherein, the detection control command is a power-on reset signal or an external fault detection command, and the detection timing signal is used to coordinate and control the start-up, execution sequence and timing relationship of multiple fault state detections.

[0092] S12. Perform corresponding fault state detection according to the detection timing signal and generate a fault flag signal corresponding to the fault state detection; wherein, the fault state detection includes at least one of the following: leakage fault state detection at the switch output terminal, open / short circuit fault state detection at the load, and fault state detection at the circuit where the switch tube is located.

[0093] S13. Generate an execution signal corresponding to the fault flag signal based on the fault flag signal.

[0094] It should be noted that the detection control command is the command used by the LED driver chip to detect fault conditions. The power-on reset signal is a signal automatically generated by the system when the LED driver chip is powered on. This signal is used to restore the chip's internal registers, logic circuits, etc., to their initial default states, and simultaneously triggers the fault detection process to ensure the chip is in normal working condition after power-on. The external fault detection command is a command sent to the LED driver chip by an external controller (such as a microcontroller, detection equipment, etc.) to initiate the fault detection process. When the external controller detects signs of potential faults in the LED driver chip or needs to troubleshoot the LED driver chip, the external controller can send this external fault detection command, requiring the LED driver chip to execute the corresponding fault detection process.

[0095] Upon receiving a detection control command, a detection timing signal can be generated based on that command. This timing signal is used to coordinate and control multiple fault state detection processes. It may include the start time, execution order, and time intervals between each fault detection item. Through proper timing arrangement, the fault detection process can be ensured to proceed in an orderly and efficient manner, avoiding interference between different detection items and improving the accuracy and reliability of the detection.

[0096] Then, corresponding fault state detection can be performed according to the detection timing signal, such as switch output leakage fault state detection, load open / short circuit fault state detection, and fault state detection of the circuit where the switching transistor is located, thereby generating a fault flag signal corresponding to the fault state detection. When the detection control command is a power-on reset signal, the system automatically executes the following types of fault state detection sequentially according to the timing sequence: switch output leakage fault state detection, switching transistor circuit fault state detection, and load open / short circuit fault state detection, thereby generating the final fault flag signal. When the detection control command is an external detection command, the system will execute the corresponding fault state detection process according to the fault detection type indicated in the external detection command. The fault flag signal is a signal generated by the LED driver chip after performing fault state detection, used to indicate the detected fault state information. The fault state signal can be a simple binary signal, such as a high level indicating a fault and a low level indicating no fault.

[0097] The switch output leakage fault detection process checks for leakage faults at the switch output of the LED driver chip. Leakage can increase the power consumption of the LED driver chip and cause unstable output current, potentially affecting the normal operation of the connected load. During the switch output leakage fault detection process, the output status signal is a leakage fault flag signal.

[0098] The fault status detection of the switching transistor's path involves checking the main power supply path of the second switching transistor and the pins of the first switching transistor in the LED driver chip to determine if there are faults such as poor contact or disconnection. The normal operation of the second switching transistor is crucial for the stable power supply of the LED driver chip; pin faults can affect the power supply to the LED driver chip, causing it to malfunction. During the execution of the fault status detection process, the output status signal is a fault flag signal for the switching transistor's path.

[0099] Load open / short circuit fault detection checks whether the load connected to the output of the LED driver chip is open or short-circuited. When the load is an LED, an open circuit may cause the LED to not light up, while a short circuit may cause excessive output current from the LED driver chip, damaging the LED driver chip or the LED. During the short-circuit fault detection step in the load open / short circuit fault detection process, the output status signal is a short-circuit fault flag signal; during the open-circuit fault detection step in the load open / short circuit fault detection process, the obtained status signal is an open-circuit fault flag signal.

[0100] Finally, an execution signal corresponding to the fault flag signal can be generated based on the fault flag signal. The execution signal, generated according to the fault state, is used to trigger the corresponding action. For example, when any fault is detected—such as leakage at the switch output, fault in the second switch transistor, short circuit in the load, or open circuit in the load—the execution signal can control the LED driver chip to take protective measures, such as shutting down the second switch transistor and the output transistor module. It should be understood that by generating execution signals to take corresponding protective measures, further escalation of the fault is prevented, the safety of the driver chip and the load is protected, and the stability of the entire system is improved.

[0101] It is understood that the fault detection method for a light-emitting diode (LED) driver chip provided in this application includes: First, generating a detection timing signal in response to a detection control command; wherein the detection control command is a power-on reset signal or an external fault detection command, and the detection timing signal is used to coordinate and control the start-up, execution sequence, and timing relationship of multiple fault state detections. Then, executing the corresponding fault state detection according to the detection timing signal, and generating a fault flag signal corresponding to the fault state detection; wherein the fault state detection includes at least one of the following: leakage fault state detection at the switch output terminal, open / short circuit fault state detection at the load, and fault state detection at the path where the switching transistor is located. Finally, generating an execution signal corresponding to the fault flag signal according to the fault flag signal. This method can be applied to LED driver chips capable of detecting leakage at the switch output terminal, open / short circuit at the load, and faults at the path where the switching transistor is located. This method allows for the immediate shutdown of the corresponding switching transistor when any of the above faults occur in the LED driver chip, preventing abnormal brightness in displays with this LED driver chip, achieving hardware-level protection and fault isolation, and improving the stability of the display screen.

[0102] In one possible implementation, the fault indication signals include: leakage fault indication signal, fault indication signal of the circuit where the switching transistor is located, open circuit fault indication signal, and short circuit fault indication signal.

[0103] Based on the detection timing signal, perform corresponding fault state detection and generate a fault flag signal corresponding to the fault state detection, including: When the detection timing signal indicates that the leakage fault status detection at the switch output terminal is valid, the leakage fault status at the switch output terminal is detected by enabling and conducting the first switch transistor, the current detection module, and the leakage detection comparison module, and by enabling and disabling the second switch transistor, the fault detection module of the path where the switch transistor is located, the output transistor module, the open circuit detection comparison module, and the short circuit detection comparison module, thereby obtaining the leakage fault flag signal.

[0104] When the timing signal indicates that the fault status of the path where the switching transistor is located is valid, the fault status of the path where the switching transistor is located is detected by enabling the fault detection module of the path where the switching transistor is located and enabling and disabling the first switching transistor, the second switching transistor, the output transistor module, the current detection module, the leakage current detection comparison module, the open circuit detection comparison module, and the short circuit detection comparison module, thereby obtaining the fault flag signal of the path where the switching transistor is located.

[0105] When the timing signal indicates that the load open-circuit fault state detection is valid, the second switch is enabled and turned on, and the first switch, the fault detection module of the path where the switch is located, the current detection module, the leakage current detection comparison module, and the output tube module are turned off. Then, the open-circuit detection comparison module and the short-circuit detection comparison module are enabled and turned on in sequence to detect the open-circuit fault state and the short-circuit fault state of the load respectively, and obtain the open-circuit fault flag signal and the short-circuit fault flag signal.

[0106] The detection timing signals may include signals to initiate the detection process for leakage current at the switch output, the detection process for fault conditions in the circuit containing the switch transistor, and the detection process for open / short circuit fault conditions in the load. When the detection timing signal is valid (e.g., high level), the corresponding detection process can proceed according to the predetermined procedure; when the detection timing signal is invalid (e.g., low level), the corresponding detection process is paused or prohibited. Based on the detection timing signals, the corresponding fault condition can be detected by the corresponding detection module, obtaining a fault flag signal corresponding to the fault condition detection. The fault flag signal can reflect information such as whether the LED driver chip has a fault and the type of fault.

[0107] Specifically, when the detection timing signal indicates that the leakage fault state detection at the switch output terminal is valid, the first switch, the current detection module, and the leakage detection comparison module are enabled and turned on, while the second switch, the fault detection module of the path where the switch is located, the output module, the open circuit detection comparison module, and the short circuit detection comparison module are enabled and turned off. The abnormal leakage current flowing through the switch output terminal is collected through the current detection module and the leakage detection comparison module, and the leakage fault state detection is started, thereby obtaining a leakage fault flag signal that characterizes the leakage situation at the switch output terminal.

[0108] When the timing signal indicates that the fault status detection of the path where the switching transistor is located is valid, the fault detection module of the path where the switching transistor is located is enabled and turned on, and the first switching transistor, the second switching transistor, the output transistor module, the current detection module, the leakage current detection comparison module, the open circuit detection comparison module, and the short circuit detection comparison module are enabled and turned off. The fault status of the path where the first switching transistor and the second switching transistor are located is detected by the fault detection module of the path where the switching transistor is located, thereby obtaining the fault flag signal of the path where the first switching transistor and the second switching transistor are located.

[0109] When the timing signal indicates that the load open / short circuit fault state detection is valid, the second switch is enabled and turned on, while the first switch, the fault detection module of the path where the switch is located, the current detection module, the leakage current detection comparison module, and the output module are enabled and turned off. Then, the open circuit detection comparison module and the short circuit detection comparison module are enabled and turned on in sequence. The open circuit detection comparison module and the short circuit detection comparison module detect the open circuit fault state and the short circuit fault state of the load, respectively, thereby obtaining the open circuit fault flag signal representing the load open circuit condition and the short circuit fault flag signal representing the load short circuit condition.

[0110] It should be understood that by logically representing the detection signal as a fault flag signal in the embodiments of this application, the fault information of the LED driver chip can be conveyed to other system modules (such as logic judgment modules) or external devices, so that other system modules or controllers can promptly detect the fault of the chip and perform response actions on the LED driver chip, which also helps to quickly locate and repair the fault.

[0111] It should be understood that the embodiments of this application can detect leakage at the switch output terminal, short circuit of the load, open circuit of the load, and fault in the path where the switch tube is located, so as to detect faults in a timely manner, ensure the stability and reliability of the LED driver chip, and also help to quickly locate and repair faults.

[0112] In one possible implementation, the execution signal includes a first execution signal and a second execution signal; wherein the first execution signal is used to enable and turn on the second switching transistor and the output transistor module; and the second execution signal is used to enable and turn off the second switching transistor and the output transistor module.

[0113] The execution signals control the operating state of relevant circuit components (such as the second switch and output transistor module). Different execution signals are generated based on different operating states to perform corresponding operations on the circuit, ensuring circuit safety or restoring normal operation. The first execution signal is generated by the logic judgment module when all fault indicator signals (leakage, short circuit, open circuit, and fault in the switch's path) are invalid, meaning the fault state detection of the LED driver chip is normal. This first execution signal enables the second switch and output transistor module to conduct, thus entering a valid operating state. The second execution signal is generated by the logic judgment module when any one of the leakage, short circuit, open circuit, or switch path fault indicator signals is valid, meaning a fault is detected in the LED driver chip. This second execution signal enables the second switch and output transistor module to turn off, thus entering an invalid operating state.

[0114] like Figure 11 As shown, Figure 11This is a flowchart illustrating a fault detection method for an LED driver chip during power-on reset, provided in one embodiment of this application. When the detection control command is a power-on reset signal, the method includes: If the detection timing signal indicates that the leakage fault status detection at the switch output terminal is valid, the leakage fault status detection at the switch output terminal is executed, and a leakage fault flag signal is generated.

[0115] If the leakage fault indicator signal is valid, a second execution signal is generated, and a response action is performed according to the second execution signal to stop fault detection.

[0116] If the leakage fault flag signal is invalid, then the fault status detection of the circuit where the switch is located is valid according to the detection timing signal, and the fault status detection of the circuit where the switch is located is executed, and the fault flag signal of the circuit where the switch is located is generated.

[0117] If the fault flag signal of the circuit where the switching transistor is located is valid, a second execution signal is generated, and a response action is performed according to the second execution signal to stop fault detection.

[0118] If the fault flag signal of the circuit where the switching transistor is located is invalid, then the load open-short circuit fault state detection is performed according to the detection timing signal as valid, and the short-circuit fault flag signal and the open-circuit fault flag signal are generated.

[0119] If the short-circuit fault flag signal is valid or the open-circuit fault flag signal is valid, a second execution signal is generated, and a response action is performed according to the second execution signal to stop fault detection.

[0120] If both the short-circuit fault indicator signal and the open-circuit fault indicator signal are invalid, a first execution signal is generated, and a response action is performed according to the first execution signal, and the system enters the normal operating mode.

[0121] like Figure 11 As shown, after the system powers on and resets, the fault status of the LED driver chip is detected. Only after the fault detection is completed will the LED driver chip enter normal operating mode. For LED driver chips that are found to be faulty, the output will be turned off, and the LED driver chip will re-enter the detection mode after power is restored.

[0122] The specific control process is as follows: After the system is powered on and reset, the power-on self-test process is executed sequentially. First, in the leakage fault detection stage at the switch output, the first switch is turned on, the second switch is turned off, and the output module is turned off. The current detection module and leakage detection comparison module are activated to determine if there is a leakage fault at the switch output. If leakage is detected, the leakage fault flag signal is latched, and the second switch and output module are turned off. If there is no leakage, the system enters the fault detection stage for the circuit containing the switch. In this stage, the first switch, the second switch, and the output module are turned off, and the fault detection module for the circuit containing the switch is activated to determine if there is a fault in the circuit containing the first and second switches. If a fault is detected, the fault flag signal for the circuit containing the switch is latched, and the second switch and output module remain off. If the second LED is detected normally, the system enters the load open / short circuit fault detection stage. During this stage, the first and output transistor modules are turned off, the second switch is turned on, and the open-circuit and short-circuit detection comparison modules are sequentially activated to detect open-circuit or short-circuit faults in the load. If an open-circuit or short-circuit fault is detected, the corresponding open-circuit or short-circuit fault flag signal is latched, and the second switch and output transistor modules are turned off. If no open or short circuit is detected in the load, it indicates that all self-test stages of the LED driver chip have passed, and the LED driver chip enters normal operating mode. The second switch and output transistor modules are activated, and then the PWM signal is used to control the on / off state of the load LED.

[0123] When any of the following fault conditions are detected—leakage, fault in the path of the switching transistor, open circuit, or short circuit—the second switching transistor and output transistor module will be turned off, cutting off the power supply to the faulty channel to achieve hardware isolation, and fault detection will stop to await reset or fault reporting. During this time, other control functions of the LED driver chip (such as data forwarding) will continue to operate normally.

[0124] It should be noted that, in another example, the fault status detection process of the LED driver chip can also be triggered by external control commands. The system receives specific command codes through communication interfaces such as single-wire protocol and I2C, activates the corresponding internal detection circuits, and the subsequent detection process (such as turning on the switching transistor, voltage sampling, voltage comparison, result latching, etc.) is exactly the same as the self-test mode performed by the LED driver chip after power-on. This mode allows detection to be initiated at any time during system operation, enhancing the flexibility and intelligence of system maintenance.

[0125] It is understood that the embodiments of this application, through the closed-loop control mechanism of "detection-judgment-latch-protection", realize accurate and rapid response to the driving circuit failure of the LED driver chip, fundamentally solve the problem of abnormal bright spots in the LED display screen during the application of LED display screen, and significantly improve the reliability of the system and the product yield.

[0126] It should be noted that the LED driver chip provided in this application embodiment is particularly suitable for the co-packaging (ARGB) application of LED driver chips and multiple LEDs. In the co-packaging device, the LED driver chip is provided with an independent detection power supply pin (VD), which is interconnected with the anode of all LEDs in the package. This allows for unified detection of leakage current in all LED paths within the package through a centralized monitoring point, effectively solving the unique internal micro-leakage problem in the co-packaging process.

[0127] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0128] Please see Figure 12 , Figure 12 This is a schematic diagram of a cascaded driving system for LED driver chips provided in an embodiment of this application. The cascaded driving system 300 for LED driver chips includes at least two LED driver chips 100 as described in any of the first aspects above.

[0129] In this configuration, every two LED driver chips 100 communicate in a cascaded manner via a cascaded communication interface; each LED driver chip 100 executes the LED driver chip fault detection method as described in any of the second aspects above.

[0130] Figure 12 This paper illustrates a cascaded driving system 300 for LED driver chips, which includes the LED driver chip 100 provided in this embodiment. The system architecture of the cascaded driving system 300 is as follows: multiple LED driver chips 100 with identical structures (labeled #1, #2…#N) communicate in a cascaded manner via a serial data signal line (DIN), are powered by a unified power supply (VDD), and are connected to each other through a cascaded communication interface. Each LED driver chip 100 has an independent fault detection terminal VD, which is connected to the anode of its respective driven LED load to provide voltage to the anode of the driven LED load. The switching output terminal OUT of each LED driver chip is connected to the cathode of its respective driven LED load, thereby forming multiple independently controllable light-emitting branches.

[0131] Understandably, this embodiment integrates multiple detection functions into a single LED driver chip with high density, and simplifies system connections through a well-defined fault detection pin (VD pin). In the cascaded drive system, each LED driver chip acts as an independent node with complete self-diagnostic and protection capabilities, collectively constructing a highly reliable and easy-to-maintain distributed LED driver network. This cascaded drive system of LED driver chips can meet the needs of large-scale LED applications, ensuring stable and reliable operation of LEDs under various working conditions, and enabling timely handling of faults, thereby improving the performance and quality of the entire LED lighting or display system.

[0132] It should be noted that the information interaction and execution process between the modules in the cascaded drive system of the aforementioned LED driver chip are based on the same concept as the method embodiment of this application. For details on their specific functions and technical effects, please refer to the method embodiment section, which will not be repeated here.

[0133] like Figure 13 As shown, Figure 13 This is a schematic diagram of an existing RGB co-packaging device. In a traditional co-packaging device, the LED driver chip and the R2, G2, and B2 tri-color LEDs are packaged on a main package substrate. DOUT1 represents the data output pad of the LED driver chip, VDD1 represents the power pad of the LED driver chip, DIN1 represents the data input pad of the LED driver chip, GND1 represents the ground pad of the LED driver chip, R1, G1, and B1 represent the corresponding light-emitting drive output pads of the LED driver chip, DOUT2 represents the data output pin of the main package substrate, VDD2 represents the power pin of the main package substrate, DIN1 represents the data input pin of the main package substrate, GND1 represents the ground pin of the main package substrate, and R2, G2, and B2 represent the red, green, and blue tri-color LEDs, respectively. The anodes of the R2, G2, and B2 tri-color LEDs are usually connected to the VDD2 pin, while the cathodes are connected to the corresponding light-emitting drive output pads R1, G1, and B1 of the LED driver chip, respectively. This architecture has significant drawbacks: First, its internal interconnect structure is relatively fixed, lacking flexibility; second, it lacks effective detection methods for potential failures within the encapsulated assembly (such as short circuits in gold wires, poor chip bonding, and micro-leakage caused by interface contamination). Once a defect exists in the packaging process, it will only manifest as abnormal LED lighting during final product testing or customer use, at which point it is irreparable, leading to the scrapping of the entire module and incurring high costs.

[0134] Please see Figure 14 , Figure 14 This is a schematic diagram of a light-emitting diode (LED) encapsulation device provided in an embodiment of this application. The LED driver chip encapsulation device includes the LED driver chip of any of the first aspects described above, and at least one LED; The LED driver chip and at least one LED are packaged on the main packaging substrate.

[0135] The first terminal of at least one fault detection terminal of the LED driver chip is connected to the anode terminal of at least one LED, the second terminal of the fault detection terminal is connected to the leakage fault detection module in the LED driver chip, and at least one switch output terminal of the LED driver chip is connected to the cathode terminal of at least one LED. The fault detection terminal has both fault state detection function and the function of providing power to the LED.

[0136] Specifically, this LED encapsulation device integrates the aforementioned LED driver chip with fault detection and power supply control functions, making it suitable for integrated, high-reliability packaging of RGB LEDs. The LED driver chip incorporates a fault detection terminal VD, which performs both fault status detection and LED power supply functions.

[0137] exist Figure 14 In this process, the LED driver chip and three LED chips (R2, G2, and B2) are packaged together in a package. The package is a transparent resin and includes the LED driver chip, LED, main package substrate, and external pins, forming an independent and controllable LED driver product.

[0138] The LED driver chip and multiple LEDs are packaged on the same main packaging substrate. The main packaging substrate provides a stable physical mounting platform for the LED driver chip 100 and multiple loads 200, enabling electrical connections between the LED driver chip and the multiple loads. It also ensures the fixed position of each chip within the device, preventing movement or collisions during transportation, installation, or use, thus protecting the chips from mechanical damage. Standard power supply pins (such as power supply pin VDD2 and ground pin GND2) and communication pins (such as data input pin DIN2 and data output pin DOUT2) are provided on the edge of the main packaging substrate for connecting to external systems, obtaining the necessary power and control signals, and feeding back the load's operating status information to the external system. The LED driver chip includes at least one detection pin VD1.

[0139] Key features of this encapsulated structure include: 1) Shared anode and detection power supply: The fault detection terminal VD of the LED driver chip (VD can be considered as the external contact point of the VD voltage generated by the internal fault detection terminal) is connected to the anode (P-pole) of all LEDs in the package via wire bonding inside the package. The fault detection terminal VD is a common port for all LEDs. That is, the anodes (P-pole) of all LEDs (R2, G2, B2) are connected to the corresponding fault detection terminal VD inside the package. This pin is internally connected to the power supply output of the detection circuit, providing a voltage source for power-on detection and runtime diagnosis. 2) The cathode (N-pole) of each LED is connected to the corresponding output port on the LED driver chip within the package via wire bonding. For example, the cathode (N-pole) of R2 can be connected to the red channel pad corresponding to LED driver chip 100. Figure 14 The cathodes of R2, G2, and B2 are designed to be connected together to a grounding substrate 201 or a large copper area that is internally connected to the GND1 pin of the chip. This design greatly simplifies the internal gold wire connections of the green and blue channels, reduces packaging complexity and parasitic parameters, improves reliability, and facilitates heat dissipation. It should be noted that the cathode connection of each LED can also be in other ways, not limited to the method provided in this application.

[0140] Since all LEDs share a single fault detection terminal VD, if each LED is connected to n (n = 3 RGB) channels for output, the fault detection terminal will detect each of the n (n = 3 RGB) channels separately. For example, in customer applications, if any switch output terminal OUT fails due to manufacturing or service life, it will be considered a product fault. The fault detection results can be used to control whether to shut down the second switching transistor or output transistor module in the LED driver chip, cutting off the power supply to the LED through the fault detection terminal VD. This prevents abnormalities (constantly lit or dimly lit) caused by leakage current at the customer end, extending the product's lifespan.

[0141] It should be understood that in this embodiment, a centralized leakage current detection mechanism is built in. By monitoring the common anode (i.e., the fault detection terminal VD) path, leakage current caused by insulation defects between the grounding substrate and the chip or other parts can be effectively screened out. For example, if the grounding substrate is connected to an undesirable location, the detection circuit can immediately identify and lock the fault channel upon power-up.

[0142] Understandably, in the encapsulation device, the control chip has an independent fault detection terminal VD. This pin is interconnected with the anode of all LED chips in the package, thereby enabling unified detection of leakage current in all LED paths within the encapsulation through a centralized monitoring point, effectively solving the unique internal micro-leakage problem in the encapsulation process.

[0143] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0144] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0145] In the embodiments provided in this application, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0146] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0147] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A light-emitting diode driver chip, characterized in that, LED driver chips include: It includes at least one signal input terminal, at least one fault detection terminal, at least one switch output terminal, a switch module, and a fault detection module; The first end of the fault detection terminal is connected to the positive end of the load; The second end of the fault detection terminal is connected to the fault detection module through the switch module; The switch output terminal is connected to the cathode end of the load; The fault detection module is used to detect the fault status of the LED driver chip through the fault detection terminal in response to the detection timing signal, and generate a fault flag signal; wherein, the detection timing signal is used to coordinate and control the start-up, execution sequence and timing relationship of multiple fault status detections; the fault detection terminal has the functions of fault status detection and providing power to the load.

2. The light-emitting diode driver chip as described in claim 1, characterized in that, The fault detection module includes a leakage current fault detection module and a circuit fault detection module where the switching transistor is located. The switching module includes a first switching transistor, a second switching transistor, and an output transistor module. The second switching transistor is connected between the fault detection terminal and the power supply to form the main power supply path; The first switching transistor is connected between the fault detection terminal and the leakage fault detection module to form a leakage detection path; The output tube module is connected between the switch output terminal and ground, and is connected in series with the load to form a current loop; The leakage fault detection module is connected to the first switch and the power supply respectively. It is used to collect the analog current signal flowing through the leakage detection path, obtain the first sampled voltage value, compare the first sampled voltage value with the first preset reference voltage value, and generate a leakage fault flag signal that characterizes the leakage fault state of the switch output terminal. The fault detection module for the circuit where the switching transistor is located is connected to the second switching transistor and the fault detection terminal, respectively. It is used to collect the voltage of the fault detection terminal, obtain a second sampled voltage value, and compare the second sampled voltage value with a second preset reference voltage value to generate a fault flag signal for the circuit where the switching transistor is located, which represents the fault status of the circuit where the first switching transistor and the second switching transistor are located.

3. The light-emitting diode driver chip as described in claim 2, characterized in that, The leakage fault detection module includes a current detection module and a leakage detection comparison module; wherein... The current detection module is connected between the first switching transistor and the power supply, and is used to convert the analog current signal flowing through the leakage current detection path into the first sampling voltage value. The leakage current detection comparison module is connected to the current detection module and is used to compare the first sampled voltage value output by the current detection module with the first preset reference voltage value to generate the leakage current fault flag signal.

4. The light-emitting diode driver chip as described in claim 3, characterized in that, The fault detection module further includes an open-circuit detection comparison module and a short-circuit detection comparison module; wherein... The open circuit detection comparison module is connected between the switch output terminal and the load. It is used to collect the voltage at the switch output terminal, obtain the open circuit sampling voltage value, compare the open circuit sampling voltage value with the preset open circuit reference voltage value, and generate an open circuit fault flag signal that represents the open circuit fault state of the load. The short-circuit detection comparison module is connected between the switch output terminal and the load. It is used to collect the voltage at the switch output terminal, obtain the short-circuit sampled voltage value, compare the short-circuit sampled voltage value with the preset short-circuit reference voltage value, and generate a short-circuit fault flag signal that characterizes the short-circuit fault state of the load.

5. The light-emitting diode driver chip as described in claim 4, characterized in that, The LED driver chip also includes a detection result latching module and a logic judgment module; wherein... The detection result latching module is connected to the leakage current detection comparison module, the fault detection module of the circuit where the switch is located, the open circuit detection comparison module, and the short circuit detection comparison module, respectively. It is used to latch the leakage current fault flag signal, the fault flag signal of the circuit where the switch is located, the open circuit fault flag signal, and the short circuit fault flag signal according to their states, to obtain a global fault status signal, and output the global fault status signal to the logic judgment module. The logic judgment module is connected to the detection result latching module, the second switch, and the output module, respectively. It is used to receive the global fault status signal output by the detection result latching module and generate a corresponding execution signal based on the global fault status signal, so as to control the second switch and the output module to be turned on or off according to the execution signal.

6. The light-emitting diode driver chip as described in claim 5, characterized in that, The LED driver chip also includes: a parallel-to-serial conversion module and a feedback control logic module; The feedback control logic module is connected to the detection result latching module through the parallel-to-serial conversion module. In response to the readback status command sent through the bidirectional input / output port, it switches the bidirectional input / output port from the input state to the output state and turns on the parallel-to-serial conversion module so that the global fault status signal read from the detection result latching module through the parallel-to-serial conversion module is output to the external controller in serial data form through the bidirectional input / output port.

7. A fault detection method for a light-emitting diode driver chip, characterized in that, The method, applied to the light-emitting diode driver chip according to any one of claims 1-6, comprises: In response to a detection control command, a detection timing signal is generated; wherein the detection control command is a power-on reset signal or an external fault detection command, and the detection timing signal is used to coordinate and control the start-up, execution sequence and timing relationship of multiple fault state detections; According to the detection timing signal, the corresponding fault state detection is performed to generate a fault flag signal corresponding to the fault state detection; wherein, the fault state detection includes at least one of the following: leakage fault state detection at the switch output terminal, open / short circuit fault state detection at the load, and fault state detection at the circuit where the switch tube is located; Based on the fault flag signal, an execution signal corresponding to the fault flag signal is generated.

8. The fault detection method for a light-emitting diode driver chip as described in claim 7, characterized in that, The fault indication signals include: leakage fault indication signal, fault indication signal of the circuit where the switching transistor is located, open circuit fault indication signal, and short circuit fault indication signal. The step of performing corresponding fault state detection based on the detection timing signal and generating a fault flag signal corresponding to the fault state detection includes: When the detection timing signal indicates that the leakage fault state detection at the switch output terminal is valid, the leakage fault state at the switch output terminal is detected by enabling and conducting the first switch transistor, the current detection module, and the leakage detection comparison module, and by enabling and disabling the second switch transistor, the fault detection module of the path where the switch transistor is located, the output transistor module, the open circuit detection comparison module, and the short circuit detection comparison module, thereby obtaining the leakage fault flag signal. When the detection timing signal indicates that the fault status detection of the path where the switch is located is valid, the fault detection module of the path where the switch is located is enabled and turned on, and the first switch, the second switch, the output tube module, the current detection module, the leakage current detection comparison module, the open circuit detection comparison module and the short circuit detection comparison module are turned off, so as to detect the fault status of the path where the first switch and the second switch are located and obtain the fault flag signal of the path where the switch is located. When the detection timing signal indicates that the load open / short circuit fault state detection is valid, the first switch, the fault detection module of the path where the switch is located, the current detection module, the leakage current detection comparison module, and the output tube module are turned off by enabling the second switch. Then, the open circuit detection comparison module and the short circuit detection comparison module are turned on in sequence to detect the open circuit fault state and the short circuit fault state of the load, respectively, and obtain the open circuit fault flag signal and the short circuit fault flag signal.

9. The fault detection method for a light-emitting diode driver chip as described in claim 8, characterized in that, The execution signal includes a first execution signal and a second execution signal; wherein, the first execution signal is used to enable and turn on the second switching transistor and the output transistor module; the second execution signal is used to enable and turn off the second switching transistor and the output transistor module; When the detection control command is the power-on reset signal, the method includes: If the detection timing signal indicates that the leakage fault status detection at the switch output terminal is valid, the leakage fault status detection at the switch output terminal is executed, and the leakage fault flag signal is generated. If the leakage fault flag signal is valid, the second execution signal is generated, and a response action is performed according to the second execution signal to stop fault detection; If the leakage fault flag signal is invalid, then if the detection timing signal indicates that the fault status detection of the circuit where the switch is located is valid, the fault status detection of the circuit where the switch is located is executed, and the fault flag signal of the circuit where the switch is located is generated. If the fault flag signal of the path where the switch is located is valid, the second execution signal is generated, and a response action is performed according to the second execution signal and the fault detection is stopped; If the fault flag signal of the path where the switch tube is located is invalid, then according to the detection timing signal, the load open-short circuit fault state detection is valid, the load open-short circuit fault state detection is executed, and the short-circuit fault flag signal and the open-circuit fault flag signal are generated. If the short-circuit fault flag signal is valid or the open-circuit fault flag signal is valid, then the second execution signal is generated, and a response action is performed according to the second execution signal and the fault detection is stopped. If both the short-circuit fault indicator signal and the open-circuit fault indicator signal are invalid, the first execution signal is generated, and a response action is performed according to the first execution signal, and the system enters the normal working mode.

10. A packaging device for a light-emitting diode driver chip, characterized in that, Includes a light-emitting diode (LED) driver chip as described in any one of claims 1-6, and at least one LED; The LED driver chip and at least one of the LEDs are packaged on a main packaging substrate; The first end of at least one fault detection terminal of the LED driver chip is connected to the anode of at least one LED, the second end of the fault detection terminal is connected to the leakage fault detection module in the LED driver chip, and at least one switch output terminal of the LED driver chip is connected to the cathode of at least one LED; wherein, the fault detection terminal has the functions of fault state detection and providing power to the LED.

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