Calibration circuit of phase change memory and phase change memory

Abstract

This application discloses a calibration circuit and a phase-change memory (PCM), relating to the field of memory technology. The circuit includes: a detection module configured to detect multiple PCM cells coupled to the same bit line, and output a detection signal when a surge current exists in one of the PCM cells; and a calibration module connected to the detection module, configured to calibrate the voltage of the data line connected to the bit line based on the detection signal. The technical solution of this disclosure improves calibration efficiency by detecting multiple PCM cells coupled to the same bit line in parallel and outputting a detection signal; and calibrating the voltage of the data line connected to the bit line based on the detection signal. Simultaneously, it ensures that the PCM cells can be opened normally, helping to reduce the risk of the PCM cells failing to open normally due to excessively high bit line voltage, and significantly improving the stability and reliability of the PCM during read operations.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a calibration circuit for a phase-change memory and a phase-change memory. Background Technology

[0002] Phase-change memory (PCM) utilizes the difference in conductivity or impedance between crystalline and amorphous states of a specific phase-change material to store data, and is a type of non-volatile memory. A PCM memory block is a large-scale memory cell structure composed of a large number of word lines (WL), bit lines (BL), and phase-change memory cells (PCM cells).

[0003] With the continuous development of Artificial Intelligence (AI) technology, computers need to process massive amounts of data, which places increasingly higher demands on the bandwidth and power consumption of memory. However, due to the inconsistency of the threshold voltage (VTH) of phase-change memory (PCM) cells, when performing a read operation on a PCM cell, the current of the first PCM cell to open will charge the voltage of the shared black-and-white (BL) node, which may cause the subsequent PCM cells to fail to open normally. Therefore, there is an urgent need for a calibration design that can quickly maintain a stable voltage at the BL node, allowing multiple PCM cells coupled to the same bit line to open normally. Summary of the Invention

[0004] A calibration circuit and a phase change memory are provided to quickly maintain a stable voltage at the BL node, thereby ensuring that multiple phase change memory cells coupled to the same bit line can be turned on normally.

[0005] In a first aspect, a calibration circuit for a phase-change memory is provided. The phase-change memory includes a plurality of phase-change memory cells, multiple bit lines, and multiple word lines. The phase-change memory cells are coupled between a word line and a bit line. The circuit includes:

[0006] The detection module is configured to detect multiple phase change memory cells coupled to the same bit line, and output a detection signal when a surge current exists in one of the multiple phase change memory cells. The calibration module, connected to the detection module, is configured to calibrate the voltage of the data line connected to the bit line based on the detection signal.

[0007] In some implementations, the detection module includes: a plurality of sensitive amplifiers; each sensitive amplifier is configured to detect whether a surge current exists in the phase change memory cell corresponding to the sensitive amplifier; wherein one end of each sensitive amplifier is connected to a phase change memory cell.

[0008] In some implementations, the detection signal includes: a first level signal and a second level signal; wherein the sensitive amplifier is configured to: output the first level signal when the sensitive amplifier detects a surge current in the phase-change memory cell corresponding to the sensitive amplifier; and output the second level signal when the sensitive amplifier detects no surge current in the phase-change memory cell corresponding to the sensitive amplifier, the second level signal being different from the first level signal.

[0009] In some implementations, the detection module further includes a feedback sub-circuit connected to multiple sensitive amplifiers and configured to generate a disconnect signal upon detecting a first-level signal output by a sensitive amplifier.

[0010] In some embodiments, the calibration circuit of the phase change memory further includes: a first switch, connected to the feedback sub-circuit, configured to disconnect when a disconnection signal is detected, so as to cut off the connection between the phase change memory cell and the sensitive amplifier corresponding to the phase change memory cell.

[0011] In some implementations, the calibration module includes a second switch configured to control the opening or closing of a path between the bit line and the data line.

[0012] In some embodiments, the calibration module further includes: a third switch, a calibration switch, and a data line calibration submodule; the third switch, one end connected to the data line and the other end connected to the data line calibration submodule, is configured to control the opening or closing of the path between the data line and the data line calibration submodule; the data line calibration submodule, connected to the detection module, is configured to close the calibration switch according to a first level signal to calibrate the voltage of the data line to a reference voltage.

[0013] In some implementations, the multiple sensitive amplifiers are further configured to: read the state of their respective connected phase-change memory cells in parallel; wherein, when the phase-change memory cell is in a low-resistance state, a surge current exists in the phase-change memory cell, and a first-level signal is output; wherein, when the phase-change memory cell is in a high-resistance state, a surge current does not exist in the phase-change memory cell, and a second-level signal is output.

[0014] In some embodiments, the calibration circuit of the phase-change memory further includes: a word line driver, wherein each of the plurality of phase-change memory cells coupled to the same bit line is coupled between a sensitive amplifier and a word line driver.

[0015] Secondly, a phase-change memory is also provided, comprising: At least one memory array, each memory array comprising multiple phase-change memory cells; The driver includes calibration circuitry for the phase-change memory as provided in the first aspect.

[0016] According to the technical solution of this application, by simultaneously detecting multiple phase-change memory cells coupled to the same bit line, compared to detecting each phase-change memory cell individually, the presence of surge current in multiple phase-change memory cells can be detected in parallel, improving the efficiency of phase-change memory cell detection. Simultaneously, when a surge current is detected in one of the multiple phase-change memory cells coupled to the same bit line and it outputs a first-level signal, the calibration module can quickly respond and calibrate the voltage of the data line connected to the bit line based on the detection signal. This allows other phase-change memory cells coupled to the same bit line to open normally, helping to reduce the risk of phase-change memory cells failing to open normally due to excessively high bit line voltage, and significantly improving the stability and reliability of the phase-change memory during read operations. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0018] Figure 1 This is a waveform diagram showing how the current from the phase-change memory cell raises the voltage of the BL node. Figure 2 This is a circuit diagram of a phase-change memory read circuit; Figure 3 This is a schematic diagram of a calibration circuit for a phase-change memory provided in some embodiments of this application; Figure 4 This is a circuit diagram illustrating the parallel reading of data line calibration of N-channel phase-change memory cells according to some embodiments of this application; Figure 5 This is a circuit diagram of parallel reading of data line calibration of four phase-change memory units provided in some embodiments of this application; Figure 6 This is a timing waveform diagram of the voltage of the data line connected to the bit line after calibration, provided in some embodiments of this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] In the description of the embodiments of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0021] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not exclude the applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0022] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0023] In related technologies, when performing parallel read operations on phase change memory cells, the phase change memory cells share the same BL. Due to the inconsistency of VTH of the phase change memory cells, during the voltage application of WL and BL, the phase change memory cells with lower VTH are turned on first (WL voltage - BL voltage > VTH), while the phase change memory cells with higher VTH are turned on later as the voltages of WL and BL continue to rise. The current of the phase change memory cells that are turned on first will charge the voltage of the BL node high, which may cause the phase change memory cells that are turned on later to fail to turn on normally. Figure 1 This is a waveform diagram showing how the current in the phase-change memory cell raises the voltage of the BL node, as shown below. Figure 1 As shown, at time t1, the voltage of the BL node is charged. If the voltage difference between WL and BL of the two subsequent phase change memory cells is always less than VTH, the two subsequent phase change memory cells may not be able to be opened.

[0024] In the existing technology, Figure 2This is a circuit diagram of a phase-change memory read circuit, such as... Figure 2 As shown, the read circuit includes: a phase-change memory cell, a sensitive amplifier, a word line, a bit line, and a data line. One end of the sensitive amplifier is connected to the word line; the other end of the word line is connected to one end of the phase-change memory cell; the other end of the phase-change memory cell is connected to one end of the bit line; and the other end of the bit line is connected to the data line. The sensitive amplifier is used to read the state of one phase-change memory cell at a time. However, using a single sensitive amplifier to detect one phase-change memory cell not only fails to meet the read speed requirements of high-bandwidth applications, but also, when multiple phase-change memory cells are coupled to the same bit line, the lack of an effective calibration mechanism means that the current generated by the first phase-change memory cell to open will still cause an increase in the bit line voltage, thus affecting the normal opening of subsequent phase-change memory cells.

[0025] To at least partially address one or more of the aforementioned problems and other potential issues, this disclosure proposes a calibration circuit for a phase-change memory (PCM). The circuit includes: a detection module configured to detect multiple PCM cells coupled to the same bit line, and output a detection signal when a surge current exists in one of the PCM cells; and a calibration module connected to the detection module, configured to calibrate the voltage of a data line connected to the bit line based on the detection signal. Thus, by simultaneously detecting multiple PCM cells coupled to the same bit line, compared to detecting each PCM cell individually, the presence of surge current in multiple PCM cells can be detected in parallel, improving the efficiency of PCM cell detection. Meanwhile, when a surge current is detected in one of the multiple phase-change memory cells coupled to the same bit line and it outputs a first-level signal, the calibration module can respond quickly and calibrate the voltage of the data line connected to the bit line according to the detection signal. This allows other phase-change memory cells coupled to the same bit line to be opened normally, which helps reduce the risk that the phase-change memory cells cannot be opened normally due to excessive bit line voltage, and significantly improves the stability and reliability of the phase-change memory during read operations.

[0026] Figure 3 This is a circuit diagram of the calibration circuit 300 of the phase-change memory provided in some embodiments of this application, such as... Figure 3 As shown, the circuit includes at least: The detection module 310 is configured to detect multiple phase change memory units 330 coupled to the same bit line, and output a detection signal when a surge current exists in one of the multiple phase change memory units 330. The calibration module 320, connected to the detection module 310, is configured to calibrate the voltage of the data line connected to the bit line based on the detection signal.

[0027] In this embodiment of the disclosure, the detection module 310 is configured to detect multiple phase change memory cells 330 coupled to the same bit line, and output a detection signal when a surge current exists in one of the multiple phase change memory cells 330.

[0028] In some embodiments, the detection module 310 includes a plurality of sensitive amplifiers; each sensitive amplifier is configured to detect whether a surge current exists in the phase-change memory cell corresponding to the sensitive amplifier; wherein one end of each sensitive amplifier is connected to a phase-change memory cell. Specifically, when a phase-change memory cell is selected and begins to conduct, if it is in a low-resistance state (i.e., data "1"), a relatively large surge current will be generated; the sensitive amplifier determines whether a surge current exists in the phase-change memory cell by detecting the magnitude of the current flowing through the corresponding phase-change memory cell or the voltage change across its terminals. For example, when the current value detected by the sensitive amplifier exceeds a preset threshold, or when a voltage change is detected across the phase-change memory cell, it is determined that a surge current exists in the phase-change memory cell.

[0029] It should be noted that this preset threshold can be set according to actual needs or design.

[0030] In some embodiments, the inrush current refers to a short-duration large current generated when a phase-change memory cell transitions from a high-resistance state (amorphous) to a low-resistance state (crystalline), or when it is selected for conduction in a low-resistance state. This current typically has the characteristics of rapid rise and high peak current, which can cause the voltage of the bit line node to be rapidly charged in a short period of time, thereby affecting the normal read operation of other phase-change memory cells on the same bit line.

[0031] In some embodiments, the detection signal includes a first level signal and a second level signal; wherein, the sensitive amplifier is configured to: output a first level signal when the sensitive amplifier detects a surge current in the phase-change memory cell corresponding to the sensitive amplifier; and output a second level signal, which is different from the first level signal, when the sensitive amplifier detects no surge current in the phase-change memory cell corresponding to the sensitive amplifier. The outputs of multiple sensitive amplifiers can be fed back to the sensitive amplifier through a feedback sub-circuit (such as an OR gate). When a surge current exists in one of the multiple phase-change memory cells 330 coupled to the same bit line, the first level signal is output. When the first level signal is detected, a disconnect signal is generated; this disconnect signal is used to indicate that a first switch is opened to disconnect the connection between the phase-change memory cell and the sensitive amplifier corresponding to the phase-change memory cell.

[0032] It should be noted that the first level signal is a high level signal; the second level signal is a low level signal.

[0033] In some embodiments, the multiple sensitive amplifiers are further configured to: read the state of their respective connected phase-change memory cells in parallel; wherein, when the phase-change memory cell is in a low-resistance state and inrush current exists, a first-level signal is output; wherein, when the phase-change memory cell is in a high-resistance state and inrush current does not exist, a second-level signal is output. Thus, parallel reading of multiple phase-change memory cells helps improve the read speed of the phase-change memory, meeting the needs of high-bandwidth applications.

[0034] In this embodiment of the disclosure, the calibration module 320, connected to the detection module 310, is configured to calibrate the voltage of the data line connected to the bit line according to the detection signal.

[0035] In some embodiments, when a surge current is detected in the phase-change memory cell, causing the bit line voltage connected to the phase-change memory cell to show an upward trend, the voltage of the data line connected to the bit line is pulled down and stabilized at a lower level, thereby ensuring that subsequent phase-change memory cells on the bit line can be turned on normally.

[0036] In some embodiments, the calibration module 320 includes a second switch configured to control the opening or closing of a path between the bit line and the data line. Thus, the second switch connects the bit line and the data line, allowing the calibration module to adjust the voltage of the data line, thereby reducing the bit line voltage.

[0037] For example, in a specific implementation, the second switch is in a closed state during the normal read operation phase.

[0038] In some embodiments, the calibration module 320 further includes: a third switch, a calibration switch, and a data line calibration submodule; the third switch, one end connected to the data line and the other end connected to the data line calibration submodule, is configured to control the opening or closing of the path between the data line and the data line calibration submodule; the data line calibration submodule, connected to the detection module, is configured to close the calibration switch according to a first level signal to calibrate the voltage of the data line to a reference voltage. When the detection module outputs the first level signal, the calibration switch closes, and the data line calibration submodule forcibly pulls the voltage of the raised data line to the reference voltage, thereby pulling the bit line voltage down through the second switch.

[0039] In some implementations, the second and third switches are in the closed state. Thus, when a surge current is detected, the bit line and data line are connected, and the data line and data line calibration submodule are connected, forming a discharge path from the bit line to the data line and then to the data line calibration submodule. This quickly and effectively reduces the voltage of the bit line and data line to the reference voltage level, achieving rapid calibration. After calibration is complete, or after the detection signal returns to the second level signal, the calibration switch can be opened to end the calibration process and resume normal reading operations.

[0040] Figure 4 This is a circuit diagram illustrating the parallel reading of data line calibration for N-channel phase-change memory cells according to some embodiments of this application, such as... Figure 4 As shown, the circuit includes: a detection module 310, a first switch, N-channel phase-change memory units, and a calibration module 320. The calibration module 320 includes: a sensitive amplifier and a feedback sub-circuit; the calibration module 320 also includes: a second switch, a third switch, and a calibration switch. The calibration module is connected to the first switch, the other end of the first switch is connected to a word line, the other end of the word line is connected to the N-channel phase-change memory units, the other end of the N-channel phase-change memory units is connected to a bit line, and the other end of the bit line is connected to the calibration module 320.

[0041] Specifically, the N sensitive amplifiers in the detection module 310 correspond one-to-one with the N phase-change memory cells corresponding to the same bit line. Each phase-change memory cell is coupled between the corresponding word line and bit line. When the circuit starts to operate, it includes the following stages: In the initial stage, the first switch controlled by the N-way word line enable signal remains closed, the second switch controlled by the bit line enable signal and the third switch controlled by the data line enable signal in the calibration module 320 remain closed, and the calibration switch is in the open state, with the reading voltage terminal ready; During the detection phase, N sensitive amplifiers read the status of their respective connected phase-change memory cells in parallel: when a surge current exists in one of the N phase-change memory cells, the N sensitive amplifiers output a first-level signal; when no surge current exists in one of the N phase-change memory cells, the N sensitive amplifiers output a second-level signal; simultaneously, the OR gate in the detection module receives the first-level signal or the second-level signal and outputs N OR gate detection signals; During the calibration phase, when the detection signal of one of the N channels is a first-level signal, the first switch of the corresponding channel is turned off, cutting off the connection between the phase-change storage unit and the sensitive amplifier to isolate surge interference. At the same time, the calibration module 320 responds to the first-level signal, the calibration switch is closed, and the calibration module calibrates the data line voltage to the reference voltage level according to the detection signal output by the detection module.

[0042] It should be noted that in the above embodiments, N is not less than 1 for the N-channel phase-change memory units.

[0043] For example, when N=4, the following describes the data line calibration circuit for parallel reading of 4 phase-change memory cells. Figure 5 This is a circuit diagram illustrating the parallel reading of data line calibration for four-channel phase-change memory units according to some embodiments of this application, such as... Figure 5As shown, the circuit includes: a detection module 310, a first switch, four phase-change memory units, and a calibration module 320. The calibration module 320 includes: a sensitive amplifier and a feedback sub-circuit; the calibration module 320 also includes: a second switch, a third switch, and a calibration switch. The calibration module is connected to the first switch, the other end of the first switch is connected to a word line, the other end of the word line is connected to the four phase-change memory units, the other end of the four phase-change memory units is connected to a bit line, and the other end of the bit line is connected to the calibration module 320.

[0044] Specifically, the four sensitive amplifiers in the detection module 310 correspond one-to-one with the four phase-change memory cells corresponding to the same bit line. Each phase-change memory cell is coupled between the corresponding word line and bit line. When the circuit starts to operate, it includes the following stages: In the initial stage, the first switch controlled by the 4-way word line enable signal remains closed, and the second switch controlled by the bit line enable signal, the third switch controlled by the data line enable signal, and the calibration switch in the calibration module 320 are in the closed state, with the reading voltage terminal ready. During the detection phase, four sensitive amplifiers read the status of their respective connected phase-change memory cells in parallel: when a surge current exists in one of the four phase-change memory cells, the sensitive amplifier corresponding to that phase-change memory cell outputs a first-level signal; when no surge current exists in any of the four phase-change memory cells, the sensitive amplifiers corresponding to the four phase-change memory cells output a second-level signal; simultaneously, the OR gate in the detection module receives either the first-level signal or the second-level signal and outputs four OR gate detection signals; During the calibration phase, when the detection signal of one of the four channels is the first level signal, the first switch of the corresponding channel is turned off, cutting off the connection between the phase change storage unit and the sensitive amplifier to isolate surge interference. At the same time, the calibration module 320 responds to the first level signal, triggering the calibration switch to close. The calibration module calibrates the data line voltage to the reference voltage level according to the detection signal output by the detection module.

[0045] Figure 6 These are timing waveform diagrams of the voltage of the data line connected to the bit line after calibration, provided in some embodiments of this application, such as... Figure 6 As shown, compared to the uncalibrated timing waveform (see...), Figure 1Without calibration, the surge currents overlap and interfere with each other; however, after calibration, the surge currents exhibit independent and ordered waveforms without overlapping interference. Without calibration, the bit line fluctuations are chaotic and interference is significant (affected by overlapping surge currents); however, after calibration, the bit line fluctuations are more regular, and the interference amplitude is significantly reduced. Furthermore, because each phase storage unit is equipped with an independent word line, independent control of different phase-change storage units is achieved; and because each phase storage unit is equipped with an independent sensitive amplifier, accurate reading of each branch is achieved.

[0046] The solution of this embodiment involves detecting multiple phase-change memory cells coupled to the same bit line, and when a surge current occurs in one of the phase-change memory cells, outputting a detection signal; and calibrating the voltage of the data line connected to the bit line based on the detection signal. In this way, by calibrating the voltage of the data line connected to the bit line based on the detection signal, the bit line node can be quickly kept at a stable voltage, thereby ensuring that the multiple phase-change memory cells coupled to the same bit line can be turned on normally.

[0047] In this embodiment of the disclosure, the detection module includes: a plurality of sensitive amplifiers; each sensitive amplifier is configured to detect whether there is a surge current in the phase change memory cell corresponding to the sensitive amplifier; wherein one end of each sensitive amplifier is connected to a phase change memory cell.

[0048] In some embodiments, the sensitive amplifier is a low-power, high-precision current comparison sensitive amplifier. For example, when the phase-change memory cell a connected to the sensitive amplifier A is in a low-resistance state and a surge current exists, the current flowing through the sensitive amplifier will significantly increase, causing the current flowing through the sensitive amplifier to exceed a preset threshold, at which point a first-level signal indicating the presence of a surge current will be output; conversely, if the phase-change memory cell a connected to the sensitive amplifier A is in a high-resistance state and no surge current flows, a second-level signal indicating the absence of a surge current will be output.

[0049] In some embodiments, one end of each sensitive amplifier is connected to a phase-change memory cell.

[0050] In this embodiment of the disclosure, the detection signal includes: a first level signal and a second level signal; wherein, the sensitive amplifier is configured to: output the first level signal when the sensitive amplifier detects a surge current in the phase change memory cell corresponding to the sensitive amplifier; and output the second level signal when the sensitive amplifier detects no surge current in the phase change memory cell corresponding to the sensitive amplifier, wherein the second level signal is different from the first level signal.

[0051] In this embodiment of the disclosure, the detection module further includes: a feedback sub-circuit connected to multiple sensitive amplifiers, configured to generate a disconnect signal after detecting that the sensitive amplifier outputs a first-level signal.

[0052] In some embodiments, the first level signal is a high level signal and the second level signal is a low level signal.

[0053] In this embodiment of the disclosure, the calibration circuit of the phase change memory further includes: a first switch, connected to the feedback sub-circuit, configured to disconnect when a disconnection signal is detected, so as to cut off the connection between the phase change memory cell and the sensitive amplifier corresponding to the phase change memory cell.

[0054] In some embodiments, the first switch can be a transistor switch controlled by the output signal of the detection module; for example, an N-channel metal-oxide-semiconductor field-effect transistor (NMOS) or a P-channel metal-oxide-semiconductor field-effect transistor (PMOS). When the detection module outputs a first-level signal, the control terminal of the first switch disconnects upon receiving the first-level signal, thereby cutting off the path between the phase-change memory cell that generates inrush current and the corresponding sensitive amplifier. This prevents the phase-change memory cell from continuously injecting current into the bit line, triggering the calibration switch to close, accelerating the discharge process of the bit line and data line, and improving calibration efficiency. When the detection signal returns to a second-level signal, the first switch closes, disconnecting the phase-change memory cell from the sensitive amplifier to allow for subsequent normal reading or other operations.

[0055] In some embodiments, when one of the multiple phase-change memory cells 330 coupled to the same bit line is detected to have a surge current and triggers calibration, its connection to the corresponding sensitive amplifier is disconnected. This prevents the phase-change memory cell from continuously affecting the sensitive amplifier or bit line; simultaneously, it also prevents interference to the sensitive amplifier during subsequent calibration and readout processes, protecting the sensitive amplifier and improving the overall circuit stability.

[0056] In this embodiment of the disclosure, the calibration module includes a second switch configured to control the opening or closing of the path between the bit line and the data line.

[0057] In some embodiments, the second switch may be a transmission gate switch made of a metal-oxide-semiconductor field-effect transistor (MOSFET). During data reading, the second switch remains closed.

[0058] In this embodiment of the present disclosure, the calibration module further includes: a third switch, a calibration switch, and a data line calibration submodule; the third switch, one end of which is connected to the data line and the other end of which is connected to the data line calibration submodule, is configured to control the opening or closing of the path between the data line and the data line calibration submodule; the data line calibration submodule, which is connected to the detection module, is configured to close the calibration switch according to the first level signal to calibrate the voltage of the data line to the reference voltage.

[0059] In some embodiments, the third switch can be a single-pole single-throw switch directly controlled by the output signal of the detection module; for example, a PMOS. During data reading, the third switch remains closed to create a path between the data line and the data line calibration submodule.

[0060] In some embodiments, the calibration switch can be an NMOS switch; when the detection module outputs a first level signal, the gate of the calibration switch receives a high level and is turned on, so that a path is formed between the data line calibration submodule and the data line, thereby starting the calibration.

[0061] It should be noted that the descriptions of the types of the first switch, the second switch, and the third switch above are merely illustrative examples and are not intended to limit all possible types of the first switch, the second switch, the third switch, and the calibration module; they are simply not exhaustive here.

[0062] In some embodiments, the data line calibration submodule can employ a voltage follower circuit composed of an operational amplifier. Its non-inverting input is connected to a reference voltage, and its inverting input is shorted to its output and connected to the data line. When the third switch is closed, the data line calibration submodule, through the action of the voltage follower, quickly pulls the voltage of the data line to match the reference voltage. For example, if the reference voltage is set to 0.5V, when the data line experiences a voltage higher than 0.5V due to bit line coupling, the output of the voltage follower will inject current into the data line, reducing the data line voltage to 0.5V; if the data line voltage is lower than 0.5V, the voltage follower will draw current from the data line, raising the data line voltage to 0.5V.

[0063] It should be noted that the reference voltage can be a preset voltage based on actual needs.

[0064] In some embodiments, a data line refers to a metal interconnect used in a phase-change memory to transmit data signals. The data line is typically made of a low-resistivity metal (such as copper or aluminum) and employs a multilayer wiring process to reduce parasitic resistance and capacitance, thereby reducing signal transmission delay and noise interference, and improving the operating speed and stability of the phase-change memory.

[0065] In some embodiments, when the detection module 310 outputs a first-level signal, the second and third switches are triggered to close, the bit line is connected to the data line through the second switch, and the data line is connected to the data line calibration submodule through the third switch. Specifically, abnormal voltage on the bit line caused by surge current generated by the phase-change memory cell will be rapidly coupled to the data line, and the data line calibration submodule calibrates the voltage of the data line according to the reference voltage.

[0066] In this embodiment of the disclosure, the multiple sensitive amplifiers are further configured to: read the state of their respective corresponding connected phase-change memory units in parallel; wherein, when the phase-change memory unit is in a low resistance state, the phase-change memory unit has a surge current and outputs a first level signal; wherein, when the phase-change memory unit is in a high resistance state, the phase-change memory unit does not have a surge current and outputs a second level signal.

[0067] In some embodiments, parallel reading of the states of their respective connected phase-change memory cells means that multiple sensitive amplifiers can simultaneously read the states of their corresponding phase-change memory cells. Specifically, when a phase-change memory cell is in a low-resistance state, it experiences inrush current and outputs a first-level signal; when it is in a high-resistance state, it does not experience inrush current and outputs a second-level signal. This significantly improves the read speed of the phase-change memory, especially in scenarios with large storage capacities where multiple memory cells need to be read simultaneously.

[0068] For example, when a phase-change memory (PCM) array includes eight PCM cells coupled to the same bit line, reading the eight PCM cells in parallel using eight sensitive amplifiers can reduce the reading time to 1 / 8 of that required by a single sensitive amplifier reading sequentially, greatly improving the efficiency of the PCM. During parallel reading, each sensitive amplifier operates independently, converting the resistance state of the corresponding PCM cell into a voltage signal, comparing the signals, and then outputting either a first-level signal or a second-level signal.

[0069] In this embodiment of the disclosure, the calibration circuit of the phase-change memory includes: a word line driver, and each of the plurality of phase-change memory cells coupled to the same bit line is coupled between a sensitive amplifier and a word line driver.

[0070] In some embodiments, the calibration circuit 300 of the phase-change memory further includes a word line driver. Each of the plurality of phase-change memory cells 330 coupled to the same bit line is coupled between a sensitive amplifier and a word line driver. The word line driver provides a driving voltage to the word line to select a specific row of phase-change memory cells for a read operation. Each phase-change memory cell corresponds to one word line driver, which allows for precise control of the gating timing of each phase-change memory cell.

[0071] This embodiment also provides a phase change memory, including: at least one memory array, each memory array including a plurality of phase change memory cells; and a driver including a calibration circuit for the phase change memory as provided in the first aspect.

[0072] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0073] The calibration circuit and phase-change memory of the phase-change memory provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A calibration circuit for a phase-change memory, the phase-change memory comprising a plurality of phase-change memory cells, a plurality of bit lines and a plurality of word lines, wherein the phase-change memory cells are coupled between a word line and a bit line, characterized in that, The circuit includes: The detection module is configured to detect multiple phase change memory cells coupled to the same bit line, and output a detection signal when a surge current exists in one of the multiple phase change memory cells. A calibration module, connected to the detection module, is configured to calibrate the voltage of the data line connected to the bit line based on the detection signal.

2. The circuit according to claim 1, characterized in that, The detection module includes: a plurality of sensitive amplifiers; each of the sensitive amplifiers is configured to detect whether there is a surge current in the phase change memory cell corresponding to the sensitive amplifier; Each of the sensitive amplifiers is connected at one end to one of the phase-change memory units.

3. The circuit according to claim 2, characterized in that, The detection signal includes: a first-level signal and a second-level signal; wherein, the sensitive amplifier is configured as follows: When the sensitive amplifier detects the presence of a surge current in the phase-change memory cell corresponding to the sensitive amplifier, it outputs the first level signal; when the sensitive amplifier detects the absence of a surge current in the phase-change memory cell corresponding to the sensitive amplifier, it outputs the second level signal, which is different from the first level signal.

4. The circuit according to claim 3, characterized in that, The detection module further includes: The feedback sub-circuit, connected to multiple of the sensitive amplifiers, is configured to generate a disconnect signal when the first level signal is detected being output by the sensitive amplifier.

5. The circuit according to claim 4, characterized in that, Also includes: A first switch, connected to the feedback sub-circuit, is configured to disconnect when the disconnection signal is detected, thereby severing the connection between the phase-change memory unit and the sensitive amplifier corresponding to the phase-change memory unit.

6. The circuit according to claim 3, characterized in that, The calibration module includes a second switch configured to control the opening or closing of the path between the bit line and the data line.

7. The circuit according to claim 5, characterized in that, The calibration module also includes: a third switch, a calibration switch, and a data cable calibration submodule; The third switch, with one end connected to the data line and the other end connected to the data line calibration submodule, is configured to control the opening or closing of the path between the data line and the data line calibration submodule; The data line calibration submodule, connected to the detection module, is configured to close the calibration switch according to the first level signal to calibrate the voltage of the data line to a reference voltage.

8. The circuit according to claim 3, characterized in that, The plurality of said sensitive amplifiers are also configured to read in parallel the state of their respective corresponding connected phase-change memory cells; When the phase-change memory unit is in a low-resistance state, the phase-change memory unit has the surge current and outputs the first level signal; When the phase-change memory unit is in a high-resistance state, there is no surge current in the phase-change memory unit, and the second level signal is output.

9. The circuit according to claim 2, characterized in that, Also includes: A word line driver, wherein each of the plurality of phase-change memory cells coupled to the same bit line is coupled between a sensitive amplifier and a word line driver.

10. A phase-change memory, characterized in that, include: At least one memory array, each of the memory arrays comprising a plurality of phase-change memory cells; The driver includes the calibration circuitry for the phase-change memory as described in claims 1-9.

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