Semiconductor memory device and memory system

Abstract

This invention provides a semiconductor memory device and memory system capable of realizing memory cells with high readability. One embodiment of the semiconductor memory device includes a plurality of memory strings arranged spaced apart from each other in a first direction. Each of the plurality of memory strings includes: a semiconductor layer extending along a second direction intersecting the first direction; a first string disposed on a first side of the semiconductor layer in a third direction intersecting both the first and second directions; and a second string disposed on a second side of the semiconductor layer in the third direction. The first string includes a first selection transistor and a plurality of first memory cell transistors arranged spaced apart from each other in the second direction, each using the semiconductor layer as a channel. The second string includes a plurality of first transistors and second selection transistors arranged spaced apart from each other in the second direction, each using the semiconductor layer as a channel.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a memory system. Background Technology

[0002] Memory systems that include semiconductor memory devices and memory controllers that control the semiconductor memory devices are known. NAND flash memory is a known semiconductor memory device. Summary of the Invention

[0003] A semiconductor storage device and memory system are provided that can achieve high readability of storage cells.

[0004] The semiconductor memory device of the embodiment includes a plurality of memory strings arranged separately from each other in a first direction. Each memory string includes: a semiconductor layer extending along a second direction intersecting the first direction; a first string disposed on a first side of the semiconductor layer in a third direction intersecting both the first and second directions; and a second string disposed on a second side of the semiconductor layer in the third direction. The first string includes a first selection transistor and a plurality of first memory cell transistors arranged separately from each other in the second direction, each using the semiconductor layer as a channel. The second string includes a plurality of first transistors and second selection transistors arranged separately from each other in the second direction, each using the semiconductor layer as a channel. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating an example of the configuration of a memory system including the semiconductor memory device of the first embodiment.

[0006] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array included in the semiconductor memory device of the first embodiment.

[0007] Figure 3 This is a top view showing an example of the planar layout of the memory cell array included in the semiconductor memory device of the first embodiment.

[0008] Figure 4 yes Figure 3 The cross-sectional view along line IV-IV shows an example of the cross-sectional structure of the memory cell array included in the semiconductor memory device of the first embodiment.

[0009] Figure 5 yes Figure 3 The cross-sectional view along line V-V shows an example of the cross-sectional structure of the memory cell array included in the semiconductor memory device of the first embodiment.

[0010] Figure 6 yes Figure 3The cross-sectional view along line VI-VI shows an example of the cross-sectional structure of the memory cell array included in the semiconductor memory device of the first embodiment.

[0011] Figure 7 yes Figure 3 The cross-sectional view along line VII-VII shows an example of the cross-sectional structure of the memory cell array included in the semiconductor memory device of the first embodiment.

[0012] Figure 8 This is a diagram showing the voltage of each wiring during the first readout operation of the semiconductor memory device according to the first embodiment.

[0013] Figure 9 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array included in a semiconductor memory device according to a variation of the first embodiment.

[0014] Figure 10 This is a top view showing an example of the planar layout of the memory cell array included in a semiconductor memory device according to a variation of the first embodiment.

[0015] Figure 11 This is a diagram showing the voltage of each wiring during the first read operation of the semiconductor memory device in a variation of the first embodiment.

[0016] Figure 12 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array included in the semiconductor memory device of the second embodiment.

[0017] Figure 13 This is a top view showing an example of the planar layout of the memory cell array included in the semiconductor memory device of the second embodiment.

[0018] Figure 14 This is a flowchart illustrating an example of the write operation of the semiconductor memory device according to the second embodiment.

[0019] Figure 15 This is a diagram showing the voltage of each wiring during the first readout operation of the semiconductor memory device according to the second embodiment.

[0020] Figure 16 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array included in a semiconductor memory device according to a variation of the second embodiment.

[0021] Figure 17 This is a top view showing an example of the planar layout of the memory cell array included in a semiconductor memory device according to a variation of the second embodiment.

[0022] Figure 18This is a diagram showing the voltage of each wiring during the first readout operation of the semiconductor memory device in a variation of the second embodiment.

[0023] Figure 19 This is a diagram illustrating the string markers used in the semiconductor memory device of the third embodiment.

[0024] Figure 20 This is a flowchart illustrating an example of the write operation of the semiconductor memory device according to the third embodiment.

[0025] Figure 21 This is a flowchart illustrating an example of the read operation of the semiconductor memory device according to the third embodiment.

[0026] Figure 22 This is a diagram showing the voltage of each wiring during the first readout operation of the semiconductor memory device according to the third embodiment.

[0027] Figure 23 This is a conceptual diagram of a serial table used in a semiconductor memory device according to the first variation of the third embodiment.

[0028] Figure 24 This is a flowchart illustrating an example of the write operation of a semiconductor memory device according to the first variation of the third embodiment.

[0029] Figure 25 This is a flowchart illustrating an example of the read operation of a semiconductor memory device according to the first variation of the third embodiment.

[0030] Figure 26 This is a diagram showing the voltage of each wiring during the first readout operation of the semiconductor memory device in the second variation of the third embodiment.

[0031] Figure 27 This is a diagram illustrating a method for specifying the storage mode of blocks in the semiconductor memory device according to the fourth embodiment.

[0032] Figure 28 This is a flowchart illustrating an example of the write operation of the semiconductor memory device according to the fourth embodiment.

[0033] Figure 29 This is a flowchart illustrating an example of the read operation of the semiconductor memory device according to the fourth embodiment.

[0034] Figure 30 This is a diagram showing the voltage of each wiring during the second readout operation of the semiconductor memory device according to the fourth embodiment.

[0035] Figure 31 This is a diagram showing the voltage of each wiring during the second readout operation of the semiconductor memory device in the first variation of the fourth embodiment.

[0036] Figure 32 This is a diagram illustrating a method for specifying the storage mode of blocks in a semiconductor memory device according to a second variation of the fourth embodiment.

[0037] Figure 33 This is a diagram illustrating the pattern symbols used in the semiconductor memory device of the second variation of the fourth embodiment.

[0038] Figure 34 This is a flowchart illustrating an example of the variable operation of a block region of a semiconductor memory device in the second variation of the fourth embodiment.

[0039] Figure 35 This is a flowchart illustrating an example of the first variable operation of a semiconductor memory device in the second variation of the fourth embodiment.

[0040] Figure 36 This is a flowchart illustrating an example of the second variable operation of a semiconductor memory device, which is a second variation of the fourth embodiment.

[0041] Figure 37 This is a flowchart illustrating an example of the read operation of a semiconductor memory device according to the second variation of the fourth embodiment.

[0042] Figure 38 This is a conceptual diagram of the pattern sheet used in the third variation of the fourth embodiment of the semiconductor memory device.

[0043] Figure 39 This is a flowchart illustrating an example of the write operation of a semiconductor memory device in the third variation of the fourth embodiment.

[0044] Figure 40 This is a flowchart illustrating an example of the variable operation of a block region of a semiconductor memory device in the third variation of the fourth embodiment.

[0045] Figure 41 This is a flowchart illustrating an example of the first variable operation of a semiconductor memory device in the third variation of the fourth embodiment.

[0046] Figure 42 This is a flowchart illustrating an example of the second variable operation of a semiconductor memory device in the third variation of the fourth embodiment.

[0047] Figure 43 This is a flowchart illustrating an example of the read operation of a semiconductor memory device according to the third variation of the fourth embodiment.

[0048] Figure 44This is a diagram illustrating a method for specifying the storage mode of blocks in a semiconductor memory device according to a fourth variation of the fourth embodiment.

[0049] Figure 45 This is a flowchart illustrating an example of the write operation of a semiconductor memory device according to the fourth variation of the fourth embodiment.

[0050] Figure 46 This is a flowchart illustrating an example of the write operation of a semiconductor memory device according to the fifth variation of the fourth embodiment.

[0051] Figure 47 This is a block diagram illustrating an example of the configuration of a memory system including the semiconductor memory device of the fifth embodiment.

[0052] Figure 48 This is a block diagram illustrating an example of the configuration of the arithmetic module included in the semiconductor memory device of the fifth embodiment.

[0053] Figure 49 This is a flowchart illustrating an example of the computational processing performed by the computation module of the semiconductor memory device according to the fifth embodiment.

[0054] Figure 50 This is a block diagram illustrating an example configuration of an AI module assembled with a memory system containing a semiconductor memory device according to the fifth embodiment. Detailed Implementation

[0055] The embodiments will now be described with reference to the accompanying drawings. The drawings are schematic, and the dimensions and scale may not be identical to actual figures. Furthermore, in the following description, constituent elements having substantially the same function and structure are labeled with the same symbols. If it is necessary to specifically distinguish elements with the same structure from each other, different text or numbers will be added to the end of the same symbols.

[0056] In the following description, the term "connected" to a certain first element by another second element includes the first element being connected to the second element directly or indirectly, either through a conductive intermediate element or without an intermediate element.

[0057] 1. First Implementation Method

[0058] The semiconductor memory device of the first embodiment will be described.

[0059] 1.1 Composition

[0060] 1.1.1 Memory System Composition

[0061] use Figure 1 The configuration of a memory system including the semiconductor memory device of the first embodiment will be described. Figure 1 This is a block diagram illustrating an example of the configuration of a memory system including the semiconductor memory device of the first embodiment.

[0062] Memory system 1 is a storage device configured to connect to an external host (not shown). Memory system 1 is, for example, an SD card. TM Memory cards such as memory cards, UFS (universal flash storage), and SSD (solid state drive). Memory system 1 includes a memory controller 2 and a semiconductor storage device 3.

[0063] The memory controller 2 is, for example, an integrated circuit such as a system-on-a-chip (SoC). Based on requests from the host, the memory controller 2 controls the semiconductor memory device 3. Specifically, for example, the memory controller 2 writes data requested to be written by the host into the semiconductor memory device 3. Additionally, the memory controller 2 reads data requested to be read by the host from the semiconductor memory device 3 and sends it back to the host.

[0064] Semiconductor memory device 3 is a non-volatile memory. Semiconductor memory device 3 is, for example, a NAND flash memory. Semiconductor memory device 3 stores data non-volatilely.

[0065] The communication between the memory controller 2 and the semiconductor memory device 3 conforms to, for example, the SDR (single data rate) interface, the Toggle DDR (double data rate) interface, or the ONFI (Open NAND flash interface) standard.

[0066] 1.1.2 Structure of Semiconductor Memory Devices

[0067] Next, refer to Figure 1 The block diagram shown illustrates the internal structure of the semiconductor memory device 3. The semiconductor memory device 3 includes, for example, a memory cell array 10, an instruction register 11, an address register 12, a sequencer 13, a driver module 14, a line decoder module 15, and a sense amplifier module 16.

[0068] The memory cell array 10 contains multiple blocks BLK0 to BLKn (n is an integer greater than or equal to 1). The number of blocks BLK in the memory cell array 10 can also be one. A block BLK is a collection of multiple memory cells. A block BLK is used, for example, as a unit for data erasure. Furthermore, the memory cell array 10 is provided with multiple bit lines and multiple word lines. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described below.

[0069] Instruction register 11 stores instructions CMD received by semiconductor memory device 3 from memory controller 2. Instructions CMD may include commands that cause sequencer 13 to perform read, write, erase, etc.

[0070] Address register 12 stores the address information ADD received by semiconductor memory device 3 from memory controller 2. The address information ADD includes, for example, block address BAd, page address PAd, and column address CAd. For example, block address BAd, page address PAd, and column address CAd are used for selecting block BLK, word line, and bit line, respectively.

[0071] The sequencer 13 controls the overall operation of the semiconductor memory device 3. For example, based on the instruction CMD stored in the instruction register 11, the sequencer 13 controls the driver module 14, the line decoder module 15, and the sense amplifier module 16 to perform read operations, write operations, erase operations, etc.

[0072] The driver module 14 generates the voltage used in read operations, write operations, erase operations, etc. Then, the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line, for example, based on the page address PAd stored in the address register 12.

[0073] The row decoder module 15 selects a block BLK within the corresponding memory cell array 10 based on the block address BAd stored in the address register 12. Then, the row decoder module 15 transmits, for example, the voltage applied to the signal line corresponding to the selected word line to the select word line within the selected block BLK.

[0074] During the write operation, the sensing amplifier module 16 applies a desired voltage to each bit line based on the write data DAT received from the memory controller 2. Furthermore, during the read operation, the sensing amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit lines and transmits the determination result as read data DAT to the memory controller 2.

[0075] 1.1.3 Circuit configuration of memory cell array

[0076] use Figure 2The circuit configuration of the memory cell array 10 will be explained. Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array 10. Figure 2 The circuit configuration of a block BLK included in the memory cell array 10 is shown as an example of the circuit configuration of the memory cell array 10. Other block BLKs also have the same... Figure 2 Same composition.

[0077] A block BLK, for example, contains four string cells SU0 to SU3. A string cell SU is, for example, a set of multiple NAND strings NS selected together in a write or read operation. A string cell SU contains multiple NAND strings NS that are associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). A NAND string NS is a set of multiple memory cell transistors MT connected in series.

[0078] The NAND string NS comprises a first string NSa and a second string NSb. The first string NSa is the string for storing data (hereinafter referred to as the "storage string"). The second string NSb is the string for supplying readout current (hereinafter referred to as the "readout string"). The first string NSa includes, for example, memory cell transistors MT0e to MT7e, and select transistors ST1a and ST1b. The second string NSb includes, for example, transistors TR0 to TR7, and select transistors ST2a and ST2b. The memory cell transistor MTe stores data non-volatilely. The memory cell transistor MTe includes a control gate and a charge storage layer. Transistors TR0 to TR7, and select transistors ST1a, ST1b, ST2a, and ST2b are switching elements. Select transistors ST1a and ST2a are used to select the string cell SU during various operations.

[0079] In the NAND string NS, memory cell transistors MT0e to MT7e are connected in series. One end of the series-connected memory cell transistors MT0e to MT7e (one end of memory cell transistor MT7e) is connected to the source of select transistor ST1b. The drain of select transistor ST1b is connected to the source of select transistor ST1a. The drain of select transistor ST1a is connected to the associated bit line BL. The other end of the series-connected memory cell transistors MT0e to MT7e (the other end of memory cell transistor MT0e) is connected to the drain of select transistor ST2b. Transistors TR0 to TR7 are connected in series. One end of the series-connected transistors TR0 to TR7 (one end of transistor TR7) is connected to the source of select transistor ST1b. The other end of the series-connected transistors TR0 to TR7 (the other end of transistor TR0) is connected to the drain of select transistor ST2b. The source of select transistor ST2b is connected to the drain of select transistor ST2a. The source of select transistor STab is connected to the source line SL.

[0080] Additionally, in the NAND string NS, one end of the memory cell transistor MT7e is connected to both ends of transistor TR7. One end of transistor TR6 is connected to the other end of memory cell transistor MT7e. One end of memory cell transistor MT6e is connected to the other end of transistor TR6. One end of transistor TR5 is connected to the other end of memory cell transistor MT6e. One end of memory cell transistor MT5e is connected to the other end of transistor TR5. One end of transistor TR4 is connected to the other end of memory cell transistor MT5e. One end of memory cell transistor MT4e is connected to the other end of transistor TR4. One end of transistor TR3 is connected to the other end of memory cell transistor MT4e. One end of memory cell transistor MT3e is connected to the other end of transistor TR3. One end of transistor TR2 is connected to the other end of memory cell transistor MT3e. One end of memory cell transistor MT2e is connected to the other end of transistor TR2. One end of transistor TR1 is connected to the other end of memory cell transistor MT2e. One end of memory cell transistor MT1e is connected to the other end of transistor TR1. One end of transistor TR0 is connected to the other end of memory cell transistor MT1e. One end of memory cell transistor MT0e is connected to the other end of transistor TR0. The drain of select transistor ST2b is connected to the other end of memory cell transistor MT0e.

[0081] In the same memory block (BLK), the control gates of memory cell transistors MT0e to MT7e are all connected to word lines WL0e to WL7e. The gates of transistors TR0 to TR7 are all connected to word lines WL0o to WL7o. The gates of each selection transistor ST1a in serial cells SU0 to SU3 are connected to selection gate decoding lines SGD0a to SGD3a. Hereinafter, without distinguishing between selection gate decoding lines SGD0a to SGD3a, they will be abbreviated as selection gate decoding line SGDa. The gates of each selection transistor ST1b in serial cells SU0 to SU3 are connected to selection gate decoding lines SGD0b to SGD3b. Additionally, selection gate decoding line SGD0b is connected to selection gate decoding line SGD0a. Selection gate decoding line SGD1b is connected to selection gate decoding line SGD1a. Selection gate decoding line SGD2b is connected to selection gate decoding line SGD2a. Selection gate decoding line SGD3b is connected to selection gate decoding line SGD3a. Hereinafter, without distinguishing between select gate decoding lines SGD0b to SGD3b, they will be abbreviated as select gate decoding line SGDb. The gate of select transistor ST2a contained in the same BLK is connected to select gate decoding line SGSa. The gate of select transistor ST2b contained in the same BLK is connected to select gate decoding line SGSb. In addition, select gate decoding line SGSb is connected to select gate decoding line SGSa.

[0082] In the circuit configuration of the memory cell array 10 described above, for example, multiple NAND strings NS in multiple string cells SU that are assigned the same column address CA share a bit line BL. For example, multiple blocks BLK share a source line SL.

[0083] A collection of multiple memory cell transistors MT connected to a common word line WL within a string cell SU is, for example, called a cell set CU. A block BLK contains multiple cell sets CU. The data stored in a cell set CU, which contains multiple memory cell transistors MT that each store 1 bit of data according to a threshold voltage, is equivalent to 1 page of data. Based on the number of bits of data stored by the memory cell transistors MT, a cell set CU can store more than 2 pages of data. In this embodiment, the memory cell transistor MT is represented by any of the following: SLC (Single Level Cell) storing 1 bit of data, MLC (MultiLevel Cell) storing 2 bits of data, TLC (Triple Level Cell) storing 3 bits of data, or QLC (Quad Level Cell) storing 4 bits of data, but other numbers of bits can also be stored.

[0084] Furthermore, the circuit configuration of the memory cell array 10 is not limited to the configuration described above. For example, the number of string cells SU contained in the block BLK, the number of memory cell transistors MT, transistors TR, and selection transistors ST1 and ST2 contained in the NAND string NS can each be arbitrary.

[0085] 1.1.4 Structure of Storage Cell Array

[0086] The structure of the memory cell array 10 will be described. The memory cell array 10 is disposed above the substrate. Hereinafter, the plane parallel to the front surface of the substrate will be defined as the XY plane. The directions that intersect each other in the XY plane will be defined as the X direction and the Y direction. The direction from the substrate toward the memory cell array 10 will be defined as the Z direction. That is, the Z direction is the direction that intersects with the Y direction and the Y direction. The Z direction can also be replaced by the upward direction.

[0087] 1.1.4.1 Planar Layout of Storage Cell Array

[0088] The planar layout of the storage cell array is described. Figure 3 This is a top view showing an example of the planar layout of the storage cell array 10. Figure 3 This shows a top view of a layer (layer) in a block BLK that is approximately equal in height to the substrate (i.e., in the Z direction). Figure 3 The part shown corresponds to Figure 2 The circuit diagram shown contains one NAND string NS.

[0089] like Figure 3 As shown, on the same level, the memory cell array 10 includes semiconductor CPS, wiring LBI, source line SL, multiple insulators INS, multiple conductive pillars CGP, SGP and TRP, multiple memory structures MS, and multiple contact plugs BC.

[0090] A semiconductor CPS is a semiconductor extended in the XY plane. A semiconductor CPS may contain, for example, polysilicon. The semiconductor CPS has a linear shape extending along the Y direction. One end of the semiconductor CPS in the Y direction is connected to the wiring line LBI. The other end of the semiconductor CPS in the Y direction is connected to the source line SL. The semiconductor CPS functions as a channel for a NAND string NS.

[0091] A wiring LBI is a conductor that extends along the X direction. The wiring LBI is connected to the bit line BL (not shown).

[0092] The source line SL is a conductor that extends along the X direction.

[0093] The insulator INS is an insulator that extends along the Y direction. The insulator INS may contain, for example, silicon oxide. The insulator INS is disposed in the region between the wiring LBI and the source line SL. Figure 3 The example shows two insulators INS arranged separately in the X direction. The semiconductor CPS is located between the two insulators INS.

[0094] Multiple conductive posts (CGP, SGP, and TRP) and multiple contact plugs (BC) extend along the Z-direction, intersecting with the insulator (INS) and the semiconductor (CPS). The conductive posts (CGP, SGP, and TRP) and contact plugs (BC) are positioned on the left and right sides of the semiconductor CPS in the region between the wiring line (LBI) and the source line (SL). Hereinafter, the left side of the semiconductor CPS will be referred to as the "front side of the semiconductor CPS" or "the first side of the semiconductor CPS in the X-direction." The right side of the semiconductor CPS will be referred to as the "back side of the semiconductor CPS" or "the second side of the semiconductor CPS in the X-direction."

[0095] On the front side of the semiconductor CPS, a first string of NSa is arranged. Within this first string of NSa, for example, along the Y direction, starting from the top of the paper, two conductive pillars SGP, eight conductive pillars CGP, and one contact plug BC are arranged sequentially. The two conductive pillars SGP, eight conductive pillars CGP, and one contact plug BC are separated from each other in the Y direction. Hereinafter, the two conductive pillars SGP will be referred to as conductive pillars SGP0e and SGP1e, respectively, starting from the top of the paper. The eight conductive pillars CGP will be referred to as conductive pillars CGP0e to CGP7e, respectively, starting from the bottom of the paper.

[0096] On the back side of the semiconductor CPS, a second string of NSb is arranged. Within this second string of NSb, for example along the Y direction, starting from the top of the paper, one contact plug BC, eight conductive posts TRP, and two conductive posts SGP are arranged sequentially. The contact plug BC, the eight conductive posts TRP, and the two conductive posts SGP are separated from each other in the Y direction. Hereinafter, the eight conductive posts TRP will be designated as conductive posts TRP0 to TRP7, starting from the bottom of the paper. The two conductive posts SGP will be designated as conductive posts SGP0o and SGP1o, starting from the bottom of the paper.

[0097] Viewed from above (Z direction), the centers of the multiple conductive pillars CGP, SGP, and TRP, as well as the multiple contact plugs BC, are staggered in the Y direction. In other words, the multiple conductive pillars CGP, SGP, and TRP, as well as the multiple contact plugs BC, are arranged in a grid pattern, for example, in 22 columns, in the area between the wiring LBI and the source line SL.

[0098] The multiple conductive pillars CGP and SGP on the front side of the semiconductor CPS, as well as the contact plug BC, are described.

[0099] A portion of the side of the conductive pillar CGP (the portion of the side facing the semiconductor CPS) is connected to one of the two sides of the memory structure MS facing the semiconductor CPS. The other of the two sides of the memory structure MS facing the semiconductor CPS is connected to the semiconductor CPS. That is, a portion of the side of the conductive pillar CGP is connected to the semiconductor CPS via the memory structure MS. The portion of the side of the conductive pillar CGP that is not connected to the memory structure MS is connected to the insulator INS.

[0100] The conductive pillar CGP comprises a conductive film 30 and an insulating film 31. The conductive film 30 may contain, for example, tungsten, titanium nitride, or a combination of both. The conductive film 30 functions as a word line (WL). The insulating film 31 surrounds the sides of the conductive film 30. The insulating film 31 may contain, for example, silicon oxide. The insulating film 31 functions as a barrier insulating film. Furthermore, the insulating film 31 may also be formed from multiple laminated layers.

[0101] The memory structure MS includes a charge storage film 32 and an insulating film 33. The charge storage film 32 covers a portion of the side surface of the insulating film 31. The charge storage film 32 contains a material with charge storage functionality. Specifically, the charge storage film 32 may contain a conductor such as silicon or a metal. Alternatively, the charge storage film 32 may also contain an insulator such as silicon nitride. The insulating film 33 covers a portion of the side surface of the charge storage film 32. The insulating film 33 is, for example, silicon oxide. The insulating film 33 functions as a tunneling insulating film. A semiconductor CPS covers a portion of the side surface of the insulating film 33.

[0102] The structure, which includes one conductive pillar CGP, one memory structure MS, and a semiconductor CPS, functions as a memory cell transistor MT. Figure 3 The eight structures shown, from the side of the paper, function sequentially as memory cell transistors MT7e, MT6e, MT5e, MT4e, MT3e, MT2e, MT1e, and MTOe. When the charge storage film 32 contains a conductor such as silicon or metal, the memory cell transistor MT functions as a floating gate type memory cell transistor MT. When the charge storage film 32 contains an insulator such as silicon nitride, the memory cell transistor MT functions as a MONOS (metal-oxide-nitride-oxide-silicon) type memory cell transistor MT.

[0103] A portion of the side of the conductive post SGP (the portion of the side facing the semiconductor CPS) is connected to the semiconductor CPS. The portion of the side of the conductive post SGP that is not connected to the semiconductor CPS is connected to the insulator INS.

[0104] The conductive pillar SGP includes a conductive film 40 and an insulating film 41. The conductive film 40 may contain, for example, tungsten, titanium nitride, or a combination of both. The conductive film 40 functions as a select gate decoder line (SGD). The insulating film 41 surrounds the sides of the conductive film 40. The insulating film 41 may contain, for example, silicon oxide. Alternatively, the insulating film 41 may be formed from multiple laminated layers.

[0105] The structure comprising a conductive pillar SGP and a semiconductor CPS functions as a selection transistor ST. Figure 3 The two structures shown, starting from the side of the paper, function as selection transistors ST1a and ST1b, respectively.

[0106] Thus, the first NSa includes selection transistors ST1a and ST1b, which are arranged separately in the Y direction using semiconductor CPS as channels, and memory cell transistors MT0e to MT7e.

[0107] A portion of the side of the contact plug BC (the portion of the side facing the semiconductor CPS) is in contact with the semiconductor CPS. The portion of the side of the contact plug BC that is not in contact with the semiconductor CPS is in contact with the insulator INS.

[0108] The contact plug BC includes a conductive film 60 and a semiconductor film 61. The conductive film 60 includes, for example, tungsten, titanium nitride, or tungsten and titanium nitride. The semiconductor film 61 surrounds the sides of the conductive film 60. The semiconductor film 61 includes, for example, polycrystalline silicon with P-type impurities. The contact plug BC functions, for example, as a hole supply source for injecting holes into the charge storage film 32 of the memory cell transistor MT during an erase operation.

[0109] The structure comprising a semiconductor CPS, two conductive pillars SGP on the front side of the semiconductor CPS, eight conductive pillars CGP, eight memory structures MS, and one contact plug BC corresponds to the first string NSa.

[0110] The conductive pillars TRP and SGP on the back side of the semiconductor CPS, as well as the contact plug BC, are described.

[0111] A portion of the side of the conductive pillar TRP (the portion of the side facing the semiconductor CPS) is connected to the semiconductor CPS. The portion of the side of the conductive pillar TRP that is not connected to the semiconductor CPS is connected to the insulator INS.

[0112] The conductive pillar TRP comprises a conductive film 50 and an insulating film 51. The conductive film 50 may contain, for example, tungsten, titanium nitride, or a combination of both. The conductive film 50 functions as a word line (WL). The insulating film 51 surrounds the sides of the conductive film 50. The insulating film 51 may contain, for example, silicon oxide. Furthermore, the insulating film 51 may also be formed from multiple laminated layers. Additionally, the conductive pillar TRP may have the same structure as the conductive pillar SGP, or it may have a different structure.

[0113] The structure comprising a conductive pillar TRP and a semiconductor CPS functions as a transistor TR. Figure 3 The eight structures shown, starting from the side of the paper, function as transistors TR7, TR6, TR5, TR4, TR3, TR2, TR1, and TR0, respectively.

[0114] A portion of the side of the conductive post SGP (the portion of the side facing the semiconductor CPS) is connected to the semiconductor CPS. The portion of the side of the conductive post SGP that is not connected to the semiconductor CPS is connected to the insulator INS. The conductive post SGP has the same structure as the conductive post SGP on the front side of the semiconductor CPS. The conductive film 30 functions as the select gate decoding line SGS.

[0115] The structure comprising a conductive pillar SGP and a semiconductor CPS functions as a selection transistor ST. Figure 3 The two structures shown, starting from the side of the paper, function as selection transistors ST2b and ST2a respectively.

[0116] Thus, the second string NSb includes transistors TR0 to TR7, which are arranged separately in the Y direction using semiconductor CPS as channels, and selection transistors ST2a and ST2b. Alternatively, transistors TR0 to TR7 may have the same structure as selection transistors ST1a, ST1b, ST2a, and ST2b.

[0117] A portion of the side of the contact plug BC (the portion of the side facing the semiconductor CPS) is in contact with the semiconductor CPS. The portion of the side of the contact plug BC that is not in contact with the semiconductor CPS is in contact with the insulator INS. The contact plug BC has the same structure as the contact plug BC on the front side of the semiconductor CPS.

[0118] The structure comprising a semiconductor CPS, two conductive pillars SGP on the back side of the semiconductor CPS, eight conductive pillars TRP, and one contact plug BC corresponds to the second string NSb.

[0119] Multiple NAND strings NS connected to the same bit line BL are configured to be separated from each other in the X direction, for example, in the region between the wiring LBI and the source line SL. Figure 3 The structure shown is more specifically, a structure comprising a semiconductor CPS, a front-side structure of the semiconductor CPS (2 conductive pillars SGP, 8 conductive pillars CGP, 8 memory structures MS and 1 contact plug BC), and a back-side structure of the semiconductor CPS (1 contact plug BC, 8 conductive pillars TRP and 2 conductive pillars SGP) (hereinafter referred to as "the first structure") is arranged separately from each other in the X direction.

[0120] Furthermore, multiple NAND strings NS connected to the same bit line BL can, for example, be configured in the region between the wiring LBI and the source line SL, with the first structure and a structure formed by swapping the front and back sides of the semiconductor CPS in the first structure (hereinafter referred to as "the second structure") arranged alternately and separated from each other in the X direction. In this case, the first structure and the second structure adjacent in the X direction can also share the conductive post CGP. The shared conductive post CGP can drive the two memory cell transistors MT on the first structure side and the second structure side.

[0121] 1.1.4.2 Three-dimensional structure of storage cell array

[0122] The three-dimensional structure of the memory cell array 10 will be described. The three-dimensional structure of the memory cell array 10 has cells arranged separately in the Z direction. Figure 3 The diagram shows a planar layout structure, where multiple NAND strings (NS) are arranged and separated from each other in the Z direction.

[0123] 1.1.4.3 Cross-sectional structure of the conductive post CGP

[0124] Figure 4 yes Figure 3 The cross-sectional view along line IV-IV shows an example of the cross-sectional structure of the memory cell array 10.

[0125] like Figure 4 As shown, the memory cell array 10 includes a substrate 20, insulating layers 21 and 23, a semiconductor layer 22, an insulator 34, conductive pillars CGP, and a memory structure MS.

[0126] The substrate 20 is, for example, a P-type semiconductor. An insulating layer 21 is disposed on the upper surface of the substrate 20. The substrate 20 and the insulating layer 21 may also contain circuitry (not shown). The circuitry contained in the substrate 20 and the insulating layer 21 may correspond to, for example, the line decoder module 15, the sense amplifier module 16, etc.

[0127] On the upper surface of the insulating layer 21, multiple semiconductor layers 22 and multiple insulating layers 23 are stacked alternately, one layer at a time. Figure 4 In this example, five semiconductor layers 22 and five insulating layers 23 are stacked alternately, one layer at a time. In other words, a plurality of semiconductor layers 22 are stacked and spaced apart in the Z direction above the substrate 20. The number of semiconductor layers 22 stacked corresponds, for example, to the number of bit lines BL connected to a wiring LBI.

[0128] Semiconductor layer 22 corresponds to semiconductor CPS and has a portion extending along the Y direction. The portion of semiconductor layer 22 extending along the Y direction (i.e., Figure 4 The portion shown in the diagram functions as a channel for the NAND string NS. Insulator layers 21 and 23, for example, contain silicon oxide. Semiconductor layer 22, for example, contains polysilicon.

[0129] Insulator 34 corresponds to insulator INS and has a portion extending in the XY plane on the same level as semiconductor layer 22.

[0130] The conductive post CGP extends along the Z-direction, intersecting with multiple semiconductor layers 22 and insulating layers 23. For example, the lower end of the conductive post CGP reaches the insulating layer 21. The upper end of the conductive post CGP is aligned with the upper end of the uppermost insulating layer 23. The conductive post CGP is electrically connected to the line decoder module 15 via the conductor (not shown) disposed above, thereby functioning as a word line WL.

[0131] The memory structure MS is located on the same level as the semiconductor layer 22.

[0132] On the same level as semiconductor layer 22, a portion of the side of the conductive pillar CGP is in contact with insulator 34. The portion of the side of the conductive pillar CGP on the same level as semiconductor layer 22 that is not in contact with insulator 34 is in contact with memory structure MS.

[0133] The conductive film 30 of the conductive pillar CGP extends along the Z direction. For example, the lower end of the conductive film 30 is located below the lowest semiconductor layer 22. The upper end of the conductive film 30 is aligned with the upper end of the highest insulating layer 23. The insulating film 31 of the conductive pillar CGP covers the periphery of the conductive film 30 except for the upper surface.

[0134] The charge storage film 32 of the memory structure MS covers a portion of the side surface of the insulating film 31 at the same level as the semiconductor layer 22. The insulating film 33 of the memory structure MS covers a portion of the side surface of the charge storage film 32 at the same level as the semiconductor layer 22. The insulating film 33 is in contact with the semiconductor layer 22.

[0135] 1.1.4.4 Cross-sectional structure of conductive post SGP

[0136] Figure 5 yes Figure 3 The cross-sectional view along the V-V line shows an example of the cross-sectional structure of the memory cell array 10.

[0137] like Figure 5 As shown, the memory cell array 10 also includes conductive pillars (SGPs). The structure other than the conductive pillars (SGPs) is similar to... Figure 4 The structures shown are identical, therefore explanations are omitted.

[0138] The conductive post SGP extends along the Z-direction, intersecting with multiple semiconductor layers 22 and insulating layers 23. For example, the lower end of the conductive post SGP reaches the insulating layer 21. The upper end of the conductive post SGP is aligned with the upper end of the uppermost insulating layer 23. The conductive post SGP is electrically connected to the line decoder module 15 via the conductor (not shown) disposed above, thereby functioning as a select gate decoding line (SGD).

[0139] On the same level as semiconductor layer 22, a portion of the side surface of the conductive pillar SGP is in contact with insulator 34. The portion of the side surface of the conductive pillar SGP on the same level as semiconductor layer 22 that is not in contact with insulator 34 is in contact with semiconductor layer 22.

[0140] The conductive film 40 of the conductive pillar SGP extends along the Z direction. For example, the lower end of the conductive film 40 is located below the lowest semiconductor layer 22. The upper end of the conductive film 40 is aligned with the upper end of the highest insulating layer 23. The insulating film 41 of the conductive pillar SGP covers the periphery of the conductive film 40 except for the upper surface.

[0141] 1.1.4.5 Cross-sectional structure of conductive post TRP

[0142] Figure 6 yes Figure 3 The cross-sectional view along line VI-VI shows an example of the cross-sectional structure of the memory cell array 10.

[0143] like Figure 6 As shown, the memory cell array 10 also includes conductive pillars (TRPs). The structure other than the conductive pillars (TRPs) is similar to... Figure 4 The structures shown are identical, therefore explanations are omitted.

[0144] The conductive pillars (TRPs) extend along the Z-direction, intersecting with multiple semiconductor layers 22 and insulating layers 23. For example, the lower end of the conductive pillar TRP reaches the insulating layer 21. The upper end of the conductive pillar TRP is aligned with the upper end of the uppermost insulating layer 23. The conductive pillar TRP is electrically connected to the line decoder module 15 via the conductors (not shown) disposed above, thereby functioning as word lines (WL).

[0145] On the same level as semiconductor layer 22, a portion of the side surface of the conductive pillar TRP is in contact with insulator 34. The portion of the side surface of the conductive pillar TRP on the same level as semiconductor layer 22 that is not in contact with insulator 34 is in contact with semiconductor layer 22.

[0146] The conductive film 50 of the conductive pillar TRP extends along the Z direction. For example, the lower end of the conductive film 50 is located below the lowest semiconductor layer 22. The upper end of the conductive film 50 is aligned with the upper end of the highest insulating layer 23. The insulating film 51 of the conductive pillar TRP covers the periphery of the conductive film 50 except for the upper surface.

[0147] 1.1.4.6 Cross-sectional structure of the contact plug BC

[0148] Figure 7 yes Figure 3 The cross-sectional view along line VII-VII shows an example of the cross-sectional structure of the memory cell array 10.

[0149] like Figure 7 As shown, the memory cell array 10 also includes contact plugs BC. The structure other than the contact plugs BC is similar to... Figure 4 The structures shown are identical, therefore explanations are omitted.

[0150] The contact plug BC extends along the Z direction, intersecting with the plurality of semiconductor layers 22 and insulating layers 23. For example, the lower end of the contact plug BC reaches the insulating layer 21. The upper end of the contact plug BC is aligned with the upper end of the uppermost insulating layer 23. The contact plug BC functions as a contact plug for supplying voltage to the conductive film 60 via a conductor (not shown) disposed above.

[0151] On the same level as semiconductor layer 22, a portion of the side of the contact plug BC is in contact with insulator 34. The portion of the side of the contact plug BC on the same level as semiconductor layer 22 that is not in contact with insulator 34 is in contact with semiconductor layer 22.

[0152] The conductive film 60 of the contact plug BC extends along the Z direction. For example, the lower end of the conductive film 60 is located below the lowest semiconductor layer 22. The upper end of the conductive film 60 is aligned with the upper end of the highest insulating layer 23. The semiconductor film 61 of the contact plug BC covers the periphery of the conductive film 60 except for the upper surface.

[0153] 1.2 Write Action

[0154] First, a summary of the write operation will be provided.

[0155] The write operation includes programming and verification operations. Furthermore, by repeating the programming loop that includes programming and verification operations, the threshold voltage of the memory cell transistor MT will rise to the target level.

[0156] Programming is an action that raises the threshold voltage by injecting electrons into the charge storage film (or keeps the threshold voltage constant by inhibiting injection). Hereinafter, the action of raising the threshold voltage is referred to as "'0' programming". A voltage (e.g., voltage VSS) for "0" programming is applied from the sense amplifier module 16 to the bit line BL, which is the target of "0" programming. The action of keeping the threshold voltage constant is referred to as "'1' programming" or "inhibiting writing". A voltage for "1" programming is applied from the sense amplifier module 16 to the bit line BL, which is the target of "1" programming.

[0157] The verification process, following the programming step, involves reading data and determining whether the threshold voltage of the memory cell transistor MT has reached the target level. If the threshold voltage of the memory cell transistor MT has reached the target level, subsequent write operations will be disabled.

[0158] Next, the write operation of the semiconductor memory device 3 according to the first embodiment will be described. The write operation of the semiconductor memory device 3 according to this embodiment includes a write operation for a storage string (hereinafter referred to as "first write operation").

[0159] For example, when the memory controller 2 receives a write request from the host, the write operation begins, and the memory controller 2 instructs the semiconductor storage device 3 to perform the first write operation.

[0160] Next, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2. More specifically, in the selection block BLK, the memory cell transistor MT corresponding to the conductive pillar CGP functioning as the selection word line WL within all the first string NSa within the string cell SU corresponding to the selected selection gate decoding line SGDa is repeatedly programmed in a loop. Hereinafter, the conductive pillar CGP functioning as the selection word line WL will be referred to as "selection CG pillar CGPsel". The conductive pillar CGP functioning as the non-selection word line WL will be referred to as "non-selection CG pillar CGPusel".

[0161] During the first write operation, in the programming operation, a voltage VPGMe is applied to the conductive film 30 of the select CG pillars CGPsel in all first-string NSa within the select string cell SU. The voltage VPGMe is a high voltage capable of raising the threshold voltage of the memory cell transistor MT. The voltage VPGMe increases, for example, as the programming cycle repeats.

[0162] In this state, the sensing amplifier module 16 applies a voltage VSS to the bit line BL, which is programmed as "0", and a power supply voltage VCC to the bit line BL, which is programmed as "1". That is, the voltage VSS or voltage VCC is applied to the wiring BLI via the bit line BL.

[0163] Then, in the selection string unit SU, data is written to the memory cell transistor MT corresponding to the selection CG pillar CGPsel in all the first string NSa connected to the bit line BL, which is programmed as "0". On the other hand, the data in the memory cell transistor MT corresponding to the selection CG pillar CGPsel in all the first string NSa connected to the bit line BL, which is programmed as "1", is maintained.

[0164] After the programming action is performed, the verification action is performed. The programming loop is then repeated in the same way. In the selection string unit SU, the programming loop for the memory cell transistor MT corresponding to the selection CG pillar CGPsel in all the memory cells MT in the first string NSA is disabled from writing.

[0165] For example, in the first NSa string, conductive posts CGP0e to CGP7e are selected in the order of CGP7e, CGP6e, ..., CGP1e, CGP0e. The first write operation ends when the programming loop for each conductive post CGP is completed. Thus, write data is written to the first NSa string. The write operation ends when the first write operation is completed.

[0166] 1.3 Reading Action

[0167] The readout operation of the semiconductor memory device 3 according to the first embodiment will be described. The readout operation of the semiconductor memory device 3 according to this embodiment includes a first readout operation. In the first readout operation, cell current is not allowed to flow in the memory cell transistor MT corresponding to the non-selection CG pillar CGPsel and the transistor TR corresponding to the conductive pillar TRP located near the selection CG pillar CGPsel, while cell current is allowed to flow in the transistor TR corresponding to the conductive pillar TRP not located near the selection CG pillar CGPsel.

[0168] For example, when the memory controller 2 receives a read request from the host, the read operation begins, and the memory controller 2 instructs the semiconductor storage device 3 to perform the first read operation.

[0169] Next, the sequencer 13 performs the first read operation based on the instruction received from the memory controller 2. Figure 8 This is a diagram showing the voltage of each wire during the first readout operation. Figure 8 The example illustrates a scenario where, in the selection block BLK, multiple memory cell transistors MT4e within the selection string unit SU are selected as read targets, and the memory cell transistors MT4e within one NAND string NS are turned on.

[0170] like Figure 8 As shown, during the first readout operation, the following voltages are applied to each conductive post SGP and CGP in the first NSa string through the line decoder module 15.

[0171] For example, a voltage VSG is applied to the conductive film 40 of the conductive pillar SGP0e, which functions as the select gate decoding line SGDa, and the conductive pillar SGP1e, which functions as the select gate decoding line SGDb. The voltage VSG is a voltage that turns on the select transistor ST1, independent of the voltage of the corresponding bit line BL. Hereinafter, the conductive pillar SGP, which functions as the selected select gate decoding line SGDa, will be referred to as "select SG pillar SGPsel". For example, a voltage VCGRV is applied to the conductive film 30 of the conductive pillar CGP4e (select CG pillar CGPsel), which functions as the word line WL4e (select word line WL). The voltage VCGRV is a readout voltage corresponding to the threshold voltage level for reading data. For example, a voltage Vcut is applied to the conductive film 30 of the conductive pillars CGP0e~CGP3e and CGP5e~CGP7e, which function as word lines WL0e~WL3e and WL5e~WL7e (non-select word lines WL), respectively. The voltage Vcut is the voltage that turns off the memory cell transistors MT and TR, regardless of the threshold voltage. For example, the voltage Vcut can also be a negative voltage.

[0172] In addition, during the first read operation, the following voltages are applied to each conductive post SGP and TRP in the NAND string NSb through the row decoder module 15.

[0173] A voltage VSG is applied, for example, to the conductive films 40 of the conductive pillars SGP0o and SGP1o, which function as select gate decoding lines SGSa and SGSb, respectively. A voltage Vcut is applied, for example, to the conductive films 50 of the conductive pillars TRP3 and TRP4, which function as word lines WL3o and WL4o, respectively. Conductive pillars TRP3 and TRP4 are conductive pillars TRP located on the back side of the semiconductor CPS and near the select CG pillar CGPsel in the X direction. More specifically, conductive pillars TRP3 and TRP4 are two conductive pillars TRP on the back side of the semiconductor CPS, located at positions closest in the +Y and -Y directions to the position opposite to the select CG pillar CGPsel on the front side of the semiconductor CPS in the X direction, respectively. Hereinafter, the conductive pillar located on the opposite side of the select CG pillar CGPsel in the X direction and near the select CG pillar CGPsel of the semiconductor CPS will be referred to as the "cut-off pillar Pcut". A voltage Vread is applied, for example, to the conductive films 50 of the conductive pillars TRP0-TRP2 and TRP5-TRP7, which function as word lines WL0o-WL2o and WL5o-WL7o, respectively. The voltage Vread is the voltage that turns on the transistor TR, regardless of the threshold voltage. The voltage Vread is higher than the voltage VCGRV. Hereinafter, conductive pillars that are not located on the opposite side of the selection CG pillar CGPsel in the X direction but are near the selection CG pillar CGPsel are referred to as "non-cut pillars Pucut".

[0174] In this state, the sensing amplifier module 16 applies a voltage Vbl to the bit line BL, which is the readout target. That is, the voltage Vbl is applied to the wiring BLI via the bit line BL. Additionally, a voltage VSS is applied to the source line SL. The voltage Vbl is a voltage higher than the voltage VSS.

[0175] In a semiconductor CPS, a conductive region, or channel region, is formed near the portions of the conductive posts SGP (SGP0e, SGP1e, SGP0o, and SGP1o) where a voltage VSG is applied. No conductive region is formed near the portions of the conductive posts CGP and TRP (CGP0e-CGP3e, CGP5e-CGP7e, TRP3, and TRP4) where a voltage Vcut is applied. A conductive region is formed near the portions of the conductive posts TRP (TRP0-TRP2 and TRP5-TRP7) where a voltage Vread is applied. A conductive region is formed near the portion of the conductive post CGP (CGP4e) where a voltage VCGRV is applied, when the selected memory cell transistor MT4e is in the ON state. No conductive region is formed when the selected memory cell transistor MT4e is in the OFF state.

[0176] Furthermore, because the width (distance in the X direction) of the semiconductor CPS is relatively small, a conductive region is also formed between the conductive region formed near the conductive pillar SGP1e and the conductive region formed near the conductive pillar TRP7 in the semiconductor CPS. When the selection cell transistor MT4e is in the ON state, conductive regions are also formed between the conductive region formed near the conductive pillar TRP5 and the conductive region formed near the selection CG pillar CGPsel, and between the conductive region formed near the selection CG pillar CGPsel and the conductive region formed near the conductive pillar TRP2.

[0177] Because the semiconductor film 61 of the contact plug BC (e.g., polycrystalline silicon containing P-type impurities) is in contact with the semiconductor CPS, no conductive region is formed in the semiconductor CPS near the portion in contact with the contact plug BC.

[0178] Therefore, when the memory cell transistor MT4e is selected to be in the ON state, such as Figure 8 As shown, the wiring LBI is electrically connected to the source line SL through the conduction region of the semiconductor CPS. Therefore, electron current flows from the wiring LBI to the source line SL. When the selection memory cell transistor MT4e is in the off state, the wiring LBI is not electrically connected to the source line SL. Therefore, in the selection string cell SU, the data of all memory cell transistors MT corresponding to the selection CG pillar CGPsel in the first string NSA are read out together.

[0179] For example, in the first NSa string, the conductive posts CGP0e to CGP7e are selected in the order of CGP7e, CGP6e, ..., CGP1e, CGP0e. When the reading for each conductive post CGP is completed, the first read operation ends. Thus, the read operation ends.

[0180] Furthermore, when the memory cell transistor MT7e is the read target, a voltage VSG is applied, for example, to the conductive film 40 of each of the conductive pillars SGP0e, SGP1e, SGP0o, and SGP1o. A voltage VCGRV is applied, for example, to the conductive film 30 of the conductive pillar CGP7e (selected CG pillar CGPsel). A voltage Vcut is applied, for example, to the conductive film 30 of each of the conductive pillars CGP0e to CGP6e, and to the conductive film 50 of each of the conductive pillars TRP6 and TRP7. A voltage Vread is applied, for example, to the conductive film 50 of each of the conductive pillars TRP0 to TRP5.

[0181] Furthermore, when the memory cell transistor MT0e is the read target, a voltage VSG is applied, for example, to the conductive film 40 of each of the conductive pillars SGP0e, SGP1e, SGP0o, and SGP1o. A voltage VCGRV is applied, for example, to the conductive film 30 of the conductive pillar CGP0e (selected CG pillar CGPsel). A voltage Vcut is applied, for example, to the conductive film 30 of each of the conductive pillars CGP1e to CGP7e and the conductive film 50 of the conductive pillar TRP0. A voltage Vread is applied, for example, to the conductive film 50 of each of the conductive pillars TRP1 to TRP7.

[0182] 1.4 Effects of this implementation method

[0183] During the read operation, if a voltage Vread is applied to the non-select word line WL, which is connected in series with the select word line WL, read interference may occur. In this case, the cell withstand capability of the memory cell transistor MT corresponding to the non-select word line WL may decrease.

[0184] To address this, the semiconductor memory device 3 of this embodiment includes a plurality of NAND strings arranged separately from each other in the Z direction. Each NAND string NS includes: a semiconductor CPS extending in the Y direction; a first string NSa disposed on the front side of the semiconductor CPS; and a second string NSb disposed on the back side of the semiconductor CPS. The first string NSa includes select transistors ST1a and ST1b, arranged separately from each other in the Y direction with the semiconductor CPS as a channel, and memory cell transistors MT0e to MT7e. The second string NSb includes transistors TR0 to TR7, arranged separately from each other in the Y direction with the semiconductor CPS as a channel, and select transistors ST2a and ST2b.

[0185] Thus, in the semiconductor memory device 3 of this embodiment, in the NAND string NS, the first string NSa and the second string NSb are arranged apart by the semiconductor CPS, and the first string NSa is used as the storage string and the second string NSb is used as the read string.

[0186] Because it has the aforementioned structure, it can be used as described. Figure 8As described above, during the read operation, in the first NSa string, the cell current can be allowed to flow in the memory cell transistor MT corresponding to the select CG pillar CGPsel, while the cell current cannot flow in the memory cell transistor MT corresponding to the non-select CG pillar CGPusel. Furthermore, in the second NSb string, the cell current cannot flow in the memory cell transistor MT corresponding to the cut-off pillar Pcut, while the cell current can flow in the memory cell transistor MT corresponding to the non-cut-off pillar Pucut. Thus, the cell current cannot flow in the memory cell transistor MT corresponding to the non-select CG pillar CGPusel. Therefore, the semiconductor memory device 3 according to this embodiment can realize a memory cell with high readability.

[0187] Furthermore, since no cell current flows in the memory cell transistor MT corresponding to the two cut-off pillars Pcut located on the back side of the semiconductor CPS and near the selected CG pillar CGPsel, the data of the memory cell transistor MT corresponding to the selected CG pillar CGPsel can be read appropriately.

[0188] Furthermore, since the second string NSb is equipped with a transistor TR that has a higher performance than the memory cell transistor MT, it is easy to obtain the cell current.

[0189] Furthermore, if the conductive pillar TRP in the second NSb is made to have the same structure as the conductive pillar SGP, then the conductive pillar TRP and SGP can be formed simultaneously in the manufacturing process.

[0190] 1.5 Variation Example

[0191] A variation of the semiconductor memory device 3A according to the first embodiment will be described. In this variation of the semiconductor memory device 3A, the circuit configuration of the memory cell array 10A, the planar layout of the memory cell array 10A, and the readout operation are different from those of the first embodiment. Hereinafter, the description will focus on the differences from the first embodiment.

[0192] 1.5.1 Circuit configuration of memory cell array

[0193] use Figure 9 The circuit configuration of the memory cell array 10A will be explained. Figure 9 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array 10A. Figure 9 The circuit configuration of a block BLK included in the memory cell array 10A is shown as an example of the circuit configuration of the memory cell array 10A. Other block BLKs also have similar characteristics. Figure 9 Same composition.

[0194] The first string NSa includes, for example, memory cell transistors MT0e to MT7e, and select transistors ST1a, ST1b, and ST2c. The second string NSb includes, for example, transistors TR0 to TR7, and select transistors ST2a, ST2b, and ST1c. Select transistors ST1c and ST2c are switching elements.

[0195] In the NAND string NS, memory cell transistors MT0e to MT7e are connected in series. One end of the series-connected memory cell transistors MT0e to MT7e (one end of memory cell transistor MT7e) is connected to the source of select transistor ST1b. The drain of select transistor ST1b is connected to the source of select transistor ST1a. The drain of select transistor ST1a is connected to the associated bit line BL. The source of select transistor ST1c is connected to the drain of select transistor ST1b. The drain of select transistor ST1c is connected to the associated bit line BL. The other end of the series-connected memory cell transistors MT0e to MT7e (the other end of memory cell transistor MT0e) is connected to the drain of select transistor ST2b. Transistors TR0 to TR7 are connected in series. One end of the series-connected transistors TR0 to TR7 (one end of transistor TR7) is connected to the source of select transistor ST1b. The other end of the series-connected transistors TR0 to TR7 (the other end of transistor TR0) is connected to the drain of select transistor ST2b. The source of selector transistor ST2b is connected to the drain of selector transistor ST2a. The source of selector transistor ST2a is connected to the source line SL. The drain of selector transistor ST2c is connected to the drain of selector transistor ST2a. The source of selector transistor ST2c is connected to the source line SL.

[0196] Additionally, in the NAND string NS, one end of the memory cell transistor MT6e is connected to one end of transistor TR6. One end of the memory cell transistor MT5e is connected to one end of transistor TR5. One end of the memory cell transistor MT4e is connected to one end of transistor TR4. One end of the memory cell transistor MT3e is connected to one end of transistor TR3. One end of the memory cell transistor MT2e is connected to one end of transistor TR2. One end of the memory cell transistor MT1e is connected to one end of transistor TR1. One end of the memory cell transistor MT0e is connected to one end of transistor TR0.

[0197] In the same BLK, the gates of the selection transistors ST1c within series units SU0 to SU3 are respectively connected to selection gate decoding lines SGD0c to SGD3c. Additionally, selection gate decoding line SGD0c is connected to selection gate decoding line SGD0a. Selection gate decoding line SGD1c is connected to selection gate decoding line SGD1a. Selection gate decoding line SGD2c is connected to selection gate decoding line SGD2a. Selection gate decoding line SGD3c is connected to selection gate decoding line SGD3a. Hereinafter, when there is no need to distinguish between selection gate decoding lines SGD0c to SGD3c, they will be abbreviated as selection gate decoding line SGDc. The gate of the selection transistor ST2c included in the same BLK is connected to selection gate decoding line SGSc. Additionally, selection gate decoding line SGSc is connected to selection gate decoding line SGSa.

[0198] Furthermore, the circuit configuration of the memory cell array 10A is not limited to the configuration described above. For example, the number of string cells SU contained in the block BLK, the number of memory cell transistors MT, transistors TR, and selection transistors ST1 and ST2 contained in the NAND string NS can each be arbitrary.

[0199] 1.5.2 Planar Layout of Storage Cell Array

[0200] Figure 10 This is a top view showing an example of the planar layout of the memory cell array 10A. Figure 10 A top view of layers in a block BLK that are approximately at the same height from the substrate is shown. Figure 10 The part shown corresponds to Figure 9 The circuit diagram shown contains one NAND string NS.

[0201] like Figure 10 As shown, on the same level, the memory cell array 10A includes semiconductor CPS, wiring LBI, source line SL, multiple insulators INS, multiple conductive pillars CGP, SGP and TRP, multiple memory structures MS, and multiple contact plugs BC.

[0202] The planar layout of the semiconductor CPS, wiring LBI, source line SL, and insulator INS is the same as shown in the first embodiment. Figure 3 same.

[0203] On the front side of the semiconductor CPS, a first string of NSa is arranged. Within this first string of NSa, for example along the Y direction, starting from the top of the paper, there are sequentially arranged 2 conductive pillars SGP, 8 conductive pillars CGP, 1 contact plug BC, and 1 conductive pillar SGP. The 2 conductive pillars SGP, 8 conductive pillars CGP, 1 contact plug BC, and 1 conductive pillar SGP are separated from each other in the Y direction. Hereinafter, the 3 conductive pillars SGP will be referred to as conductive pillars SGP0e, SGP1e, and SGP2e, starting from the top of the paper.

[0204] On the back side of the semiconductor CPS, a second string of NSb is arranged. Within this second string of NSb, for example along the Y direction, starting from the top of the paper, are arranged one conductive post SGP, one contact plug BC, eight conductive posts TRP, and two conductive posts SGP. The one conductive post SGP, the one contact plug BC, the eight conductive posts TRP, and the two conductive posts SGP are separated from each other in the Y direction. Hereinafter, the three conductive posts SGP will be referred to as conductive posts SGP0o, SGP1o, and SGP2o, starting from the bottom of the paper.

[0205] Viewed from above, the two conductive pillars SGP, eight conductive pillars CGP, one contact plug BC, and one conductive pillar SCP on the front side of the semiconductor CPS are facing each other in the X direction, as are the one conductive pillar SGP, eight conductive pillars TRP, one contact plug BC, and two conductive pillars SCP on the back side of the semiconductor CPS.

[0206] On the front side of the semiconductor CPS, the conductive pillar SGP2e has the same structure as the other conductive pillars SGP. The structure of the two conductive pillars SGP besides SGP2e, the eight conductive pillars CGP, and the one contact plug BC is the same as shown in the first embodiment. Figure 3 The same. The structure comprising a semiconductor CPS, three conductive pillars SGP on the front side of the semiconductor CPS, eight conductive pillars CGP, eight memory structures MS, and one contact plug BC corresponds to the first string NSa.

[0207] On the back side of the semiconductor CPS, the conductive post SGP2o has the same structure as the other conductive posts SGP. The structure of the two conductive posts SGP besides SGP2o, the eight conductive posts TRP, and the one contact plug BC is the same as shown in the first embodiment. Figure 3 Same. The structure comprising a semiconductor CPS, three conductive pillars SGP on the back side of the semiconductor CPS, eight conductive pillars TRP, and one contact plug BC corresponds to the second string NSb.

[0208] Multiple NAND strings NS connected to the same bit line BL are configured, for example, in the same way as in the first embodiment.

[0209] 1.5.3 Three-dimensional structure of storage cell array

[0210] The three-dimensional structure of the memory cell array 10A will be described. The three-dimensional structure of the memory cell array 10A has cells arranged separately in the Z direction. Figure 10 The diagram shows a planar layout structure, where multiple NAND strings (NS) are arranged and separated from each other in the Z direction.

[0211] 1.5.4 Write Action

[0212] The write operation of the semiconductor memory device 3A in the variation of the first embodiment is the same as the write operation described in the first embodiment.

[0213] 1.5.5 Reading Action

[0214] The read operation of the semiconductor memory device 3A in the variation of the first embodiment will be described. The read operation of the semiconductor memory device 3A in this variation of the embodiment includes the first read operation.

[0215] Figure 11 This is a diagram showing the voltage of each wire during the first readout operation. Figure 11 The example illustrates a scenario where, in the selection block BLK, multiple memory cell transistors MT4e within the selection string unit SU are selected as read targets, and the memory cell transistors MT4e within one NAND string NS are turned on.

[0216] like Figure 11 As shown, during the first readout operation, the following voltages are applied to each conductive post SGP and CGP in the first NSa string.

[0217] For example, a voltage VSG is applied to the conductive films 40 of the conductive pillars SGP0e, SGP1e, and SGP2e, which function as the select gate decoding lines SGDa, SGDb, and SGSc, respectively. For example, a voltage VCGRV is applied to the conductive film 30 of the conductive pillar CGP4e. For example, a voltage Vcut is applied to the conductive films 30 of the conductive pillars CGP0e to CGP3e and CGP5e to CGP7e, respectively.

[0218] In addition, during the first read operation, the following voltages are applied to each conductive post SGP and TRP within the NAND string NSb.

[0219] A voltage VSG is applied, for example, to the conductive films 40 of the conductive pillars SGP0o, SGP1o, and SGP2o, which function as the select gate decoding lines SGSa, SGSb, and SGDc, respectively. A voltage Vcut is applied, for example, to the conductive film 50 of the conductive pillar TRP4. The conductive pillar TRP4 is a conductive pillar TRP located on the back side of the semiconductor CPS and near the select CG pillar CGPsel. More specifically, the conductive pillar TRP4 is a conductive pillar TRP on the back side of the semiconductor CPS, located in the X direction opposite to the select CG pillar CGPsel on the front side of the semiconductor CPS. A voltage Vread is applied, for example, to the conductive films 50 of the conductive pillars TRP0 to TRP3 and TRP5 to TRP7.

[0220] In this state, a voltage Vbl is applied to the bit line BL, which is the target of the readout, and a voltage VSS is applied to the source line SL.

[0221] In a semiconductor CPS, a conductive region is formed near the portions connected to conductive posts SGP0e, SGP1e, SGP2e, SGP0o, SGP1o, and SGP2o, respectively. No conductive region is formed near the portions connected to conductive posts CGP0e-CGP3e, CGP5e-CGP7e, and TRP4, respectively. Conductive regions are formed near the portions connected to conductive posts TRP0-TRP3 and TRP5-TRP7, respectively. Near the portion connected to conductive post CGP4e, a conductive region is formed when the selected memory cell transistor MT4e is in the ON state, and no conductive region is formed when the selected memory cell transistor MT4e is in the OFF state.

[0222] Furthermore, because the width of the semiconductor CPS is relatively small, conductive regions are also formed between the conductive regions formed near conductive pillar SGP2o and SGP1e, between the conductive regions formed near conductive pillar SGP1e and TRP7, and between the conductive regions formed near conductive pillar SGP1o and SGP2e. When the selection cell transistor MT4e is in the ON state, conductive regions are also formed between the conductive regions formed near conductive pillar TRP5 and CGPsel, and between the conductive regions formed near CGPsel and TRP3.

[0223] In semiconductor CPS, no conductive region is formed near the portion that connects to the contact plug BC.

[0224] Therefore, when the memory cell transistor MT4e is selected to be in the ON state, such as Figure 11As shown, the wiring LBI is electrically connected to the source line SL, and electron current flows from the wiring LBI to the source line SL. However, when the selected memory cell transistor MT4e is in the off state, the wiring LBI is not electrically connected to the source line SL.

[0225] Furthermore, when the memory cell transistor MT7e is the read target, a voltage VSG is applied, for example, to the conductive film 40 of each of the conductive pillars SGP0e, SGP1e, SGP2e, SGP0o, SGP1o, and SGP2o. A voltage VCGRV is applied, for example, to the conductive film 30 of the conductive pillar CGP7e (selected CG pillar CGPsel). A voltage Vcut is applied, for example, to the conductive film 30 of each of the conductive pillars CGP0e to CGP6e and the conductive film 50 of the conductive pillar TRP7. A voltage Vread is applied, for example, to the conductive film 50 of each of the conductive pillars TRP0 to TRP6.

[0226] Furthermore, when the memory cell transistor MT0e is the read target, a voltage VSG is applied, for example, to the conductive film 40 of each of the conductive pillars SGP0e, SGP1e, SGP2e, SGP0o, SGP1o, and SGP2o. A voltage VCGRV is applied, for example, to the conductive film 30 of the conductive pillar CGP0e (selected CG pillar CGPsel). A voltage Vcut is applied, for example, to the conductive film 30 of each of the conductive pillars CGP1e to CGP7e and the conductive film 50 of the conductive pillar TRP0. A voltage Vread is applied, for example, to the conductive film 50 of each of the conductive pillars TRP1 to TRP7.

[0227] 1.5.6 Effects of this variation example

[0228] According to this variation, the same effect as the first embodiment is achieved.

[0229] Additionally, if using Figure 11 As described above, during the readout operation, a conductive region is formed between the conductive region formed near the conductive pillar SGP2o and the conductive region formed near the conductive pillar SGP1e in the semiconductor CPS, thereby increasing the cell current.

[0230] 2. Second Implementation Method

[0231] The semiconductor memory device 3B according to the second embodiment will be described. In the semiconductor memory device 3B of the second embodiment, the circuit configuration of the second string of NSb, the planar layout of the second string of NSb, and the write operation are different from those of the first embodiment. Hereinafter, the description will focus on the differences from the first embodiment.

[0232] 2.1 Circuit configuration of memory cell array

[0233] use Figure 12 The circuit configuration of the memory cell array 10B will be explained. Figure 12 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array 10B. Figure 12 The circuit configuration of a block BLK included in the memory cell array 10B is shown as an example of the circuit configuration of the memory cell array 10B. Other block BLKs also have the same... Figure 12 Same composition.

[0234] like Figure 12 As shown, the circuit configuration of the memory cell array 10B, in addition to Figure 2 Except for the fact that transistors TR0 to TR7 in the second string NSb shown are replaced with memory cell transistors MT0o to MT7o, everything else is the same as shown in the first embodiment. Figure 2 The circuit configuration is the same. The configuration of the memory cell transistors MT0o to MT7o is the same as that of the memory cell transistors MT0e to MT7e. The first string NSa is the storage string, and the second string NSb is the read string.

[0235] 2.2 Planar Layout of Storage Cell Array

[0236] Figure 13 This is a top view showing an example of the planar layout of the memory cell array 10B. Figure 13 A top view of layers in a block BLK that are approximately at the same height from the substrate is shown. Figure 13 The part shown corresponds to Figure 12 The circuit diagram shown contains one NAND string NS.

[0237] like Figure 13 As shown, the planar layout of the storage cell array 10B, in addition to Figure 3 Except for the fact that the 8 conductive pillars TRP in the second string NSb shown are replaced with 8 conductive pillars CGP and 8 memory structures MS, everything else is the same as shown in the first embodiment. Figure 3 The floor plan layout is the same.

[0238] On the back side of the semiconductor CPS, a second string of NSb is arranged. Within this second string of NSb, for example along the Y direction, starting from the top of the paper, one contact plug BC, eight conductive posts CGP, and two conductive posts SGP are arranged sequentially. The contact plug BC, the eight conductive posts CGP, and the two conductive posts SGP are separated from each other in the Y direction. Hereinafter, the eight conductive posts CGP will be designated as CGP0o to CGP7o sequentially from the bottom of the paper.

[0239] On the back side of the semiconductor CPS, the conductive pillar CGP and memory structure MS have the same structure as the conductive pillar CGP and memory structure MS on the front side of the semiconductor CPS. This structure, comprising one conductive pillar CGP, one memory structure MS, and the semiconductor CPS, functions as a memory cell transistor MT. Figure 13 The eight structures shown, starting from the top of the paper, function as memory cell transistors MT7o, MT6o, MT5o, MT4o, MT3o, MT2o, MT1o, and MT0o, respectively. The structure comprising a semiconductor CPS, three conductive pillars SGP on the back side of the semiconductor CPS, eight conductive pillars CGP, eight memory structures MS, and one contact plug BC corresponds to the second string NSb.

[0240] Thus, the second NSb includes memory cell transistors MT0o to MT7o, which are arranged separately in the Y direction using semiconductor CPS as channels, and selection transistors ST2a and ST2b.

[0241] Multiple NAND strings NS connected to the same bit line BL are configured, for example, in the same way as in the first embodiment.

[0242] 2.3 Three-dimensional structure of storage cell array

[0243] The three-dimensional structure of the memory cell array 10B will be described. The three-dimensional structure of the memory cell array 10B has cells arranged separately in the Z direction. Figure 13 The diagram shows a planar layout structure, where multiple NAND strings (NS) are arranged and separated from each other in the Z direction.

[0244] 2.4 Write Action

[0245] The write operation of the semiconductor memory device 3B according to the second embodiment will be described. The write operation of the semiconductor memory device 3B according to this embodiment includes a first write operation and a write operation for the read string (hereinafter referred to as "second write operation"). Figure 14 This is a flowchart illustrating an example of the write operation of the semiconductor memory device 3B in this embodiment.

[0246] For example, when a write operation begins, the memory controller 2 instructs the semiconductor memory device 3B to perform the first write operation and the second write operation.

[0247] Next, the sequencer 13 performs the first write operation (S101) based on the instruction received from the memory controller 2. That is, it writes write data to the first string NSa.

[0248] Then, the sequencer 13 performs the second write operation (S102) based on the instruction received from the memory controller 2. More specifically, in the selection block BLK, the memory cell transistor MT corresponding to the selection CG pillar CGPsel in all the second string NSb in the selection string unit SU is repeatedly programmed in a loop.

[0249] During the second write operation, in the programming operation, a voltage VPGMo is applied to the conductive film 30 of the select CG pillar CGPsel in all second string NSb cells SU. The voltage VPGMo is a high voltage capable of raising the threshold voltage of the memory cell transistor MT. The voltage VPGMo increases, for example, as the programming cycle repeats.

[0250] In this state, a voltage VSS is applied to the bit line BL, which is programmed as "0", and a voltage VCC is applied to the bit line BL, which is programmed as "1".

[0251] Then, in the selection string unit SU, data is written to the memory cell transistor MT corresponding to the selection CG pillar CGPsel in all the second string NSb connected to the bit line BL which is programmed as "0". On the other hand, the data in the memory cell transistor MT corresponding to the selection CG pillar CGPsel in all the second string NSb connected to the bit line BL which is programmed as "1" is maintained.

[0252] After the programming action is performed, the verification action is performed. Then, the programming loop is repeated in the same manner as the first write action.

[0253] For example, in the second string of NSb, conductive posts CGP0o to CGP7o are selected in the order of CGP7o, CGP6o, ..., CGP1o, CGP0o. The second write operation ends when the programming cycle for each conductive post CGP is completed. For example, data with relatively strong read interference resistance and data retention is written to the second string of NSb. This data is, for example, write-level data in SLC or data of equivalent strength. That is, predetermined data is written to the second string of NSb. The write operation ends when the second write operation is completed.

[0254] Furthermore, data already written to the read string can be erased during the erase operation, or it can be left unerased. When erasing, a second write operation can be performed after the erase operation to write data as described above, thus establishing a state where data has been written. When not erasing, the written data is preserved, so a second write operation can be omitted after the erase operation, thus preventing data from being written.

[0255] 2.5 Reading Action

[0256] The readout operation of the semiconductor memory device 3B according to the second embodiment will be described. The readout operation of the semiconductor memory device 3B according to this embodiment includes a first readout operation. In the first readout operation, no cell current flows in the memory cell transistor MT corresponding to the non-selected CG pillar CGPsel and the memory cell transistor MT corresponding to the conductive pillar CGPo located near the selected CG pillar CGPsel, and cell current flows in the memory cell transistor MT corresponding to the conductive pillar CGPo not located near the selected CG pillar CGPsel.

[0257] Figure 15 This is a diagram showing the voltage of each wire during the first readout operation. Figure 15 The example illustrates a scenario where, in the selection block BLK, multiple memory cell transistors MT4e within the selection string unit SU are selected as read targets, and the memory cell transistors MT4e within one NAND string NS are turned on.

[0258] like Figure 15 As shown, the voltage of each wire during the first readout operation, except for... Figure 8 The only difference from the first embodiment is that the voltage application to the eight conductive posts TRP within the second string NSb is replaced by the voltage application to the eight conductive posts CGP. Figure 8 The voltage of each wire is the same during the first readout operation.

[0259] A voltage Vcut is applied, for example, to the conductive films 30 of the conductive pillars CGP3o and CGP4o, which function as word lines WL3o and WL4o, respectively. The conductive pillars CGP3o and CGP4o are conductive pillars CGPo located on the back side of the semiconductor CPS and near the selection CG pillar CGPsel in the X direction. More specifically, the conductive pillars CGP3o and CGP4o are two conductive pillars CGPo on the back side of the semiconductor CPS, located at positions closest in the +Y and -Y directions to the position opposite the selection CG pillar CGPsel on the front side of the semiconductor CPS in the X direction, respectively. A voltage Vread is applied, for example, to the conductive films 30 of the conductive pillars CGP0o~CGP2o and CGP5o~CGP7o, which function as word lines WL0o~WL2o and WL5o~WL7o, respectively. The voltage Vread is a voltage that turns on the memory cell transistor MT, regardless of the threshold voltage. The voltage Vread is a voltage higher than the voltage VCGRV.

[0260] In the semiconductor CPS, a conduction region is formed in the same manner as in the first embodiment. Therefore, when the memory cell transistor MT4e is selected to be in the ON state, as... Figure 15As shown, the wiring LBI is electrically connected to the source line SL, and electron current flows from the wiring LBI to the source line SL. However, when the selected memory cell transistor MT4e is in the off state, the wiring LBI is not electrically connected to the source line SL.

[0261] 2.6 Effects of this implementation method

[0262] According to the second embodiment, the same effect as the first embodiment is achieved.

[0263] Furthermore, since the conductive post CGP in the first NSa string has the same structure as the conductive post CGP in the second NSb string, these conductive post CGPs can be formed simultaneously during the manufacturing process.

[0264] Furthermore, because data with relatively strong resistance to read interference and data retention is written to the second NSb, a storage unit with high readability can be achieved.

[0265] 2.7 Variation Examples

[0266] A variation of the semiconductor memory device 3C according to the second embodiment will be described. In this variation of the semiconductor memory device 3C, the circuit configuration of the memory cell array 10C, the planar layout of the memory cell array 10C, and the readout operation are different from those of the second embodiment. Hereinafter, the description will focus on the differences from the second embodiment.

[0267] 2.7.1 Circuit configuration of memory cell array

[0268] use Figure 16 The circuit configuration of the memory cell array 10C will be explained. Figure 16 This is a circuit diagram illustrating an example of the circuit configuration of a memory cell array 10C. Figure 16 The circuit configuration of a block BLK included in the memory cell array 10C is shown as an example of the circuit configuration of the memory cell array 10C. Other block BLKs also have the same... Figure 16 Same composition.

[0269] like Figure 16 As shown, the circuit configuration of the memory cell array 10C, in addition to Figure 9 Except for the fact that transistors TR0 to TR7 in the second string NSb shown are replaced with memory cell transistors MT0o to MT7o, everything else is the same as shown in the variation example of the first embodiment. Figure 9 The circuit configuration is the same. The configuration of the memory cell transistors MT0o to MT7o is the same as that of the memory cell transistors MT0e to MT7e. The first string NSa is the storage string, and the second string NSb is the read string.

[0270] 2.7.2 Planar Layout of Storage Cell Array

[0271] Figure 17 This is a top view showing an example of the planar layout of the memory cell array 10C. Figure 17 A top view of layers in a block BLK that are approximately at the same height from the substrate is shown. Figure 17 The part shown corresponds to Figure 16 The circuit diagram shown contains one NAND string NS.

[0272] like Figure 17 As shown, the planar layout of the memory cell array 10C, in addition to Figure 10 Except for the fact that the eight conductive pillars TRP in the second string NSb shown are replaced with eight conductive pillars CGP and eight memory structures MS, the rest is the same as the variation shown in the first embodiment. Figure 10 The floor plan layout is the same.

[0273] On the back side of the semiconductor CPS, a second string of NSb is arranged. Within the second string of NSb, for example along the Y direction, starting from the top of the paper, one conductive post SGP, one contact plug BC, eight conductive posts CGP, and two conductive posts SGP are arranged sequentially. The one conductive post SGP, one contact plug BC, eight conductive posts CGP, and two conductive posts SGP are separated from each other in the Y direction.

[0274] On the back side of the semiconductor CPS, the conductive pillar CGP and memory structure MS have the same structure as the conductive pillar CGP and memory structure MS on the front side of the semiconductor CPS. This structure, comprising one conductive pillar CGP, one memory structure MS, and the semiconductor CPS, functions as a memory cell transistor MT. Figure 17 The eight structures shown, starting from the top of the paper, function as memory cell transistors MT7o, MT6o, MT5o, MT4o, MT3o, MT2o, MT1o, and MT0o, respectively. The structure comprising a semiconductor CPS, three conductive pillars SGP on the back side of the semiconductor CPS, eight conductive pillars CGP, eight memory structures MS, and one contact plug BC corresponds to the second string NSb.

[0275] Multiple NAND strings NS connected to the same bit line BL are configured, for example, in the same way as in the first embodiment.

[0276] 2.7.3 Three-dimensional structure of storage cell array

[0277] The three-dimensional structure of the memory cell array 10C will be described. The three-dimensional structure of the memory cell array 10C has cells arranged separately in the Z direction. Figure 17 The diagram shows a planar layout structure, where multiple NAND strings (NS) are arranged and separated from each other in the Z direction.

[0278] 2.7.4 Write Action

[0279] The write operation of the semiconductor memory device 3C in the variation of the second embodiment is the same as the write operation described in the second embodiment.

[0280] 2.7.5 Reading Action

[0281] The read operation of the semiconductor memory device 3C in the variation of the second embodiment will be described. The read operation of the semiconductor memory device 3C in this variation of the embodiment includes a first read operation.

[0282] Figure 18 This is a diagram showing the voltage of each wire during the first readout operation. Figure 18 The example illustrates a scenario where, in the selection block BLK, multiple memory cell transistors MT4e within the selection string unit SU are selected as read targets, and the memory cell transistors MT4e within one NAND string NS are turned on.

[0283] like Figure 18 As shown, the voltage of each wire during the first readout operation, except for... Figure 11 The only difference from the variation shown in the first embodiment is that the voltage application to the eight conductive posts TRP within the second string NSb is replaced by the voltage application to the eight conductive posts CGP. Figure 11 The voltage of each wire is the same during the first readout operation.

[0284] A voltage Vcut is applied, for example, to the conductive film 30 of the conductive pillar CGP4o. The conductive pillar CGP4o is a conductive pillar CGPo located on the back side of the semiconductor CPS and near the selected CG pillar CGPsel. More specifically, the conductive pillar CGP4o is a conductive pillar CGPo on the back side of the semiconductor CPS, located in the X direction opposite to the selected CG pillar CGPsel on the front side of the semiconductor CPS. A voltage Vread is applied, for example, to the conductive film 30 of each of the conductive pillars CGP0o to CGP3o and CGP5o to CGP7o.

[0285] In the semiconductor CPS, a conduction region is formed in the same manner as in the variation of the first embodiment. Therefore, when the memory cell transistor MT4e is selected to be in the ON state, as... Figure 18 As shown, the wiring LBI is electrically connected to the source line SL, and electron current flows from the wiring LBI to the source line SL. However, when the selected memory cell transistor MT4e is in the off state, the wiring LBI is not electrically connected to the source line SL.

[0286] 2.7.6 Effects of this variation example

[0287] According to this variation, the same effect as the second embodiment is achieved.

[0288] In addition, similar to the variation of the first embodiment, the unit current can be increased.

[0289] 3. Third Implementation Method

[0290] The semiconductor memory device 3D according to the third embodiment will be described. In this embodiment of the semiconductor memory device 3D, the storage string and the read string can be switched on a block BLK basis, which differs from the second embodiment. Furthermore, the circuit configuration of the memory cell array 10D is the same as that shown in the second embodiment. Figure 12 The same. Of the first string NSa and the second string NSb, one is the storage string and the other is the read string. The planar layout of the storage cell array 10D is the same as that shown in the second embodiment. Figure 13 Same. The following description focuses on the differences from the second embodiment.

[0291] 3.1 String of Markers

[0292] In this embodiment, within the NAND string NS in block BLK, a string flag flgS is used to indicate which of the first string NSa and the second string NSb is the storage string (hereinafter referred to as "string information"). Figure 19 The string flag flgS is explained. Figure 19 This is a diagram illustrating the string flag flgS used in the semiconductor memory device 3D of this embodiment.

[0293] like Figure 19 As shown, each BLK stores the string flag flgS in the memory cell transistor MT within the memory area. For example, as the string flag flgS, "0" is stored when the first string NSa is the storage string, and "1" is stored when the second string NSb is the storage string.

[0294] 3.2 Write Action

[0295] The write operation of the semiconductor memory device 3D according to the third embodiment will be described. The write operation of the semiconductor memory device 3D according to this embodiment includes a first write operation and a second write operation. Figure 20 This is a flowchart illustrating an example of the write operation of the semiconductor memory device 3D in this embodiment.

[0296] For example, when a write operation begins, the memory controller 2 accesses the semiconductor storage device 3D and obtains the string flag flgS from the selection block BLK (S201).

[0297] Next, the memory controller 2 swaps the storage string and the read string based on the string flag flgS (S202). This determines the swapped storage string and the read string.

[0298] Then, the memory controller 2 instructs the semiconductor memory device 3D to perform a first write operation for the swapped memory string and a second write operation for the swapped read string.

[0299] Next, sequencer 13 performs a first write operation (S203) based on the instruction received from memory controller 2. In the first write operation, sequencer 13 also writes (updates) the string flag flgS in the selection block BLK.

[0300] Then, sequencer 13 performs the second write operation (S204) based on the instruction received from memory controller 2. When the second write operation is completed, the write operation ends.

[0301] Thus, in the first string NSa and the second string NSb, the strings to be written with data are switched periodically in blocks.

[0302] The example illustrates the case where the string of data to be written switches whenever a write operation is performed on the block BLK (selected block BLK) specified by block address BAd. However, the write operation of the semiconductor memory device 3D in this embodiment is not limited to this. For example, the string of data to be written may switch whenever multiple write operations are performed on the selected block BLK, or whenever an erase operation is performed.

[0303] 3.3 Reading Action

[0304] The readout operation of the semiconductor memory device 3D according to the third embodiment will be described. The readout operation of the semiconductor memory device 3D according to this embodiment includes a first readout operation. Figure 21 This is a flowchart illustrating an example of the readout operation of the semiconductor memory device 3D according to this embodiment.

[0305] For example, when the read operation begins, the memory controller 2 accesses the semiconductor memory device 3D and obtains the string flag flgS from the selection block (S211).

[0306] Next, the memory controller 2 instructs the semiconductor memory device 3D to perform the first read operation based on the string flag flgS.

[0307] Then, the sequencer 13 performs the first read operation (S212) based on the instruction received from the memory controller 2. Figure 22 This is a diagram showing the voltage of each wire during the first readout operation. Figure 22The example illustrates a scenario where, in the selection block BLK, multiple memory cell transistors MT4o within the selection string unit SU are selected as read targets, and the memory cell transistors MT4o within one NAND string NS are turned on.

[0308] like Figure 22 As shown, during the first readout operation, the following voltages are applied to each conductive post SGP and CGP in the first NSa string.

[0309] A voltage VSG is applied, for example, to the conductive film 40 of each of the conductive pillars SGP0e and SGP1e. A voltage Vcut is applied, for example, to the conductive film 30 of each of the conductive pillars CGP4e and CGP5e. The conductive pillars CGP4e and CGP5e are conductive pillars CGPe located on the front side of the semiconductor CPS and near the selected CG pillar CGPsel. More specifically, the conductive pillars CGP4e and CGP5e are two conductive pillars CGPe on the front side of the semiconductor CPS, located at positions closest in the +Y and -Y directions to the position opposite to the selected CG pillar CGPsel on the back side of the semiconductor CPS in the X direction, respectively. A voltage Vread is applied, for example, to the conductive film 30 of each of the conductive pillars CGP0e to CGP3e, CGP6e, and CGP7e.

[0310] In addition, during the first read operation, the following voltages are applied to each conductive post SGP and CGP within the NAND string NSb.

[0311] For example, a voltage VSG is applied to the conductive film 40 of each of the conductive pillars SGP0o and SGP1o. For example, a voltage VCGRV is applied to the conductive film 30 of the conductive pillar CGP4o (selected as CG pillar CGPsel). For example, a voltage Vcut is applied to the conductive film 30 of the conductive pillars CGP0o to CGP3o and CGP5o to CGP7o.

[0312] In this state, a voltage Vbl is applied to the bit line BL, which is the target of the readout, and a voltage VSS is applied to the source line SL.

[0313] In a semiconductor CPS, a conductive region is formed near the portions connected to conductive pillars SGP0e, SGP1e, SGP0o, and SGP1o, respectively. No conductive region is formed near the portions connected to conductive pillars CGP4e, CGP5e, CGP0o–CGP3o, and CGP5o–CGP7o. A conductive region is formed near the portions connected to conductive pillars CGP0e–CGP3e, CGP6e, and CGP7e. Near the portion connected to conductive pillar CGP4o, a conductive region is formed when the selected memory cell transistor MT4o is in the ON state. No conductive region is formed when the selected memory cell transistor MT4o is in the OFF state.

[0314] Furthermore, because the width of a semiconductor CPS is relatively small, when the selection memory cell transistor MT4o is in the ON state, a conductive region is also formed between the conductive region formed near the conductive pillar CGP6e and the conductive region formed near the selection CG pillar CGPsel, and between the conductive region formed near the selection CG pillar CGPsel and the conductive region formed near the conductive pillar CGP3e. A conductive region is also formed between the conductive region formed near the conductive pillar CGP0e and the conductive region formed near the conductive pillar SGP1o.

[0315] In semiconductor CPS, no conductive region is formed near the portion that connects to the contact plug BC.

[0316] Therefore, when the memory cell transistor MT4o is selected to be in the ON state, such as Figure 22 As shown, the wiring LBI is electrically connected to the source line SL, and electron current flows from the wiring LBI to the source line SL. However, when the selected memory cell transistor MT4o is in the off state, the wiring LBI is not electrically connected to the source line SL.

[0317] Furthermore, when the memory cell transistor MT7o is the read target, a voltage VSG is applied, for example, to the conductive film 40 of each of the conductive pillars SGP0e, SGP1e, SGP0o, and SGP1o. A voltage VCGRV is applied, for example, to the conductive film 30 of the conductive pillar CGP7o (selected CG pillar CGPsel). A voltage Vcut is applied, for example, to the conductive film 30 of each of the conductive pillars CGP7e and CGP0o to CGP6o. A voltage Vread is applied, for example, to the conductive film 30 of each of the conductive pillars CGP0e to CGP6e.

[0318] Furthermore, when the memory cell transistor MT0o is the read target, a voltage VSG is applied, for example, to the conductive film 40 of each of the conductive pillars SGP0e, SGP1e, SGP0o, and SGP1o. A voltage VCGRV is applied, for example, to the conductive film 30 of the conductive pillar CGP0o (selected CG pillar CGPsel). A voltage Vcut is applied, for example, to the conductive film 30 of each of the conductive pillars CGP0e, CGP1e, and CGP1o to CGP7o. A voltage Vread is applied, for example, to the conductive film 30 of each of the conductive pillars CGP2e to CGP7e.

[0319] 3.4 Effects of this implementation method

[0320] According to the third embodiment, the same effect as the second embodiment is achieved.

[0321] In addition, because the storage string and the read string are switched periodically (e.g., during write or erase operations), the write or erase pressure can be uniformized, amplifying the cycle limit of the storage cell.

[0322] 3.5 Example of Variation 1

[0323] The semiconductor memory device 3E of the first variation of the third embodiment will be described. In this variation of the semiconductor memory device 3E, a string table tblS is used as the string information, which differs from the third embodiment. Furthermore, the circuit configuration and planar layout of the memory cell array 10E are the same as in the third embodiment. The following description focuses on the differences from the third embodiment.

[0324] 3.5.1 String Tables

[0325] use Figure 23 The string table tblS will be explained. Figure 23 This is a conceptual diagram of the serial table tblS used in the semiconductor memory device 3E of this variation example.

[0326] like Figure 23 As shown, the string table tblS has multiple entries. Each entry contains the block address BAd and the string flag flgS. Figure 23 In the example, the string flag flgS corresponding to block addresses BAd0 and BAd1 is "0" respectively. The string flag flgS corresponding to block address BAd2 is "1". For example, in the block BLK corresponding to block addresses BAd0 and BAd1 respectively, the first string NSa is the storage string, and in the block BLK corresponding to block address BAd2, the second string NSb is the storage string.

[0327] The string table tblS is stored, for example, within any block of the memory cell array 10E. For example, upon power-on, the string table tblS is loaded from the semiconductor memory device 3E into a non-shown RAM (Random Access Memory) within the memory controller 2. The string table tblS in RAM is updated, for example, each time a storage string is switched. The initial value of the string flag flgS is, for example, "1". Furthermore, the string table tblS within the block BLK is updated at any given time.

[0328] 3.5.2 Write Action

[0329] The write operation of the semiconductor memory device 3E in the first variation of the third embodiment will be described. Figure 24 This is a flowchart illustrating an example of the write operation of the semiconductor memory device 3E in this variation.

[0330] For example, when a write operation begins, the memory controller 2 obtains the string flag flgS corresponding to the selection block BLK from the string table tblS (S221).

[0331] Next, the memory controller 2 swaps the storage string and the read string based on the string flag flgS, and updates the string flag flgS corresponding to the selection block BLK in the string table tblS (S222).

[0332] Then, the memory controller 2 instructs the semiconductor memory device 3E to perform a first write operation for the swapped memory string and a second write operation for the swapped read string.

[0333] Next, the sequencer 13 performs the first write operation (S223) based on the instruction received from the memory controller 2.

[0334] Then, sequencer 13 performs the second write operation (S224) based on the instruction received from memory controller 2. When the second write operation is completed, the write operation ends.

[0335] 3.5.3 Reading Action

[0336] The readout operation of the semiconductor memory device 3E in the first variation of the third embodiment will be described. Figure 25 This is a flowchart illustrating an example of the read operation of the semiconductor memory device 3E in this variation.

[0337] For example, when the read operation begins, the memory controller 2 obtains the string flag flgS corresponding to the selection block BLK from the string table tblS (S231).

[0338] Next, the memory controller 2 instructs the semiconductor memory device 3E to perform the first read operation based on the string flag flgS.

[0339] Then, the sequencer 13 performs the first read operation (S232) based on the instruction received from the memory controller 2.

[0340] 3.5.4 Effects of this variation example

[0341] According to this variation, the same effect as the third embodiment is achieved.

[0342] 3.6 Example of Variation 2

[0343] The semiconductor memory device 3F of the second variation of the third embodiment will be described. In this variation of the semiconductor memory device 3F, the circuit configuration, planar layout of the memory cell array 10F, and readout operation differ from those of the third embodiment. Furthermore, the circuit configuration of the memory cell array 10F differs from that shown in the variation of the second embodiment. Figure 16 The same. Of the first string NSa and the second string NSb, one is the storage string and the other is the read string. The planar layout of the storage cell array 10F is shown in the variation example of the second embodiment. Figure 17 Same. The following description will focus on the differences from the third embodiment.

[0344] 3.6.1 Write Action

[0345] The write operation of the semiconductor memory device 3F in the second variation of the third embodiment is the same as the write operation described in the third embodiment.

[0346] 3.6.2 Reading Action

[0347] The read operation of the semiconductor memory device 3F in the second variation of the third embodiment will be described. A flowchart illustrating an example of the read operation of the semiconductor memory device 3F in this variation is shown in the third embodiment. Figure 21 same.

[0348] Figure 26 This is a diagram showing the voltage of each wire during the first readout operation. Figure 26 The example illustrates a scenario where, in the selection block BLK, multiple memory cell transistors MT4o within the selection string unit SU are selected as read targets, and the memory cell transistors MT4o within one NAND string NS are turned on.

[0349] like Figure 26 As shown, during the first readout operation, the following voltages are applied to each conductive post SGP and CGP in the first NSa string.

[0350] A voltage VSG is applied, for example, to the conductive film 40 of each of the conductive pillars SGP0e to SGP2e. A voltage Vcut is applied, for example, to the conductive film 30 of the conductive pillar CGP4e. The conductive pillar CGP4e is a conductive pillar CGPe located on the front side of the semiconductor CPS and near the selected CG pillar CGPsel. More specifically, the conductive pillar CGP4e is a conductive pillar CGPe on the front side of the semiconductor CPS, located in the X direction opposite to the selected CG pillar CGPsel on the back side of the semiconductor CPS. A voltage Vread is applied, for example, to the conductive film 30 of each of the conductive pillars CGP0e to CGP3e and CGP5e to CGP7e.

[0351] In addition, during the first read operation, the following voltages are applied to each conductive post SGP and CGP within the NAND string NSb.

[0352] A voltage VSG is applied, for example, to the conductive film 40 of each of the conductive pillars SGP0o to SGP2o. A voltage VCGRV is applied, for example, to the conductive film 30 of the conductive pillar CGP4o. A voltage Vcut is applied, for example, to the conductive film 30 of each of the conductive pillars CGP0o to CGP3o and CGP5o to CGP7o.

[0353] In this state, a voltage Vbl is applied to the bit line BL, which is the target of the readout, and a voltage VSS is applied to the source line SL.

[0354] In a semiconductor CPS, a conductive region is formed near the portions connected to conductive pillars SGP0e-SGP2e and SGP0o-SGP2o, respectively. No conductive region is formed near the portions connected to conductive pillars CGP4e, CGP0o-CGP3o, and CGP5o-CGP7o, respectively. A conductive region is formed near the portions connected to conductive pillars CGP0e-CGP3e and CGP5e-CGP7e, respectively. Near the portion connected to conductive pillar CGP4o, a conductive region is formed when the selected memory cell transistor MT4o is in the ON state. No conductive region is formed when the selected memory cell transistor MT4o is in the OFF state.

[0355] Furthermore, because the width of the semiconductor CPS is relatively small, conductive regions are also formed between the conductive regions formed near conductive pillar SGP2o and SGP1e, between conductive pillar CGP0e and SGP0o, and between conductive pillar SGP0o and SGP2e. When the selection cell transistor MT4o is in the ON state, conductive regions are also formed between the conductive regions formed near conductive pillar CGP5e and CGPsel, and between the conductive regions formed near selection CG pillar CGPsel and CGP3e.

[0356] In semiconductor CPS, no conductive region is formed near the portion that connects to the contact plug BC.

[0357] Therefore, when the memory cell transistor MT4o is selected to be in the ON state, such as Figure 26 As shown, the wiring LBI is electrically connected to the source line SL, and electron current flows from the wiring LBI to the source line SL. However, when the selected memory cell transistor MT4o is in the off state, the wiring LBI is not electrically connected to the source line SL.

[0358] Furthermore, when the memory cell transistor MT7o is the read target, a voltage VSG is applied, for example, to the conductive film 40 of each of the conductive pillars SGP0e, SGP1e, SGP2e, SGP0o, SGP1o, and SGP2o. A voltage VCGRV is applied, for example, to the conductive film 30 of the conductive pillar CGP7o (selected CG pillar CGPsel). A voltage Vcut is applied, for example, to the conductive film 30 of each of the conductive pillars CGP7e and CGP0o to CGP6o. A voltage Vread is applied, for example, to the conductive film 30 of each of the conductive pillars CGP0e to CGP6e.

[0359] Furthermore, when the memory cell transistor MT0o is the read target, a voltage VSG is applied, for example, to the conductive film 40 of each of the conductive pillars SGP0e, SGP1e, SGP2e, SGP0o, SGP1o, and SGP2o. A voltage VCGRV is applied, for example, to the conductive film 30 of the conductive pillar CGP0o (selected CG pillar CGPsel). A voltage Vcut is applied, for example, to the conductive film 30 of each of the conductive pillars CGP0e and CGP1o to CGP7o. A voltage Vread is applied, for example, to the conductive film 30 of each of the conductive pillars CGP1e to CGP7e.

[0360] 3.6.3 Effects of this variation example

[0361] According to this variation, the same effect as the third embodiment is achieved.

[0362] In addition, similar to the variation of the first embodiment, the unit current can be increased.

[0363] 4. Fourth Implementation Method

[0364] The semiconductor memory device 3G according to the fourth embodiment will be described. In this embodiment of the semiconductor memory device 3G, it is possible to select, on a block BLK basis, whether to use the first string NSa as the storage string and the second string NSb as the read string, or to use both the first string NSa and the second string NSb as the storage string, which differs from the second embodiment. Hereinafter, the storage mode of the block BLK using the first string NSa as the storage string and the second string NSb as the read string is referred to as the "high readability mode". The storage mode of the block BLK using both the first string NSa and the second string NSb as the storage string is referred to as the "normal mode". Furthermore, the circuit configuration of the memory cell array 10G is the same as that shown in the second embodiment. Figure 12 The same. The planar layout of the storage cell array 10G is the same as that shown in the second embodiment. Figure 13 Same. The differences from the second embodiment will be explained below.

[0365] 4.1 Method for specifying the storage mode of blocks

[0366] This implementation describes the case where the storage mode of the fixed block BLK is specified as a high readability mode. Figure 27 This diagram illustrates a method for specifying the storage mode of the block BLK in the semiconductor memory device 3G according to this embodiment. (See diagram for example.) Figure 27 As shown, in this embodiment, the storage mode of the fixed block BLK is specified as a high readability mode. Figure 27 In the example, block BLK0's storage mode is specified as high readability mode. The storage mode of other block BLKs is specified as normal mode. Hereinafter, block BLKs specified as high readability mode will be referred to as "High Readability BLKs". Block BLKs specified as normal mode will be referred to as "Normal BLKs".

[0367] High-readability BLKs are used for storing information with a defined purpose, such as FAT (File Allocation Table). For example, a user can specify a BLK block containing information with a defined purpose as high-readability mode via the host.

[0368] 4.2 Write Action

[0369] The write operation of the semiconductor memory device 3G according to the fourth embodiment will be described. The write operation of the semiconductor memory device 3G in this embodiment includes a first write operation and a second write operation. Figure 28 This is a flowchart illustrating an example of the write operation of the semiconductor memory device 3G in this embodiment.

[0370] For example, when a write operation begins, the memory controller 2 determines whether the selected block BLK is a high readability BLK (S301).

[0371] When the selected block BLK is a high readability BLK (S301_Yes), the memory controller 2 instructs the semiconductor memory device 3G to perform a first write operation for the storage string (first string NSa) and a second write operation for the read string (second string NSb). Next, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S302). That is, write data to the first string NSa in the block BLK whose storage mode is specified as high readability mode. Then, the sequencer 13 performs the second write operation based on the instruction received from the memory controller 2 (S303).

[0372] If the selected block BLK is not a high-readability BLK (i.e., a normal BLK) (S301_No), the memory controller 2 instructs the semiconductor storage device 3G to perform a first write operation for the storage strings (the first string NSa and the second string NSb). Then, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S304). That is, in the block BLK where the storage mode is specified as normal mode, write data is written to both the first string NSa and the second string NSb. For example, in the NAND string NS, the conductive pillars CGP0e to CGP7e and CGP0o to CGP7o are selected in the order of conductive pillars CGP7e, CGP6e, ..., CGP1e, CGP0e, CGP7o, CGP6o, ..., CGP1o, CGP0o.

[0373] 4.3 Reading Action

[0374] The read operation of the semiconductor memory device 3G according to the fourth embodiment will be described. The read operation of the semiconductor memory device 3G in this embodiment includes a first read operation and a second read operation. The first read operation is a read operation for a high readability BLK. The second read operation is a read operation for a normal BLK. Figure 29 This is a flowchart illustrating an example of the readout operation of the semiconductor memory device 3G in this embodiment.

[0375] For example, when the read operation begins, the memory controller 2 determines whether the selected block BLK is a high readability BLK (S311).

[0376] If the selected block BLK is a high readability BLK (S311_Yes), the memory controller 2 instructs the semiconductor storage device 3G to perform the first read operation. Then, the sequencer 13 performs the first read operation based on the instruction received from the memory controller 2 (S312).

[0377] If the selected block BLK is not a high readability BLK (S311_No), the memory controller 2 instructs the semiconductor storage device 3G to perform the second read operation. Then, the sequencer 13 performs the second read operation based on the instruction received from the memory controller 2 (S313). Figure 30 This is a diagram showing the voltage of each wire during the second readout operation. Figure 30 The example illustrates a scenario where, in the selection block BLK, multiple memory cell transistors MT4e within the selection string unit SU are selected as read targets, and the memory cell transistors MT4e within one NAND string NS are turned on.

[0378] like Figure 30As shown, during the second readout operation, the following voltages are applied to each conductive post SGP and CGP in the first NSa string.

[0379] For example, a voltage VSG is applied to the conductive film 40 of each of the conductive pillars SGP0e and SGP1e. For example, a voltage VCGRV is applied to the conductive film 30 of the conductive pillar CGP4e (selected as CG pillar CGPsel). For example, a voltage Vread is applied to the conductive film 30 of each of the conductive pillars CGP0e to CGP3e and CGP5e to CGP7e.

[0380] In addition, during the second read operation, the following voltages are applied to each conductive post SGP and CGP within the NAND string NSb.

[0381] A voltage VSG is applied, for example, to the conductive film 40 of each of the conductive pillars SGP0o and SGP1o. A voltage Vcut is applied, for example, to the conductive film 30 of each of the conductive pillars CGP3o and CGP4o. A voltage Vread is applied, for example, to the conductive film 30 of each of the conductive pillars CGP0o to CGP2o and CGP5o to CGP7o.

[0382] In this state, a voltage Vbl is applied to the bit line BL, which is the target of the readout, and a voltage VSS is applied to the source line SL.

[0383] In a semiconductor CPS, a conductive region is formed near the portions connected to conductive pillars SGP0e, SGP1e, SGP0o, and SGP1o, respectively. No conductive region is formed near the portions connected to conductive pillars CGP3o and CGP4o, respectively. Conductive regions are formed near the portions connected to conductive pillars CGP0e–CGP3e, CGP5e–CGP7e, CGP0o–CGP2o, and CGP5o–CGP7o, respectively. Near the portion connected to conductive pillar CGP4e, a conductive region is formed when the selected memory cell transistor MT4e is in the ON state. No conductive region is formed when the selected memory cell transistor MT4e is in the OFF state.

[0384] Furthermore, because the width of the semiconductor CPS is relatively small, conductive regions are also formed between the conductive regions formed near the conductive pillar SGP1e and the conductive regions formed near the conductive pillar CGP7o, and between the conductive regions formed near the conductive pillar CGP0e and the conductive regions formed near the conductive pillar SGP1o. When the selection cell transistor MT4e is in the ON state, conductive regions are also formed between the conductive regions formed near the conductive pillar CGP5o and the conductive regions formed near the selection CG pillar CGPsel, and between the conductive regions formed near the selection CG pillar CGPsel and the conductive regions formed near the conductive pillar CGP2o.

[0385] In semiconductor CPS, no conductive region is formed near the portion that connects to the contact plug BC.

[0386] Therefore, when the memory cell transistor MT4e is selected to be in the ON state, such as Figure 30 As shown, the wiring LBI is electrically connected to the source line SL, and electron current flows from the wiring LBI to the source line SL. However, when the selected memory cell transistor MT4e is in the off state, the wiring LBI is not electrically connected to the source line SL.

[0387] For example, in the NAND string NS, the conductive pillars CGP0e~CGP7e and CGP0o~CGP7o are selected in the order of conductive pillars CGP7e, CGP6e, ..., CGP1e, CGP0e, CGP7o, CGP6o, ..., CGP1o, CGP0o.

[0388] 4.4 Effects of this implementation method

[0389] According to the fourth embodiment, the same effect as the second embodiment is achieved.

[0390] Furthermore, in the semiconductor memory device 3G of this embodiment, in the high readability BLK, either the first string NSa or the second string NSb is used as a storage string, while in the ordinary BLK, both the first string NSa and the second string NSb are used as storage strings. Therefore, a high readability memory cell can be realized in the high readability BLK, and the storage capacity of the memory cell can be increased in the ordinary BLK.

[0391] Furthermore, such as using Figure 30 As described above, during the second read operation, the cell current is circulated in the memory cell transistor MT corresponding to the non-selected CGPusel, thereby increasing the cell current.

[0392] In addition, since it is possible to specify the fixed block BLK as the high read BLK, it can be used in situations where the purpose is already determined.

[0393] 4.5 Example of Variation 1

[0394] The semiconductor memory device 3H of the first variation of the fourth embodiment will be described. In this variation of the semiconductor memory device 3H, the circuit configuration, planar layout, and readout operation of the memory cell array 10H differ from those of the fourth embodiment. Furthermore, the circuit configuration of the memory cell array 10H differs from that shown in the variation of the second embodiment. Figure 16 The same. The planar layout of the storage cell array 10H is shown in the variation example of the second embodiment. Figure 17Same. The following description will focus on the differences from the fourth embodiment.

[0395] 4.5.1 Write Action

[0396] The write operation of the semiconductor memory device 3H in the first variation of the fourth embodiment is the same as the write operation described in the fourth embodiment.

[0397] 4.5.2 Reading Action

[0398] The read operation of the semiconductor memory device 3H in the first variation of the fourth embodiment will be described. A flowchart illustrating an example of the read operation of the semiconductor memory device 3H in this variation is shown in the fourth embodiment. Figure 29 same.

[0399] Figure 31 This is a diagram showing the voltage of each wire during the second readout operation. Figure 31 The example illustrates a scenario where, in the selection block BLK, multiple memory cell transistors MT4e within the selection string unit SU are selected as read targets, and the memory cell transistors MT4e within one NAND string NS are turned on.

[0400] like Figure 31 As shown, during the second readout operation, the following voltages are applied to each conductive post SGP and CGP in the first NSa string.

[0401] For example, a voltage VSG is applied to the conductive film 40 of each of the conductive pillars SGP0e to SGP2e. For example, a voltage VCGRV is applied to the conductive film 30 of the conductive pillar CGP4e (selected as CG pillar CGPsel). For example, a voltage Vread is applied to the conductive film 30 of each of the conductive pillars CGP0e to CGP3e and CGP5e to CGP7e.

[0402] In addition, during the second read operation, the following voltages are applied to each conductive post SGP and CGP within the NAND string NSb.

[0403] A voltage VSG is applied, for example, to the conductive film 40 of each of the conductive pillars SGP0o to SGP2o. A voltage Vcut is applied, for example, to the conductive film 30 of each of the conductive pillars CGP4o. A voltage Vread is applied, for example, to the conductive film 30 of each of the conductive pillars CGP0o to CGP3o and CGP5o to CGP7o.

[0404] In this state, a voltage Vbl is applied to the bit line BL, which is the target of the readout, and a voltage VSS is applied to the source line SL.

[0405] In a semiconductor CPS, a conductive region is formed near the portions connected to conductive pillars SGP0e-SGP2e and SGP0o-SGP2o, respectively. No conductive region is formed near the portion connected to conductive pillar CGP4o. Conductive regions are formed near the portions connected to conductive pillars CGP0e-CGP3e, CGP5e-CGP7e, CGP0o-CGP3o, and CGP5o-CGP7o, respectively. Near the portion connected to conductive pillar CGP4e, a conductive region is formed when the selected memory cell transistor MT4e is in the ON state. No conductive region is formed when the selected memory cell transistor MT4e is in the OFF state.

[0406] Furthermore, because the width of the semiconductor CPS is relatively small, conductive regions are also formed between the conductive regions formed near conductive pillar SGP2o and SGP1e, and between the conductive regions formed near conductive pillar SGP1e and CGP7o. Conductive regions are also formed between the conductive regions formed near conductive pillar CGP0e and SGP1o, and between the conductive regions formed near conductive pillar SGP1o and SGP2e. When the selection cell transistor MT4e is in the ON state, conductive regions are also formed between the conductive regions formed near conductive pillar CGP5o and CGPsel, and between the conductive regions formed near selection CG pillar CGPsel and CGP3o.

[0407] In semiconductor CPS, no conductive region is formed near the portion that connects to the contact plug BC.

[0408] Therefore, when the memory cell transistor MT4e is selected to be in the ON state, such as Figure 31 As shown, the wiring LBI is electrically connected to the source line SL, and electron current flows from the wiring LBI to the source line SL. However, when the selected memory cell transistor MT4e is in the off state, the wiring LBI is not electrically connected to the source line SL.

[0409] 4.5.3 Effects of this variation example

[0410] According to this variation, the same effect as the fourth embodiment is achieved.

[0411] In addition, similar to the variation of the first embodiment, the unit current can be increased.

[0412] 4.6 Example of the second variation

[0413] The semiconductor memory device 3I of the second variation of the fourth embodiment will be described. In this variation of the semiconductor memory device 3I, the method for specifying the storage mode of the block BLK is different from that of the fourth embodiment. Hereinafter, the description will focus on the differences from the fourth embodiment.

[0414] 4.6.1 Method for specifying the storage mode of a block

[0415] This variation example demonstrates how to make the regions of a block BLK whose storage mode is specified as high readability mode variable. Figure 32 This is a diagram illustrating the method for specifying the storage mode of block BLK in the semiconductor memory device 3I of this variation example. (See diagram for details.) Figure 32 As shown, in this variation example, the area of ​​the block BLK designated as high readability mode is variable. That is, the boundary between the high readability BLK and the normal BLK will be changed. Figure 32 In the example, the storage mode for blocks BLK0 to BLK2 is specified as high readability mode. The storage mode for other blocks BLK is specified as normal mode.

[0416] 4.6.2 Pattern Marker

[0417] In this variation, the mode flag flgM is used to indicate whether the storage mode of the selected block BLK has been specified as either high readability mode or normal mode (hereinafter referred to as "storage mode information"). Figure 33 The pattern flag flgM is explained. Figure 33 This is a diagram illustrating the pattern symbol flgM used in the semiconductor memory device 3I of this variation example.

[0418] like Figure 33 As shown, each BLK stores the mode flag flgM in the memory cell transistor MT within the memory area. As the mode flag flgM, for example, "0" is stored in the normal mode and "1" is stored in the high readability mode.

[0419] 4.6.3 Write Action

[0420] The write operation of the semiconductor memory device 3I in the second variation of the fourth embodiment will be described. The write operation of the semiconductor memory device 3I in this variation includes a first write operation.

[0421] For example, when a write operation begins, the memory controller 2 instructs the semiconductor memory device 3I to perform a first write operation for the storage strings (the first string NSa and the second string NSb). Then, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2. During the first write operation, the sequencer 13 also writes (updates) the mode flag flgM (e.g., "0") within the selection block BLK.

[0422] 4.6.4 Variable Actions in Block Regions

[0423] The block region variable operation of the semiconductor memory device 3I in the second variation of the fourth embodiment will be described. The block region variable operation of the semiconductor memory device 3I in this variation includes a first variable operation and a second variable operation. Figure 34 This is a flowchart illustrating an example of the variable operation of a block region in the semiconductor memory device 3I of this variation.

[0424] For example, the memory controller 2 accesses the semiconductor memory device 3I at fixed time intervals to obtain the mode flag flgM from the selection block BLK (S321).

[0425] Next, the memory controller 2 determines whether the mode flag flgM represents the normal mode (S322).

[0426] When the mode flag flgM is in normal mode (S322_ is), the memory controller 2 executes the first variable action (S323).

[0427] When the mode flag flgM is in high readability mode (S322_No), the memory controller 2 performs the second variable action (S324).

[0428] (First variable action)

[0429] The first variable action will be explained. Figure 35 This is a flowchart illustrating an example of the first variable operation of the semiconductor memory device 3I in this variation.

[0430] For example, the memory controller 2 determines whether the number of times the data of the selected block BLK is read within a certain period of time exceeds the threshold TH1 (S331).

[0431] If the number of reads exceeds the threshold TH1 (S331_Yes), the memory controller 2 switches the storage mode (S332). The storage mode is then switched to a high readability mode. Next, the memory controller 2 instructs the semiconductor storage device 3I to perform a first write operation and a second write operation. Then, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S333). During the first write operation, the sequencer 13 also writes (updates) the mode flag flgM (e.g., "1") within the selection block BLK. Next, the sequencer 13 performs the second write operation based on the instruction received from the memory controller 2 (S334). Thus, if the number of reads of data in the normal BLK exceeds the threshold TH1 within a certain time period, the storage mode of the normal BLK is switched to a high readability mode, thereby changing the normal BLK into a high readability BLK. As a result, the area of ​​the high readability BLK increases (the boundary between the high readability BLK and the normal BLK changes), and the first variable operation ends.

[0432] If the number of reads does not exceed the threshold TH1 (S331_No), the first variable action ends.

[0433] (Second variable action)

[0434] The second variable action will be explained. Figure 36 This is a flowchart illustrating an example of the second variable operation of the semiconductor memory device 3I in this variation.

[0435] For example, the memory controller 2 determines whether data has been read from the selected block BLK within a certain time period (S341).

[0436] If a readout occurs within a certain time period (S341_ is), the second variable action ends.

[0437] If no data is read within a certain time (S341_No), the memory controller 2 switches the storage mode (S342). The storage mode is then switched to normal mode. Next, the memory controller 2 instructs the semiconductor storage device 3I to perform a first write operation. Then, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S343). In the first write operation, the sequencer 13 also writes (updates) the mode flag flgM (e.g., "0") within the selection block BLK. Thus, if no data is read from the high-readability BLK within a certain time, the storage mode of the high-readability BLK is switched to normal mode, thereby changing the high-readability BLK into a normal BLK. As a result, the area of ​​the high-readability BLK is reduced (the boundary between the high-readability BLK and the normal BLK changes), and the second variable operation ends.

[0438] As described above, in the block area variable action, the boundary position between high readability BLK and normal BLK within multiple block BLKs is changed based on the number of accesses to the data of the selected block BLK.

[0439] 4.6.5 Reading Action

[0440] The readout operation of the semiconductor memory device 3I in the second variation of the fourth embodiment will be described. Figure 37 This is a flowchart illustrating an example of the read operation of the semiconductor memory device 3I in this variation.

[0441] For example, when the read operation begins, the memory controller 2 accesses the semiconductor storage device 3I and obtains the mode flag flgM from the selection block BLK (S351).

[0442] Next, the memory controller 2 determines whether the mode flag flgM is in normal mode (S352).

[0443] When the mode flag flgM is in normal mode (S352_yes), the memory controller 2 instructs the semiconductor memory device 3I to perform the second read operation. Then, the sequencer 13 performs the second read operation based on the instruction received from the memory controller 2 (S353).

[0444] If the mode flag flgM is in high readability mode (S352_No), the memory controller 2 instructs the semiconductor memory device 3I to perform the first read operation. Then, the sequencer 13 performs the first read operation based on the instruction received from the memory controller 2 (S354).

[0445] 4.6.6 Effects of this variation example

[0446] According to this variation, the same effect as the fourth embodiment is achieved.

[0447] Furthermore, because the boundary between the high readability BLK and the normal BLK can be changed, it can be used as a cache memory, for example. For instance, depending on the number of accesses, the data storage target address can be changed from an external DRAM cache memory (not shown) to a high readability BLK, or from a high readability BLK to a normal BLK.

[0448] 4.7 Example of the third variation

[0449] The semiconductor memory device 3J of the third variation of the fourth embodiment will be described. In this variation of the semiconductor memory device 3J, a mode table tblM is used as the memory mode information, which differs from the second variation of the fourth embodiment. Furthermore, the circuit configuration and planar layout of the memory cell array 10J are the same as in the second variation of the fourth embodiment. The following description focuses on the differences from the second variation of the fourth embodiment.

[0450] 4.7.1 Schema Table

[0451] use Figure 38 The schema table tblM will be described. Figure 38 This is a conceptual diagram of the schema table tblM used in the semiconductor memory device 3J of this variation example.

[0452] like Figure 38 As shown, the pattern table tblM has multiple entries. Each entry contains the block address BAd and the pattern flag flgM. Figure 38 In the example, the mode flag flgM corresponding to block addresses BAd0 and BAd1 is "1". The mode flag flgM corresponding to block address BAd2 is "0". For example, the block BLK corresponding to block addresses BAd0 and BAd1 is in high readability mode, and the block BLK corresponding to block address BAd2 is in normal mode.

[0453] The pattern table tblM is stored, for example, within any block BLK of the memory cell array 10J. For example, upon power-on, the pattern table tblM is loaded from the semiconductor memory device 3J into the RAM within the memory controller 2. The pattern table tblM in RAM is updated, for example, each time a memory mode is switched. The initial value of the mode flag flgM is, for example, "0". Furthermore, the pattern table tblM within the block BLK is updated at any given time.

[0454] 4.7.2 Write Action

[0455] The write operation of the semiconductor memory device 3J in the third variation of the fourth embodiment will be described. The write operation of the semiconductor memory device 3J in this variation includes a first write operation. Figure 39 This is a flowchart illustrating an example of the write operation of the semiconductor memory device 3J in this variation.

[0456] For example, when a write operation begins, the memory controller 2 updates the mode flag flgM corresponding to the selection block BLK in the mode table tblM (S361).

[0457] Next, the memory controller 2 instructs the semiconductor memory device 3J to perform a first write operation on the storage strings (the first string NSa and the second string NSb). Then, the sequencer 13 performs the first write operation (S362) based on the instruction received from the memory controller 2. When the first write operation ends, the write operation ends.

[0458] 4.7.3 Variable Actions in Block Regions

[0459] The block region variable operation of the semiconductor memory device 3J in the third variation of the fourth embodiment will be described. The block region variable operation of the semiconductor memory device 3J in this variation includes a first variable operation and a second variable operation. Figure 40 This is a flowchart illustrating an example of the variable operation of a block region in the semiconductor memory device 3J of this variation.

[0460] For example, the memory controller 2 retrieves the mode flag flgM corresponding to the selection block BLK from the mode table tblM at fixed time intervals (S371).

[0461] Next, the memory controller 2 determines whether the mode flag flgM represents the normal mode (S372).

[0462] When the mode flag flgM is in normal mode (S372_yes), the memory controller 2 executes the first variable action (S373).

[0463] When the mode flag flgM is in high readability mode (S372_No), the memory controller 2 performs the second variable action (S374).

[0464] (First variable action)

[0465] The first variable action will be explained. Figure 41 This is a flowchart illustrating an example of the first variable operation of the semiconductor memory device 3J in this variation.

[0466] For example, the memory controller 2 determines whether the number of times the data of the selected block BLK is read within a certain period of time exceeds the threshold TH1 (S381).

[0467] If the number of reads exceeds the threshold TH1 (S381_Yes), the memory controller 2 switches the storage mode and updates the mode flag flgM corresponding to the selected block BLK in the mode table tblM (S382). Thus, the storage mode is switched to high readability mode.

[0468] Next, the memory controller 2 instructs the semiconductor memory device 3J to perform a first write operation and a second write operation. Then, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S383). Next, the sequencer 13 performs the second write operation based on the instruction received from the memory controller 2 (S384). As a result, the area of ​​the high readability BLK increases, and the first variable operation ends.

[0469] If the number of reads does not exceed the threshold TH1 (S381_No), the first variable action ends.

[0470] (Second variable action)

[0471] The second variable action will be explained. Figure 42 This is a flowchart illustrating an example of the second variable operation of the semiconductor memory device 3J in this variation.

[0472] For example, the memory controller 2 determines whether data has been read from the selected block BLK within a certain time period (S391).

[0473] If a readout occurs within a certain time period (S391_ is), the second variable action ends.

[0474] If no data is read within a certain time (S391_No), the memory controller 2 switches the memory mode and updates the mode flag flgM corresponding to the selected block BLK in the mode table tblM (S392). Thus, the memory mode is switched to normal mode. Next, the memory controller 2 instructs the semiconductor memory device 3J to perform the first write operation. Then, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S393). As a result, the area of ​​the high-readability BLK decreases, and the second variable operation ends.

[0475] 4.7.4 Reading Action

[0476] The readout operation of the semiconductor memory device 3J in the third variation of the fourth embodiment will be described. Figure 43 This is a flowchart illustrating an example of the read operation of the semiconductor memory device 3J in this variation.

[0477] For example, when the read operation begins, the memory controller 2 obtains the mode flag flgM corresponding to the selection block BLK from the mode table tblM (S401).

[0478] Next, the memory controller 2 determines whether the mode flag flgM is in normal mode (S402).

[0479] When the mode flag flgM is in normal mode (S402_ is), the memory controller 2 instructs the semiconductor memory device 3J to perform the second read operation. Then, the sequencer 13 performs the second read operation based on the instruction received from the memory controller 2 (S403).

[0480] If the mode flag flgM is in high readability mode (S402_No), the memory controller 2 instructs the semiconductor memory device 3J to perform the first read operation. Then, the sequencer 13 performs the first read operation based on the instruction received from the memory controller 2 (S404).

[0481] 4.7.5 Effects of this variation example

[0482] According to this variation, the same effect as the second variation of the fourth embodiment is achieved.

[0483] 4.8 Example of the fourth variation

[0484] The semiconductor memory device 3K of the fourth variation of the fourth embodiment will be described. In this variation of the semiconductor memory device 3K, the method for specifying the storage mode of block BLK is different from that of the fourth embodiment. Hereinafter, the description will focus on the differences from the fourth embodiment.

[0485] 4.8.1 Method for specifying the storage mode of a block

[0486] This variation example illustrates the case where the storage mode of the block BLK is specified during a write operation. Figure 44 This is a diagram illustrating the method for specifying the storage mode of block BLK in the semiconductor memory device 3K of this variation example. (See diagram for example.) Figure 44 As shown, in this variation, it is possible to specify either the high readability mode or the normal mode. Figure 44 In the example, blocks BLK0, BLK3, and BLK5 are specified as high readability mode. The other blocks are specified as normal mode.

[0487] 4.8.2 Pattern Marker

[0488] In this variation, similar to the second variation of the fourth embodiment, the mode flag flgM is used as the storage mode information.

[0489] 4.8.3 Write Action

[0490] The write operation of the semiconductor memory device 3K in the fourth variation of the fourth embodiment will be described. The write operation of the semiconductor memory device 3K in this variation includes a first write operation and a second write operation. Figure 45 This is a flowchart illustrating an example of the write operation of the semiconductor memory device 3K in this variation.

[0491] For example, when a write operation begins, the memory controller 2 selects the storage mode of the selected block BLK based on the write data (S411). The memory controller 2 can, for example, select either a high readability mode or a normal mode based on the type of write data.

[0492] Next, the memory controller 2 determines whether the selected memory mode is a normal mode (S412).

[0493] If the selected storage mode is normal mode (S412_Yes), the memory controller 2 instructs the semiconductor storage device 3K to perform a first write operation. Then, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S413). In the first write operation, the sequencer 13 also writes (updates) the mode flag flgM within the selection block BLK. When the first write operation ends, the write operation ends.

[0494] If the selected storage mode is a high readability mode (S412_No), the memory controller 2 instructs the semiconductor memory device 3K to perform a first write operation and a second write operation. Then, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S414). In the first write operation, the sequencer 13 also writes (updates) the mode flag flgM in the selection block BLK. Next, the sequencer 13 performs the second write operation based on the instruction received from the memory controller 2 (S415). When the second write operation ends, the write operation ends.

[0495] 4.8.4 Reading Action

[0496] The read operation of the semiconductor memory device 3K in the fourth variation of the fourth embodiment will be described. The read operation of the semiconductor memory device 3K in this variation is the same as the read operation described in the second variation of the fourth embodiment.

[0497] 4.8.5 Effects of this variation example

[0498] According to this variation, the same effect as the fourth embodiment is achieved.

[0499] In addition, because the storage mode can be specified based on the type of data being written during a write operation, the flexibility in handling data is improved.

[0500] 4.9 Fifth variation example

[0501] The semiconductor memory device 3L of the fifth variation of the fourth embodiment will be described. In this variation of the semiconductor memory device 3L, a mode table tblM is used as the memory mode information, which differs from the fourth variation of the fourth embodiment. Furthermore, the circuit configuration and planar layout of the memory cell array 10L are the same as in the fourth variation of the fourth embodiment. The following description focuses on the differences from the fourth variation of the fourth embodiment.

[0502] 4.9.1 Schema Table

[0503] In this variation, similar to the third variation of the fourth embodiment, the pattern table tblM is used to store pattern information.

[0504] 4.9.2 Write Action

[0505] The write operation of the semiconductor memory device 3L in the fifth variation of the fourth embodiment will be described. Figure 46 This is a flowchart illustrating an example of the write operation of the semiconductor memory device 3L in this variation.

[0506] For example, when a write operation begins, the memory controller 2 selects the storage mode of the selection block BLK based on the write data and updates the mode flag flgM corresponding to the selection block BLK in the mode table tblM (S421).

[0507] Next, the memory controller 2 determines whether the selected memory mode is a normal mode (S422).

[0508] If the selected storage mode is normal mode (S422_Yes), the memory controller 2 instructs the semiconductor storage device 3L to perform the first write operation. Then, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S423). When the first write operation ends, the write operation ends.

[0509] If the selected storage mode is a high readability mode (S422_No), the memory controller 2 instructs the semiconductor memory device 3K to perform a first write operation and a second write operation. Then, the sequencer 13 performs the first write operation based on the instruction received from the memory controller 2 (S424). Next, the sequencer 13 performs the second write operation based on the instruction received from the memory controller 2 (S425). When the second write operation is completed, the write operation ends.

[0510] 4.9.3 Reading Action

[0511] The read operation of the semiconductor memory device 3L in the fifth variation of the fourth embodiment will be described. The read operation of the semiconductor memory device 3L in this variation is the same as the read operation described in the third variation of the fourth embodiment.

[0512] 4.9.4 Effects of this variation example

[0513] According to this variation, the same effect as the fourth variation of the fourth embodiment is achieved.

[0514] 5. Fifth Implementation Method

[0515] The semiconductor memory device 3M according to the fifth embodiment will be described. This semiconductor memory device 3M has computational capabilities, which differs from the fourth variation of the fourth embodiment. The following description will focus on the differences from the fourth variation of the fourth embodiment.

[0516] 5.1 Composition of Semiconductor Memory Devices

[0517] use Figure 47 The configuration of the semiconductor memory device 3M according to the fifth embodiment will be described. Figure 47 This is a block diagram illustrating an example of the configuration of a memory system 1M including the semiconductor memory device 3M of the fifth embodiment.

[0518] like Figure 47 As shown, the semiconductor memory device 3M also includes a computing module 17.

[0519] The arithmetic module 17 is a module that performs various arithmetic operations using the data stored in the memory cell transistor MT. Additionally, the sequencer 13 controls the arithmetic module 17.

[0520] 5.2 Composition of the arithmetic module

[0521] use Figure 48 The structure of the arithmetic module 17 will be explained. Figure 48 This is a block diagram illustrating an example of the structure of the arithmetic module 17. Figure 48 The image also shows the memory cell array 10 and the bit line BL.

[0522] like Figure 48 As shown, the arithmetic module 17 includes multiple registers 18 and multiple arithmetic circuits 19.

[0523] Register 18 stores data received from the memory cell transistor MT within the memory cell array 10, as well as data generated during computational processing. Register 18 contains multiple latch circuits. Data is stored in each latch circuit.

[0524] The operational circuit 19 is a circuit that performs various arithmetic operations. These operations include, for example, addition, subtraction, and comparison.

[0525] On the same bit line BL, there are multiple NAND strings NS, register 18 and arithmetic circuit 19 in each BLK.

[0526] Each BLK within the storage cell array 10 can be either a high-readability BLK or a normal BLK. The NAND string NS within the high-readability BLK stores reference data, such as operation-specified data. Operation-specified data specifies the operation content; for example, "1" indicates addition and "0" indicates subtraction. The NAND string NS within the normal BLK stores input / output data, for example.

[0527] 5.3 Calculation and Processing

[0528] The computational processing performed by the computation module 17 of the semiconductor memory device 3M in the fifth embodiment will be described. Figure 49 This is a flowchart illustrating an example of the computational processing performed by the arithmetic module 17 of the semiconductor memory device 3M in this embodiment.

[0529] For example, when the memory controller 2 receives a computational processing request from the outside, the memory controller 2 instructs the semiconductor memory device 3M to perform computational processing.

[0530] Next, the sequencer 13 controls the arithmetic module 17 based on the instructions received from the memory controller 2. Then, the arithmetic module 17 performs arithmetic processing.

[0531] More specifically, the arithmetic circuit 19 obtains the specified data for arithmetic from the NAND string NS within the high readability BLK (S501).

[0532] Next, the arithmetic circuit 19 obtains input / output data from the NAND string NS in the ordinary BLK (S502).

[0533] Then, the arithmetic circuit 19 performs arithmetic processing based on the arithmetic specification data of the NAND string NS in the high-readability BLK and the input / output data of the NAND string NS in the ordinary BLK. For example, the arithmetic circuit 19 performs arithmetic processing using input / output data based on the arithmetic content specified by the arithmetic specification data (S503).

[0534] Next, the arithmetic circuit 19 stores the arithmetic result RES1 obtained through the arithmetic process into the NAND string NS (S504) within the normal BLK. For example, the arithmetic circuit 19 stores the arithmetic result RES1 into another NAND string NS within the normal BLK. In addition, the arithmetic result RES1 can also be output to the outside of the memory system 1M via the memory controller 2.

[0535] Then, the arithmetic circuit 19 executes the pre-specified algorithm processing based on the arithmetic result RES1 (S505).

[0536] Next, the arithmetic circuit 19 updates the reference data of the NAND string NS within the high readability BLK based on the execution result RES2 (S506). For example, the arithmetic circuit 19 updates the data of the NAND string NS within the high readability BLK based on the execution result RES2.

[0537] 5.4 Composition of the AI ​​(Artificial Intelligence) Module

[0538] The memory system 1M, which includes the semiconductor memory device 3M of the fifth embodiment, can be applied, for example, to an AI module. Figure 50 This is a block diagram illustrating an example of the configuration of an AI module assembled with a memory system 1M including a semiconductor memory device 3M according to the fifth embodiment.

[0539] like Figure 50 As shown, AI module 4 is, for example, a chip with AI installed. AI module 4 includes, for example, a GPU (Graphics Processing Unit) 5 and a memory system 1M.

[0540] GPU5 includes a CPU (Central Processing Unit) 6 and multiple DRAMs (Dynamic Random Access Memory) 7. GPU5 is connected to the memory system 1M.

[0541] CPU6 is, for example, a general-purpose CPU. CPU6 performs various processes. CPU6 is connected to multiple DRAMs 7.

[0542] DRAM7 is, for example, working memory. For instance, DRAM7 stores large amounts of data used in generative AI. Figure 50 The example shows a GPU5 containing 3 DRAM7s, but the number of DRAM7s in a GPU5 may not be 3.

[0543] For example, CPU6 sends an arithmetic processing request to memory system 1M. After receiving the arithmetic processing request, memory system 1M performs the arithmetic processing through arithmetic module 17 of semiconductor storage device 3M.

[0544] 5.5 Effects of this implementation method

[0545] According to this embodiment, the same effect as the fourth variation of the fourth embodiment is achieved.

[0546] Furthermore, in generative AI such as LLM (Large Language Model), machine learning is performed on large amounts of data to generate results. Additionally, in AI modules, for example, the transfer rate between external storage devices is low, thus requiring data to be stored in large amounts of internal DRAM.

[0547] The semiconductor memory device 3M of this embodiment further includes an arithmetic module 17. The arithmetic module 17 includes multiple registers 18 each connected to any bit line BL, and multiple arithmetic circuits 19 each connected to any bit line BL. Additionally, multiple NAND strings NS within the high-readability BLK are each connected to any bit line BL. Multiple NAND strings NS within the ordinary BLK are each connected to any bit line BL.

[0548] Because it has the aforementioned structure, it can be used as described. Figure 49 As described above, it can store reference data, such as calculation-specific data, in a high-readability BLK, and input / output data in a regular BLK. Furthermore, it has computational capabilities. Therefore, it can both store large amounts of reference data and input / output data, and perform computational processing.

[0549] 6. Other

[0550] As described above, the semiconductor memory device (3) of the embodiment includes a plurality of memory strings (NS) arranged separately from each other in a first direction (Z). The plurality of memory strings (NS) each include: a semiconductor layer (22 (CPS)) extending along a second direction (Y) intersecting the first direction (Z); a first string (NSa) disposed on a first side of the semiconductor layer (22) in a third direction (X) intersecting the first direction (Z) and the second direction (Y); and a second string (NSb) disposed on a second side of the semiconductor layer (22) in the third direction (X). The first string (NSa) includes a first selection transistor (ST1a) and a plurality of first memory cell transistors (MT0e to MT7e) arranged separately from each other in the second direction (Y) with the semiconductor layer (22) as a channel. The second string (NSb) includes a plurality of first transistors (TR0 to TR7) and second selection transistors (ST2a) arranged separately from each other in the second direction (Y) with the semiconductor layer (22) as the channel.

[0551] Furthermore, the implementation method is not limited to the method described above, but can be varied in various ways.

[0552] The embodiments and variations described can also be combined within feasible limits. For example, the second variation of the third embodiment can also be combined with the first variation of the third embodiment. The method shown in the second variation of the second embodiment can also be applied to the second to fifth variations of the fourth embodiment and the fifth embodiment. Figure 17 The structure is as follows. The fifth embodiment can also be combined with any of the fourth embodiment, and the first, second, third and fifth variations of the fourth embodiment.

[0553] Furthermore, the processing order of the flowcharts described in the embodiments can be changed within feasible limits.

[0554] In the third embodiment, the string flgS within the block BLK is used. In the first variation of the third embodiment, the string table tblS is used, but the string flag flgS can also be added to the FAT to replace these.

[0555] In the second and fourth variations of the fourth embodiment, the pattern flgM within the block BLK is used, and in the third and fifth variations of the fourth embodiment, the pattern table tblM is used, but the pattern flag flgM can also be added to the FAT to replace these.

[0556] Several embodiments of the present invention have been described, but these embodiments are merely examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are also included within the scope of the invention and its equivalents as described in the claims.

[0557] [Explanation of Symbols]

[0558] 1. Memory System

[0559] 2. Memory controller

[0560] 3 Semiconductor memory devices

[0561] 4 AI modules

[0562] 5 GPU

[0563] 6 CPU

[0564] 7 DRAM

[0565] 10-cell array

[0566] 11 Instruction Register

[0567] 12 Address Register

[0568] 13 Sequencer

[0569] 14 Driver Module

[0570] 15-line decoder module

[0571] 16 Sensing Amplifier Module

[0572] 17. Computation Module

[0573] 18 registers

[0574] 19 Operational Circuits

[0575] 20 substrates

[0576] 21 Insulating layer

[0577] 22 Semiconductor Layer

[0578] 23 Insulating layer

[0579] 30 Conductive film

[0580] 31 Insulating film

[0581] 32 Charge storage membrane

[0582] 33 Insulating film

[0583] 34 Insulators

[0584] 40 Conductive film

[0585] 41 Insulating film

[0586] 50 Conductive film

[0587] 51 Insulating film

[0588] 60 Conductive film

[0589] 61 Semiconductor film

[0590] CPS Semiconductor

[0591] INS insulator

[0592] CGP, SGP, TRP conductive pillars

[0593] MS memory architecture

[0594] BC contact plug

[0595] LBI cabling.

Claims

1. A semiconductor memory device, comprising: Multiple storage strings configured to be separated from each other in the first direction, and The plurality of storage strings each contain: A semiconductor layer extends along a second direction intersecting the first direction; The first string is disposed on the first side of the semiconductor layer in a third direction intersecting the first direction and the second direction; and The second string is disposed on the second side of the semiconductor layer in the third direction; The first string includes a first selection transistor and a plurality of first memory cell transistors arranged and spaced apart from each other in the second direction, each using the semiconductor layer as a channel. The second string includes a plurality of first transistors and second selection transistors arranged and separated from each other in the second direction, each with the semiconductor layer as a channel.

2. The semiconductor memory device according to claim 1, wherein The plurality of first transistors in the second string each have the same structure as the first selection transistor and the second selection transistor.

3. The semiconductor memory device according to claim 1, wherein... During the read operation, for the plurality of first memory cell transistors within the first string, cell current is prevented from flowing in the first memory cell transistors other than the selected first memory cell transistor. Regarding the plurality of first transistors within the second string, cell current is not allowed to flow in one or more first transistors located near the selected first memory cell transistor, while cell current flows in the remaining first transistors.

4. A semiconductor memory device, comprising: Multiple storage strings, each separated from the others in the first direction and configured in each of the multiple blocks, and The plurality of storage strings each contain: A semiconductor layer extends along a second direction intersecting the first direction; The first string is disposed on the first side of the semiconductor layer in a third direction intersecting the first direction and the second direction; and The second string is disposed on the second side of the semiconductor layer in the third direction; The first string includes a first selection transistor and a plurality of first memory cell transistors arranged and spaced apart from each other in the second direction, each using the semiconductor layer as a channel. The second string includes a plurality of second memory cell transistors and a second selection transistor arranged and spaced apart from each other in the second direction, each using the semiconductor layer as a channel. Write write data to either the first string or the second string.

5. The semiconductor memory device according to claim 4, wherein The string to be written into the write data is switched in units of blocks.

6. The semiconductor memory device according to claim 5, wherein The string to be written into the data is switched periodically.

7. The semiconductor memory device according to claim 6, wherein Whenever a write operation is performed on the selected block, the string to be written with the write data is switched.

8. The semiconductor memory device according to claim 4, wherein Write predetermined data into either the first string or the second string.

9. The semiconductor memory device according to claim 8, wherein The predetermined data is the write level data in the SLC.

10. A semiconductor memory device, comprising: Multiple storage strings, each separated from the others in the first direction and configured in each of the multiple blocks, and The plurality of storage strings each contain: A semiconductor layer extends along a second direction intersecting the first direction; The first string is disposed on the first side of the semiconductor layer in a third direction intersecting the first direction and the second direction; and The second string is disposed on the second side of the semiconductor layer in the third direction; The first string includes a first selection transistor and a plurality of first memory cell transistors arranged and spaced apart from each other in the second direction, each using the semiconductor layer as a channel. The second string includes a plurality of second memory cell transistors and a second selection transistor arranged and spaced apart from each other in the second direction, each using the semiconductor layer as a channel. Regarding the plurality of blocks, in the first block where the storage mode is specified as the first mode, write data is written to either the first string or the second string; in the second block where the storage mode is specified as the second mode, write data is written to both the first string and the second string.

11. The semiconductor memory device of claim 10, wherein... Of the plurality of blocks, the fixed block is designated as the first mode.

12. The semiconductor memory device of claim 10, wherein... Based on the number of accesses to the data in the selected block, the boundary position between the first block and the second block within the plurality of blocks is changed.

13. The semiconductor memory device according to claim 12, wherein Regarding the multiple blocks, if the number of reads of the data in the second block exceeds a first threshold within a certain period of time, the storage mode of the second block is switched to the first mode; if the data in the first block is not read within a certain period of time, the storage mode of the first block is switched to the second mode.

14. The semiconductor memory device of claim 10, wherein... During a write operation, specify the storage mode for the selected block.

15. The semiconductor memory device of claim 14, wherein... The plurality of blocks respectively store a first flag as information indicating which of the first and second modes the storage mode of the selected block has been specified as, and During the write operation, update the first flag.

16. A memory system comprising: The semiconductor memory device according to claim 14; and The memory controller controls the semiconductor memory device; and The memory controller includes a first table containing information indicating which of the first and second modes the selected block's storage mode has been assigned to, and updates the first table during write operations.

17. The semiconductor memory device according to claim 10, further comprising: Multiple bit lines, respectively connected to any one of the multiple memory strings contained in each of the multiple blocks; and The computation module; and The computing module includes: Multiple registers, each connected to any one of the bit lines; and Multiple operational circuits are respectively connected to any one of the bit lines; The arithmetic circuit performs arithmetic processing based on the first data of the first storage string in the first block and the second data of the second storage string in the second block, respectively.

18. The semiconductor memory device according to claim 17, wherein The arithmetic circuits perform the arithmetic processing using the second data, based on the arithmetic content specified by the first data.

19. The semiconductor memory device according to claim 17, wherein The arithmetic circuit stores the result of the arithmetic processing into the third storage string within the second block.

20. The semiconductor memory device of claim 17, wherein The arithmetic circuit executes a pre-specified algorithm based on the result of the arithmetic processing, and updates the first data of the first storage string in the first block based on the result of the algorithm processing.

Images