A building electrical distributed power supply access and power balance control method

Abstract

The application relates to the technical field of building electricity and discloses a building electricity distributed power supply access and power balance control method, which comprises the following steps: mapping a micro-grid physical topology state into a legal topology mapping hash state word before operation, and combining power grid disturbance and power supply support capacity to deduce and generate a basic action matrix and an action mask matrix. In a steady state, power supply energy margin is updated into an adequacy state word through synchronous computing power slow loop evaluation, and a dynamic boundary threshold value is deduced; meanwhile, bus electrical quantity change rates are extracted through asynchronous logic fast loop. When the change rates exceed the limit, asynchronous interrupt signals are generated and the current state words are latched, absolute addressing pointers are generated based on this, two groups of matrices are read in parallel, logical operation is carried out, discrete control words are outputted to trigger switch action and power distribution is balanced. The application converts complex software serial iteration calculation into constant time static memory addressing, reduces response delay to the level of hardware gate circuits, and effectively intercepts switching instructions exceeding physical limits.

Description

Technical Field

[0001] This invention relates to the field of building electrical technology, specifically to a method for distributed power supply access and power balance control in building electrical systems. Background Technology

[0002] With the widespread integration of distributed power sources into building electrical systems, power balance control of microgrid systems encountering transient high-frequency fluctuations has become increasingly complex. Conventional control methods mainly rely on a microprocessor-based pure software serial execution architecture, unifying tasks such as monitoring sudden changes in electrical quantities on the distribution bus, assessing energy margins, and calculating control thresholds within the same microprocessor's software computation loop. This mechanism, which relies on instruction fetching, decoding, and serial execution to handle grid transient fluctuations, inevitably introduces multi-level instruction cycle delays, making it difficult to meet the stringent constraints of ultra-fast deterministic physical response time under extreme operating conditions.

[0003] When dealing with the dynamic physical topology of microgrids, the changing state of the power grid, and the operational adequacy of distributed power sources, traditional control schemes typically employ power balancing based on software algorithms, conditional branching, and numerical iterative calculations. Because the number of convergence steps of the software iterative algorithm varies under different system operating conditions, the processing from data acquisition to the output of control commands exhibits significant time uncertainty, severely impacting the synchronization stability of the microgrid system during transient processes.

[0004] In the final control command generation and output stage, existing technologies typically rely solely on software-level logical judgment parameters to constrain switching actions, lacking a low-level hardware-level adjudication mechanism independent of the microprocessor. When the software algorithm fails to accurately align with the chemical discharge limit or thermal safety power limit of the distributed power source before issuing the command due to runtime blockage or communication delays, the control system is prone to issuing over-limit switching actions to the lower-level power execution units. This control behavior, lacking underlying physical isolation, can easily cause severe voltage drops at the microgrid bus in actual operation, and may even lead to secondary disconnection of the microgrid system. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a method for accessing and balancing distributed power sources in building electrical systems. This method solves the problem that existing microgrid power balance control methods, which rely on serial calculations using software instructions, result in excessively long system response delays and cannot meet the constraints on deterministic, ultra-fast physical response time under transient high-frequency fluctuations.

[0006] To achieve the above objectives, the present invention provides the following technical solution: Before the system officially goes into operation, the physical topology state of the microgrid system is mapped to a valid topology mapping hash state word. Combined with the grid disturbance state word characterizing the microgrid's features and the physical support capabilities of distributed generation, a basic action matrix and an action mask matrix are generated and pre-stored. During steady-state operation, the system is separated into a synchronous computing power slow loop and an asynchronous logic fast loop: the available energy margin of distributed generation is evaluated through the synchronous computing power slow loop and converted into a margin state word, while the dynamic boundary thresholds characterizing grid transient fluctuations are dynamically deduced. In parallel, the rate of change of electrical quantities on the microgrid distribution bus is directly extracted via an asynchronous logic fast loop. When the rate of change exceeds a preset static threshold or dynamic boundary threshold, an asynchronous interruption event signal is generated at the pure hardware level. At the instant the asynchronous interruption event is captured, the valid topology mapping hash state word, grid disturbance state word, and adequacy state word are directly latched, and an absolute addressing pointer to the storage block is generated based on each state word. The basic action matrix and action mask matrix are read in parallel using the absolute addressing pointer, and a discrete control word is output through underlying hardware logic operations to directly trigger the power electronic switch action to complete power rebalancing.

[0007] Preferably, when processing the physical topology state of a microgrid system, to eliminate invalid or dangerous topology combinations, this invention obtains the physical auxiliary contact levels of the switches at each node within the microgrid, arranged sequentially as a high-dimensional original physical topology state word. Subsequently, combinations of switching quantities that would cause a short circuit on the microgrid bus or unplanned islanding backfeed are extracted as electrical exclusion dead zones, and these dead zones are stripped from the state space of the original physical topology state word to obtain a set of valid topologies. Finally, a combinational logic gate array is used to compress and encode the high-dimensional valid topology set into a low-dimensional valid topology mapping hash state word. When the input original physical topology state word falls into the electrical exclusion dead zone, the underlying wiring logic actively truncates the mapping path and outputs a forced reset to a preset safe islanding state word.

[0008] In one specific embodiment, the process of separately deriving the basic action matrix and the action mask matrix includes a physically isolated storage design. The optimal switching strategy is derived by jointly using the legal topology mapping hash state word and the grid disturbance state word, generating a basic action vector representing the circuit breaker's action direction and assembling it into a basic action matrix, which is then loaded into the first storage block. Simultaneously, for each quantization level of distributed power adequacy, action mask vectors for blocking or allowing branch switching are constructed and assembled into an action mask matrix, independently loaded into the second storage block. To ensure alignment operations for subsequent hardware decisions, the total bit width of the action mask vector is forcibly constrained to be completely consistent with the total bit width of the basic action vector.

[0009] Preferably, the process of synchronous computing power slow loop evaluation of the available energy margin of distributed power sources is as follows: acquire battery state of charge data and inverter switch junction temperature data, and perform linear interpolation alignment with the absolute timestamp at the start of the current calculation cycle; calculate the chemical discharge power limit based on the state of charge and the thermal safety power limit based on the junction temperature limit respectively, and take the smaller value of the two as the maximum available output active power; perform continuous definite integral on the maximum available output active power within a preset time window to obtain the energy margin, and use a preset multi-level numerical comparison interval to quantize and reduce its dimension to discrete sufficiency state words.

[0010] In one specific embodiment, to address the dynamic changes in microgrid impedance and dynamically deduce dynamic boundary thresholds, the current Thevenin equivalent impedance magnitude is identified online based on synchronously sampled steady-state voltage and current sequences of the bus. Using the microgrid system's preset engineering proportional tuning coefficient, and dividing it by the sum of the Thevenin equivalent impedance magnitude and a preset minimum constant compensation term, the dynamic boundary threshold of the transient power derivative with inverse proportional characteristics is derived. Subsequently, the digital dynamic boundary threshold is converted into a continuous analog reference voltage signal and continuously sent to the analog comparison terminal of the asynchronous logic fast loop.

[0011] Preferably, the mechanism by which the asynchronous logic fast loop generates the asynchronous interrupt event signal relies on pure analog physical comparison. The continuous-time derivatives of the bus active power and bus voltage are extracted as rates of change through analog differentiation operations. These rates of change are then compared logically with the issued continuous analog reference voltage signal and the static voltage derivative threshold. When the continuous-time derivative of the active power exceeds the dynamic boundary threshold, or the continuous-time derivative of the bus voltage exceeds the static voltage derivative threshold, and the difference exceeds the set nonlinear hardware hysteresis band, a hardware hysteresis comparison flip is executed, generating a rising-edge triggered asynchronous interrupt event signal to eliminate false triggering caused by high-frequency switching ripple.

[0012] Preferably, the generation of the absolute addressing pointer is accomplished by calling the internal routing resources of the system call. The captured and latched status words are executed to shift up and concatenated with the physical bits. The concatenated one-dimensional data sequence is directly and equivalently mapped to the absolute addressing pointer for reading the basic action matrix and action mask matrix, saving the software overhead of the processor addressing cycle.

[0013] Furthermore, to prevent address pointer overflow from causing illegal memory access, the system is configured with hard-wired out-of-bounds redirection logic. The absolute address pointer generated by physical bit concatenation is monitored in real time. When it exceeds the physical space limit of the underlying static storage block where data is actually loaded, the hardware logic forcibly truncates the regular addressing enable signal and redirects the absolute address pointer, locking it to a preset safe standby address pool.

[0014] In one specific embodiment, the specific execution steps of the decision-making through logical operation are as follows: the absolute addressing pointer is applied in parallel to the address reading end of the storage matrix, and parity check and forced alignment check are performed on the basic action vector and action mask vector output by synchronous decoding; after the check passes, it is imported into the underlying AND gate logic array to perform bitwise logical AND operation, and the corresponding switching instructions that exceed the safe working area of ​​the distributed power supply in the basic action vector are blocked from the physical level using the action mask vector, and the final discrete control word after being filtered by the actual energy constraint is output.

[0015] Preferably, in the final execution stage of completing microgrid power balancing, the generated discrete control word data stream is independent of the system command bus, directly performs opto-isolation and power push-pull amplification processing, and outputs a strong drive current to turn on or off the relay control coil and power semiconductor drive circuit in the microgrid, thus completing physical-level power switching compensation.

[0016] This invention provides a method for the access and power balance control of distributed power sources in building electrical systems. It has the following beneficial effects: 1. This invention constructs a control architecture that separates synchronous computing power slow loop and asynchronous logic fast loop. Energy assessment and threshold calculation are placed in the synchronous computing power slow loop, while electrical quantity mutation monitoring is placed in the asynchronous logic fast loop. When the rate of change of electrical quantity on the distribution bus exceeds the boundary threshold, the pure hardware link directly generates an asynchronous interrupt event signal, bypassing the serial instruction fetching, decoding, and calculation cycle of the microprocessor, thereby reducing the response delay of microgrid power balance control to the level of physical propagation delay of hardware gate circuits.

[0017] 2. This invention reduces the microgrid physical topology, grid disturbance state, and distributed power source adequacy to discrete state words. Upon capturing an interruption event, it physically concatenates the latched state words to generate absolute addressing pointers to the basic action matrix and action mask matrix. This operation transforms the complex power balancing iterative calculation process into a static memory direct read process with a fixed time complexity, eliminating the time uncertainty caused by branch jumps in software algorithms.

[0018] 3. This invention introduces a dual independent storage structure for the basic action matrix and the action mask matrix. Before outputting the final discrete control word, a bitwise AND operation is performed on the synchronously read basic action vector and action mask vector using a low-level AND gate logic array. The above hardware adjudication mechanism directly blocks switching commands that exceed the chemical discharge limit or thermal safety power limit of the distributed power source, preventing over-limit switching actions from being sent to lower levels, which could cause a drop in bus voltage or secondary disconnection of the system. Attached Figure Description

[0019] Figure 1 This is a hardware architecture topology diagram of an embodiment of the present invention; Figure 2This is a general flowchart of the process of an embodiment of the present invention; Figure 3 The above are waveform comparisons of the transient response of the bus voltage in an embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] See attached document Figure 1 To address the serial waiting latency issue inherent in traditional microprocessors when executing centralized full-scale algorithms, this embodiment employs a heterogeneous dual-ring hardware structure at the physical level, based on deep coupling between a microcontroller unit or digital signal processor and a field-programmable gate array (FPGA). Specifically, the system is divided into a synchronous computing power slow ring for processing low-frequency complex floating-point data calculations, and an asynchronous logic fast ring for executing high-frequency transient load response instructions.

[0022] The synchronous computing slow loop mainly consists of a digital signal processor (DSP), a digital-to-analog converter (DAC), and a communication data bus. As a preferred approach, the DSP is used to collect basic operating parameters of distributed power sources and energy storage devices within the building microgrid, calculate the energy margin of these power sources, and simultaneously acquire the voltage and current sequences of the microgrid bus via the DAC module, identifying the current equivalent impedance of the microgrid online based on the sequence data. The digital signal input of the DAC is connected to the control pin of the DSP, converting the discrete control thresholds calculated and output by the DSP into continuous-time analog reference voltage signals to drive the analog devices in the asynchronous logic fast loop to perform comparison operations.

[0023] The asynchronous logic fast loop mainly includes an analog differentiator circuit, a high-speed analog comparator with hysteresis comparison band, and a field-programmable gate array (FPGA) containing multiple independent dual-port static random access memories. The input of the analog differentiator circuit is connected to voltage and current transformers installed on the busbar of the microgrid distribution cabinet, and its output is electrically connected to the signal comparison input of the high-speed analog comparator. The reference voltage input of the high-speed analog comparator is connected to the analog signal output of the aforementioned digital-to-analog converter, and its level-transition output is physically connected to the external interrupt pin of the FPGA via hardwired connection. The FPGA stores the control logic mapping data of the microgrid switching nodes in its internal storage blocks. Its output pins, after being isolated and amplified by optocouplers, are directly connected to the trip coils of the circuit breakers in each branch of the microgrid and the power semiconductor drive circuits of the distributed power grid-connected inverters.

[0024] To achieve efficient collaboration of the aforementioned hardware architecture, this embodiment constructs a complete control link including preprocessing and real-time dual-loop operation. The macroscopic workflow of this control system is based on the causal transmission relationship of multi-dimensional data, and is specifically divided into the following operation steps: Before the building microgrid system is officially put into operation, based on the electrical interlocking rules for preventing bus short circuits and unplanned backfeeding, the system compresses and reduces the massive original physical topology space into a low-dimensional set of legal topologies. Subsequently, the computer offline simulates the optimal switching strategy under different operating conditions, generates the basic action matrix and action mask matrix, and pre-loads them into the physically isolated first and second storage blocks inside the field-programmable gate array, thereby establishing a control mapping path at the underlying level that does not require clock tick cycles.

[0025] During steady-state operation of the microgrid system, the digital signal processor (DSP) collects real-time data on the battery state of charge (SBC) of the distributed power sources and the junction temperature of the inverter switching transistors. It then deduces the available power margin under current physical constraints and discretizes it into a margin status word, which is refreshed to the underlying registers. Simultaneously, based on the identified Thevenin equivalent impedance of the bus, the processor inversely estimates the dynamic boundary threshold of the transient power derivative and converts it into a smooth, continuous analog reference voltage via a digital-to-analog converter (DAC), continuously sending it to the high-speed analog comparator at the front end.

[0026] Based on the dynamic threshold background of real-time simulation in the slow loop, the fast loop is responsible for independently executing the transient response logic in the absolute time domain. The analog voltage and current sensing signals of the building microgrid bus directly enter the analog differentiating circuit to extract the bus voltage change rate and active power change rate. The high-speed analog comparator performs a composite comparison between the above continuous change rates and the issued analog reference voltage; when encountering a step disturbance caused by the start-up and shutdown of high-power equipment and exceeding the safety hysteresis band, the comparator channel level flips instantaneously, pulling high the external interrupt pin of the field-programmable gate array, generating a globally highest priority asynchronous interrupt event.

[0027] At the moment the rising edge of an asynchronous interrupt event is captured, the field-programmable gate array (FPGA) forcibly freezes and latches the current system topology pin levels, grid disturbance status word, and adequacy status word in the underlying hardware. The system calls internal wiring resources to perform physical bit concatenation of the above multidimensional discrete states, which is equivalent to directly reading the absolute address pointer of the dual-port memory. Subsequently, the two memory blocks output the basic action vector and action mask vector in parallel. After being decided by bitwise logic operations of pure hardware and the FPGA, the final discrete control word is output, which directly triggers the power electronic switch to complete the power realignment of the microgrid.

[0028] See attached document Figure 2To address the engineering flaw of directly concatenating full-dimensional addresses after forcibly discretizing multidimensional continuous physical quantities, which can easily lead to exponential expansion of the underlying hardware memory space, this embodiment constructs a dimensionality reduction mapping mechanism and a cascaded lookup table structure based on pure combinational logic. To ensure zero-instruction-cycle addressing during operation, both the space compression and matrix assembly processes are completed during the offline configuration phase before the system is officially powered on. Specifically, the execution steps are as follows: The system statically acquires the physical auxiliary contact level potentials of the grid-connected circuit breaker, bus tie switch, and solid-state contactors of each branch through the general-purpose input / output port of the microgrid controller. Considering the unavoidable bouncing oscillations of the mechanical auxiliary contacts of the physical switching devices during operation, direct reading can easily generate high-frequency pseudo-topology states and induce matrix addressing out-of-bounds errors. As a preferred approach, this embodiment connects a hardware debouncing logic block based on a shift register in series after the general-purpose input / output port bus. The contact change is only confirmed as valid when a stable, identical level state is captured within a preset number of consecutive clock cycles. The aforementioned debouncing discrete level signals are then sequentially combined and arranged according to the device electrical topology hierarchy to generate a bit-width... The original physical topology state word.

[0029] In this embodiment, for a typical medium- and low-voltage building microgrid, this bit width The value range is typically 16 to 32. This status word constitutes an addressing size of... The original high-dimensional topological state space.

[0030] Furthermore, building microgrids have stringent electrical equipment interlocking restrictions, and not all switch combinations have legitimate physical operational significance. For example, when the main grid incoming circuit breaker and the diesel generator emergency incoming circuit breaker are simultaneously closed without the intervention of a synchronizing grid-connected device, a serious asynchronous shoot-through short-circuit accident will occur. Therefore, the system extracts dangerous switch combinations that lead to microgrid bus short circuits, abnormal circulating currents, or unplanned islanding backfeeding, defining them as an electrical exclusion dead zone topology set.

[0031] To avoid address space explosion caused by independent inputs of multidimensional state variables, the system needs to perform dimensionality pruning at the hardware level. Based on the previously established electrically exclusive dead-zone topology set, unsafe combinations in the original high-dimensional state space are removed to obtain a set of actually runnable legal topologies. To compress the high-dimensional legal topology set to an addressing dimension that can be fully accommodated by the static buffer block inside a low-cost field-programmable gate array, this embodiment uses a pure combinational logic gate array to design a hardware hash mapping path. The essence of this mapping mechanism is to use the Boolean logic simplification function of gate circuits to re-encode the sparse set of valid states into a continuous and compact absolute address space. Considering the fault tolerance requirement of the system under extreme electromagnetic pulse interference, where occasional distortions at the input ports cause the state word to fall into the dead-zone space, this embodiment constructs a segmented hardware mapping logic model with safe redirection protection, as follows: ; In the formula, This represents the valid topological mapping hash state word output after dimensionality reduction through combinational logic gates, and its bit width is [value missing]. And strictly meet ,generally The value is limited to between 8 and 12, thereby compressing the original addressing requirements of hundreds of megabytes to the kilobyte level; The hash mapping function is generated by synthesizing the underlying logic gate circuits embedded inside the field-programmable gate array; The original physical topology status word generated by direct connection of physical pins; A predefined set of electrical exclusion dead zone topologies; For a safety islanding topology word pre-defined in the underlying hardwired layer, its corresponding physical state is defined as forcibly disconnecting all non-critical loads and disconnecting the external grid-connected switch. The engineering purpose of the above piecewise function is to perform efficient addressing compression under normal operating conditions, while simultaneously addressing the state word when abnormal distortion causes it to meet certain conditions. At this time, the underlying routing logic will truncate the normal mapping path, forcibly reset the hash mapping pin and lock it to a guaranteed safe island address, cutting off the path for unexpected out-of-bounds addressing from the physical hardware level. For the specific polynomial simplification and routing network implementation of this hardware hash mapping function, those skilled in the art can use conventional hardware description languages ​​and electronic design automation synthesis tools to generate gate-level netlists and verify timing convergence. The digital circuit synthesis process is well-known in the field and will not be elaborated here.

[0032] Based on the legal topology mapping hash state words generated by dimensionality reduction, and the grid disturbance state words reflecting the fundamental characteristics of the steady-state voltage and current of the bus, the two constitute the basic pointer space for joint addressing. Based on this space, an offline computer is used to deduce the optimal switching strategy for the building microgrid under various superimposed conditions of topology nodes and disturbance step jumps. According to the aforementioned offline strategy, basic action vectors representing only the closing or opening direction of circuit breakers are generated, and all the traversed and generated basic action vectors are arranged in ascending order of absolute address, assembling them to form a basic action matrix. The essential physical meaning of this basic action matrix lies in constructing a basic topology correction benchmark for the passive response of the microgrid system to grid impacts under the ideal constraint of disregarding the attenuation of available energy storage from distributed power sources. The computer, through the standard debugging interface of the joint testing working group, completely and permanently loads the basic action matrix into the first independently allocated dual-port static random access memory within the field-programmable gate array.

[0033] After obtaining the ideal topology correction baseline, since the actual transient discharge capability of distributed generation is not infinite, dynamic real-world constraints must be imposed on it for command filtering. To address the physical constraints that the actual output power of distributed generation is limited by the state of charge and junction temperature, a bit-width parameter is introduced. The adequacy status word serves as a post-addressable pointer. For each quantization level of the adequacy status word, the offline computer constructs a control enable mask vector to block or allow the underlying switching action. This vector sequence is then assembled to form an action mask matrix. To ensure channel alignment in subsequent hardware cascade operations, the total bit width of the mask vector is strictly constrained to be completely consistent with the basic action vector. Internally, a 1 represents allowing the corresponding electrical branch to perform a switching action, and a 0 represents forcibly blocking the branch's action. The technical purpose of this action mask matrix is ​​to construct a dynamic energy constraint filter connected in series with the execution terminal, utilizing the exclusivity of the mask logic to determine whether the switching instructions in the basic action vector are allowed to execute under the current physical support capabilities of the distributed power supply. The computer independently loads the action mask matrix into a second dual-port static random access memory (SRAM) physically isolated from the first memory within the field-programmable gate array (FPGA).

[0034] Based on the aforementioned multidimensional parameter decoupling and physical isolation loading strategy, this embodiment decomposes the global reconfiguration control logic into two orthogonal low-dimensional storage matrices: the basic topology response mapping and the power supply physical capability constraints. Without increasing hardware costs, the system effectively alleviates the memory addressing overflow problem commonly faced by traditional multidimensional lookup tables by utilizing cascaded lookup tables and hash dimensionality reduction mechanisms, establishing a hardware data architecture foundation for subsequent zero-clock-cycle parallel combinational logic execution.

[0035] See attached document Figure 1 and attached Figure 2In this embodiment, because the physical support capabilities of the underlying equipment and the electrical connection strength of the external power grid are constantly changing during the transition between steady-state and transient states in the building microgrid, a synchronous computing power slow loop based on a digital signal processor is configured to match the hard-wired triggering behavior of the asynchronous logic fast loop with the current actual physical boundaries. This slow loop is independent of the underlying nanosecond-level combinational logic execution channel, operates under a fixed timer interrupt cycle at the millisecond level, and is responsible for processing slowly changing parameters that require high-precision floating-point computing power but have low real-time requirements. Its specific parameter background update mechanism includes the following steps: The digital signal processor (DSP) continuously acquires operating parameters from each distributed power node within the microgrid via an external communication interface. Considering that battery state-of-charge (SOC) data, reflecting the energy storage capacity, is typically reported by the battery management system via the controller area network (CLAN) bus, its communication baud rate is low and uncontrollable transmission queuing delays exist; while inverter switching transistor junction temperature data, reflecting the overload capacity of power electronic devices, is directly sampled by an internal thermistor via a high-frequency analog-to-digital converter (ADC), there is an objective physical time difference between the two when they reach the DSP. To avoid subsequent power integration distortion caused by asynchronous multi-source heterogeneous data, the system uses an internal hardware timer to add an absolute timestamp to each arriving data frame. Before performing fusion calculations, the DSP performs linear interpolation on the SOC and junction temperature parameter sequences with historical timestamps, using the current calculation cycle start point as a reference, forcing their operating conditions to align to a unified time observation cross-section.

[0036] After aligning the operating time of the multi-source heterogeneous data, the system needs to quantitatively evaluate the overall disturbance rejection capability of the power system. The general principle of this evaluation is to transform the instantaneous physical power boundary into an energy integral over a continuous time window, thereby reflecting the sustained support depth of the equipment during transient processes. The digital signal processor evaluates the maximum energy support surface that each distributed power source can provide in response to sudden load jumps, based on the current physical constraint state of each source. This process is achieved by definite integration of the constrained maximum available output active power over a specific time window, and its calculation model is as follows: ; In the formula, Representing continuous time The available power integral margin, in essence, is the maximum safe energy pool that a distributed power source can release within the allowable overload time. The time evaluation window preset by the control system is set to 50 milliseconds to 200 milliseconds in this embodiment to effectively cover the transient period caused by the start-up of typical high-power inductive devices. For the integral time infinitesimal; It represents the maximum available active power output of a distributed power source under specific physical constraints. Indicating distributed power sources in Battery state-of-charge parameters after alignment at any given moment; This indicates that the core switching transistor of the inverter is in Junction temperature parameters after alignment processing. As a specific implementation, for the aforementioned maximum available output active power... In its specific deduction, the system employs a multi-dimensional parallel "barrel effect" adjudication logic: the digital signal processor calculates the chemical discharge power limit allowed by the battery based on its current state of charge, and the thermal safety power limit derived by the inverter based on its current junction temperature limit, and uses the smaller of the two values ​​as the final dynamic constraint boundary. This avoids equipment damage due to overcurrent or thermal breakdown caused by relying on a single-dimensional parameter.

[0037] After obtaining a continuous power integral margin, to adapt to the pure logic addressing format of the underlying field-programmable gate array, the digital signal processor uses internally preset multi-level numerical comparison intervals to forcibly reduce the dimensionality of the continuous floating-point number and quantize it into a bit-width format. The binary adequacy status word. In this embodiment, the total bit width of the status word is... Typical values ​​range from 2 to 4 bits, corresponding to the discrete division of the continuous energy assessment space into 4 to 16 safety enable control echelons to balance hardware memory overhead and control granularity. After quantization, the digital signal processor asynchronously refreshes the adequacy status word to the static buffer register configured inside the field-programmable gate array (FPGA) via internal high-level scalable interfaces and other parallel communication buses. The above operations construct the real-time addressing pointer of the underlying action mask matrix, ensuring that the power capability assessment data relied upon by subsequent hardware when executing transient instructions is always kept in the latest steady-state context.

[0038] The ability of a microgrid to resist external power fluctuations is closely related to its electrical distance from the main grid. A digital signal processor (DSP) continuously identifies the Thevenin equivalent impedance of the microgrid bus as viewed from the power source side based on synchronously sampled steady-state voltage and current sequences. For the online identification process of this equivalent impedance, those skilled in the art can use a recursive least squares method with a forgetting factor to estimate the parameters in the discrete-time domain. The specific derivation and calculation steps of the iterative update matrix are well-known techniques in the field and will not be elaborated here.

[0039] After obtaining the Thevenin equivalent impedance modulus, the system needs to dynamically generate a power derivative boundary threshold for triggering pre-event events. The setting of this boundary threshold follows an inverse proportional physical causal logic: when the equivalent impedance is large, it indicates that the microgrid is in an islanded state or at the end of a long-distance power supply, and the grid exhibits fragile properties; even small power fluctuations can trigger excessive voltage drops at the bus. Therefore, the trigger threshold needs to be lowered to improve system response sensitivity. Conversely, when the equivalent impedance is extremely small, it indicates that the microgrid is connected to a large-capacity main grid, and the grid exhibits rigid properties. To avoid frequent false triggers caused by normal load switching, the trigger threshold must be significantly increased. Based on the above causal relationship, the derivation model for the dynamic boundary threshold is as follows: ; In the formula, For continuous time The calculated power derivative triggers the dynamic boundary threshold; The engineering proportional setting factor configured for the initialization of the microgrid system is physically represented as the product of the impedance voltage drop allowed before the system reaches critical instability. It is derived based on the maximum allowable bus voltage deviation rate of building electrical equipment, and in this embodiment, its preferred value range is 1.5 to 3.0. To identify the updated Thevenin equivalent impedance modulus of the microgrid bus; This is an artificially introduced compensation term for minimal normal numbers. As a preferred implementation, The typical value is set to 10. -4 The technical purpose of setting this parameter is to build a bottom-level divide-by-zero protection barrier, effectively preventing the microprocessor's arithmetic logic unit from overflowing or crashing when the impedance suddenly drops to zero due to a near-end metallic short circuit.

[0040] Considering that the core triggering device of the asynchronous logic fast loop is a purely analog high-speed comparator, its physical pins cannot directly identify and parse the digital floating-point format variables output by the microprocessor. To eliminate signal barriers between the hardware and software architectures, the digital signal processor writes the derived dynamic boundary threshold into the data register of the off-chip digital-to-analog converter (DAC). The DAC, based on its reference voltage source and internal resistor network, smoothly converts this discrete digital threshold into a continuous analog reference voltage signal and continuously injects it into the inverting input of the high-speed analog comparator. Through this mechanism, the synchronous computing slow loop completes the dynamic background replacement of the physical trigger boundary with a hardware transmission delay of microseconds without interfering with the continuity of the underlying analog signal.

[0041] See attached document Figure 1 and attached Figure 2Traditional microgrid control systems, when handling transient changes, inevitably introduce inherent software delays of several milliseconds to tens of milliseconds due to their heavy reliance on the discrete sampling period of the analog-to-digital converter and the clock polling mechanism of the processor. To completely overcome this physical bottleneck of the clock cycle, this embodiment constructs an asynchronous logic loop at the front end of the control system, bypassing the digital processing chip. It utilizes pure hardware analog computation and level transition mechanisms to achieve absolute time-domain capture of transient disturbances in the microgrid. This hardwired event triggering mechanism is specifically divided into the following execution steps: The voltage and current transformers at the distribution bus of the building microgrid continuously output analog voltage and current sensing signals. As a preferred low-level feature implementation, these continuous voltage and current sensing signals are directly input in parallel to a high-frequency analog multiplier circuit. Through transconductance amplification and real-time multiplication by the analog devices, an analog voltage scale signal characterizing the continuous active power of the microgrid bus is generated. Subsequently, this power scale signal and the original bus voltage signal are independently fed into an analog differentiating circuit composed of a high-slew-rate operational amplifier and a precision RC network. Based on the physical characteristic that the capacitor charging current is proportional to the rate of change of the terminal voltage, the analog differentiating circuit continuously outputs the time derivative of the bus active power and the time derivative of the bus voltage in the absolute time domain. For the specific source follower or RC parameter matching of the analog multiplier and analog differentiating circuit, those skilled in the art can use conventional analog operational circuit topologies for design and impedance balancing. The hardware implementation details are well-known in the field and will not be elaborated here.

[0042] After acquiring the continuous rate of change signal, the system inputs it into a high-speed analog comparator array with hysteresis comparison characteristics. The non-inverting input of this comparator array receives the real-time rate of change amplitude output from the analog differentiating circuit, while its inverting input is connected to the dynamic power derivative threshold issued by the aforementioned synchronous computing slow loop and the static voltage derivative threshold set by the hardware voltage divider network, respectively. The high-speed analog comparator continuously performs physical-level level comparisons. The logical judgment model for determining whether load surges caused by the start-up and shutdown of high-power electrical equipment within the building meet the system intervention conditions is as follows: ; In the formula, This represents the active power continuously mapped from the building microgrid bus. Indicates the continuous operating voltage of the busbar; The continuous-time derivative of the bus active power extracted for the simulation differential circuit; The continuous-time derivative of the bus voltage is extracted to simulate the differentiating circuit. The dynamic boundary threshold is triggered by the power derivative of the input mapped by the digital-to-analog converter; This is the static simulation threshold for the rate of change of voltage set in the system.

[0043] In this embodiment, The value is determined based on the critical voltage drop slope of the phase-locked loop of the grid-connected inverter in the microgrid for safety derating, with a typical setting range of 5% to 8% per millisecond of the nominal voltage. The technical purpose of the above composite triggering criterion is to, without increasing software overhead, physically or logically fuse the power derivative, which characterizes the intensity of external load impact, with the voltage derivative, which characterizes the vulnerability of the grid itself, effectively avoiding one-sided overshoot misjudgment when the system responds to the switching of locally high-impedance, lightly loaded equipment.

[0044] Furthermore, in the actual operating environment of a microgrid, when the power electronic inverter of a distributed power source performs high-frequency pulse width modulation, a large amount of high-frequency switching ripple will inevitably be superimposed on the bus voltage and current waveforms. If an ideal comparator is used directly, these ripples can easily cause the comparator to experience high-frequency logic flips and oscillations when crossing the critical threshold.

[0045] To address this implementation deficiency, this embodiment incorporates a positive feedback resistor network on the peripheral pins of the high-speed analog comparator, thereby constructing a nonlinear hardware hysteresis comparator band. As a preferred configuration, the voltage hysteresis width of this band is set to 5% to 10% of the reference comparison threshold. The physical significance of this design is to forcibly widen the comparator's state-flipping dead zone, ensuring that minute ripple fluctuations cannot exceed the hysteresis boundary. This guarantees that deterministic state transitions only occur within the comparator's internal channels when the microgrid encounters a substantial high-power step disturbance and generates a significant unidirectional rate of change.

[0046] When the aforementioned composite logic criterion is met, and the increment of the differential input voltage successfully overcomes the hysteresis constraint, the push-pull output stage inside the high-speed analog comparator switches to the on state. The comparator output then generates a voltage rising edge signal with an extremely steep edge. This rising edge signal is fed directly into the pre-allocated external highest-priority interrupt pin of the field-programmable gate array (FPGA) via a dedicated microstrip line on the printed circuit board using physical hard-wired connections. Upon capturing the rising edge of this asynchronous interrupt event, the FPGA's underlying input buffer module immediately wakes up and triggers the subsequent hardware logic's data freeze and absolute memory addressing process. Based on this mechanism, this purely hardware-based triggering path completely isolates the system instruction bus, strictly compressing the entire link time overhead from event perception to generation to a nanosecond-level transistor signal propagation delay, thus securing an irreplaceable physical time window for the zero-cycle output of the subsequent power balancing matrix.

[0047] See attached document Figure 1 and attached Figure 2After acquiring the hardware trigger pulse generated by the asynchronous logic fast-loop preamplifier, conventional microprocessor architectures are prone to uncontrollable software latency cycles due to the serial execution mechanism of instruction decoding, bus arbitration, and arithmetic logic unit operations. To overcome this inherent defect and achieve ultra-fast response from physical state perception to low-level instruction issuance, this embodiment constructs a cascaded absolute addressing and pure combinational logic output link completely independent of the system clock scan cycle at the hardware physical level of the field-programmable gate array (FPGA). Its specific hardware response and execution process includes the following steps: When the highest priority external interrupt pin configured by the field-programmable gate array (FPGA) captures the rising edge of an asynchronous interrupt event generated by the preamplifier analog comparator, its underlying hardware triggering network immediately freezes and latches the current system communication ports and internal buffer registers' level states. Specifically, the latched multidimensional binary data sequence includes the valid topology mapping status word output after dimensionality reduction via combinational logic hashing, the grid disturbance status word characterizing bus voltage and power fluctuations, and the adequacy status word calculated and refreshed by the synchronous computing slow loop under the latest steady-state background.

[0048] In the general technical principle of mapping multidimensional states to one-dimensional memory addresses, the traditional approach usually relies on the arithmetic addressing adder of a general-purpose processor; however, this embodiment bypasses processor overhead and relies on the programmable routing resources inside the field-programmable gate array to directly perform hardware-level physical bit splicing operations. This physical bit splicing operation uses static routing to shift multidimensional state variables to higher levels and apply pin combinations, and its equivalent mathematical mapping model is as follows: ; ; In the formula, This is a multi-bit absolute addressing vector used to directly read the basic action matrix stored in the first dual-port static random access memory; This is a multi-bit absolute addressing vector used to read the action mask matrix stored in the second dual-port static random access memory; The first state word mapped to the legal topology of the microgrid Bit-bit discrete binary data; The first of the bus grid disturbance status words Bit-bit discrete binary data; The first quantization of cache sufficiency status word Bit-bit discrete binary data; This represents the total bit width of the dimensionality reduction word in a valid topological mapping. The total bit width of the power grid disturbance status word; The total bit width of the sufficiency status word; , , These represent the physical bit order indexes corresponding to each status word. As a typical engineering configuration, this embodiment... The value is limited to between 8 and 12. and They are set to 8 bits and 2 to 4 bits respectively.

[0049] The physical significance of implementing the aforementioned forced binary shift concatenation lies in effectively mapping the multi-dimensional combination of operating conditions, which originally relied heavily on conditional branch statements, into a continuous one-dimensional hardware memory addressing space. Considering that under extreme strong electromagnetic pulse conditions, pin level distortion may cause the concatenated address pointer to exceed the actual memory loading depth, leading to address out-of-bounds access and system deadlock, this embodiment adds hard-wired out-of-bounds monitoring and redirection logic outside the high-efficiency bits of the underlying address decoding network. When the parallel address vector exceeds the preset physical space limit, the hardware logic will immediately truncate the address enable signal and forcibly redirect the pointer to the underlying safe standby address pool, thereby effectively preventing the system from outputting uncontrollable random and dangerous instructions.

[0050] After establishing an absolute hardware memory pointer with out-of-bounds protection, the system executes a comprehensive topology response benchmark and considers the actual energy support capability to output the final power drive control sequence. The generated absolute addressing pointer... and The signals are applied directly and in parallel as physical electrical signals to the address pins of the internally independent first dual-port static random access memory (SRAM) and second dual-port SRAM. After a hardware delay of one basic register read cycle, the data bus ports of the two static memory blocks synchronously output the basic action vector and action mask vector in the corresponding address space.

[0051] To ensure the rigor of subsequent multidimensional constraint logic, the underlying hardware performs forced alignment checks on the two sets of output vectors. Only when both sets have the same bit width and the parity check bits are normal, are these two sets of parallel data sequences carrying different engineering constraint dimensions imported into the underlying pure hardware AND gate logic array via pre-installed printed interconnects within the chip. Utilizing the independent and parallel electrical signal conduction characteristics of hardware gate circuits, the system completes the composite dimensionality reduction operation of basic control commands and actual energy constraints within a nanosecond scale. The logical model for its mask filtering execution and final action output is as follows: ; In the formula, The system outputs high and low level discrete control word data streams to each switch actuator of the microgrid after undergoing two-dimensional logic filtering. The basic action vector is decoded and output from the first dual-port static random access memory based on the combined physical address; The dynamic action mask vector for the synchronous decoding output of the second dual-port static random access memory; This represents bitwise logic AND operations implemented based on underlying silicon-based transistor gate circuits.

[0052] For the extraction of parasitic capacitance, matching of logic gate fan-out capability, and assessment of critical path delay in the internal hardware routing of field-programmable gate arrays, those skilled in the art can use standard digital front-end synthesis and timing analysis tools for timing convergence design. The specific underlying physical synthesis and routing technology is a well-known technology in this field and will not be elaborated here.

[0053] The technical purpose of employing this hardware cascaded masking arithmetic system is to use the current power margin capacity pool determined under a slow-loop background as a bottom-level rigid filter to unconditionally block irrational switching actions in the basic action vector that might force power devices to exceed their safe operating range (such as heat dissipation limits or lower discharge depth limits). Based on this architecture, the complete computation link of the discrete control word is completely independent of the system's central processing unit and system bus. The time overhead of its instruction generation is limited only by the physical charging and discharging propagation delay of the transistor junction capacitance within the multi-level logic gates. Finally, the logic level data stream generated by the general-purpose output port undergoes opto-isolation and power push-pull amplification via a high-speed optocoupler configured on an external circuit board, directly turning on or off the solid-state relay control coils and power switches in the microgrid with a strong drive current. This achieves rapid intervention and power rebalancing of the microgrid's anti-disturbance strategy from the physical execution end.

[0054] To visualize the underlying hardware architecture and abstract mathematical logic constructed above, a specific application example based on a microgrid in a typical commercial building is provided below.

[0055] Specific application scenario parameter configuration: In the specific application scenario of this embodiment, a microgrid of a commercial complex containing multi-source heterogeneous equipment is selected as the control object. The nominal voltage of the main distribution bus of this microgrid is 380V, and the following main electrical equipment is connected in parallel internally: Distributed power generation and energy storage nodes: a rooftop photovoltaic power generation array with an installed capacity of 250kW, and a lithium iron phosphate battery energy storage system with a rated power of 200kW and a capacity of 500kWh (connected to the bus via a full-bridge grid-connected inverter).

[0056] Typical load nodes: stable loads such as basic lighting and office equipment are about 100kW; building central air conditioning chillers are about 150kW; high-power elevator traction motor groups can generate a step change in active power of up to 120kW when multiple units start up simultaneously.

[0057] Actual operational simulation of heterogeneous dual-ring architecture: Based on the above physical topology, the system executes the following multi-dimensional control logic during operation: During steady-state operation, the microgrid is connected to the grid, with stable base load and normal operation of the central air conditioning system. The digital signal processor (DSP) in the slow loop of the synchronous computing power continuously monitors the status of the energy storage system. Assuming the battery management system reports a state of charge of 45% and the inverter junction temperature is 65°C, the DSP calculates that the energy storage system still has a transient overload capacity of 150kW and quantifies this capacity as a margin status word, writing it into the underlying field-programmable gate array (FPGA). Simultaneously, the processor identifies online that the Thevenin equivalent impedance of the microgrid looking towards the main grid is approximately 0.05Ω. Combining this with the system's proportional gain setting of 2.0, the slow loop extrapolates the current power derivative trigger boundary as follows: ; The digital signal processor converts the discrete threshold into an analog reference voltage via a digital-to-analog converter and sends it to the high-speed comparator.

[0058] When multiple elevators inside the building start simultaneously at the same absolute point in time, the power distribution busbar suffers a severe inductive load impact. The waveform of the current transformer at the distribution cabinet exhibits high-slope distortion. The analog differential circuit in the asynchronous logic fast loop detects in real time that the rate of change of active power on the busbar instantly surges to 55kW / ms, significantly exceeding the aforementioned dynamic safety threshold of 39.92kW / ms.

[0059] At this moment, the high-speed analog comparator overcomes hysteresis, and its output level flips instantaneously, generating a nanosecond-level hardware interrupt. Upon capturing this rising edge, the field-programmable gate array (FPGA) immediately freezes all port states. Since the current adequacy status word indicates that the energy storage system (150kW support capacity) is sufficient to cover the step disturbance (120kW) during elevator startup, the underlying bitwise AND operation (mask logic) will allow the energy storage system to issue additional commands. Without microprocessor intervention, the FPGA directly sends a pulse-width modulation (PWM) intervention signal to the energy storage inverter via an optocoupler, forcing it to enter a transient high-frequency discharge mode, thus completing on-site compensation for the power deficit at the physical ultra-fast response level.

[0060] Experimental verification and effect comparison: To further verify the response performance of the above heterogeneous dual-ring architecture under real physical boundaries, as a preferred comparative verification method, this embodiment builds an accurate electromagnetic transient model containing high-frequency switching actions in a simulation environment, and compares the performance of the present invention with that of the traditional microgrid control scheme based on serial polling scanning of programmable logic controller (PLC) under the same operating conditions.

[0061] Combined with appendix Figure 3 It can be seen that, Figure 3This is a comparative waveform diagram of the transient response of the bus voltage in a building microgrid under high-power load sudden change conditions. In the figure, the horizontal axis is set as absolute physical time (s), and the vertical axis represents the effective value of the bus voltage of the microgrid (V). The horizontal dotted line in the figure represents the critical safe voltage baseline allowed by national standards (i.e., the extreme boundary of the nominal voltage of 380V allowed to float down by 7%, corresponding to 353.4V).

[0062] Based on the above simulation environment, the system is set to encounter an extreme test condition at 0.1s absolute physical time, where multiple high-power elevators start up simultaneously. The power distribution bus is instantly subjected to a severe step impact from the inductive load, and the voltage begins to show a sharp drop.

[0063] observe Figure 3 As shown by the thick dashed line (traditional control scheme), the traditional serial architecture is limited by the sample-and-hold period of the analog-to-digital converter, data queuing on the communication bus, and the interrupt suspension mechanism inside the microprocessor. This results in a significant millisecond-level lag in the control link from the occurrence of a disturbance to the output of a compensation command. This physical response dead zone leads to a severe short-term power imbalance at the grid connection point, with the bus voltage continuously bottoming out and dropping to a global minimum of 318V at approximately 0.12 seconds. This extreme value significantly breaches the safety baseline of 353.4V, with an actual maximum voltage deviation rate as high as 16.3%. In engineering applications, such deep voltage sags can easily trigger unplanned grid disconnection protection for low-voltage sensitive equipment such as frequency converters and precision medical instruments within the system, and may even cause large-scale power outages in the microgrid.

[0064] contrast Figure 3 The thick solid line in the diagram (in this embodiment) illustrates how the heterogeneous dual-loop control system constructed using this invention enables extremely rapid capture of sudden changes through a bypass link composed of pure combinational logic and analog comparators. Since the entire link delay consistently converges to a nanosecond scale within 850ns, the energy storage device's power generation command is directly triggered and executed via hard-wired connection. Reflected in the transient waveform, the bus voltage is forcibly clamped and quickly bottoms out and rebounds approximately 0.105s after the disturbance occurs, with its extreme drop effectively limited to 368V.

[0065] Based on a comprehensive comparison of waveform data, the solution of this invention, through its underlying nanosecond-level cascaded masking interception, successfully reduced the maximum voltage deviation rate under high-power step disturbances to 3.1%, converging above the safety margin (353.4V) for building electrical equipment. Combined with... Figure 3 The subsequent recovery slopes of the two curves clearly indicate that this embodiment not only fundamentally reduces the voltage drop depth but also significantly shortens the transient recovery time for the system to rebuild a steady state, effectively and significantly improving the power quality and transient resilience of the microgrid from the physical execution end.

Claims

1. A method for accessing and controlling distributed power sources in building electrical systems, characterized in that, Includes the following steps: Before the microgrid system is officially put into operation, the physical topology state of the microgrid system is reduced in dimension and mapped to a valid topology mapping hash state word. Combined with the grid disturbance state word that characterizes the microgrid and the physical support capability of distributed power sources, the basic action matrix and action mask matrix are generated and stored respectively. During steady-state operation, the available energy margin of distributed power sources is evaluated through a slow loop of synchronous computing power and updated to discrete sufficiency state words. At the same time, dynamic boundary thresholds characterizing transient fluctuations of the power grid are dynamically deduced. The rate of change of electrical quantities of the microgrid distribution bus is extracted by an asynchronous logic fast loop. When the rate of change is greater than a preset static threshold or a dynamic boundary threshold, an asynchronous interruption event signal is generated. At the instant the asynchronous interrupt event is captured, the current valid topology mapping hash state word, the power grid disturbance state word, and the adequacy state word are directly latched. Physical bit concatenation is performed on each latched state word to generate absolute address pointers pointing to the basic action matrix and the action mask matrix, respectively. The basic action matrix and the action mask matrix are read in parallel using the absolute addressing pointer. After logical operation and decision-making, a discrete control word is output to trigger the power electronic switch action to complete the power rebalancing of the microgrid.

2. The method for building electrical distributed power supply access and power balance control according to claim 1, characterized in that, The specific process of reducing the dimensionality of the physical topology state of the microgrid system to a valid topology mapping hash state word is as follows: The physical auxiliary contact levels of each node switch in the microgrid are obtained, and the physical auxiliary contact levels are arranged sequentially to generate a high-dimensional original physical topology state word. Extract the combinations of switching quantities that could lead to short circuits in the microgrid bus or unplanned backfeeding in islanding, and define the combinations of switching quantities as electrical exclusion dead zones; The electrical exclusion dead zone is extracted from the state space corresponding to the original physical topology state word to obtain a high-dimensional legal topology set; The high-dimensional legal topology set is compressed and encoded into a low-dimensional legal topology mapping hash state word using a combinational logic gate array; Specifically, when the input original physical topology status word falls into the electrical exclusion dead zone, the mapping path is cut off through the underlying wiring logic, and a forced reset to the preset safe island status word is output.

3. The method for building electrical distributed power supply access and power balance control according to claim 1, characterized in that, The specific process of separately deriving and generating the basic action matrix and the action mask matrix is ​​as follows: By combining the legal topology mapping hash state word and the power grid disturbance state word, the optimal switching strategy is deduced, and a basic action vector representing the closing or opening direction of the circuit breaker is generated. This vector is then assembled into a basic action matrix and loaded into the first storage block. For each quantization level of distributed power adequacy, construct an action mask vector for blocking or allowing the corresponding electrical branch to perform switching actions, assemble it into the action mask matrix, and load it independently into a physically isolated second storage block; The total bit width of the action mask vector is forcibly constrained to be exactly the same as the total bit width of the basic action vector.

4. The method for building electrical distributed power supply access and power balance control according to claim 1, characterized in that, The specific process of evaluating the available energy margin of distributed power sources and updating it to discrete sufficiency state words is as follows: Obtain the battery state-of-charge data and inverter switch junction temperature data of the distributed power source, and perform linear interpolation alignment of the absolute timestamp based on the start of the current calculation cycle. Calculate the chemical discharge power limit allowed based on the battery state of charge data and the thermal safety power limit limited based on the inverter switch junction temperature data, respectively. Compare the chemical discharge power limit and the thermal safety power limit, and determine the smaller of the two values ​​as the maximum available output active power. The available energy margin is obtained by continuously integrating the maximum available output active power within a preset time window. The available energy margin is then quantified and reduced to discrete sufficiency state words using a preset multi-level numerical comparison interval.

5. The method for building electrical distributed power supply access and power balance control according to claim 1, characterized in that, The specific process of dynamically extrapolating and characterizing the dynamic boundary threshold for transient fluctuations in the power grid is as follows: Based on the synchronously sampled steady-state voltage and current sequences of the microgrid bus, the current Thevenin equivalent impedance magnitude is identified and obtained online. By using the preset engineering proportional setting coefficient of the microgrid system and dividing it by the sum of the Thevenin equivalent impedance modulus and the preset minimum constant compensation term, the dynamic boundary threshold of the inverse proportional characteristic is derived. The preset engineering ratio setting coefficient is obtained based on the maximum allowable voltage deviation limit of the microgrid bus and the rated capacity setting of the distributed power source. The dynamic boundary threshold in digital format is converted into a smooth, continuous analog reference voltage signal and continuously sent to the analog comparison terminal of the asynchronous logic fast loop.

6. The method for building electrical distributed power supply access and power balance control according to claim 5, characterized in that, The specific process for generating the asynchronous interrupt event signal is as follows: The continuous-time derivatives of the bus active power and the bus voltage are extracted as the rate of change by analog differential operation. The continuous-time derivatives of the extracted bus active power and bus voltage are compared in hardware with the issued continuous analog reference voltage signal and the static threshold, respectively. When the difference between the continuous-time derivative of the active power of the bus and the continuous analog reference voltage signal, or the difference between the continuous-time derivative of the bus voltage and the static threshold, is greater than the set nonlinear hardware hysteresis band, a hardware hysteresis comparison flip is executed, generating an asynchronous interrupt event signal triggered by a rising edge.

7. The method for building electrical distributed power supply access and power balance control according to claim 1, characterized in that, The specific process for generating an absolute addressing pointer is as follows: The internal wiring resources are invoked to perform upshifting of each latched status word and concatenation with the physical bits. The one-dimensional data sequence after bit concatenation is equivalently mapped to an absolute addressing pointer for directly reading the basic action matrix and the action mask matrix.

8. A method for accessing and balancing distributed power sources in building electrical systems according to claim 7, characterized in that, After generating the absolute address pointer, the process also includes a hard-wired out-of-bounds redirection logic process, which specifically includes: The absolute addressing pointer generated by the physical bit splicing is monitored in real time. When the absolute addressing pointer is greater than the physical space limit of the actual data loaded in the underlying static storage block, the hardware logic cuts off the normal addressing enable signal and forcibly redirects and locks the absolute addressing pointer to the preset safe standby address pool.

9. A method for accessing and balancing distributed power sources in building electrical systems according to claim 1, characterized in that, The specific process of making a decision through logical operations is as follows: The absolute addressing pointers are applied in parallel to the address reading end of the storage matrix, and parity check and forced alignment check are performed on the basic action vector and action mask vector of the synchronous decoding output. After verification, the data is imported into the underlying AND gate logic array to perform bitwise AND operations. The action mask vector is used to block the corresponding switching instructions in the basic action vector that exceed the safe operating area of ​​the distributed power supply. The final discrete control word is then output after being filtered by the actual energy constraints.

10. A method for accessing and balancing distributed power sources in building electrical systems according to claim 1, characterized in that, The specific process for completing the power realignment of the microgrid is as follows: The generated discrete control word data stream is independent of the system instruction bus. After direct opto-isolation and power push-pull amplification, it uses a strong drive current to turn on or off the relay control coil and power semiconductor drive circuit in the microgrid, thus completing the power switching compensation at the hardware execution end.

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