Spiking absorption circuit, spiking absorption method and switched mode power supply

Abstract

A spike absorption circuit, a spike absorption method, and a switching power supply are disclosed. The spike absorption circuit, applied in a switching converter, includes: a clamping transistor; a clamping capacitor connected in series with the clamping transistor and then connected to a synchronous rectifier to form a closed loop; and a clamping control module. After the main power transistor is turned on, the module detects the drain-source voltage of the clamping transistor, times a first time interval from when the drain-source voltage of the clamping transistor falls below a first threshold to when it rises above a second threshold, and controls the clamping transistor to conduct for a second time interval from the end of the time interval until the main power transistor is turned off. This precisely limits the charging and discharging time of the clamping capacitor, allowing it to absorb the voltage spike generated on the synchronous rectifier when the main power transistor is turned on during the first time interval, and recover the absorbed energy to the input terminal during the second time interval. This reduces stress on the secondary side, ensures system safety, reduces absorption losses, and improves system efficiency.

Description

Technical Field

[0001] This application relates to the field of switching power supply technology, specifically to a spike absorption circuit, a spike absorption method, and a switching power supply. Background Technology

[0002] With the rapid development of electronic systems, people have increasingly higher demands for high power density and high efficiency switching power supply converters. Isolated switching power supplies have been widely studied and applied due to their excellent characteristics such as high efficiency, full-range soft switching, and adaptability to high switching frequencies.

[0003] Common isolated switching power supplies, such as flyback converters and forward converters, typically include a main power transistor, a transformer, and a synchronous rectifier. The transformer includes a primary winding and a secondary winding. The main power transistor and a sampling resistor are connected to the primary winding, and the main power transistor's on / off state is controlled by a primary-side control circuit. The synchronous rectifier is connected to the secondary winding, and its on / off state is controlled by a synchronous rectification control circuit. The main power transistor and the synchronous rectifier generally operate alternately on and off.

[0004] With the advent of PD adapters, the output voltage range has expanded from 3.3V to 48V. To provide sufficient duty cycle margin at low voltage output, the transformer turns ratio has to be made smaller. However, with the same turns ratio, the secondary-side reflected voltage increases exponentially at high voltage output. When the main power transistor is turned on, the parasitic capacitance on the inductor and synchronous rectifier resonates, generating a voltage spike across the synchronous rectifier. Due to the increased secondary-side reflected voltage, the peak stress experienced by the synchronous rectifier at the moment of turn-off increases dramatically. While traditional Zener diode or TVS diode clamping is simple, it converts all leakage inductance energy into heat, resulting in significant efficiency loss, especially at high voltages. Adding RC absorption on the secondary side can recover some energy, but this increases both the number of components and the heat dissipation area, failing to meet the requirements for size and cost. Similarly, slowing down the primary-side turn-on speed also degrades system efficiency. Therefore, there is currently no solution that can dynamically suppress stress spikes on the secondary side, recover leakage inductance energy without loss, and simultaneously balance cost and system efficiency. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a spike absorption circuit, a spike absorption method, and a switching power supply, which can clamp the stress on the secondary side within a safe range while recovering leakage inductance energy and improving system efficiency.

[0006] According to one aspect of the present invention, a spike absorption circuit is provided for use in a switching converter, the switching converter including a transformer, a main power transistor connected to the primary winding of the transformer, and a synchronous rectifier connected to the secondary winding of the transformer, wherein the spike absorption circuit includes: a clamping transistor; a clamping capacitor connected in series with the clamping transistor and then connected to the synchronous rectifier to form a closed loop; and a clamping control module that detects the drain-source voltage of the clamping transistor after the main power transistor is turned on, times a first time interval from when the drain-source voltage of the clamping transistor is below a first threshold to when it is above a second threshold, and controls the clamping transistor to be turned on for a second time interval from when the timing ends until the main power transistor is turned off.

[0007] Optionally, the clamping control module controls the clamping transistor to remain on during the first time interval or to allow freewheeling through the body diode of the clamping transistor, so that the clamping transistor, the clamping capacitor, and the synchronous rectifier form a current loop, and absorb the energy generated by the voltage spike across the synchronous rectifier when the main power transistor is turned on through the clamping capacitor.

[0008] Optionally, the clamping transistor is turned on during the second time interval so that the clamping transistor, the clamping capacitor, and the secondary winding form a current loop, thereby recovering the energy on the clamping capacitor to the input terminal of the switching converter.

[0009] Optionally, the current direction on the clamping tube is opposite during the first time interval and the second time interval.

[0010] Optionally, when the clamping control module detects that the drain-source voltage of the clamping transistor is less than a first threshold, it controls the clamping transistor to turn on and starts timing. After the clamping transistor is turned on for the first time interval, it controls the clamping transistor to continue to be turned on for the second time interval and then turns off the clamping transistor.

[0011] Optionally, when the clamping control module detects that the drain-source voltage of the clamping transistor is less than a first threshold, it controls the clamping transistor to turn on and starts timing. After the first time interval ends, the clamping transistor is turned off to reach a third time interval. Then, the clamping transistor is turned on again for the second time interval, and then the clamping transistor is turned off again.

[0012] Optionally, when the clamping control module detects that the drain-source voltage of the clamping transistor is less than a first threshold, it controls the clamping transistor to remain on for a set fourth time interval, the fourth time interval being greater than the first time interval.

[0013] Optionally, the clamping control module also receives an error amplification signal characterizing the turn-on time of the main power transistor, so as to control the clamping transistor to be turned on for a period of time before the turn-on time of the main power transistor, so that the main power transistor achieves zero-voltage turn-on, wherein the error amplification signal is obtained based on the feedback signal of the output voltage and the reference voltage.

[0014] Optionally, the clamping capacitor is connected in series with the clamping tube and then in parallel across the two ends of the synchronous rectifier tube, or in parallel across the two ends of the secondary winding of the transformer, wherein the synchronous rectifier tube includes a transistor or a diode.

[0015] Optionally, the clamping control module includes: a voltage detection module for real-time detection of the drain-source voltage of the clamping transistor; a timing module for starting timing when the drain-source voltage of the clamping transistor is greater than a first threshold and ending timing when the drain-source voltage of the clamping transistor is greater than a second threshold; and a conduction control module for generating a drive signal based on the outputs of the voltage detection module and the timing module to control the on / off state of the clamping transistor.

[0016] Optionally, the clamping transistor and the clamping control module are integrated into the same chip, the chip including: a first pin, led out from the drain end of the clamping transistor; a second pin, led out from the source end of the clamping transistor and externally connected to the clamping capacitor; and a third pin, serving as the power supply pin of the chip.

[0017] Optionally, the chip is packaged together with a synchronous rectification control circuit that controls the conduction state of the synchronous rectifier tube.

[0018] According to another aspect of the present invention, a switching power supply is provided, comprising a transformer, the transformer including a primary winding and a secondary winding, wherein the switching power supply further comprises: a main power transistor connected to the primary winding; a synchronous rectifier transistor connected to the secondary winding; and the aforementioned spike absorption circuit for absorbing the energy generated by voltage spikes on the synchronous rectifier transistor when the main power transistor is turned on.

[0019] According to another aspect of the present invention, a spike absorption method is provided, applied in a switching converter, the switching converter including a transformer, a main power transistor connected to the primary winding of the transformer, and a synchronous rectifier connected to the secondary winding of the transformer, the synchronous rectifier forming a closed loop with a clamping transistor and a clamping capacitor, wherein the spike absorption method includes: detecting the drain-source voltage of the clamping transistor after the main power transistor is turned on; timing a first time interval from when the drain-source voltage of the clamping transistor is below a first threshold to when it is above a second threshold; and controlling the clamping transistor to be turned on for a second time interval from when the timing ends until the main power transistor is turned off.

[0020] Optionally, the spike absorption method further includes: controlling the clamping transistor to remain on or to freewheel through the body diode of the clamping transistor during the first time interval, so that the clamping transistor, the clamping capacitor and the synchronous rectifier form a current loop.

[0021] The embodiments of the present invention have at least the following beneficial effects:

[0022] The spike absorption circuit, spike absorption method, and switching power supply provided by this invention connect a clamping transistor and a clamping capacitor in series with a synchronous rectifier to form a closed loop. A first time interval is defined by detecting the drain-source voltage of the clamping transistor. By comparing a first threshold and a second threshold, the first time interval is calculated in real time based on the transient changes in the drain-source voltage, thereby precisely defining the charging and discharging time of the clamping capacitor. This ensures that the leakage inductance energy is absorbed by the clamping capacitor within the required time, reducing stress on the secondary side, minimizing absorption losses while recovering leakage inductance, and improving system efficiency. Furthermore, during the first time interval, the clamping capacitor absorbs the energy generated by voltage spikes on the synchronous rectifier, while during the second time interval, the energy absorbed by the clamping capacitor is recovered through the secondary winding, achieving energy reuse, ensuring system safety and stability, and improving overall system efficiency.

[0023] Furthermore, during the first time interval, the clamping transistor is kept either on or off, forming an absorption circuit with a clamping capacitor via a body diode. During the second time interval, the clamping transistor is controlled to turn on, forming an energy recovery circuit. The length and start time of the second time interval can be adjusted in real time, resulting in diverse control modes to adapt to different circuit requirements. Additionally, when keeping the clamping transistor on during the first time interval, the second time interval can continue to be on after the first time interval ends, followed by the clamping transistor being turned off, simplifying the control scheme. Alternatively, the third time interval can be turned off after the first time interval ends, followed by the second time interval, achieving intermittent energy recovery, avoiding the impact of a single large current on the circuit, and reducing EMI. Furthermore, a fourth time interval can be directly set when the drain-source voltage is detected to be less than a first threshold, further simplifying the control scheme. Multiple schemes are adaptively adjusted to enhance the applicability of the spike absorption circuit.

[0024] Furthermore, the clamping transistor can be turned on for a short period of time before the main power transistor turns on, so as to discharge the charge on the parasitic capacitance of the main power transistor, achieve zero-voltage turn-on of the main power transistor, reduce turn-on losses, and improve system efficiency.

[0025] Furthermore, by removing the clamping capacitor from the spike absorption circuit and packaging it into a three-pin chip, spike absorption can be achieved with only one external surface-mount capacitor. Compared to traditional absorption circuits, the new product has a smaller area and higher density. It can also be integrated with synchronous rectification control circuits, further reducing costs and size.

[0026] It should be noted that the above general description and the following detailed description are exemplary and explanatory only, and do not limit the present invention. Attached Figure Description

[0027] Figure 1 A schematic circuit diagram of a switching power supply according to an embodiment of the present invention is shown;

[0028] Figure 2 A schematic circuit block diagram of a spike absorption circuit according to an embodiment of the present invention is shown;

[0029] Figure 3 A schematic circuit diagram of a spike absorption circuit according to a first embodiment of the present invention is shown;

[0030] Figure 4 A schematic circuit diagram of a spike absorption circuit according to a second embodiment of the present invention is shown;

[0031] Figure 5 A schematic waveform diagram of various signals of a switching power supply during operation according to an embodiment of the present invention is shown;

[0032] Figure 6 A schematic structural block diagram of an integrated chip according to an embodiment of the present invention is shown;

[0033] Figure 7 A schematic flowchart of a peak absorption method according to an embodiment of the present invention is shown. Detailed Implementation

[0034] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0035] Figure 1 A schematic circuit diagram of a switching power supply according to an embodiment of the present invention is shown. The switching power supply is, for example, an isolated switching power supply, including a transformer T, which includes a primary winding Np and a secondary winding Ns coupled together. Adapted switching power supplies may include conventional flyback converters, asymmetric half-bridge flyback converters, and active clamp flyback converters, etc. This embodiment uses a conventional flyback topology as an example.

[0036] like Figure 1 As shown, the flyback switching power supply 10 of this embodiment includes a main circuit, a primary-side control circuit 20, a synchronous rectification control circuit 30, and a spike absorption circuit 100. The main circuit includes a primary-side main power transistor Q1, a secondary-side synchronous rectifier transistor Q2, and a transformer T. The main power transistor Q1 and the synchronous rectifier transistor Q2 can be transistors, such as MOSFETs, or GaN transistors, SiC transistors, etc. The synchronous rectifier transistor Q2 can also be a diode. The source of the main power transistor Q1 is grounded, for example, through a sampling resistor Rcs, the drain is connected to the primary winding Np, and the gate is connected to the primary-side control circuit 20. The main power transistor Q1 is turned on and off according to the primary-side drive signal Vq1. The gate of the synchronous rectifier transistor Q2 is connected to the synchronous rectification control circuit 30, and the synchronous rectifier transistor Q2 is turned on and off according to the drive signal Vq2. The source of synchronous rectifier Q2 is connected to the secondary winding Ns via leakage inductance Lms, and the drain is connected to the output terminal. A voltage Vsec is obtained at the common node of synchronous rectifier Q2 and leakage inductance Lms. A diode D1 and a capacitor C0 are connected between the drain of the primary power transistor Q1 and the input power supply Vin. A resistor Ri is connected in parallel across capacitor C0. D1, C0, and Ri are not intended to limit the flyback converter structure of this invention; other structures can be used to achieve the same function. A filter capacitor Ci is also connected between the input power supply and ground. The AC source AC forms the input voltage Vin after passing through the rectifier bridge BD. A filter capacitor Co is connected between the drain of synchronous rectifier Q2 and ground on the secondary side.

[0037] exist Figure 1In the illustrated embodiment, the primary winding Np can be equivalently connected to a magnetizing inductor (not shown in the figure). The node voltage Vsw, obtained from the common node of the primary winding Np and the main power transistor Q1, represents the drain-source voltage of the main power transistor Q1. The output voltage Vout is obtained from the output terminal. Based on the output voltage Vout and the reference voltage, the error amplification signal Vcomp can be obtained. The conduction time of the main power transistor Q1 can be obtained through this error amplification signal Vcomp (the relevant circuit can be referred to in the prior art). During the switching cycle of the switching power supply, when the main power transistor Q1 is turned on, the input voltage Vin excites the transformer T through the main power transistor Q1, the synchronous rectifier Q2 is turned off, and the output filter capacitor Co supplies power to the load. When the main power transistor Q1 is turned off, the synchronous rectifier Q2 is turned on, the electrical energy stored on the transformer T is transferred to the secondary side to supply power to the load, and the capacitor Co is charged. When the main power transistor Q1 is turned on, the inductor Lms and the parasitic capacitance on the synchronous rectifier Q2 will resonate, generating a voltage spike across the synchronous rectifier Q2, thus affecting device performance, power consumption, and output stability. Therefore, the switching power supply in this embodiment also includes a spike absorption circuit 100 to absorb the energy generated by the voltage spike across the synchronous rectifier Q2. The spike absorption circuit 100 can be connected in parallel across the synchronous rectifier Q2 or in parallel across the secondary winding Ns. The following describes... Figures 2-6 The spike absorption circuit 100 of the present invention is described in detail.

[0038] Figure 2 A schematic circuit block diagram of a spike absorption circuit according to an embodiment of the present invention is shown.

[0039] like Figure 2As shown, the spike absorption circuit 100 of this embodiment includes a clamping transistor M1, a clamping capacitor C1, and a clamping control module 101. The clamping capacitor C1 is connected in series with the clamping transistor M1 and then connected to the synchronous rectifier Q2 to form a closed loop, creating an energy absorption and recovery loop on the secondary side. The clamping control module 101 includes a voltage detection module 110, a timing module 120, and a conduction control module 130. The voltage detection module 110 detects the drain-source voltage Vds of the clamping transistor M1 in real time, and outputs a trigger signal to the timing module 120 when the voltage first drops to the first threshold V1 after the main power transistor Q1 is turned on. The timing module 120 then starts timing until the drain-source voltage Vds rises again to the second threshold V2, thus accurately timing the first time interval T1. The conduction control module 130 generates a drive signal Vdr based on the outputs of the voltage detection module 110 and the timing module 120 to control the on / off state of the clamping transistor M1. For example, during the period from the end of the timing cycle to the turn-off of the main power transistor Q1, the clamping transistor M1 is driven to conduct for a second time interval T2. This second time interval T2 can be greater than, equal to, or less than the first time interval T1, or it can be set proportionally to the first time interval T1. This allows the clamping capacitor C1 to absorb the spike energy generated by the leakage inductance resonance across the synchronous rectifier transistor Q2 during the first time interval T1, and then feed the energy back to the output terminal without loss during the second time interval T2 before the main power transistor Q1 turns off, achieving efficient and low-loss spike suppression and energy recovery.

[0040] Specifically, the clamping control module 101 controls the clamping transistor M1 to remain on or off during the first time interval T1. During the off period, current flows through the body diode or reverse channel of the clamping transistor M1, so that the clamping transistor M1, the clamping capacitor C1, and the synchronous rectifier Q2 form a current loop. The clamping capacitor C1 absorbs the energy generated by the voltage spike across the synchronous rectifier Q2 when the main power transistor Q1 is turned on. During the second time interval T2, the clamping transistor M1 remains on, so that the clamping transistor M1, the clamping capacitor C1, and the secondary winding Ns form a current loop, and the energy on the clamping capacitor C1 is recovered to the input terminal of the switching converter.

[0041] When the clamping transistor M1 is continuously conducting within the first time interval T1, the start time of the second time interval T2 can be the end time of the first time interval T1, or it can be separated from the end time of the first time interval T1 by a third time interval t3. This can be divided into two cases: In the first case, when the clamping control module 101 detects that the drain-source voltage Vds of the clamping transistor M1 is less than the first threshold V1, it controls the clamping transistor M1 to conduct and starts timing. After the clamping transistor M1 conducts for the first time interval T1, it controls the clamping transistor M1 to continue conducting for the second time interval T2 before turning off the clamping transistor. During this process, the clamping transistor M1 is continuously conducting within the consecutive first time interval T1 and second time interval T2, with a conduction time of T1+T2. In the second scenario, when the clamping control module 101 detects that the drain-source voltage Vds of the clamping transistor M1 is less than the first threshold V1, it controls the clamping transistor M1 to turn on and starts timing. After the first time interval T1 ends, the clamping transistor M1 is turned off until the third time interval t3, at which point the clamping transistor M1 is turned on again for the second time interval T2, and then the clamping transistor M1 is turned off. During this process, the first time interval T1 and the second time interval T2 are interspersed with the third time interval t3, thus clearly separating the charging and discharging phases.

[0042] The second time interval T2 is set to be equal to or slightly longer than the first time interval T1 to ensure that energy is fully recovered and utilized. In some special embodiments, the second time interval T2 can also be less than the first time interval T1, that is, the conduction time of the clamping tube M1 is T1 + k × T1, where k is a positive real number.

[0043] Therefore, when the first time interval T1 and the second time interval T2 are consecutive, in order to further simplify the control, the clamp control module 101 can also control the clamp tube M1 to continue to conduct for a set fourth time interval t4 when it detects that the drain-source voltage Vds of the clamp tube M1 is less than the first threshold V1. The fourth time interval t4 is greater than the first time interval T1.

[0044] Regardless of the settings, the length of the first time interval T1 is limited by the first threshold V1 and the second threshold V2, and changes in real time with the circuit. The length and position of the second time interval T2 can be set according to the actual situation, but the end time of the second time interval T2 must be earlier than the turn-off time of the main power transistor Q1, that is, the clamping transistor M1 is turned off before the main power transistor Q1 is turned off.

[0045] Furthermore, the clamp control module 101 can receive an error amplification signal Vcomp that characterizes the turn-on time of the main power transistor Q1, so as to control the clamp transistor M1 to be turned on for a period of time before the turn-on time of the main power transistor Q1. The error amplification signal Vcomp is obtained based on the feedback signal of the output voltage Vout and the reference voltage Vref, and then the turn-on time of the main power transistor Q1 is obtained through a certain circuit. Before this turn-on time, the clamp transistor M1 is turned on for a short period of time to release the charge on the parasitic capacitance of the main power transistor Q1, so that the main power transistor Q1 achieves zero-voltage turn-on.

[0046] Figure 3 A schematic circuit diagram of a spike absorption circuit according to a first embodiment of the present invention is shown.

[0047] like Figure 3 As shown, in the first embodiment, the clamping capacitor C1 and the clamping transistor M1 are connected in series and then in parallel across the secondary winding Ns of the transformer. When the main power transistor Q1 is turned on, the leakage inductance Lms resonates with the parasitic capacitance Cs of the synchronous rectifier Q2, generating a positive spike voltage across the drain and source of the synchronous rectifier Q2. At this time, when the voltage detection module 110 detects that the drain-source voltage Vds of the clamping transistor M1 is lower than the first threshold V1, the timing module 120 starts timing, and the turn-on control module 130 controls the clamping transistor M1 to turn on. Thus, the synchronous rectifier Q2, the clamping capacitor C1, and the clamping transistor M1 form a current loop, allowing the clamping capacitor C1 to absorb leakage inductance energy during this period, wherein the current flow direction is... Figure 3 The direction indicated by the solid line.

[0048] The timing module 120 records the first time interval T1 required for the drain-source voltage Vds to rise from the first threshold V1 to the second threshold V2. After the timing ends, the conduction control module 130 drives the clamping transistor M1 to continue conducting for a second time interval T2 equal to the first time interval T1. During this time interval, the clamping transistor M1, the clamping capacitor C1, and the secondary winding Ns form a current loop, releasing the energy on the clamping capacitor C1 through the secondary winding Ns, which is equivalent to transferring it back to the primary winding Np, feeding the previously absorbed energy back to the input terminal, achieving lossless recovery. During this process, the current flow direction is as follows: Figure 3 As shown by the dashed line, the current direction on the clamping transistor M1 is opposite during the first time interval T1 and the second time interval T2. Since the first time interval T1 and the second time interval T2 are equal, the energy transfer process is precisely limited, which avoids the additional losses caused by over-clamping and ensures that the voltage stress of the synchronous rectifier transistor Q2 is always lower than its rated withstand voltage.

[0049] Figure 4 A schematic circuit diagram of a spike absorption circuit according to a second embodiment of the present invention is shown.

[0050] like Figure 4 As shown, the difference between this embodiment and the first embodiment is that the clamping capacitor C1 and the clamping transistor M1 are connected in series and then in parallel across the drain and source terminals of the synchronous rectifier Q2, instead of being directly connected in parallel across the secondary winding Ns. This arrangement allows the energy absorption circuit to locally clamp the peak voltage across the synchronous rectifier Q2. In this topology, when the main power transistor Q1 is turned on, the leakage inductance Lms resonates with the parasitic capacitance Cs of the synchronous rectifier Q2, generating a peak across the synchronous rectifier Q2. After the voltage detection module 110 detects that the drain-source voltage Vds is lower than the first threshold V1, the turn-on control module 130 drives the clamping transistor M1 to turn on, and the timing module 120 starts recording the first time interval T1. During the first time interval T1, the synchronous rectifier Q2, the clamping capacitor C1, and the clamping transistor M1 form an energy absorption circuit, allowing the clamping capacitor C1 to absorb the peak energy. The current direction of the energy absorption circuit is as follows: Figure 4 As shown by the solid line. Subsequently, during the second time interval T2, when the clamping transistor M1 continues to conduct, the clamping transistor M1, the clamping capacitor C1, and the secondary winding Ns form a reverse current path, feeding energy back to the input terminal. The current direction of the energy recovery path is as follows. Figure 4 As shown by the dashed line, the current direction on the clamping transistor M1 is opposite during the first time interval T1 and the second time interval T2. Since the clamping capacitor C1 is directly connected in parallel with the synchronous rectifier Q2, the energy recovery path is shorter and the loop impedance is lower, further improving the energy recovery efficiency and significantly reducing electromagnetic interference.

[0051] Figure 5 A schematic waveform diagram of various signals of a switching power supply according to an embodiment of the present invention is shown during operation.

[0052] like Figure 5 As shown, with Figure 3 and Figure 4 In any embodiment, the node voltage Vsw represents the drain-source voltage of the main power transistor Q1, Vsrds represents the drain-source voltage of the synchronous rectifier Q2, Vq2 is the driving voltage of the synchronous rectifier Q2, Vsec is the node voltage between the synchronous rectifier Q2 and the secondary winding Ns, Vdr is the driving voltage of the clamping transistor M1, Vds is the drain-source voltage of the clamping transistor M1, IM1 is the current flowing through the clamping transistor M1, and Ip is the current through the main power transistor Q1.

[0053] Specifically, at time t0, the main power transistor Q1, clamping transistor M1, and synchronous rectifier transistor Q2 are all in the off state. At time t1, the main power transistor Q1 begins to conduct, while the synchronous rectifier transistor Q2 is turned off, generating stress on the secondary side, i.e. Figure 5The portion shown in the ellipse represents the energy generated by the voltage spike. The node voltage Vsec drops to -Vin / N, where N is the turns ratio of the primary and secondary windings. Immediately at time t2, the drain-source voltage Vds is detected to be less than the first threshold V1, at which point the clamping transistor M1 is turned on by the positive drive voltage Vdr. This first threshold V1 is, for example, approximately -40mV. The clamping capacitor C1 begins to absorb energy, generating a negative current IM1 in the circuit. At time t3, the drain-source voltage Vds is detected to be greater than the second threshold V2, and the first time interval T1 ends. Then, the second time interval T2 begins. During the second time interval T2, the drive voltage Vdr continues to turn on the clamping transistor M1, and the clamping capacitor C2 begins to discharge, forming a positive current path and generating a positive current IM1. This second threshold V2 is, for example, approximately -10mV. The first time interval T1 is the period from t2 to t3, and the second time interval T2 is the period from t3 to t4. Typically, the interval between times t1 and t2 is very short, and clamping transistor M1 turns on immediately after main power transistor Q1. During the time interval t3-t4, clamping capacitor C1 discharges, recovering energy. Due to energy recovery, the current Ip waveform on main power transistor Q1 forms a downward dip during the second time interval T2. In this embodiment, the time intervals t2-t3 and t3-t4 are of equal length. At time t4, clamping transistor M1 turns off, drain-source voltage Vds increases, and the current IM1 in the circuit drops to zero. Then, at time t5, main power transistor Q1 turns off, node voltage Vsec rises to Vo, which is the output voltage Vout, and drain-source voltage Vds also rises to Vo+Vin / N. Therefore, clamping transistor M1 is turned off before main power transistor Q1 turns off. After time t5, synchronous rectifier transistor Q2 begins to conduct. After synchronous rectifier transistor Q2 turns off, the ringing phase begins. This process repeats for multiple switching cycles, repeating the above actions.

[0054] Figure 6 A schematic structural block diagram of an integrated chip according to an embodiment of the present invention is shown.

[0055] like Figure 6 As shown, when used as a chip, the clamping transistor M1 and the clamping control module 101 are integrated into the same chip 200. In this case, the clamping control module 101 includes... Figure 2 In addition to the voltage detection module 110, timing module 120, and conduction control module 130 shown, a power supply module 140 is also included. The chip 200 includes three pins: pin 1 is led out from the drain terminal of clamping transistor M1; pin 2 is led out from the source terminal of clamping transistor M1 and connected to an external clamping capacitor C1; pin 3 is the power supply pin. The clamping capacitor C1 is connected between pin 2 and pin 3, and an external power supply is connected to pin 3 for power supply.

[0056] Furthermore, chip 200 can also be packaged together with synchronous rectification control circuit 30 that controls the conduction state of synchronous rectifier tube Q2.

[0057] Figure 7 A schematic flowchart of a peak absorption method according to an embodiment of the present invention is shown.

[0058] This spike absorption method is applied in the aforementioned switching power supply and spike absorption circuit to absorb the energy generated by the voltage spike of the synchronous rectifier diode Q2. See [link to relevant documentation]. Figure 7 The peak absorption method in this embodiment includes, for example, the following steps:

[0059] In step S101, the drain-source voltage of the clamping transistor is detected after the main power transistor is turned on.

[0060] In step S102, the drain-source voltage of the timing clamping transistor is between a first time interval from below the first threshold to above the second threshold.

[0061] In step S103, during the time period from the end of the timing to the turn-off of the main power transistor, the clamping transistor is controlled to conduct the second time interval.

[0062] Furthermore, the spike absorption method also includes: controlling the clamping transistor to remain on or to freewheel through the body diode of the clamping transistor during the first time interval, so that the clamping transistor, clamping capacitor and synchronous rectifier form a current loop.

[0063] The spike absorption method in this embodiment is based on the spike absorption circuit described above. The specific circuit principle, structure and working process have been described above and will not be repeated here.

[0064] It is understood that the above embodiments of this application are mainly described and illustrated using a common flyback switching power supply as an example, but are not limited to this converter structure. Other similar converters, such as asymmetric half-bridge flyback switching power supplies or active clamp flyback switching power supplies, can also be used. Applying the control scheme of this application to similar converter structures can also achieve the same or similar beneficial technical effects. The embodiments of this application do not limit this.

[0065] It should be noted that the numerical values ​​in this article are for illustrative purposes only. In other embodiments of the present invention, other numerical values ​​may be sampled to implement this solution. The specific values ​​should be reasonably set according to the actual situation, and the present invention does not limit them.

[0066] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating the present invention and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

[0067] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A spike absorption circuit, applied in a switching converter, the switching converter comprising a transformer, a main power transistor connected to the primary winding of the transformer, and a synchronous rectifier transistor connected to the secondary winding of the transformer, wherein, The spike absorption circuit includes: Clamping tube; A clamping capacitor, connected in series with the clamping transistor, and then connected to the synchronous rectifier transistor to form a closed circuit; and The clamping control module detects the drain-source voltage of the clamping transistor after the main power transistor is turned on, times a first time interval from when the drain-source voltage of the clamping transistor is below a first threshold to when it is above a second threshold, and controls the clamping transistor to be turned on for a second time interval from when the timing ends until the main power transistor is turned off.

2. The spike absorption circuit according to claim 1, wherein, The clamping control module controls the clamping transistor to remain on or freewheel through the body diode of the clamping transistor during the first time interval, so that the clamping transistor, the clamping capacitor and the synchronous rectifier form a current loop, and absorb the energy generated by the voltage spike across the synchronous rectifier when the main power transistor is turned on through the clamping capacitor.

3. The spike absorption circuit according to claim 2, wherein, The clamping transistor is turned on during the second time interval so that the clamping transistor, the clamping capacitor, and the secondary winding form a current loop, thereby recovering the energy on the clamping capacitor to the input terminal of the switching converter.

4. The spike absorption circuit according to claim 3, wherein, During the first time interval and the second time interval, the current on the clamping tube is in the opposite direction.

5. The spike absorption circuit according to claim 2, wherein, When the clamping control module detects that the drain-source voltage of the clamping transistor is less than a first threshold, it controls the clamping transistor to turn on and starts timing. After the clamping transistor has been turned on for the first time interval, it controls the clamping transistor to continue to be turned on for the second time interval and then turns off the clamping transistor.

6. The spike absorption circuit according to claim 2, wherein, When the clamping control module detects that the drain-source voltage of the clamping transistor is less than a first threshold, it controls the clamping transistor to turn on and starts timing. After the first time interval ends, it turns off the clamping transistor to reach a third time interval, and then turns the clamping transistor on again for the second time interval, and then controls the clamping transistor to turn off again.

7. The spike absorption circuit according to claim 1, wherein, When the clamping control module detects that the drain-source voltage of the clamping transistor is less than a first threshold, it controls the clamping transistor to remain on for a set fourth time interval, which is greater than the first time interval.

8. The spike absorption circuit according to claim 1, wherein, The clamping control module also receives an error amplification signal characterizing the turn-on time of the main power transistor, so as to control the clamping transistor to be turned on for a period of time before the turn-on time of the main power transistor, so that the main power transistor achieves zero-voltage turn-on, wherein the error amplification signal is obtained based on the feedback signal of the output voltage and the reference voltage.

9. The spike absorption circuit according to claim 1, wherein, The clamping capacitor is connected in series with the clamping transistor and then in parallel across the two ends of the synchronous rectifier, or in parallel across the two ends of the secondary winding of the transformer. The synchronous rectifier includes a transistor or a diode.

10. The spike absorption circuit according to claim 1, wherein, The clamping control module includes: The voltage detection module detects the drain-source voltage of the clamping transistor in real time. The timing module starts timing when the drain-source voltage of the clamping transistor is greater than a first threshold, and ends timing when the drain-source voltage of the clamping transistor is greater than a second threshold. The conduction control module generates a drive signal based on the outputs of the voltage detection module and the timing module to control the on / off state of the clamping transistor.

11. The spike absorption circuit according to any one of claims 1 to 9, wherein, The clamping transistor and the clamping control module are integrated into the same chip, the chip comprising: The first pin is led out from the drain end of the clamping tube; The second pin is led out from the source end of the clamping transistor and connected to the clamping capacitor. The third pin serves as the power supply pin for the chip.

12. The spike absorption circuit according to claim 11, wherein, The chip is packaged together with the synchronous rectification control circuit that controls the conduction state of the synchronous rectifier tube.

13. A switching power supply, comprising a transformer, the transformer including a primary winding and a secondary winding, wherein, The switching power supply also includes: The main power transistor is connected to the primary winding; Synchronous rectifier diode, connected to the secondary winding; and The spike absorption circuit according to any one of claims 1 to 12 is used to absorb the energy generated by the voltage spike on the synchronous rectifier when the main power transistor is turned on.

14. A peak absorption method applied in a switching converter, the switching converter comprising a transformer, a main power transistor connected to the primary winding of the transformer, and a synchronous rectifier transistor connected to the secondary winding of the transformer, wherein the synchronous rectifier transistor, a clamping transistor, and a clamping capacitor form a closed loop, wherein... The peak absorption method includes: The drain-source voltage of the clamping transistor is detected after the main power transistor is turned on. The timing is set for a first time interval between the drain-source voltage of the clamping transistor starting below a first threshold and ending above a second threshold; During the time period from the end of the timing to the turn-off of the main power transistor, the clamping transistor is controlled to conduct the second time interval.

15. The peak absorption method according to claim 14, wherein, Also includes: During the first time interval, the clamping transistor is controlled to remain on or to freewheel through the body diode of the clamping transistor, so that the clamping transistor, the clamping capacitor and the synchronous rectifier form a current loop.

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