A multi-stage charge pump circuit for wide input voltage range and a control method

Abstract

The application relates to a multi-stage charge pump circuit and a control method for a wide input voltage range, and belongs to the technical field of semiconductors. The multi-stage charge pump circuit comprises an N-bit temperature code ADC and an N-stage charge pump circuit. The output VC<1:N> of the N-bit temperature code ADC corresponds to the high and low of the input voltage VDD. The Nth-stage charge pump circuit in the N-stage charge pump circuit corresponds to the Nth-stage temperature code VC <n>connect; when the Nth temperature agent code VC <n>When the high level, the N level charge pump circuit does not work; when the N level temperature agent code VC <n>When the low level is ensured, the multi-stage charge pump circuit works to realize the boosting function; when the input voltage VDD is high, the working stages of the charge pump are reduced, and the output voltage VPN is also reduced correspondingly, so that the output voltage will not exceed the AMR voltage of the chip. The multi-stage charge pump circuit and the control method have simple system, fast response speed, high efficiency and reliability.< / n> < / n> < / n>

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and particularly to the field of charge pump circuit technology, specifically a multi-stage charge pump circuit and control method for a wide input voltage range. Background Technology

[0002] Switched capacitor charge pumps are widely used in boost circuits due to their simple structure and ease of integration. By using multi-stage charge pump units connected in series, the input voltage can be boosted multiple times. Theoretically, the highest output voltage of an N-stage charge pump is (N+1)*VDD.

[0003] However, traditional N-stage charge pump circuits cannot dynamically adjust the boost factor over a wide input voltage range, which may lead to the risk that the output voltage may exceed the chip's AMR (Absolute Maximum Range) voltage when the input voltage is high.

[0004] Therefore, how to provide a multi-stage charge pump circuit suitable for a wide input voltage range that prevents the output voltage from exceeding the AMR voltage when the input voltage is too high, thus avoiding chip damage, has become an urgent problem to be solved in this field. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a multi-stage charge pump circuit and control method for a wide input voltage range, which ensures that the output voltage does not exceed the AMR voltage when the input voltage is too high, thus avoiding chip damage.

[0006] To achieve the above objectives, the multi-stage charge pump circuit for a wide input voltage range of the present invention has the following configuration: It includes: an N-bit temperature code ADC and an N-stage charge pump circuit.

[0007] The N-bit temperature dosing code ADC is connected to the input voltage VDD and outputs an N-bit temperature dosing code VC<1:N> corresponding to the high or low level of the input voltage VDD. Each stage of the N-stage charge pump circuit has the same circuit structure. The input terminal of the first-stage charge pump circuit PUMP_CORE_N is connected to the corresponding bit of the temperature code VC in the N-bit temperature code VC<1:N>. <n>It is also connected to the output voltage VPN-1 of the previous stage charge pump circuit PUMP_CORE_N-1 and the clock signal CLK. The input terminal of the first stage charge pump is connected to the input voltage VDD, and the output terminal of the Nth stage charge pump provides the output voltage VPN for this multi-stage charge pump circuit with a wide input voltage range. When the temperature code VC is at this level <n>When the voltage level is high, the charge pump circuit PUMP_CORE_N of this stage does not operate; when the temperature code VC of this stage is high... <n>When the voltage level is low, the charge pump circuit PUMP_CORE_N operates to implement the boost function.

[0008] In this multi-stage charge pump circuit used over a wide input voltage range, each temperature code VC in the N-bit temperature code VC<1:N> is... <n>The charge pump circuit is matched from low to high. When the input voltage VDD is high, the high-order bits of the N-bit temperature code VC<1:N> are high, causing the corresponding high-order charge pump circuit to not work.

[0009] In this multi-stage charge pump circuit for a wide input voltage range, each stage of the charge pump circuit includes NMOS transistors M1 and M2; PMOS transistors M3, M4, and M5; inverters INV1 and INV2; and capacitors C1 and C2. The temperature code VC mentioned above <n>The gate of the PMOS transistor M5 is connected to the inverter INV2. The source of the PMOS transistor M5 is connected to the output voltage VPN-1 of the previous stage charge pump circuit PUMP_CORE_N-1. The drain of the PMOS transistor M5 is the output voltage VPN of the current stage charge pump circuit. The drains of NMOS transistors M1 and M2 are connected to the output voltage VPN-1 of the previous stage charge pump circuit PUMP_CORE_N-1. The source of NMOS transistor M1 and the gate of NMOS transistor M2 are connected to node VX, and the source of NMOS transistor M2 and the gate of NMOS transistor M1 are connected to node VY. The clock signal CLK is connected to node VX via capacitor C1, and the clock signal CLK is connected to node VY via inverter INV1 and capacitor C2. Node VX is also connected to the gate of PMOS transistor M3 and the source of PMOS transistor M4, and node VY is also connected to the gate of PMOS transistor M4 and the source of PMOS transistor M3. The drains of PMOS transistors M3 and M4 are both connected to the output voltage VPN of the current stage charge pump circuit. When the temperature code VC is at this level <n>When the voltage is high, the PMOS transistor M5 is turned on through the inverter INV2. At this time, the output voltage VPN-1 of the previous stage charge pump circuit PUMP_CORE_N-1 is connected to the output voltage VPN of this stage charge pump circuit, and this stage charge pump circuit does not work. When the temperature code VC is at this level <n>When the clock signal CLK is low, the PMOS transistor M5 is turned off, and the charge pump circuit of this stage is working. If the voltage at node VX is VPN-1 and the voltage at node VY is VDD+VPN-1 when the clock signal CLK is low, NMOS transistors M1 and M3 are turned on, and NMOS transistors M2 and M4 are turned off, then the output voltage VPN of this stage charge pump circuit is VDD+VPN-1. If the voltage at node VY is VPN-1 and the voltage at node VX is VDD+VPN-1 when the clock signal CLK is high, NMOS transistors M1 and M3 are turned off, and NMOS transistors M2 and M4 are turned on, then the output voltage VPN of this stage charge pump circuit is VDD+VPN-1.

[0010] The present invention also provides a control method for the above-mentioned multi-stage charge pump circuit with a wide input voltage range, comprising: The N-bit temperature code ADC provides an N-bit temperature code VC<1:N> corresponding to the high and low levels of the input voltage VDD to the N-stage charge pump circuit; In the N-stage charge pump circuit, each stage of the charge pump circuit has its own temperature code VC. <n>When the voltage level is high, the charge pump circuit PUMP_CORE_N of this stage does not operate; when the temperature code VC of this stage is high... <n>When the voltage is low, the PUMP_CORE_N stage charge pump circuit operates to implement the boost function. The output voltage of this stage charge pump is boosted based on the output voltage VPN-1 of the previous stage charge pump circuit.

[0011] In the control method for a multi-stage charge pump circuit with a wide input voltage range, each temperature code VC in the N-bit temperature code VC<1:N> is... <n>The charge pump circuit is matched from low to high to the corresponding level, and the temperature code VC at this level is... <n>When the level is high, the charge pump circuit PUMP_CORE_N of this stage does not work, specifically: When the input voltage VDD is high, the high-order bits of the N-bit temperature code VC<1:N> are at a high level, causing the corresponding high-order charge pump circuit to not work.

[0012] In the control method for a multi-stage charge pump circuit with a wide input voltage range, the temperature code VC at this stage is described. <n>When the voltage level is high, the charge pump circuit PUMP_CORE_N of this stage does not operate; when the temperature code VC of this stage is high... <n>When the voltage level is low, the charge pump circuit PUMP_CORE_N operates to implement the boost function, specifically as follows: In each stage of the N-stage charge pump circuit, the temperature code VC for that stage is... <n>The gate of PMOS transistor M5 is connected via inverter INV2. When the temperature code VC is at this level <n>When the voltage is high, PMOS transistor M5 is turned on. At this time, the output voltage VPN-1 of the previous stage charge pump circuit PUMP_CORE_N-1 is connected to the output voltage VPN of this stage charge pump circuit, and this stage charge pump circuit does not work. When the temperature code VC is at this level <n>When the clock signal CLK is low, the PMOS transistor M5 is turned off, and the charge pump circuit of this stage is working. If the node VX voltage is VPN-1 and the node VY voltage is VDD+VPN-1 when the clock signal CLK is low, the NMOS transistors M1 and M3 are turned on, and the NMOS transistors M2 and M4 are turned off. At this time, the output voltage VPN of the charge pump circuit of this stage is VDD+VPN-1. If the clock signal CLK is high, the node VY voltage is VPN-1 and the node VX voltage is VDD+VPN-1, the NMOS transistors M2 and M4 are turned on, and the NMOS transistors M1 and M3 are turned off. At this time, the output voltage VPN of the charge pump circuit of this stage is VDD+VPN-1.

[0013] The invention employs a multi-stage charge pump circuit and control method for a wide input voltage range. The circuit includes an N-bit temperature code ADC and an N-stage charge pump circuit. The N-bit temperature code provides an N-bit temperature code VC<1:N> corresponding to the high and low levels of the input voltage VDD. Each stage of the N-stage charge pump circuit is connected to its corresponding temperature code VC<1:N>. <n>In this temperature dose code VC <n>When the voltage level is high, the charge pump circuit of this stage does not operate; when the temperature code VC of this stage is high... <n>When the voltage level is low, this stage of the charge pump circuit operates to achieve a boost function; ensuring that when the input voltage VDD is high, the number of charge pump stages decreases, and the output voltage VPN also decreases accordingly, so that the output voltage does not exceed the chip's AMR voltage. The multi-stage charge pump circuit and control method of this invention are simple in system design, have a fast response speed, and balance high efficiency and reliability. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the circuit structure of the multi-stage charge pump circuit for a wide input voltage range according to the present invention; Figure 2 This is a schematic diagram of the mechanism of a first-stage charge pump circuit in a multi-stage charge pump circuit for a wide input voltage range according to the present invention; Figure 3 This is a schematic diagram comparing the output voltage waveforms of the multi-stage adaptive charge pump circuit of the present invention with those of a conventional N-stage charge pump. Detailed Implementation

[0015] To better understand the technical content of this invention, the following embodiments are provided for detailed explanation.

[0016] Please see Figure 1 The diagram shown is a schematic diagram of the circuit structure of the multi-stage charge pump circuit for a wide input voltage range according to the present invention.

[0017] In one embodiment, the multi-stage charge pump circuit for a wide input voltage range includes an N-bit temperature code ADC and an N-stage charge pump circuit.

[0018] The N-bit temperature dosing code ADC is connected to the input voltage VDD and outputs an N-bit temperature dosing code VC<1:N> corresponding to the high or low level of the input voltage VDD. The circuit structure of each stage of the N-stage charge pump circuit is the same, and they are all as follows: Figure 2 The cross-coupled charge pump circuit is shown. The input of each stage of the charge pump circuit PUMP_CORE_N is connected to the corresponding bit of the N-bit temperature code VC<1:N> for that stage. <n>It is also connected to the output voltage VPN-1 of the previous stage charge pump circuit PUMP_CORE_N-1 and the clock signal CLK. The input terminal of the first stage charge pump is connected to the input voltage VDD, and the output terminal of the Nth stage charge pump provides the output voltage VPN for this multi-stage charge pump circuit with a wide input voltage range. When the temperature code VC is at this level <n>When the voltage level is high, the charge pump circuit PUMP_CORE_N of this stage does not operate; when the temperature code VC of this stage is high... <n>When the voltage level is low, the charge pump circuit PUMP_CORE_N operates to implement the boost function.

[0019] In a preferred embodiment, each temperature code VC in the N-bit temperature code VC<1:N> <n>The charge pump circuit is matched from low to high. When the input voltage VDD is high, the high-order bits of the N-bit temperature code VC<1:N> are high, causing the corresponding high-order charge pump circuit to not work.

[0020] In a more preferred embodiment, each charge pump circuit includes NMOS transistors M1 and M2; PMOS transistors M3, M4, and M5; inverters INV1 and INV2; and capacitors C1 and C2. The temperature code VC mentioned above <n>The gate of the PMOS transistor M5 is connected to the inverter INV2. The source of the PMOS transistor M5 is connected to the output voltage VPN-1 of the previous stage charge pump circuit PUMP_CORE_N-1. The drain of the PMOS transistor M5 is the output voltage VPN of the current stage charge pump circuit. The drains of NMOS transistors M1 and M2 are connected to the output voltage VPN-1 of the previous stage charge pump circuit PUMP_CORE_N-1. The source of NMOS transistor M1 and the gate of NMOS transistor M2 are connected to node VX, and the source of NMOS transistor M2 and the gate of NMOS transistor M1 are connected to node VY. The clock signal CLK is connected to node VX via capacitor C1, and the clock signal CLK is connected to node VY via inverter INV1 and capacitor C2. Node VX is also connected to the gate of PMOS transistor M3 and the source of PMOS transistor M4, and node VY is also connected to the gate of PMOS transistor M4 and the source of PMOS transistor M3. The drains of PMOS transistors M3 and M4 are both connected to the output voltage VPN of the current stage charge pump circuit. When the temperature code VC is at this level <n>When the voltage is high, the PMOS transistor M5 is turned on through the inverter INV2. At this time, the output voltage VPN-1 of the previous stage charge pump circuit PUMP_CORE_N-1 is connected to the output voltage VPN of this stage charge pump circuit, and this stage charge pump circuit does not work. When the temperature code VC is at this level <n>When the clock signal CLK is low, the PMOS transistor M5 is turned off, and the charge pump circuit of this stage is working. If the voltage at node VX is VPN-1 and the voltage at node VY is VDD+VPN-1 when the clock signal CLK is low, NMOS transistors M1 and M3 are turned on, and NMOS transistors M2 and M4 are turned off, then the output voltage VPN of this stage charge pump circuit is VDD+VPN-1. If the voltage at node VY is VPN-1 and the voltage at node VX is VDD+VPN-1 when the clock signal CLK is high, NMOS transistors M1 and M3 are turned off, and NMOS transistors M2 and M4 are turned on, then the output voltage VPN of this stage charge pump circuit is VDD+VPN-1.

[0021] The present invention also provides a control method for the multi-stage charge pump circuit with a wide input voltage range, comprising the following steps: The N-bit temperature code ADC provides an N-bit temperature code VC<1:N> corresponding to the high and low levels of the input voltage VDD to the N-stage charge pump circuit; In the N-stage charge pump circuit, each stage of the charge pump circuit has its own temperature code VC. <n>When the voltage level is high, the charge pump circuit PUMP_CORE_N of this stage does not operate; when the temperature code VC of this stage is high... <n>When the voltage is low, the PUMP_CORE_N stage charge pump circuit operates to implement the boost function. The output voltage of this stage charge pump is boosted based on the output voltage VPN-1 of the previous stage charge pump circuit.

[0022] In a preferred embodiment, each temperature code VC in the N-bit temperature code VC<1:N> <n>The charge pump circuit is matched from low to high to the corresponding level, and the temperature code VC at this level is... <n>When the level is high, the charge pump circuit PUMP_CORE_N of this stage does not work, specifically: When the input voltage VDD is high, the high-order bits of the N-bit temperature code VC<1:N> are at a high level, causing the corresponding high-order charge pump circuit to not work.

[0023] In a more preferred embodiment, the temperature-controlled VC level is described. <n>When the voltage level is high, the charge pump circuit PUMP_CORE_N of this stage does not operate; when the temperature code VC of this stage is high... <n>When the voltage level is low, the charge pump circuit PUMP_CORE_N operates to implement the boost function, specifically as follows: In each stage of the N-stage charge pump circuit, the temperature code VC for that stage is... <n>The gate of PMOS transistor M5 is connected via inverter INV2. When the temperature code VC is at this level <n>When the voltage is high, PMOS transistor M5 is turned on. At this time, the output voltage VPN-1 of the previous stage charge pump circuit PUMP_CORE_N-1 is connected to the output voltage VPN of this stage charge pump circuit, and this stage charge pump circuit does not work. When the temperature code VC is at this level <n>When the clock signal CLK is low, the PMOS transistor M5 is turned off, and the charge pump circuit of this stage is working. If the node VX voltage is VPN-1 and the node VY voltage is VDD+VPN-1 when the clock signal CLK is low, the NMOS transistors M1 and M3 are turned on, and the NMOS transistors M2 and M4 are turned off. At this time, the output voltage VPN of the charge pump circuit of this stage is VDD+VPN-1. If the clock signal CLK is high, the node VY voltage is VPN-1 and the node VX voltage is VDD+VPN-1, the NMOS transistors M2 and M4 are turned on, and the NMOS transistors M1 and M3 are turned off. At this time, the output voltage VPN of the charge pump circuit of this stage is VDD+VPN-1.

[0024] In practical applications, Figure 1 The N-bit thermometer code ADC shown quantizes the magnitude of the input voltage VDD, and the output VC<1:N> controls each stage of the N-stage charge pump. When the input voltage VDD is high, the number of charge pump stages decreases, and the output voltage also decreases accordingly.

[0025] The working principle of the charge pump PUMP_CORE circuit is as follows: VC <n>For the temperature code corresponding to this stage in the ADC output signal, when the temperature code of this stage is VC... <n>When the voltage is high, PMOS transistor M5 is turned on, and the output voltage VPN of this stage is shorted to the output voltage VPN-1 of the previous stage, so the charge pump of this stage does not work; when the temperature code VC of this stage is high... <n>When the voltage level is low, the boost function is enabled. The specific working principle is as follows: When the clock signal CLK is low, Figure 2 The voltage at node VX is VPN-1, the voltage at node VY is VDD+VPN-1, NMOS transistors M1 and M3 are turned on, and NMOS transistors M2 and M4 are turned off. The output voltage of this stage is VPN=VDD+VPN-1. When the clock signal CLK is high, the voltage at node VY is VPN-1, the voltage at node VX is VDD+VPN-1, NMOS transistors M1 and M3 are turned off, and NMOS transistors M2 and M4 are turned on. VPN=VDD+VPN-1.

[0026] A comparison of the output voltage waveform of the multi-stage adaptive charge pump circuit of this invention with that of a conventional N-stage charge pump is shown below. Figure 3 As shown. Compared to traditional N-stage charge pumps, this invention avoids the risk that the charge pump output voltage may exceed the chip's AMR (Absolute Maximum Range) voltage when the input voltage is too high.

[0027] The invention employs a multi-stage charge pump circuit and control method for a wide input voltage range. The circuit includes an N-bit temperature code ADC and an N-stage charge pump circuit. The N-bit temperature code provides an N-bit temperature code VC<1:N> corresponding to the high and low levels of the input voltage VDD. Each stage of the N-stage charge pump circuit is connected to its corresponding temperature code VC<1:N>. <n>In this temperature dose code VC <n>When the voltage level is high, the charge pump circuit of this stage does not operate; when the temperature code VC of this stage is high... <n>When the voltage level is low, this stage of the charge pump circuit operates to achieve a boost function; ensuring that when the input voltage VDD is high, the number of charge pump stages decreases, and the output voltage VPN also decreases accordingly, so that the output voltage does not exceed the chip's AMR voltage. The multi-stage charge pump circuit and control method of this invention are simple in system design, have a fast response speed, and balance high efficiency and reliability.

[0028] In this specification, the invention has been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and variations can be made without departing from the spirit and scope of the invention. Therefore, the specification and drawings should be considered illustrative rather than restrictive.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A multi-stage charge pump circuit for a wide input voltage range, characterized in that, include: An N-bit temperature dosing code ADC is connected to an input voltage VDD and outputs an N-bit temperature dosing code VC<1:N> corresponding to the high or low values ​​of the input voltage VDD. The N-stage charge pump circuit has the same circuit structure for each stage. The input terminal of the first-stage charge pump circuit PUMP_CORE_N is connected to the corresponding bit of the temperature code VC in the N-bit temperature code VC<1:N>. <n> It is also connected to the output voltage VPN-1 of the previous stage charge pump circuit PUMP_CORE_N-1 and the clock signal CLK. The input terminal of the first stage charge pump is connected to the input voltage VDD, and the output terminal of the Nth stage charge pump provides the output voltage VPN for this multi-stage charge pump circuit with a wide input voltage range.< / n> When the temperature code VC is at this level <n>When the voltage level is high, the charge pump circuit PUMP_CORE_N of this stage does not operate; when the temperature code VC of this stage is high... <n> When the voltage level is low, the charge pump circuit PUMP_CORE_N operates to implement the boost function.< / n> < / n> 2. The multi-stage charge pump circuit for a wide input voltage range according to claim 1, characterized in that, Each temperature code VC in the N-bit temperature code VC<1:N> <n> The charge pump circuit is matched from low to high. When the input voltage VDD is high, the high-order bits of the N-bit temperature code VC<1:N> are high, causing the corresponding high-order charge pump circuit to not work.< / n> 3. The multi-stage charge pump circuit for a wide input voltage range according to claim 2, characterized in that, Each stage of the charge pump circuit includes NMOS transistors M1 and M2; PMOS transistors M3, M4, and M5; inverters INV1 and INV2; and capacitors C1 and C2. The temperature code VC mentioned above <n> The gate of the PMOS transistor M5 is connected to the inverter INV2. The source of the PMOS transistor M5 is connected to the output voltage VPN-1 of the previous stage charge pump circuit PUMP_CORE_N-1. The drain of the PMOS transistor M5 is the output voltage VPN of the current stage charge pump circuit.< / n> The drains of NMOS transistors M1 and M2 are connected to the output voltage VPN-1 of the previous stage charge pump circuit PUMP_CORE_N-1. The source of NMOS transistor M1 and the gate of NMOS transistor M2 are connected to node VX, and the source of NMOS transistor M2 and the gate of NMOS transistor M1 are connected to node VY. The clock signal CLK is connected to node VX via capacitor C1, and the clock signal CLK is connected to node VY via inverter INV1 and capacitor C2. Node VX is also connected to the gate of PMOS transistor M3 and the source of PMOS transistor M4, and node VY is also connected to the gate of PMOS transistor M4 and the source of PMOS transistor M3. The drains of PMOS transistors M3 and M4 are both connected to the output voltage VPN of the current stage charge pump circuit. When the temperature code VC is at this level <n> When the voltage is high, the PMOS transistor M5 is turned on through the inverter INV2. At this time, the output voltage VPN-1 of the previous stage charge pump circuit PUMP_CORE_N-1 is connected to the output voltage VPN of this stage charge pump circuit, and this stage charge pump circuit does not work.< / n> When the temperature code VC is at this level <n>When the clock signal CLK is low, the PMOS transistor M5 is turned off, and the charge pump circuit of this stage is working. If the voltage at node VX is VPN-1 and the voltage at node VY is VDD+VPN-1 when the clock signal CLK is low, NMOS transistors M1 and M3 are turned on, and NMOS transistors M2 and M4 are turned off, then the output voltage VPN of this stage charge pump circuit is VDD+VPN-1. If the voltage at node VY is VPN-1 and the voltage at node VX is VDD+VPN-1 when the clock signal CLK is high, NMOS transistors M1 and M3 are turned off, and NMOS transistors M2 and M4 are turned on, then the output voltage VPN of this stage charge pump circuit is VDD+VPN-1.< / n> 4. A control method for a multi-stage charge pump circuit with a wide input voltage range as described in claim 1, characterized in that, include: The N-bit temperature code ADC provides an N-bit temperature code VC<1:N> corresponding to the high and low levels of the input voltage VDD to the N-stage charge pump circuit; In the N-stage charge pump circuit, each stage of the charge pump circuit has its own temperature code VC. <n>When the voltage level is high, the charge pump circuit PUMP_CORE_N of this stage does not operate; when the temperature code VC of this stage is high... <n> When the voltage is low, the PUMP_CORE_N stage charge pump circuit operates to implement the boost function. The output voltage of this stage charge pump is boosted based on the output voltage VPN-1 of the previous stage charge pump circuit.< / n> < / n> 5. The control method for a multi-stage charge pump circuit with a wide input voltage range according to claim 4, characterized in that, Each temperature code VC in the N-bit temperature code VC<1:N> <n>The charge pump circuit is matched from low to high to the corresponding level, and the temperature code VC at this level is... <n> When the level is high, the charge pump circuit PUMP_CORE_N of this stage does not work, specifically:< / n> < / n> When the input voltage VDD is high, the high-order bits of the N-bit temperature code VC<1:N> are at a high level, causing the corresponding high-order charge pump circuit to not work.

6. The control method for a multi-stage charge pump circuit with a wide input voltage range according to claim 5, characterized in that, The temperature code VC mentioned above is used in this class of temperature distribution. <n>When the voltage level is high, the charge pump circuit PUMP_CORE_N of this stage does not operate; when the temperature code VC of this stage is high... <n> When the voltage level is low, the charge pump circuit PUMP_CORE_N operates to implement the boost function, specifically as follows:< / n> < / n> In each stage of the N-stage charge pump circuit, the temperature code VC for that stage is... <n> The gate of PMOS transistor M5 is connected via inverter INV2.< / n> When the temperature code VC is at this level <n> When the voltage is high, PMOS transistor M5 is turned on. At this time, the output voltage VPN-1 of the previous stage charge pump circuit PUMP_CORE_N-1 is connected to the output voltage VPN of this stage charge pump circuit, and this stage charge pump circuit does not work.< / n> When the temperature code VC is at this level <n> When the clock signal CLK is low, the PMOS transistor M5 is turned off, and the charge pump circuit of this stage is working. If the node VX voltage is VPN-1 and the node VY voltage is VDD+VPN-1 when the clock signal CLK is low, the NMOS transistors M1 and M3 are turned on, and the NMOS transistors M2 and M4 are turned off. At this time, the output voltage VPN of the charge pump circuit of this stage is VDD+VPN-1. If the clock signal CLK is high, the node VY voltage is VPN-1 and the node VX voltage is VDD+VPN-1, the NMOS transistors M2 and M4 are turned on, and the NMOS transistors M1 and M3 are turned off. At this time, the output voltage VPN of the charge pump circuit of this stage is VDD+VPN-1.< / n>

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