A single-pole double-throw high-power switch chip with positive input

Abstract

This invention proposes a single-pole double-throw (SPD) high-power switch chip with a positive input voltage, comprising transistors M1-M18, DC blocking capacitors C1-C5, bonding inductors L1-L3, microstrip lines TL1-TL5, and bias resistors R1-R3. By adding two bias resistors at the input, this invention transforms the original negative input SPD double-throw switch into one that only requires a positive input voltage, simplifying the circuit implementation. Furthermore, by stacking multiple series-parallel switching transistors on the basis of traditional series-parallel switches, this invention achieves high-power input. Simultaneously, the multiple parallel transistors ensure good isolation and isolation bandwidth over a wide frequency range, and the microstrip line matching results in excellent switch insertion loss and other performance characteristics.

Description

Technical Field

[0001] This invention relates to the field of radio frequency front-end chips, specifically a single-pole double-throw high-power switch chip with positive input voltage. Background Technology

[0002] In fields such as radio frequency systems, communication equipment, and power control, single-pole double-throw (SPDT) switches are widely used as a key component in signal path switching, mode selection, and power distribution. As the requirements for power capacity, integration, and reliability of systems continue to increase, traditional high-power switching circuits built with discrete components (such as PIN diodes and MOSFETs) are gradually becoming unable to meet the stringent requirements of modern equipment for size, power consumption, and consistency.

[0003] Currently, several integrated high-power switching chips are available on the market, mostly manufactured using silicon-based or gallium arsenide processes. They employ negative voltage control or a dual positive and negative power supply architecture to achieve efficient switching of RF or DC high-power signals. However, these solutions typically have the following limitations: First, negative voltage control often requires additional negative voltage generation circuitry, increasing system complexity and cost. Second, many existing high-power switching chips still exhibit significant bottlenecks in key performance aspects such as power handling capability, on-resistance, and isolation under a single positive power supply, especially under high-frequency, high-current operating conditions, where their insertion loss and thermal stability are poor.

[0004] Furthermore, for systems that only have positive power supply (such as many portable devices or industrial equipment with simplified power architecture), existing high-power SPDT switching chips are often not directly applicable, or require external level shifting circuits to achieve compatibility. This not only introduces additional signal delay and power consumption, but also reduces the overall reliability of the system. Summary of the Invention

[0005] To address the above technical challenges, this invention proposes a single-pole double-throw high-power switch chip with a positive input voltage. This chip can operate directly under a single positive power supply while simultaneously meeting the requirements of low on-resistance, high isolation, excellent thermal performance, and stable reliability. This simplifies system design, improves energy efficiency, and adapts to a wider range of application scenarios. The technical solution provided by this invention is as follows:

[0006] A single-pole double-throw high-power switching chip with positive input voltage has one end of bias resistors R1 and R2 connected between the input bonding inductor L1 and microstrip line TL1, and the other end connected to the first control voltage V1 and the second control voltage V2 respectively. The other end of microstrip line TL1 is connected to the microstrip line TL2 of channel one circuit and channel two circuit. The other end of L1 is connected to the DC blocking capacitor C1 to the radio frequency input terminal RFC.

[0007] Both Channel 1 and Channel 2 circuits include a first transistor stacking unit, a second transistor stacking unit, and a third transistor stacking unit. Each transistor stacking unit includes N transistors of the same size, where N is an integer greater than 1. The drains and sources of the N transistors are connected sequentially to form a transistor stacking structure. The gate of each transistor is connected to a bias resistor R3. Specifically, in the first transistor stacking unit, the drain of the first transistor is connected to microstrip line TL2, and the source of the Nth transistor is connected to microstrip line TL3. In the second transistor stacking unit, the drain of the first transistor is connected to microstrip lines TL3 and TL4, and the source of the Nth transistor is connected to a DC blocking capacitor C4, with the other end of the DC blocking capacitor C4 grounded. In the third transistor stacking unit, the drain of the first transistor is connected to microstrip lines TL4 and TL5, and the source of the Nth transistor is connected to a DC blocking capacitor C5, with the other end of the DC blocking capacitor C5 grounded.

[0008] The first channel circuit connects the bonding inductor L2 and the DC blocking capacitor C2, and finally connects to the RF output terminal RF1; the second channel circuit connects the bonding inductor L3 and the DC blocking capacitor C3, and finally connects to the RF output terminal RF2.

[0009] In the first channel circuit, the gate of the first transistor stack unit is connected to the second control voltage V2 after being connected to the bias resistor R3. The gates of the second and third transistor stack units are connected to the first control voltage V1 after being connected to the bias resistor R3. In the second channel circuit, the gate of the first transistor stack unit is connected to the first control voltage V1 after being connected to the bias resistor R3. The gates of the second and third transistor stack units are connected to the second control voltage V2 after being connected to the second control voltage V2.

[0010] Preferably, each of the three transistor stacking units has 6 transistors.

[0011] Preferably, the bonding inductors L1 to L3 are all individually bonded with gold wire or gold strip, and the number and length of the bonding wires are determined according to the actual measurement conditions.

[0012] Preferably, the DC blocking capacitors C1 to C3, the specific values ​​of which vary depending on the frequency band used, are all connected externally.

[0013] Preferably, all transistors are controlled by 5V / 0V level logic.

[0014] Compared with existing technologies, the beneficial effects achieved by this invention are as follows: By adding two bias resistors to the input, this invention transforms the original single-pole double-throw switch, which required a negative input voltage, into one that only needed a positive input voltage, thus simplifying the circuit implementation. Furthermore, by stacking multiple series-parallel switching transistors on the basis of traditional series-parallel switches, this invention achieves high-power input for the switching chip. Simultaneously, the multiple parallel transistors ensure good isolation and isolation bandwidth over a wide frequency range, and the microstrip line matching results in excellent performance indicators such as insertion loss. Attached Figure Description

[0015] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0016] Figure 1 The circuit diagram is for a single-pole double-throw high-power switch chip with positive input proposed in this invention.

[0017] Figure 2 This is a graph showing the relationship between insertion loss and frequency;

[0018] Figure 3 This is a graph showing the relationship between isolation and frequency;

[0019] Figure 4 This is a graph showing the relationship between input / output callback loss and frequency;

[0020] Figure 5 This is a graph showing the maximum input power the chip can withstand. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] To make the above-mentioned objectives, features and effects of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] A single-pole double-throw high-power switching chip with positive input includes transistors M1~M18, DC blocking capacitors C1~C5, bonding inductors L1~L3, microstrip lines TL1~TL5, and bias resistors R1~R3. Figure 1As shown, one end of the bias resistors R1 and R2 is connected between the input bonding inductor L1 and the microstrip line TL1, and the other end is connected to the first control voltage V1 and the second control voltage V2, respectively. The other end of the microstrip line TL1 is connected to the microstrip line TL2 of the channel one circuit and the channel two circuit. The other end of L1 is connected to the DC blocking capacitor C1 to the radio frequency input terminal RFC.

[0024] Both Channel 1 and Channel 2 circuits include the following identical structure: the drains and sources of transistors M1 to M6 of the same size are connected sequentially to form a stack of 6 transistors. The gates of all transistors are connected to bias resistor R3. The drain of M1 is connected to microstrip line TL2, and the source of M6 is connected to microstrip line TL3. The drains and sources of transistors M7 to M12 of the same size are connected sequentially. The gates of all transistors are connected to bias resistor R3. The drain of M7 is connected to microstrip lines TL3 and TL4. The source of M12 is connected to DC blocking capacitor C4, and the other end of DC blocking capacitor C4 is grounded. The drains and sources of transistors M13 to M18 of the same size are connected sequentially. The gates of all transistors are connected to bias resistor R3. The drain of M13 is connected to microstrip lines TL4 and TL5. The source of M18 is connected to DC blocking capacitor C5, and the other end of DC blocking capacitor C5 is grounded.

[0025] The first channel circuit connects the bonding inductor L2 and the DC blocking capacitor C2, and finally connects to the RF output terminal RF1; the second channel circuit connects the bonding inductor L3 and the DC blocking capacitor C3, and finally connects to the RF output terminal RF2.

[0026] In channel one circuit, transistors M1-M6 have their gates connected to the second control voltage V2 via bias resistor R3. Transistors M7-M12 and M13-M18 have their gates connected to the first control voltage V1 via bias resistor R3 and one end of bias resistor R1. In channel two circuit, transistors M1-M6 have their gates connected to the first control voltage V1 via bias resistor R3. Transistors M7-M12 and M13-M18 have their gates connected to the second control voltage V2 via bias resistor R3 and one end of bias resistor R2.

[0027] DC blocking capacitors C1~C3 are used to provide isolation between DC and RF. The specific values ​​vary depending on the frequency band used and they are all connected off-chip. Bonding inductors L1~L3 are reserved for chip packaging bonding inductors. They are all individually bonded with gold wire or gold strip. The number and length of the bonding wires are determined according to the actual measurement.

[0028] The working principle of this invention is as follows: When the first control voltage V1 is 0V and the second control voltage V2 is 5V, transistors M1~M6 in channel one circuit are turned on, and transistors M7~M12 and M13~M18 are turned off. In channel two circuit, transistors M1~M6 are turned off, and transistors M7~M12 and M13~M18 are turned on, and the radio frequency signal is transmitted from the radio frequency signal input terminal RFC to the radio frequency signal output terminal RF1. When the first control voltage V1 is 5V and the second control voltage V2 is 0V, transistors M1~M6 in channel one circuit are turned off, and transistors M7~M12 and M13~M18 are turned on. In channel two circuit, transistors M1~M6 are turned on, and transistors M7~M12 and M13~M18 are turned off. The radio frequency signal is transmitted from the radio frequency signal input terminal RFC to the radio frequency signal output terminal RF2.

[0029] The essence of a transistor FET as a switching device is to control the opening and closing of the semiconductor channel between the drain and source by changing the gate-source voltage. Taking the depletion-type N-channel field-effect transistor (MOSFET) of the present invention as an example, when a negative gate-source voltage is applied and Vgs≤Vth(off), the conductive channel disappears, and the switch is equivalent to "off". When the gate-source voltage Vgs≥0, the channel exists by default, and the switch is equivalent to conduction. In the present invention, because of the voltage division effect of the bias resistors R1 and R2, it is only necessary to apply a voltage of 0V / 5V to the first and second control voltages V1 and V2 to realize the conduction and turn-off of the switching chip.

[0030] The power of a FET is limited by the drain-source saturation current in the low-resistance state and the gate-drain avalanche voltage in the high-resistance state. The total power can be increased by simultaneously increasing the total gate length and stacking multiple transistors in series. By using a new technique of stacking multiple FETs, the voltage is evenly distributed among the stacked FETs, thereby increasing the overall voltage withstand capability of the parallel FETs. When the number of transistors in series is N, the maximum power the switch can withstand is:

[0031]

[0032] Where V DSS Z0 is the drain breakdown voltage and Z0 is the characteristic impedance. Therefore, considering the actual application scenario, this embodiment preferably uses 6 stacked transistors.

[0033] In summary, the single-pole double-throw high-power chip of the present invention was simulated using ADS software. Figure 2 The figure shows the insertion loss when the RF path RF1 of the switching chip is turned on, with control voltage V1 at 0V and V2 at 5V. Figure 3 The figure shows the isolation when the RF path RF2 of the switching chip is turned off when the control voltage V1 is 0V and V2 is 5V. Figure 4 The diagram shows the input / output callback loss when the switching chip is turned off and on. Figure 5 This represents the chip's maximum power handling capability.

[0034] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A single-pole double-throw high-power switch chip with positive input voltage, characterized in that, It includes one RF input terminal, two RF output terminals, two control voltages, and two channel circuits. The specific structure is as follows: One end of the bias resistors R1 and R2 is connected between the bonding inductor L1 and the microstrip line TL1, and the other end is connected to the first control voltage V1 and the second control voltage V2, respectively. The other end of the microstrip line TL1 is connected to the microstrip line TL2 of the channel one circuit and the channel two circuit. The other end of the bonding inductor L1 is connected to the DC blocking capacitor C1 to the radio frequency input terminal RFC. Both Channel 1 and Channel 2 circuits include a first transistor stacking unit, a second transistor stacking unit, and a third transistor stacking unit. Each transistor stacking unit includes N transistors of the same size, where N is an integer greater than 1. The drains and sources of the N transistors are connected sequentially to form a transistor stacking structure. The gate of each transistor is connected to a bias resistor R3. Specifically, in the first transistor stacking unit, the drain of the first transistor is connected to microstrip line TL2, and the source of the Nth transistor is connected to microstrip line TL3. In the second transistor stacking unit, the drain of the first transistor is connected to microstrip lines TL3 and TL4, and the source of the Nth transistor is connected to a DC blocking capacitor C4, with the other end of the DC blocking capacitor C4 grounded. In the third transistor stacking unit, the drain of the first transistor is connected to microstrip lines TL4 and TL5, and the source of the Nth transistor is connected to a DC blocking capacitor C5, with the other end of the DC blocking capacitor C5 grounded. The first channel circuit connects the bonding inductor L2 and the DC blocking capacitor C2, and finally connects to the RF output terminal RF1; the second channel circuit connects the bonding inductor L3 and the DC blocking capacitor C3, and finally connects to the RF output terminal RF2. In the first channel circuit, the gate of the first transistor stack unit is connected to the second control voltage V2 after being connected to the bias resistor R3. The gates of the second and third transistor stack units are connected to the first control voltage V1 after being connected to the bias resistor R3. In the second channel circuit, the gate of the first transistor stack unit is connected to the first control voltage V1 after being connected to the bias resistor R3. The gates of the second and third transistor stack units are connected to the second control voltage V2 after being connected to the second control voltage V2.

2. The single-pole double-throw high-power switch chip with positive input as described in claim 1, characterized in that, Each of the three transistor stacking units has 6 transistors.

3. A single-pole double-throw high-power switch chip with positive input as described in claim 1, characterized in that, Bonded inductors L1, L2, and L3 are all individually bonded with gold wire or gold strip. The number and length of the bonding wires are determined based on the actual measurement conditions.

4. A single-pole double-throw high-power switch chip with positive input as described in claim 1, characterized in that, The DC blocking capacitors C1, C2, and C3 have different values ​​depending on the frequency band used, and are all connected externally.

5. A single-pole double-throw high-power switch chip with positive input as described in any one of claims 1-4, characterized in that, All transistors are controlled using 5V / 0V level logic.

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