A current steering digital-to-analog converter based on randomized differential four-switch control

Abstract

This invention discloses a current-driven digital-to-analog converter (DAC) based on randomized differential four-switch control. The invention includes a basic DAC structure, a four-switch interleaved control module, a randomized differential four-switch module, a current source array, and a load module. The four-switch interleaved control module performs zero-reset processing on the decoded signal and generates four-switch control signals. The randomized differential four-switch module randomizes these control signals, randomly selecting different differential switch pairs in each clock cycle, thereby reducing the impact of switch mismatch on dynamic performance. The current source array and load module convert current to voltage and output a differential analog signal. By introducing randomized differential four-switch control technology, this invention effectively suppresses data-related switching distortion and image spurious signals caused by differential switch mismatch, thus improving the dynamic performance of the DAC.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, specifically a current-driven digital-to-analog converter based on randomized differential four-switch control. Background Technology

[0002] With the development of broadband communication, radar systems, and high-speed signal synthesis, high-speed digital-to-analog converters (DACs) have been widely adopted in related applications. Current-controlled DACs, due to their inherent high-speed characteristics, have become the mainstream architecture for achieving GS / s sampling rates and broadband output. However, under high-speed operating conditions, data-dependent switching distortion has gradually become a major bottleneck restricting the improvement of spurious-free dynamic range (SFDR). Ideally, the DAC's switching should produce a symmetrical and consistent transient response when the input code changes. However, due to the non-ideal characteristics of the devices, actual switching processes often exhibit phenomena such as asymmetric turn-on and turn-off transients, inconsistent high and low level pulse widths, and differences in rising and falling edge responses. This leads to switching errors that are related to the input code pattern, i.e., data-dependent switching distortion. In the frequency domain, this error modulates the input signal, generating non-harmonic spurious components and reducing spurious-free dynamic range. To suppress these distortions, Differential-Quad Switching (DQS) technology has been proposed. By adding a second set of complementary switches to the traditional differential switch, a constant number of switches are maintained throughout each clock cycle, thus eliminating transient inconsistencies caused by changes in the number of switch switches depending on the code pattern. Under ideal matching conditions, this technique can convert the error introduced by switch non-ideality into an equivalent gain error, without producing nonlinear distortion.

[0003] However, in existing technologies, as manufacturing processes move into deep submicron nodes, device size shrinkage and process variations intensify, inevitably leading to mismatches in the transient responses between different differential switch pairs. In a fixed-rotation mode, these mismatch errors are periodically modulated, generating image spurious components in the frequency domain, limiting the dynamic performance improvement of the DQS architecture. Therefore, an improved technique is needed to simultaneously suppress data-dependent switching distortion and image spurious components to enhance the performance of high-speed current-controlled DACs. Summary of the Invention

[0004] The purpose of this invention is to provide a current-controlled digital-to-analog converter based on randomized differential four-switch control in order to solve the problems mentioned above.

[0005] The technical solution adopted in this invention is as follows: a current-rudder type digital-to-analog converter based on randomized differential four-switch control, comprising: a digital-to-analog converter, a four-switch interleaved control module, a randomized differential four-switch module, a current source and a load module;

[0006] The decoded data signals W1 and W2 output by the digital-to-analog converter are respectively connected to the data input terminals of the true single-phase clock triggers TSPC1 and TSPC3 in the four-switch interleaved control module;

[0007] The first zero-return control signal D1P, the first complementary zero-return control signal D1N, the second zero-return control signal D2P, and the second complementary zero-return control signal D2N output by the four-switch interleaved control module are respectively connected to the first input terminals of the NAND gates NAND1~NAND8 in the random differential four-switch module.

[0008] The control signals SW1, SW2, SWB1, and SWB2 output by the random differential four-switch module are respectively connected to the gates of the switching MOSFETs M3, M5, M4, and M6 in the current source and load module.

[0009] The drain of the internal current source MOSFET M1 of the current source and load module is connected to the source of the common-source MOSFET M2.

[0010] The drain of M2 inside the current source and load module is simultaneously connected to the source of switching MOSFETs M3 and M5.

[0011] The drains of M3 and M5 inside the current source and load module are connected to the positive terminal load to output a positive analog voltage.

[0012] The drains of M4 and M6 inside the current source and load module are connected to the negative load to output a negative analog voltage. The sources of M4 and M6 are grounded, and the source of M1 is connected to the power supply terminal, together forming a complete current-to-voltage output path.

[0013] In a preferred embodiment, the four-switch interleaved control module includes: four true single-phase clock triggers TSPC1~TSPC4, four AND gates AND1~AND4, and six inverters INV1~INV6.

[0014] In a preferred embodiment, the first decoded data signal W1 in the digital-to-analog converter is connected to the data input terminal of a true single-phase clock flip-flop TSPC1. W1 is inverted by an inverter INV1 and then connected to the data input terminal of a true single-phase clock flip-flop TSPC2. The clock input terminals of TSPC1 and TSPC2 are connected to the same clock signal CK1. The output terminal of TSPC1 is connected to the first input terminal of an AND gate AND1, and the second input terminal of AND gate AND1 is connected to the clock signal CKB1, wherein CKB1 and CK1 have the same frequency but opposite phase. The output terminal of AND1 outputs a first return-to-zero control signal D1P via an inverter INV2. The output terminal of TSPC2 is connected to the first input terminal of an AND gate AND2, and the second input terminal of AND gate AND2 is connected to the clock signal CKB1. The output terminal of AND2 outputs a first complementary return-to-zero control signal D1N via an inverter INV3.

[0015] In a preferred embodiment, the second decoded data signal W2 in the digital-to-analog converter is connected to the data input terminal of the true single-phase clock flip-flop TSPC3. W2 is inverted by inverter INV4 and then connected to the data input terminal of the true single-phase clock flip-flop TSPC4. The clock input terminals of TSPC3 and TSPC4 are connected to the clock signal CKB1. The output terminal of TSPC3 is connected to the first input terminal of AND gate AND3. The second input terminal of AND gate AND3 is connected to the clock signal CK1. The output terminal of AND3 outputs the second return-to-zero control signal D2P via inverter INV5. The output terminal of TSPC4 is connected to the first input terminal of AND gate AND4. The second input terminal of AND gate AND4 is connected to the clock signal CK1. The output terminal of AND4 outputs the second complementary return-to-zero control signal D2N via inverter INV6.

[0016] In a preferred embodiment, the four-switch interleaving control module is used to perform zeroing processing on the decoded digital signal to generate a fixed interleaving zeroing control signal for driving two sets of differential switch pairs, so as to suppress inter-symbol interference while avoiding insufficient output signal setup time and energy loss.

[0017] In a preferred embodiment, the random differential four-switch module includes: eight inverters INV1 to INV8, eight NAND gates NAND1 to NAND8, four 2-to-1 data selectors MUX1 to MUX4, and a pseudo-random number generator.

[0018] In a preferred embodiment, the output signal of the four-switch interleaved control module is used as the input signal of the random differential four-switch module, wherein:

[0019] The input signal D1P is connected to the first input terminals of NAND gates NAND1 and NAND2 respectively. The random control signal R1 and the inverted signal output by the pseudo-random number generator are connected to the second input terminals of NAND gates NAND1 and NAND2 respectively. The outputs of NAND1 and NAND2 are connected to the two input terminals of the 2-to-1 data selector MUX1 respectively. The output of the 2-to-1 data selector MUX1 is the control signal SW1.

[0020] The input signal D2P is connected to the first input terminals of NAND gates NAND3 and NAND4 respectively. The random control signal R2 and the inverted signal output by the pseudo-random number generator are connected to the second input terminals of NAND gates NAND3 and NAND4 respectively. The outputs of NAND3 and NAND4 are connected to the two input terminals of the 2-to-1 data selector MUX2 respectively. The output of the 2-to-1 data selector MUX2 is the control signal SW2.

[0021] The input signal D1N is connected to the first input terminals of NAND gates NAND5 and NAND6 respectively. The random control signal R1 and the inverted signal are connected to the second input terminals of NAND gates NAND5 and NAND6 respectively. The outputs of NAND5 and NAND6 are connected to the two input terminals of a 2-to-1 data selector MUX3 respectively. The output of the 2-to-1 data selector MUX3 is the control signal SWB1.

[0022] The input signal D2N is connected to the first input terminals of NAND gates NAND7 and NAND8 respectively. The random control signal R2 and the inverted signal are connected to the second input terminals of NAND gates NAND7 and NAND8 respectively. The outputs of NAND7 and NAND8 are connected to the two input terminals of a 2-to-1 data selector MUX4 respectively. The output of the 2-to-1 data selector MUX4 is the control signal SWB2.

[0023] The data paths for input signals D2P and D2N are similar to those for D1P and D1N, respectively. When the random control signal R2 is high, D2P is converted into control signal SW1 and D2N is converted into control signal SWB1; when R2 is low, D2P is converted into control signal SW2 and D2N is converted into control signal SWB2.

[0024] The random control signals R1 and R2 are generated by the pseudo-random number generator in each clock cycle and are used to randomly select differential switch pairs to suppress the image spurious components generated by the periodic modulation of differential switch pair mismatch under fixed interleaving control conditions.

[0025] In a preferred embodiment, the current source and load module includes: a current source MOSFET M1, a common source MOSFET M2, and four switching MOSFETs M3, M4, M5, and M6.

[0026] In a preferred embodiment, M1 is a unit current source transistor, and M2 is connected between the drain of M1 and the source of the switching transistor to increase the output impedance of the current source.

[0027] In a preferred embodiment, M3 and M4 constitute a first pair of differential switches, and M5 and M6 constitute a second pair of differential switches. The two pairs of differential switches together form a differential four-switch structure and cooperate with the load to realize the conversion of current signal to differential voltage signal.

[0028] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0029] 1. This invention introduces a randomized control mechanism to fundamentally mitigate the negative impact of mismatch between two pairs of differential switches. In traditional architectures, switch mismatch causes data-related switching distortion and generates spurious image components, directly limiting the spurious-free dynamic range of the high-speed current-controlled digital-to-analog converter. The randomized control mechanism breaks the periodic modulation pattern of the mismatch error, allowing the originally concentrated error signal to be distributed in a more dispersed form. This effectively reduces the impact of data-related switching distortion and spurious image components, significantly improving the spurious-free dynamic range of the digital-to-analog converter and enabling it to maintain excellent signal conversion quality even in high-speed operating scenarios.

[0030] 2. In this invention, the four-switch interleaving control module provides precise timing management for digital signal processing and switch control. This module performs zeroing processing on the decoded digital signal to avoid interference caused by signal residue. Simultaneously, by using fixed interleaving to select different differential switch pairs, it ensures that only one set of differential switch pairs is active in each clock cycle. This design reduces inter-symbol interference that may occur when multiple sets of switches switch simultaneously, and also provides sufficient settling time for the output signal, allowing it to stabilize fully before output. Through rigorous timing control, the high-precision dynamic performance of the digital-to-analog converter is reliably guaranteed, ensuring continuous output of high-quality analog signals even during high-speed data conversion.

[0031] 3. In this invention, the randomized differential four-switch structure further optimizes the spectral characteristics of the digital-to-analog converter (DAC) by dynamically and randomly selecting the differential switches to participate in operation. In fixed-gating mode, harmonics generated by switch mismatch exhibit significant periodicity, affecting the spectral purity of the output signal and thus limiting overall dynamic performance. The random gating mechanism, however, ensures that the operating switches are randomized within each clock cycle. The originally concentrated harmonics are dispersed into broadband noise, no longer concentrated in a specific frequency band, fundamentally improving the spectral purity of the DAC. This optimization not only makes the output signal spectrum cleaner but also comprehensively enhances the overall dynamic performance of the DAC, making it more adaptable to applications with stringent signal quality requirements. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the current-driven digital-to-analog converter structure of the present invention;

[0033] Figure 2 This is a circuit diagram of the four-switch interleaved control module in this invention;

[0034] Figure 3 This is a timing diagram of the four-switch interleaved control and random differential four-switch control in this invention;

[0035] Figure 4 This is the circuit diagram of the random differential four-switch module in this invention;

[0036] Figure 5 This is a circuit diagram of the current source in this invention. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0038] Example: Refer to Figure 1-5 ,like Figure 1 As shown, a current-driven digital-to-analog converter based on randomized differential four-switch control is provided. Its operation is as follows: the external high-speed differential digital signal is first converted into a single-ended digital signal by the LVDS receiving module and then sent to the parallel-to-serial conversion module; the parallel-to-serial conversion module converts the high-speed serial digital signal into two low-speed parallel digital signals and outputs them to the Dynamic Element Matching Decoder (DEM) module; the decoded digital signal is then processed sequentially by the four-switch interleaving control module and the randomized differential four-switch module, and used to drive the differential four switches in the current source array, thereby realizing current-to-voltage conversion on the load module to obtain a differential analog output signal. The reference current required by the current source array is generated by the reference voltage produced by the bandgap reference module via the voltage-to-current conversion module and distributed to each current source unit through the bias module.

[0039] In this embodiment, the digital-to-analog converter is a 14-bit, 1GS / s current-driven DAC, employing a "4+5+5" segmented structure. Its digital section includes a parallel-to-serial conversion circuit, an input register array, a low-order pseudo-decoding circuit, a dynamic element matching decoding module, a four-switch interleaved control module, a random differential four-switch module, and a latch array for synchronizing random control signals. The analog section includes an LVDS receiver, a current source array, a bias circuit, and load resistors, among other modules, to achieve differential analog signal output.

[0040] like Figure 2 As shown, the four-switch interleaved control module is used to perform timing alignment and zeroing processing on the digital control signals output by the dynamic element matching decoding module. Specifically, the four-switch interleaved control module includes: four true single-phase clock flip-flops TSPC1~TSPC4, four AND gates AND1~AND4, and six inverters INV1~INV6.

[0041] The decoded data signal W1 is connected to the data input of a true single-phase clock flip-flop TSPC1. After being inverted by inverter INV1, W1 is connected to the data input of a true single-phase clock flip-flop TSPC2. The clock inputs of TSPC1 and TSPC2 are connected to the same clock signal CK1. The output of TSPC1 is connected to the first input of AND gate AND1, and the second input of AND gate AND1 is connected to the clock signal CKB1, where CKB1 and CK1 have the same frequency but opposite phase. The output of AND1 outputs the first return-to-zero control signal D1P via inverter INV2. The output of TSPC2 is connected to the first input of AND gate AND2, and the second input of AND gate AND2 is connected to the clock signal CKB1. The output of AND2 outputs the first complementary return-to-zero control signal D1N via inverter INV3.

[0042] The second decoded data signal W2 is connected to the data input terminal of the true single-phase clock flip-flop TSPC3. W2 is inverted by inverter INV4 and then connected to the data input terminal of the true single-phase clock flip-flop TSPC4. The clock input terminals of TSPC3 and TSPC4 are connected to the clock signal CKB1. The output terminal of TSPC3 is connected to the first input terminal of AND gate AND3. The second input terminal of AND gate AND3 is connected to the clock signal CK1. The output terminal of AND3 outputs the second return-to-zero control signal D2P through inverter INV5. The output terminal of TSPC4 is connected to the first input terminal of AND gate AND4. The second input terminal of AND gate AND4 is connected to the clock signal CK1. The output terminal of AND4 outputs the second complementary return-to-zero control signal D2N through inverter INV6.

[0043] In the four-switch interleaved control module, the first-stage true single-phase clock trigger is used to align the timing of the two decoded signals and their complementary signals. The second-stage AND gate is used to perform zeroing processing on the data. The final-stage inverter is used to flip the level of the control signal to adapt to the conduction control of the PMOS current source switch. D1P and D2P constitute a set of dual-channel interleaved zeroing control signals. Their control method is to alternately select different differential switch pairs in adjacent clock cycles, thereby ensuring that only one set of differential switch pairs participates in current steering in each clock cycle and keeping the switching reversal behavior constant in each clock cycle to reduce code-related switching transient interference. D1N and D2N are the complementary control signals corresponding to D1P and D2P.

[0044] like Figure 3 The diagram shown illustrates the timing relationship between the four-switch interleaved control and the random differential four-switch control in an embodiment of the present invention. The upper part shows the timing relationship of the four-switch interleaved control module, and the lower part shows the timing relationship of the random differential four-switch module. The following explanation, in conjunction with this timing diagram, describes the operation of the four-switch interleaved control module.

[0045] The timing diagram illustrates the process by which the four-switch interleaved control module zeroes the input data over several clock cycles and generates fixed interleaved four-switch control signals in adjacent clock cycles. To illustrate the non-ideal characteristics of the switch switching process, it is assumed that when the input code changes from "1" to "0", the switch transitions from the off state to the on state, generating a non-ideal rising transient; while when the input code changes from "0" to "1", the current turn-off process is relatively ideal. Furthermore, to illustrate the impact of differential switch mismatch on the output spectrum, it is assumed that the error generated by the first set of differential switch pairs is e1, and the error generated by the second set of differential switch pairs is e2.

[0046] Specifically, the data D after LVDS differential-to-single-ended conversion <1> For example, let's analyze a segment of the data sequence "11001". After processing by the parallel-to-serial conversion module and the dynamic element matching decoding module, this data yields two decoded signals W1. <1> With W2 <1> The two differ in timing by half a clock cycle. W1 <1> With W2 <1> After being input to the four-switch interleaved control module, the signal is logically combined with the clock signal and inverted to generate control signals D1P, D1N, D2P, and D2N.

[0047] Without introducing a random differential four-switch module, the above control signals are directly used to drive the differential switches in the digital-to-analog converter, and the corresponding actual output is as follows: Figure 3 The solid line OUT represents the output of the digital-to-analog converter, while the dashed line represents the ideal digital-to-analog converter output. The difference between the two lines yields the error signal. If there is no mismatch between the two differential switch pairs (e1=e2), the error depends only on the sign of the output polarity and is independent of changes in the input code pattern. In this case, the mismatch effect is equivalent to a constant gain error, which does not modulate the input signal or introduce nonlinear distortion.

[0048] When there is a mismatch between two sets of differential switch pairs (e1 ≠ e2), under a fixed interleaving control mode, the mismatch errors of different differential switch pairs will be periodically selected according to a definite rotation pattern, thus forming periodic error modulation in the time domain. This modulation process is equivalent to superimposing a periodic modulation component with a frequency of fs / 2 onto the output signal, shifting the mismatch error in the frequency domain to around (2n+1)fs / 2±fin, forming a mirror spurious component, which in turn becomes an important factor limiting the dynamic performance of the digital-to-analog converter.

[0049] like Figure 4 As shown, the random differential four-switch module includes: 8 inverters INV1 to INV8, 8 NAND gates NAND1 to NAND8, 4 2-to-1 data selectors MUX1 to MUX4, and a pseudo-random number generator;

[0050] The output signal of the four-switch interleaved control module serves as the input signal of the random differential four-switch module, where:

[0051] The input signal D1P is connected to the first input terminals of NAND gates NAND1 and NAND2 respectively. The random control signal R1 and the inverted signal output by the pseudo-random number generator are connected to the second input terminals of NAND gates NAND1 and NAND2 respectively. The outputs of NAND1 and NAND2 are connected to the two input terminals of the 2-to-1 data selector MUX1 respectively. The output of the 2-to-1 data selector MUX1 is the control signal SW1.

[0052] The input signal D2P is connected to the first input terminals of NAND gates NAND3 and NAND4 respectively. The random control signal R2 and the inverted signal output by the pseudo-random number generator are connected to the second input terminals of NAND gates NAND3 and NAND4 respectively. The outputs of NAND3 and NAND4 are connected to the two input terminals of the 2-to-1 data selector MUX2 respectively. The output of the 2-to-1 data selector MUX2 is the control signal SW2.

[0053] The input signal D1N is connected to the first input terminals of NAND gates NAND5 and NAND6 respectively. The random control signal R1 and the inverted signal are connected to the second input terminals of NAND gates NAND5 and NAND6 respectively. The outputs of NAND5 and NAND6 are connected to the two input terminals of the 2-to-1 data selector MUX3 respectively. The output of the 2-to-1 data selector MUX3 is the control signal SWB1.

[0054] The input signal D2N is connected to the first input terminals of NAND gates NAND7 and NAND8 respectively. The random control signal R2 and the inverted signal are connected to the second input terminals of NAND gates NAND7 and NAND8 respectively. The outputs of NAND7 and NAND8 are connected to the two input terminals of the 2-to-1 data selector MUX4 respectively. The output of the 2-to-1 data selector MUX4 is the control signal SWB2.

[0055] The random differential four-switch module operates as follows:

[0056] When the random control signal R1 is high, the input signal D1P is converted into the control signal SW1 and connected to the gate of the MOSFET M3 in the four-switch structure of the subsequent current source module. The input signal D1N is converted into the control signal SWB1 and connected to the gate of the MOSFET M4. M3 and M4 form a differential switch pair.

[0057] When the random control signal R1 is low, the input signal D1P is converted into the control signal SW2 and connected to the gate of MOSFET M5, and the input signal D1N is converted into the control signal SWB2 and connected to the gate of MOSFET M6. M5 and M6 form another set of differential switch pairs; among them, M3, M4, M5 and M6 together form a four-switch structure.

[0058] The data paths for input signals D2P and D2N are similar to those for D1P and D1N, respectively. When the random control signal R2 is high, D2P is converted into control signal SW1 and D2N is converted into control signal SWB1; when R2 is low, D2P is converted into control signal SW2 and D2N is converted into control signal SWB2.

[0059] Random control signals R1 and R2 are generated by a pseudo-random number generator in each clock cycle to randomly select differential switch pairs in order to suppress image spurious components generated by the periodic modulation of differential switch pair mismatch under fixed interleaving control conditions.

[0060] like Figure 3 The lower half shows a timing diagram of the random differential four-switch module in an embodiment of the present invention, which is used to illustrate the random selection process of the differential switch pairs and the working mechanism of reducing the error introduced by the mismatch of the differential switch pairs through randomization.

[0061] In the random differential four-switch control mode, a set of differential switch pairs is randomly selected by a random control signal to participate in current steering within each clock cycle. This causes the non-ideal switching transient errors e1 and e2 caused by differential switch pair mismatch to be randomly distributed within each clock cycle. By randomizing the mismatch error, which originally had a deterministic periodicity under fixed interleaved control conditions, the deterministic modulation relationship between it and the input signal can be effectively broken. This reduces the amplitude of the image spurious component formed by the mismatch error in the frequency domain and weakens its impact on the dynamic performance of the digital-to-analog converter.

[0062] like Figure 5 As shown, the current source and load module includes: a current source MOSFET M1, a common-source MOSFET M2, and four switching MOSFETs M3, M4, M5, and M6;

[0063] Among them, M1 is a current source transistor, and its device size affects the matching accuracy of the current source; M2 is connected between the drain of M1 and the source of the switching transistor, and together with M1, they form a common source and common gate structure to improve the output impedance of the current source, thereby reducing the nonlinear error caused by the change of output current with output impedance; M3 and M4 form the first pair of differential switching transistors, and M5 and M6 form the second pair of differential switching transistors. The above two pairs of differential switching transistors together form a differential four-switch structure, and cooperate with the load to realize the conversion of current signal to differential voltage signal;

[0064] In this embodiment, the gate control signals of M3 and M5 correspond to SW1 and SW2 outputs of the random differential quad-switch module, respectively, and are used to control the DAC positive terminal output current Iop; the gate control signals of M4 and M6 correspond to SWB1 and SWB2 outputs of the random differential quad-switch module, respectively, and are used to control the DAC negative terminal output current Ion. To reduce the parasitic capacitance of the switching MOSFETs and improve high-speed switching performance, the channel lengths of M3 to M6 are all designed with the minimum size allowed by the process.

[0065] Under the randomized differential four-switch control, only one pair of the first or second differential switches is randomly selected to participate in current steering in each clock cycle, while the gate of the other pair of differential switches that is not selected remains at the off level, thereby avoiding transient interference and additional power consumption caused by multiple pairs of differential switches being turned on at the same time.

[0066] Wherein, Vcs and Vcg are the bias voltages of the current source transistor M1 and the common-source gate transistor M2, respectively. In this embodiment, the current source transistor is implemented using a PMOS device. Compared with the NMOS current source, the PMOS device has lower flicker noise and smaller substrate coupling effect, which is beneficial for reducing output noise and improving the dynamic performance of the high-speed current-controlled DAC.

[0067] From the above, we can conclude that:

[0068] This invention introduces a randomized control mechanism to fundamentally mitigate the negative impact of mismatch between two pairs of differential switches. In traditional architectures, switch mismatch causes data-dependent switching distortion and generates spurious image components, directly limiting the spurious-free dynamic range of the high-speed current-controlled digital-to-analog converter (DAC). The randomized control mechanism breaks the periodic modulation pattern of the mismatch error, distributing the originally concentrated error signal in a more dispersed manner. This effectively reduces the impact of data-dependent switching distortion and spurious image components, significantly improving the spurious-free dynamic range of the DAC and enabling it to maintain excellent signal conversion quality even in high-speed operating scenarios.

[0069] In this invention, the four-switch interleaving control module provides precise timing management for digital signal processing and switch control. This module performs zero-reset processing on the decoded digital signal to avoid interference from signal residue. Simultaneously, by using fixed interleaving to select different differential switch pairs, it ensures that only one set of differential switch pairs is active in each clock cycle. This design reduces inter-symbol interference that may occur when multiple sets of switches switch simultaneously, and also provides sufficient settling time for the output signal, allowing it to stabilize fully before output. Through rigorous timing control, the high-precision dynamic performance of the digital-to-analog converter is reliably guaranteed, ensuring continuous output of high-quality analog signals even during high-speed data conversion.

[0070] In this invention, the randomized differential four-switch structure further optimizes the spectral characteristics of the digital-to-analog converter (DAC) by dynamically and randomly selecting the differential switches to participate in operation. In fixed-gating mode, harmonics generated by switch mismatch exhibit significant periodicity, affecting the spectral purity of the output signal and thus limiting overall dynamic performance. The random gating mechanism, however, ensures that the operating switches are randomized within each clock cycle. The originally concentrated harmonics are dispersed into broadband noise, no longer concentrated in a specific frequency band, fundamentally improving the spectral purity of the DAC. This optimization not only makes the output signal spectrum cleaner but also comprehensively enhances the overall dynamic performance of the DAC, making it more adaptable to applications with stringent signal quality requirements.

[0071] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0072] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A current-controlled analog-to-digital converter based on randomized differential four-switch control, characterized in that: include: Digital-to-analog converter, four-switch interleaved control module, random differential four-switch module, current source and load module; The decoded data signals W1 and W2 output by the digital-to-analog converter are respectively connected to the data input terminals of the true single-phase clock triggers TSPC1 and TSPC3 in the four-switch interleaved control module; The first zero-return control signal D1P, the first complementary zero-return control signal D1N, the second zero-return control signal D2P, and the second complementary zero-return control signal D2N output by the four-switch interleaved control module are respectively connected to the first input terminals of the NAND gates NAND1~NAND8 in the random differential four-switch module. The control signals SW1, SW2, SWB1, and SWB2 output by the random differential four-switch module are respectively connected to the gates of the switching MOSFETs M3, M5, M4, and M6 in the current source and load module. The drain of the internal current source MOSFET M1 of the current source and load module is connected to the source of the common-source MOSFET M2. The drain of M2 inside the current source and load module is simultaneously connected to the source of switching MOSFETs M3 and M5. The drains of M3 and M5 inside the current source and load module are connected to the positive terminal load to output a positive analog voltage. The drains of M4 and M6 inside the current source and load module are connected to the negative load to output a negative analog voltage. The sources of M4 and M6 are grounded, and the source of M1 is connected to the power supply terminal, together forming a complete current-to-voltage output path.

2. The current-driven digital-to-analog converter based on randomized differential four-switch control as described in claim 1, characterized in that: The four-switch interleaved control module includes: four true single-phase clock triggers TSPC1~TSPC4, four AND gates AND1~AND4, and six inverters INV1~INV6.

3. The current-driven digital-to-analog converter based on randomized differential four-switch control as described in claim 1, characterized in that: In the digital-to-analog converter, the first decoded data signal W1 is connected to the data input terminal of the true single-phase clock flip-flop TSPC1. After being inverted by the inverter INV1, W1 is connected to the data input terminal of the true single-phase clock flip-flop TSPC2. The clock input terminals of TSPC1 and TSPC2 are connected to the same clock signal CK1. The output terminal of TSPC1 is connected to the first input terminal of the AND gate AND1, and the second input terminal of the AND gate AND1 is connected to the clock signal CKB1, where CKB1 and CK1 have the same frequency but opposite phase. The output terminal of AND1 outputs the first return-to-zero control signal D1P through the inverter INV2. The output terminal of TSPC2 is connected to the first input terminal of the AND gate AND2, and the second input terminal of the AND gate AND2 is connected to the clock signal CKB1. The output terminal of AND2 outputs the first complementary return-to-zero control signal D1N through the inverter INV3.

4. The current-controlled digital-to-analog converter based on randomized differential four-switch control as described in claim 1, characterized in that: In the digital-to-analog converter, the second decoded data signal W2 is connected to the data input terminal of the true single-phase clock trigger TSPC3. W2 is inverted by inverter INV4 and then connected to the data input terminal of the true single-phase clock trigger TSPC4. The clock input terminals of TSPC3 and TSPC4 are connected to the clock signal CKB1. The output terminal of TSPC3 is connected to the first input terminal of AND gate AND3. The second input terminal of AND gate AND3 is connected to the clock signal CK1. The output terminal of AND3 outputs the second return-to-zero control signal D2P via inverter INV5. The output terminal of TSPC4 is connected to the first input terminal of AND gate AND4. The second input terminal of AND gate AND4 is connected to the clock signal CK1. The output terminal of AND4 outputs the second complementary return-to-zero control signal D2N via inverter INV6.

5. A current-controlled analog-to-digital converter based on randomized differential four-switch control as described in claim 1, characterized in that: The four-switch interleaved control module is used to perform zeroing processing on the decoded digital signal to generate a fixed interleaved zeroing control signal for driving two sets of differential switch pairs, so as to suppress inter-symbol interference while avoiding insufficient output signal setup time and energy loss.

6. A current-controlled analog-to-digital converter based on randomized differential four-switch control as described in claim 1, characterized in that: The random differential four-switch module includes: eight inverters INV1 to INV8, eight NAND gates NAND1 to NAND8, four 2-to-1 data selectors MUX1 to MUX4, and a pseudo-random number generator.

7. A current-controlled analog-to-digital converter based on randomized differential four-switch control as described in claim 1, characterized in that: The output signal of the four-switch interleaved control module serves as the input signal of the random differential four-switch module, wherein: The input signal D1P is connected to the first input terminals of NAND gates NAND1 and NAND2 respectively. The random control signal R1 and the inverted signal output by the pseudo-random number generator are connected to the second input terminals of NAND gates NAND1 and NAND2 respectively. The outputs of NAND1 and NAND2 are connected to the two input terminals of the 2-to-1 data selector MUX1 respectively. The output of the 2-to-1 data selector MUX1 is the control signal SW1. The input signal D2P is connected to the first input terminals of NAND gates NAND3 and NAND4 respectively. The random control signal R2 and the inverted signal output by the pseudo-random number generator are connected to the second input terminals of NAND gates NAND3 and NAND4 respectively. The outputs of NAND3 and NAND4 are connected to the two input terminals of the 2-to-1 data selector MUX2 respectively. The output of the 2-to-1 data selector MUX2 is the control signal SW2. The input signal D1N is connected to the first input terminals of NAND gates NAND5 and NAND6 respectively. The random control signal R1 and the inverted signal are connected to the second input terminals of NAND gates NAND5 and NAND6 respectively. The outputs of NAND5 and NAND6 are connected to the two input terminals of a 2-to-1 data selector MUX3 respectively. The output of the 2-to-1 data selector MUX3 is the control signal SWB1. The input signal D2N is connected to the first input terminals of NAND gates NAND7 and NAND8 respectively. The random control signal R2 and the inverted signal are connected to the second input terminals of NAND gates NAND7 and NAND8 respectively. The outputs of NAND7 and NAND8 are connected to the two input terminals of a 2-to-1 data selector MUX4 respectively. The output of the 2-to-1 data selector MUX4 is the control signal SWB2. The data paths for input signals D2P and D2N are similar to those for D1P and D1N, respectively. When the random control signal R2 is high, D2P is converted into control signal SW1 and D2N is converted into control signal SWB1; when R2 is low, D2P is converted into control signal SW2 and D2N is converted into control signal SWB2. The random control signals R1 and R2 are generated by the pseudo-random number generator in each clock cycle and are used to randomly select differential switch pairs to suppress the image spurious components generated by the periodic modulation of differential switch pair mismatch under fixed interleaving control conditions.

8. A current-controlled digital-to-analog converter based on randomized differential four-switch control as described in claim 1, characterized in that: The current source and load module includes: a current source MOSFET M1, a common source MOSFET M2, and four switching MOSFETs M3, M4, M5, and M6.

9. A current-controlled analog-to-digital converter based on randomized differential four-switch control as described in claim 8, characterized in that: M1 is a unit current source transistor, and M2 is connected between the drain of M1 and the source of the switching transistor to increase the output impedance of the current source.

10. A current-controlled analog-to-digital converter based on randomized differential four-switch control as described in claim 8, characterized in that: M3 and M4 form the first pair of differential switches, and M5 and M6 form the second pair of differential switches. The two pairs of differential switches together form a differential four-switch structure and work with the load to convert the current signal into a differential voltage signal.

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