Signal verification method, device and equipment performed by electronic device and medium

Abstract

This disclosure provides a signal verification method, apparatus, device, and medium performed by an electronic device, which can be applied to the field of communication technology. The method includes: reading an original codeword set from a register; performing K partial verifications based on the original codeword set to obtain a signal verification result; wherein the k-th partial verification process includes: performing a quasi-cyclic shift on the (k-1)-th updated codeword set to obtain an extended updated codeword set, and constructing an extended updated codeword matrix based on the extended updated codeword set; extracting random rows and columns from the extended updated codeword matrix to obtain a shortened codeword matrix; performing a Gaussian row transform on the shortened codeword matrix to obtain a sampling verification matrix, and extracting low code weight vectors from the sampling verification matrix; constructing a k-th partial decoding matrix related to the k-th partial verification based on a sparse vector set; and using the k-th partial decoding matrix to perform partial verification on the (k-1)-th updated codeword set to obtain the k-th updated codeword set.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and more specifically to a signal verification method, apparatus, device, and medium performed by an electronic device. Background Technology

[0002] Wireless communication systems typically use channel coding techniques to correct errors that may occur during data transmission. Traditional signal verification methods for non-cooperative parties generally require receiving a large number of codewords to crack the corresponding parity-check matrix using Gaussian elimination. However, this method is quite sensitive to channel errors. Since channel errors gradually accumulate during Gaussian elimination, traditional signal verification methods cannot crack the parity-check matrix under conditions of high channel error. Summary of the Invention

[0003] In view of the above problems, this disclosure provides a method, apparatus, device and medium for signal verification performed by an electronic device.

[0004] According to a first aspect of this disclosure, a signal verification method performed by an electronic device is provided, comprising: in response to receiving a communication signal transmitted by a transmitter, storing an original codeword set included in the communication signal into a register; reading the original codeword set from the register, and performing K partial verifications based on the original codeword set to obtain a signal verification result, wherein the process of the k-th partial verification includes: performing a quasi-cyclic shift on the (k-1)-th updated codeword set to obtain an extended updated codeword set, and constructing an extended updated codeword matrix based on the extended updated codeword set, wherein the (k-1)-th updated... The codeword set is obtained based on the (k-1)th partial check; random rows and columns are extracted from the above extended and updated codeword matrix to obtain a shortened codeword matrix; a Gaussian row transformation is performed on the above shortened codeword matrix to obtain the extracted check matrix, and low code weight vectors are extracted from the above extracted check matrix to obtain a sparse vector set; based on the above sparse vector set, a k-th partial decoding matrix related to the k-th partial check is constructed; if the above k-th partial decoding matrix does not meet the preset conditions, the above k-th partial decoding matrix is ​​used to perform partial check on the above (k-1)th updated codeword set to obtain the k-th updated codeword set.

[0005] According to embodiments of this disclosure, the communication signal includes at least one of the following: an audio signal and an image signal.

[0006] According to an embodiment of this disclosure, the above-mentioned determination of low-key vectors from the above-mentioned extraction verification matrix to obtain a sparse vector set includes: performing Q-time low-key vector filtering based on the above-mentioned extraction verification matrix to obtain the above-mentioned sparse vector set, wherein the process of determining the q-th low-key vector includes: extracting any two row vectors from the above-mentioned (q-1)-th extraction verification matrix and performing a bitwise XOR operation on the above-mentioned two row vectors to obtain a target vector, wherein the above-mentioned (q-1)-th extraction verification matrix is ​​obtained based on the (q-1)-th low-key vector filtering; if the number of preset elements in the above-mentioned target vector is less than or equal to a preset threshold, and the above-mentioned sparse vector set does not include the above-mentioned target vector, adding the above-mentioned target vector to the above-mentioned sparse vector set; and swapping any two columns in the above-mentioned (q-1)-th extraction verification matrix to obtain the q-th extraction verification matrix.

[0007] According to an embodiment of this disclosure, the original codeword set includes M codewords, the codeword length of the codewords is N, and the construction of the k-th partial decoding matrix based on the sparse vector set includes: when the length of the sparse vector set is less than N, deduplication is performed on the sparse vector set to obtain the partial decoding matrix.

[0008] According to an embodiment of this disclosure, the method further includes: when the length of the sparse vector set is equal to N, performing a quasi-cyclic shift on the sparse vectors to obtain a candidate partial decoding matrix; and performing a deduplication operation on the candidate partial decoding matrix to obtain the partial decoding matrix.

[0009] According to an embodiment of this disclosure, the method further includes: when the length of the sparse vector set is equal to N, performing a quasi-cyclic shift on the sparse vectors to obtain a candidate partial decoding matrix; and performing a deduplication operation on the candidate partial decoding matrix to obtain the partial decoding matrix.

[0010] According to an embodiment of this disclosure, the above-mentioned Gaussian row transformation of the shortened codeword matrix to obtain the decimation check matrix includes: performing Gaussian elimination on the shortened codeword matrix in the row direction to obtain the decimation matrix; and performing a canonical form transformation on the decimation matrix to obtain the decimation check matrix.

[0011] A second aspect of this disclosure provides a signal verification apparatus, comprising: a storage module, configured to, in response to receiving a communication signal transmitted by a transmitter, store an original codeword set included in the communication signal into a register; and a verification module, configured to read the original codeword set from the register and perform K partial verifications based on the original codeword set to obtain a signal verification result, wherein the k-th partial verification process includes: a shift module, configured to perform a quasi-cyclic shift on the (k-1)-th updated codeword set to obtain an extended updated codeword set, and construct an extended updated codeword matrix based on the extended updated codeword set, wherein the (k-1)-th updated codeword set is a base... The codeword set is obtained from the (k-1)th partial verification. The extraction module is used to extract random rows and columns from the extended update codeword matrix to obtain a shortened codeword matrix. The transformation module performs a Gaussian row transformation on the shortened codeword matrix to obtain an extraction verification matrix, and extracts low-weight vectors from the extraction verification matrix to obtain a sparse vector set. The construction module constructs a k-th partial decoding matrix related to the k-th partial verification based on the sparse vector set. If the k-th partial decoding matrix does not meet preset conditions, it uses the k-th partial decoding matrix to perform partial verification on the (k-1)th updated codeword set to obtain the k-th updated codeword set.

[0012] A third aspect of this disclosure provides an electronic device comprising: one or more processors; and a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the method described above.

[0013] A fourth aspect of this disclosure also provides a computer-readable storage medium having a computer program or instructions stored thereon, which, when executed by a processor, implement the steps of the above-described method.

[0014] The fifth aspect of this disclosure also provides a computer program product, including a computer program or instructions that, when executed by a processor, implement the steps of the above-described method.

[0015] According to embodiments of this disclosure, new codewords are obtained by performing a quasi-cyclic shift on the received original codeword set, thereby expanding the original codeword set. This allows non-cooperative receivers to crack the parity check matrix even with a small number of original codewords. Furthermore, random row and column sampling is performed on the expanded and updated codeword set after the quasi-cyclic shift, and a low-code-weight vector search is conducted within the randomly sampled shortened codeword matrix. This constructs a partial decoding matrix to partially verify the updated codeword set. Since erroneous codewords are sparsely and randomly distributed in the original codeword set, in a single... The probability of selecting a large number of erroneous codewords during partial verification is reduced. Even if erroneous codewords are randomly selected during the process, the corresponding verification matrix is ​​difficult to meet the requirements of low code weight vectors because the erroneous codewords remain sparse in the shortened codeword matrix. Therefore, it is difficult for them to enter the partial decoding matrix, thus avoiding the accumulation of erroneous codewords. This allows the recovery of the verification matrix even under conditions of high channel bit error rate. At the same time, since the sparse vector set only contains a small number of non-zero elements, the processor can quickly calculate the sparse vector set and construct the partial decoding matrix, thereby reducing the pressure on hardware processing. Attached Figure Description

[0016] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0017] Figure 1 This illustration schematically depicts an application scenario of a signal verification device performed by an electronic device according to an embodiment of the present disclosure.

[0018] Figure 2 A flowchart illustrating a signal verification method performed by an electronic device according to an embodiment of the present disclosure is shown schematically.

[0019] Figure 3 The illustration shows a schematic diagram of quasi-cyclic shifting of codeword ci according to an embodiment of the present disclosure;

[0020] Figure 4 A schematic block diagram of a signal verification apparatus according to an embodiment of the present disclosure is shown.

[0021] Figure 5 A block diagram schematically illustrates an electronic device suitable for implementing a signal verification method performed by an electronic device, according to an embodiment of the present disclosure. Detailed Implementation

[0022] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0024] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0025] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0026] Wireless communication systems typically use channel coding techniques to correct errors that may occur during data transmission. Common channel coding methods include BCH codes, RM codes, RS codes, quasi-cyclic QC-LDPC codes (Quasi-Cyclic Low-Density Parity-Check codes), and polar codes. Among these, quasi-cyclic LDPC codes are widely used in various wireless communication standards due to their excellent error correction performance and low hardware implementation complexity, including DVB-S2 (Digital Video Broadcasting - Satellite - Second Generation), CCSDS (Consultative Committee for Space Data System), and fifth-generation mobile communication standards. In these wireless communication systems using quasi-cyclic LDPC codes, cooperative receivers can obtain the decoding matrix of the quasi-cyclic LDPC codes used in transmission in advance and then use the decoding matrix to complete the decoding at the receiving end. In scenarios such as non-cooperative communication and sensing radio communication, non-cooperative receivers cannot obtain the decoding matrix used in the transmission in advance. They can only use the received codewords to first identify the decoding matrix and then use the decoding matrix to decode the received data.

[0027] Traditional quasi-cyclic LDPC code recognition techniques can be mainly divided into the following two categories: (1) Quasi-cyclic LDPC code recognition method based on closed sets. This method assumes that the non-cooperative receiver knows a set consisting of several LDPC code parity check matrices, which is called the LDPC code closed set. The LDPC code parity check matrix to be identified is a matrix in this closed set, and the non-cooperative receiver only needs to determine which matrix in this closed set the LDPC code parity check matrix to be identified is. (2) Quasi-cyclic LDPC code recognition method based on open sets. This method assumes that the non-cooperative receiver cannot obtain information related to the closed set and needs to recover the parity check matrix from scratch. Usually, Gaussian elimination is used to perform row and column transformations on the received codeword matrix, and then the low-weight linear combination is found.

[0028] For the first type of method, since it assumes that non-cooperative receivers can obtain the closed set of LDPC codes, its application scenarios are very limited. Especially in scenarios such as non-cooperative reception, the information of the closed set of LDPC codes is usually unknown, so it is impossible to use this method to crack the parity check matrix. For the second type of method, its disadvantages are: (1) It is sensitive to channel errors. Since channel errors gradually accumulate during Gaussian elimination, the open set quasi-cyclic LDPC code identification method based on Gaussian elimination cannot crack the parity check matrix H under the condition of high channel error; (2) It requires a large number of received codewords. In non-cooperative communication scenarios, the number of received codewords is often very limited, so it cannot meet the prerequisite for the application of this method. Therefore, neither of the above two methods can properly realize the identification of the quasi-cyclic LDPC code parity check matrix, which is difficult to meet the needs of non-cooperative communication.

[0029] In view of this, embodiments of this disclosure provide a signal verification method performed by an electronic device, comprising: in response to receiving a communication signal transmitted by a transmitter, storing the original codeword set included in the communication signal into a register; reading the original codeword set from the register, and performing K partial verifications based on the original codeword set to obtain a signal verification result, wherein the process of the k-th partial verification includes: performing a quasi-cyclic shift on the (k-1)-th updated codeword set to obtain an extended updated codeword set, and constructing an extended updated codeword matrix based on the extended updated codeword set, wherein the (k-1)-th updated codeword set... The new codeword set is obtained based on the (k-1)th partial check; random rows and columns are extracted from the extended update codeword matrix to obtain the shortened codeword matrix; a Gaussian row transformation is performed on the shortened codeword matrix to obtain the extracted check matrix, and low code weight vectors are extracted from the extracted check matrix to obtain a sparse vector set; based on the sparse vector set, a k-th partial decoding matrix related to the k-th partial check is constructed. If the k-th partial decoding matrix does not meet the preset conditions, the k-th partial decoding matrix is ​​used to perform partial check on the (k-1)th updated codeword set to obtain the k-th updated codeword set.

[0030] Figure 1 The illustration schematically depicts an application scenario of a signal verification device performed by an electronic device according to an embodiment of the present disclosure.

[0031] like Figure 1 As shown, application scenario 100 according to this embodiment may include a first terminal device 101, a second terminal device 102, a third terminal device 103, a network 104, and a server 105. The network 104 serves as a medium for providing a communication link between the first terminal device 101, the second terminal device 102, the third terminal device 103, and the server 105. The network 104 may include various connection types, such as wired or wireless communication links, or fiber optic cables, etc.

[0032] Users can use the first terminal device 101, the second terminal device 102, and the third terminal device 103 to interact with the server 105 via the network 104 to receive or send messages, etc. Various communication client applications can be installed on the first terminal device 101, the second terminal device 102, and the third terminal device 103, such as shopping applications, web browser applications, search applications, instant messaging tools, email clients, social media platform software, etc. (for example only).

[0033] The first terminal device 101, the second terminal device 102, and the third terminal device 103 can be various electronic devices with displays and support web browsing, including but not limited to smartphones, tablets, laptops, and desktop computers.

[0034] Server 105 can be a server that provides various services, such as a backend management server that supports websites browsed by users using the first terminal device 101, the second terminal device 102, and the third terminal device 103 (this is just an example). The backend management server can analyze and process data such as received user requests, and feed back the processing results (such as web pages, information, or data obtained or generated according to user requests) to the terminal devices.

[0035] It should be noted that the signal verification method performed by the electronic device provided in this embodiment can generally be executed by the server 105. Correspondingly, the signal verification device provided in this embodiment can generally be located in the server 105. The signal verification method performed by the electronic device provided in this embodiment can also be executed by a server or server cluster that is different from the server 105 and capable of communicating with the first terminal device 101, the second terminal device 102, the third terminal device 103, and / or the server 105. Correspondingly, the signal verification device provided in this embodiment can also be located in a server or server cluster that is different from the server 105 and capable of communicating with the first terminal device 101, the second terminal device 102, the third terminal device 103, and / or the server 105.

[0036] It should be understood that Figure 1 The number of terminal devices, networks, and servers shown is merely illustrative. Depending on implementation needs, any number of terminal devices, networks, and servers can be included.

[0037] The following will be based on Figure 1 The described scene, through Figures 2-3 The signal verification method performed by an electronic device according to the disclosed embodiments will be described in detail.

[0038] Figure 2 A flowchart illustrating a signal verification method performed by an electronic device according to an embodiment of the present disclosure is shown schematically.

[0039] like Figure 2 As shown, the signal verification method performed by the electronic device in this embodiment includes operations S210 to S220.

[0040] In operation S210, in response to receiving a communication signal sent by the transmitting end, the set of original codewords included in the communication signal is stored in a register.

[0041] According to embodiments of this disclosure, the aforementioned original codeword set can be represented as follows: Where M represents the number of codewords, and the parameters of the original codewords combined with the corresponding parity check matrix are (N, k', q'), where N is the code length corresponding to the original codeword set, k' is the length of the information bits in the original codeword set (i.e., QC-LDPC code), and q' is the cyclic block size of the original codeword set. M, N, k', and q' are all positive integers.

[0042] In operation S220, the original codeword set is read from the register, and K partial checks are performed based on the original codeword set to obtain the signal check result.

[0043] The process of the kth partial verification includes operations S221 to S224.

[0044] In operation S221, the (k-1)th update codeword set is quasi-cyclically shifted to obtain an extended update codeword set, and an extended update codeword matrix is ​​constructed based on the extended update codeword set.

[0045] The k-1th updated codeword set is obtained based on the k-1th partial verification.

[0046] According to embodiments of this disclosure, for each codeword Perform a quasi-cyclic shift, where, Let j be a positive integer, taking the value 0 or 1. It can be used to encode characters c. i Perform sequentially with lengths of The quasi-cyclic shift operation yields the extended update codeword. Where p is a positive integer, , For typing The new codeword obtained after performing a quasi-cyclic shift operation of length p. ,in = mod() is the modulo operation, which yields the expanded and updated codeword set.

[0047] Furthermore, for the extended update codeword set, the extended update codeword matrix can be constructed according to the following equation (1).

[0048] (1)

[0049] in, This represents the extended update codeword matrix (size (Mq') × N), where M represents the number of codewords, i represents the i-th codeword, p represents the quasi-circular shift length, N is the codeword length corresponding to the original codeword set, and q' is the circular block size of the original codeword set.

[0050] Figure 3 This illustration schematically shows the codeword c according to an embodiment of the present disclosure. i A schematic diagram of a quasi-cyclic shift.

[0051] like Figure 3 As shown, codeword c i Composed of a series of code elements Composed of, where j represents the position of the symbol in the codeword, j is greater than or equal to 1 and less than or equal to N. When codeword c i When shifting 1 bit to the right in a quasi-cyclic shift, each symbol Move one position to the right, the rightmost symbol It was moved to the leftmost position. (When the character 'c' is typed...) i When shifting right by quasi-circular shift q'-1 bits (q' is the size of the circular block), each symbol Shift q'-1 bits to the right, so that the rightmost symbol becomes .

[0052] In operation S222, random rows and columns are extracted from the extended update codeword matrix to obtain the shortened codeword matrix.

[0053] According to embodiments of this disclosure, the initial number of row extractions can be set. Initial number of draws for column Then update the codeword matrix from the extended version. Random selection Action and Columns form a shortened codeword matrix .

[0054] In operation S223, a Gaussian row transform is performed on the shortened codeword matrix to obtain a decimation check matrix, and low code weight vectors are extracted from the decimation check matrix to obtain a sparse vector set.

[0055] The Gaussian row transform is a method in linear algebra used to convert a matrix into row echelon form. The parity check matrix is ​​used to verify the correctness of the transmitted original codeword; it contains crucial information for error detection and correction. Low codeweight vectors are vectors with fewer non-zero elements. A sparse vector set is a collection of vectors where most elements are zero, with only a few non-zero elements. Sparse vector sets can reduce the complexity of encoding and decoding while maintaining sufficient redundancy to correct potential errors.

[0056] In operation S224, a k-th partial decoding matrix related to the k-th partial verification is constructed based on the sparse vector set. If the k-th partial decoding matrix does not meet the preset conditions, the k-th partial decoding matrix is ​​used to perform partial verification on the (k-1)-th updated codeword set to obtain the k-th updated codeword set.

[0057] According to embodiments of this disclosure, a sparse vector set can be used... Construct the k-th partial decoding matrix This allows for the decoding of the (k-1)th updated codeword set, correcting transmission errors and obtaining the kth updated codeword set. .

[0058] According to embodiments of this disclosure, new codewords are obtained by performing a quasi-cyclic shift on the received original codeword set, thereby expanding the original codeword set. This allows non-cooperative receivers to crack the parity check matrix even with a small number of original codewords. Furthermore, random row and column sampling is performed on the expanded and updated codeword set after the quasi-cyclic shift, and a low-code-weight vector search is conducted within the randomly sampled shortened codeword matrix. This constructs a partial decoding matrix to partially verify the updated codeword set. Since erroneous codewords are sparsely and randomly distributed in the original codeword set, in a single... The probability of selecting a large number of erroneous codewords during partial verification is reduced. Even if erroneous codewords are randomly selected during the process, the corresponding verification matrix is ​​difficult to meet the requirements of low code weight vectors because the erroneous codewords remain sparse in the shortened codeword matrix. Therefore, it is difficult for them to enter the partial decoding matrix, thus avoiding the accumulation of erroneous codewords. This allows the recovery of the verification matrix even under conditions of high channel bit error rate. At the same time, since the sparse vector set only contains a small number of non-zero elements, the processor can quickly calculate the sparse vector set and construct the partial decoding matrix, thereby reducing the pressure on hardware processing.

[0059] According to embodiments of this disclosure, the communication signal includes at least one of the following: an audio signal and an image signal.

[0060] Communication signals can be used to transmit different types of data, such as sound data, image data, and location data, and this disclosure is not limited thereto. Sound signals generally refer to audio signals, which can be speech, music, or other audio data. In communication systems, sound signals can be encoded, transmitted, and decoded to reproduce the original sound at the receiving end. Image signals can be still images (such as photographs) or moving images (such as videos). Image signals typically require compression and encoding to reduce the data size, making them suitable for transmission within limited bandwidth. Location signals are generally related to determining the geographical location of a device or object. In communication systems, location signals can be used to provide positioning services, such as GPS signals. These signals can be used for applications such as navigation, tracking, and geotagging, and can also be combined with other types of signals (such as sound or images) to provide context or enhance real-world interactive experiences.

[0061] According to an embodiment of this disclosure, the above-mentioned determination of low-key vectors from the extraction check matrix to obtain a sparse vector set includes: performing Q-fold low-key vector filtering based on the extraction check matrix to obtain a sparse vector set, wherein the process of determining the q-th low-key vector includes: extracting any two row vectors from the (q-1)-th extraction check matrix and performing a bitwise XOR operation on the two row vectors to obtain a target vector, wherein the (q-1)-th extraction check matrix is ​​obtained based on the (q-1)-th low-key vector filtering; if the number of preset elements in the target vector is less than or equal to a preset threshold and the sparse vector set does not include the target vector, adding the target vector to the sparse vector set; swapping any two columns in the (q-1)-th extraction check matrix to obtain the q-th swap matrix, and performing Gaussian elimination on the q-th swap matrix to obtain the q-th extraction check matrix.

[0062] According to embodiments of this disclosure, for extracting the verification matrix Any two row vectors in and The target vector is obtained by calculating the vector sum (i.e., bitwise XOR operation) of the two row vectors mentioned above. =mod( + ,2), the sparse vector set does not include the target vector, and the target vector If the number of elements (preset elements) is less than the preset threshold w, the target vector can be... Add to sparse vector set In the middle. After each search, the extraction verification matrix is ​​swapped. Given any two columns, we obtain the q-th exchange matrix. Furthermore, Gaussian elimination is performed on the q-th exchange matrix along the row direction to obtain the matrix in standard form. The aforementioned matrix is ​​then used as the verification matrix for the qth extraction to initiate a new round of searching, until the maximum number of searches is reached. .

[0063] According to embodiments of this disclosure, the target vector is obtained by performing a bitwise XOR operation in parallel by the processor, which allows for rapid filtering. Furthermore, after judging the target vector and the sparse vector set, the target vector that meets the conditions is added to the sparse vector set to ensure that the sparse vector set does not contain redundant or highly complex vectors. At the same time, the processor continuously updates the sparse vector set by iteratively executing XOR, threshold judgment, column swapping and Gaussian elimination operations, so that it has verification capability while maintaining low density, thereby supporting accurate recovery of the parity check matrix under high error channel conditions.

[0064] According to an embodiment of this disclosure, the original codeword set includes M codewords, and the codeword length is N. The k-th partial decoding matrix is ​​constructed based on the sparse vector set, including: when the length of the sparse vector set is less than N, deduplication is performed on the sparse vector set to obtain the partial decoding matrix.

[0065] According to embodiments of this disclosure, when the length of the sparse vector set is less than N, the sparse vectors can be used as a partial decoding matrix. The row vectors in the matrix are then deduplicated to obtain a partial decoding matrix.

[0066] According to embodiments of this disclosure, by leveraging the processor's parallel shifting and fast comparison capabilities, and while maintaining the verification relationship, the sparse vector set is deduplicated to achieve maximum set diversity with minimal storage capacity. This improves the robustness and computational efficiency of subsequent decoding and further reduces hardware resource consumption.

[0067] According to an embodiment of this disclosure, the method further includes: when the length of the sparse vector set is equal to N, performing a quasi-cyclic shift on the sparse vectors to obtain a candidate partial decoding matrix; and performing a deduplication operation on the candidate partial decoding matrix to obtain a partial decoding matrix.

[0068] According to embodiments of this disclosure, when the length of the sparse vector set is equal to N, each sparse vector in the sparse vector set can be sequentially divided into segments of length N. The quasi-circular shift uses the original vector and the quasi-circular shifted vector as part of the decoding matrix. The row vectors in the matrix are then deduplicated to obtain a partial decoding matrix.

[0069] According to embodiments of this disclosure, the aforementioned preset conditions include: the size of a portion of the decoding matrix is ​​equal to M×N.

[0070] According to an embodiment of this disclosure, the above-mentioned Gaussian row transformation of the shortened codeword matrix to obtain the decimation check matrix includes: performing Gaussian elimination on the shortened codeword matrix in the row direction to obtain the decimation matrix; and performing a canonical form transformation on the decimation matrix to obtain the decimation check matrix.

[0071] According to embodiments of this disclosure, the shortened codeword matrix can be... Gaussian elimination is performed in the row direction to obtain a shortened codeword matrix in standard form. , where the matrix for * identity matrix, matrix for *( - The dense matrix is ​​then used to obtain the standard form of the decimation check matrix based on the relationship between the check matrix and the generator matrix in channel coding theory. ; where, matrix for * identity matrix, matrix For matrix The transpose of .

[0072] The signal verification method performed by an electronic device according to this disclosure will be further described below through an embodiment.

[0073] In one embodiment of this disclosure, it is assumed that the received original codeword set includes 12 codewords (i.e., M=12 in the above text), and the parity check matrix parameters (N,k',q') defined in the IEEE 802.11n standard are (1296, 648, 54), and the initial number of row extractions is... Set to 100, initial number of draws for the column. Set to 648.

[0074] At the receiving end, for each codeword in the received raw codeword set, the non-cooperative receiver... Perform sequentially with lengths of Quasi-cyclic shifting yields the extended update codeword set.

[0075] Where i = 1, 2, ..., 12, Secondly, at the receiving end, the codeword set is updated based on the extended version. Construct an extended update codeword matrix

[0076]

[0077] , where the matrix The size is 648×1296, and 100 rows and 648 columns are randomly selected from the extended update codeword matrix to form a shortened codeword matrix. Then, Gaussian elimination is performed on the shortened codeword matrix in the row direction to obtain the standard shortened codeword matrix. , where the matrix The matrix is ​​a 100x100 identity matrix. This is a dense matrix of size 100*548. Then, based on the relationship between the parity-check matrix and the generator matrix in channel coding theory, the standard form of the decimation parity-check matrix is ​​obtained. , where the matrix The matrix is ​​an identity matrix of size 548*548. For matrix The transpose of . Further, from the extracted verification matrix Search for low-key heavy vectors in the middle to obtain a sparse vector set. After obtaining the sparse vector set During the process, the code length N of the codeword can be used as a criterion. That is, when the length of the sparse vector set is less than 1296, the sparse vector set can be directly deduplicated, and a partial decoding matrix can be constructed based on the deduplicated coefficient vector set. When the sparse vector length is equal to 1296, each coefficient vector in the sparse vector set is sequentially divided into sets of length N. The quasi-cyclic shift and deduplication are performed to obtain a partial decoding matrix. Finally, if the size of the partial decoding matrix is ​​less than 648*1296, the partial decoding matrix is ​​used to decode the (k-1)th updated codeword set until the size of the partial decoding matrix is ​​equal to 648*1296. The partial decoding matrix obtained at this point is the final recovered decoding matrix, and the decryption process ends.

[0078] Table 1 below shows the verification effect of the signal verification method performed by an electronic device according to an embodiment of the present disclosure.

[0079] Table 1

[0080]

[0081] It can be seen that for different preset BCS channel cross frequencies, even at the disclosed cross frequency (5e-6, five parts per million), the success rate of the parity check matrix can still reach 100%, which shows that the signal verification performed by the electronic device in the embodiments of this disclosure has good error correction capability under these channel conditions.

[0082] Based on the signal verification method performed by the electronic device described above, this disclosure also provides a signal verification apparatus. The following will be combined with... Figure 4 The device is described in detail.

[0083] Figure 4 A schematic block diagram of a signal verification apparatus according to an embodiment of the present disclosure is shown.

[0084] like Figure 4 As shown, the signal verification device 400 in this embodiment includes a storage module 410 and a verification module 420.

[0085] The storage module 410 is used to store the set of original codewords included in the communication signal into a register in response to receiving the communication signal sent by the transmitting end. In one embodiment, the storage module 410 can be used to perform the operation S210 described above, which will not be repeated here.

[0086] The verification module 420 is used to read the original codeword set from the register and perform K partial verifications based on the original codeword set to obtain the signal verification result. In one embodiment, the verification module 420 can be used to perform the operation S220 described above, which will not be repeated here.

[0087] The verification module 420 includes a shift submodule 421, an extraction submodule 422, a transformation submodule 423, and a construction submodule 424.

[0088] The shift submodule 421 is used to perform a quasi-cyclic shift on the (k-1)th updated codeword set to obtain an extended updated codeword set, and to construct an extended updated codeword matrix based on the extended updated codeword set, wherein the (k-1)th updated codeword set is obtained based on the (k-1)th partial check. In one embodiment, the shift submodule 421 can be used to perform the operation S221 described above, which will not be repeated here.

[0089] The extraction submodule 422 is used to extract random rows and columns from the extended update codeword matrix to obtain a shortened codeword matrix. In one embodiment, the extraction submodule 422 can be used to perform the operation S222 described above, which will not be repeated here.

[0090] The transformation submodule 423 is used to perform a Gaussian row transform on the shortened codeword matrix to obtain a parity-check matrix, and to extract low code weight vectors from the parity-check matrix to obtain a sparse vector set. In one embodiment, the transformation submodule 423 can be used to perform the operation S223 described above, which will not be repeated here.

[0091] The construction module 424 is used to construct the k-th partial decoding matrix related to the k-th partial verification based on the sparse vector set. If the k-th partial decoding matrix does not meet the preset conditions, the k-th partial decoding matrix is ​​used to perform partial verification on the (k-1)-th updated codeword set to obtain the k-th updated codeword set. In one embodiment, the construction module 424 can be used to execute the operation S224 described above, which will not be repeated here.

[0092] According to embodiments of this disclosure, the transformation submodule 423 includes:

[0093] The XOR unit is used to extract any two row vectors from the (q-1)th extraction check matrix and perform a bitwise XOR operation on the two row vectors to obtain the target vector. The (q-1)th extraction check matrix is ​​obtained based on the (q-1)th low code heavy vector filtering.

[0094] The addition unit is used to add the target vector to the sparse vector set when the number of preset elements in the target vector is less than or equal to a preset threshold and the target vector is not included in the sparse vector set.

[0095] The swapping unit is used to swap any two columns in the (q-1)th extraction verification matrix to obtain the qth swapping matrix, and then perform Gaussian elimination on the qth swapping matrix to obtain the qth extraction verification matrix.

[0096] According to an embodiment of this disclosure, the original codeword set includes M codewords, the codeword length of which is N. The construction module 424 includes: a first deduplication unit, used to deduplicatize the sparse vector set when the length of the sparse vector set is less than N, to obtain a partial decoding matrix.

[0097] According to an embodiment of this disclosure, the apparatus further includes: a shifting unit, configured to perform quasi-cyclic shifting on sparse vectors when the length of the sparse vector set is equal to N, to obtain a candidate partial decoding matrix; and a second deduplication unit, configured to perform deduplication operation on the candidate partial decoding matrix to obtain a partial decoding matrix.

[0098] According to an embodiment of this disclosure, the transformation submodule 423 further includes: an elimination unit for performing Gaussian elimination on the shortened codeword matrix in the row direction to obtain a decimation matrix; and a standard transformation unit for performing a standard form transformation on the decimation matrix to obtain a decimation check matrix.

[0099] According to embodiments of this disclosure, any plurality of modules in storage module 410 and verification module 420 may be combined into one module, or any one of these modules may be split into multiple modules. Alternatively, at least a portion of the functionality of one or more of these modules may be combined with at least a portion of the functionality of other modules and implemented in one module. According to embodiments of this disclosure, at least one of storage module 410 and verification module 420 may be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or any other reasonable means of integrating or packaging circuitry, or implemented in software, hardware, or firmware, or in any appropriate combination of any of these three implementation methods. Alternatively, at least one of storage module 410 and verification module 420 may be at least partially implemented as a computer program module, which, when run, can perform corresponding functions.

[0100] Figure 5 A block diagram schematically illustrates an electronic device suitable for implementing a signal verification method performed by an electronic device, according to an embodiment of the present disclosure.

[0101] like Figure 5 As shown, an electronic device 500 according to an embodiment of the present disclosure includes a processor 501, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 502 or a program loaded from a storage portion 508 into a random access memory (RAM) 503. The processor 501 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 501 may also include onboard memory for caching purposes. The processor 501 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present disclosure.

[0102] RAM 503 stores various programs and data required for the operation of electronic device 500. Processor 501, ROM 502, and RAM 503 are interconnected via bus 504. Processor 501 performs various operations of the method flow according to embodiments of the present disclosure by executing programs in ROM 502 and / or RAM 503. It should be noted that the programs may also be stored in one or more memories other than ROM 502 and RAM 503. Processor 501 may also perform various operations of the method flow according to embodiments of the present disclosure by executing programs stored in said one or more memories.

[0103] According to embodiments of this disclosure, the electronic device 500 may further include an input / output (I / O) interface 505, which is also connected to a bus 504. The electronic device 500 may also include one or more of the following components connected to the input / output (I / O) interface 505: an input section 506 including a keyboard, mouse, etc.; an output section 507 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 508 including a hard disk, etc.; and a communication section 509 including a network interface card such as a LAN card, modem, etc. The communication section 509 performs communication processing via a network such as the Internet. A drive 510 is also connected to the input / output (I / O) interface 505 as needed. A removable medium 511, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 510 as needed so that computer programs read from it can be installed into the storage section 508 as needed.

[0104] This disclosure also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs that, when executed, implement the method according to the embodiments of this disclosure.

[0105] According to embodiments of this disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of this disclosure, the computer-readable storage medium may include ROM 502 and / or RAM 503 and / or one or more memories other than ROM 502 and RAM 503 described above.

[0106] Embodiments of this disclosure also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code enables the computer system to implement the signal verification method performed by an electronic device as provided in embodiments of this disclosure.

[0107] When the computer program is executed by the processor 501, it performs the functions defined in the system / apparatus of this disclosure embodiments. According to embodiments of this disclosure, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0108] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and may be downloaded and installed via the communication section 509, and / or installed from a removable medium 511. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0109] In such an embodiment, the computer program can be downloaded and installed from a network via communication section 509, and / or installed from removable medium 511. When the computer program is executed by processor 501, it performs the functions defined in the system of this disclosure embodiment. According to embodiments of this disclosure, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0110] According to embodiments of this disclosure, program code for executing the computer programs provided in embodiments of this disclosure can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can execute entirely on a user's computing device, partially on a user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0111] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0112] Those skilled in the art will understand that the features described in the various embodiments of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0113] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A signal verification method performed by an electronic device, characterized in that, The method includes performing the following operations using a processor in the electronic device: In response to receiving a communication signal sent by the transmitting end, the set of original codewords included in the communication signal is stored in a register; The original codeword set is read from the register, and K partial checks are performed based on the original codeword set to obtain the signal check result. The process of the kth partial check includes: The (k-1)th update codeword set is quasi-cyclically shifted to obtain an extended update codeword set, and an extended update codeword matrix is ​​constructed based on the extended update codeword set, wherein the (k-1)th update codeword set is obtained based on the (k-1)th partial check. Random rows and columns are extracted from the extended update codeword matrix to obtain the shortened codeword matrix; A Gaussian row transform is performed on the shortened codeword matrix to obtain a decimation check matrix, and low code weight vectors are extracted from the decimation check matrix to obtain a sparse vector set. Based on the sparse vector set, construct the kth partial decoding matrix related to the kth partial verification. If the kth partial decoding matrix does not meet the preset conditions, use the kth partial decoding matrix to perform partial verification on the (k-1)th updated codeword set to obtain the kth updated codeword set.

2. The method according to claim 1, characterized in that, The communication signal includes at least one of the following: sound signal and image signal.

3. The method according to claim 1, characterized in that, The step of determining low code weight vectors from the extracted verification matrix to obtain a sparse vector set includes: Based on the extracted verification matrix, Q low-key heavy vector filtering is performed to obtain the sparse vector set, wherein the process of determining the q-th low-key heavy vector includes: Extract any two row vectors from the (q-1)th extraction verification matrix and perform a bitwise XOR operation on the two row vectors to obtain the target vector. The (q-1)th extraction verification matrix is ​​obtained based on the (q-1)th low code heavy vector filtering. If the number of preset elements in the target vector is less than or equal to a preset threshold, and the target vector is not included in the sparse vector set, then the target vector is added to the sparse vector set. Swap any two columns in the (q-1)th extraction verification matrix to obtain the qth swap matrix, and perform Gaussian elimination on the qth swap matrix to obtain the qth extraction verification matrix.

4. The method according to claim 1, characterized in that, The original codeword set includes M codewords, each codeword having a codeword length of N. The construction of the k-th partial decoding matrix based on the sparse vector set includes: If the length of the sparse vector set is less than N, the sparse vector set is deduplicated to obtain the partial decoding matrix.

5. The method according to claim 4, characterized in that, The method further includes: When the length of the sparse vector set is equal to N, the sparse vectors are quasi-cyclically shifted to obtain the candidate partial decoding matrix; The candidate partial decoding matrix is ​​deduplicated to obtain the partial decoding matrix.

6. The method according to claim 5, characterized in that, The preset conditions include: The size of the partial decoding matrix is ​​equal to M×N.

7. The method according to claim 1, characterized in that, The step of performing a Gaussian row transform on the shortened codeword matrix to obtain the extraction parity matrix includes: Gaussian elimination is performed on the shortened codeword matrix in the row direction to obtain the extraction matrix; The extraction matrix is ​​transformed into its standard form to obtain the extraction verification matrix.

8. A signal verification device, characterized in that, The device includes: A storage module is used to store the set of original codewords included in the communication signal into a register in response to receiving a communication signal sent by the transmitting end; A verification module is used to read the original codeword set from the register and perform K partial verifications based on the original codeword set to obtain the signal verification result. The verification module includes: The shift submodule is used to perform quasi-cyclic shift on the (k-1)th update codeword set to obtain an extended update codeword set, and to construct an extended update codeword matrix based on the extended update codeword set, wherein the (k-1)th update codeword set is obtained based on the (k-1)th partial check. The extraction submodule is used to extract random rows and columns from the extended and updated codeword matrix to obtain a shortened codeword matrix. The transformation submodule is used to perform a Gaussian row transformation on the shortened codeword matrix to obtain a decimation check matrix, and to extract low code weight vectors from the decimation check matrix to obtain a sparse vector set. A construction submodule is used to construct a k-th partial decoding matrix related to the k-th partial verification based on the sparse vector set. If the k-th partial decoding matrix does not meet the preset conditions, the k-th partial decoding matrix is ​​used to perform partial verification on the (k-1)-th updated codeword set to obtain the k-th updated codeword set.

9. An electronic device, comprising: One or more processors; Memory, used to store one or more computer programs. The characteristic feature is that the one or more processors execute the one or more computer programs to implement the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program or instructions stored thereon, characterized in that, When the computer program or instructions are executed by a processor, they implement the steps of the method according to any one of claims 1 to 7.

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