LDPC high-speed coding device based on CCSDS deep space communication standard

Abstract

The application discloses a kind of LDPC high-speed coding device based on CCSDS deep space communication standard, it is related to communication coding field.It is by data buffer, data shunt, LDPC information bit serial memory, LDPC information bit block parallel memory, cyclic shift register, LDPC check bit generator, check bit storage and bit sequence adjuster, data output selector and so on module composition.The application utilizes the cyclic characteristic of LDPC encoding matrix in CCSDS deep space communication standard, and the characteristics that FPGA is good at processing logic operation and is not good at processing arithmetic operation, completes the high-speed coding of LDPC.The application can complete the efficient coding of LDPC by only knowing the '1', '0' position information in supervision matrix, saves FPGA resource, and improves coding rate.

Description

Technical Field

[0001] This invention relates to the field of communication coding technology, and in particular to a high-speed LDPC coding device based on the CCSDS deep space communication standard. Background Technology

[0002] Low-density parity check (LDPC) codes are linear block codes that approach the Shannon limit. They are now widely used in network communications, broadcasting, deep space exploration, satellite communications, and many other fields. Standard protocols include IEEE protocols, DVB-S2, CCSDS, and several other LDPC protocols.

[0003] Based on the satellite communication distance, the CCSDS Standards Committee proposed two types of LDPC standards: near-Earth communication and deep-space communication. Near-Earth communication uses the LDPC (8160, 7136) encoding method, while the CCSDS standard recommends three code rates: 1 / 2, 2 / 3, and 4 / 5 for deep-space communication. Following this standard, I completed the design of five encoding and decoding methods: 1 / 2 (2048, 1024), 1 / 2 (8192, 4096), 2 / 3 (1536, 1024), 2 / 3 (6144, 4096), and 4 / 5 (5088, 4064). In practical application tests, the performance compared to the reference values ​​is excellent and meets the requirements.

[0004] CCSDS recommends a serial encoding implementation, but it is slow and cannot achieve efficient, high-speed encoding. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the above-mentioned background technology and provide a high-speed LDPC encoding device based on the CCSDS deep space communication standard. This device adopts a high-speed parallel mode, does not rely on matrices or matrix vectors, and can achieve efficient and high-speed encoding.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A high-speed LDPC encoding device based on the CCSDS deep space communication standard includes a data buffer 1, a data splitter 2, an LDPC information bit serial memory 3-1, an LDPC information bit parallel memory 3-2, a circular shift register 4, an LDPC parity bit generator 5, a parity bit storage and bit order adjuster 6, and an output selector 7.

[0008] Data buffer 1 receives externally input data C to be encoded. The length of the data area of ​​the data to be encoded is identified by the data enable B. Data synchronization is controlled by the input clock A. Data buffer 1 completes the buffering and format processing of external data, so that the data format is input to data splitter 2 in the form of serial frames.

[0009] Data splitter 2 divides the input serial data into two identical paths, which are sent to the LDPC information bit serial memory 3-1 and the LDPC information bit parallel memory 3-2, respectively.

[0010] The information bit serial memory 3-1 stores the externally input information bits to be encoded serially into the memory under clock control;

[0011] Under clock control, the LDPC information bit parallel memory 3-2 divides the externally input information bits to be encoded into 4 data blocks, which are stored in 4 parallel RAMs respectively. After all the information bits are stored, the data stored in the 4 parallel RAMs are output simultaneously, arranged in high and low bit order, with the high bit first and the low bit last, and stored in the circular shift register 4. The length L of the register is the length of the circular submatrix.

[0012] Under clock control, the cyclic shift register 4 is triggered to shift once on the rising edge of the clock until L-1 shifts are completed and it returns to the initial phase. The L bits of data in the cyclic shift register 4 are sent to the LDPC parity bit generator 5, where the LDPC parity bit is generated. After the LDPC parity bit is generated, it is sent to the parity bit storage and bit order adjuster 6 for LDPC parity bit storage and bit order adjustment. Finally, the output selector 7 uses a switching switch to output the information bits stored in the LDPC information bit serial memory 3-1, as well as the parity bit information stored in the parity bit storage and bit order adjuster 6.

[0013] Furthermore, the LDPC parity generator 5 includes a data input multiplexer 8, a data selector 11, and 4K column branches. Each column branch includes eight cyclic submatrix calculation modules 9 and a parity generator 10. K is selected according to CCSDS specifications, with different values ​​for different code rates: K=2 when the code rate is 1 / 2, K=4 when the code rate is 2 / 3, and K=8 when the code rate is 4 / 5.

[0014] After receiving the data input from the cyclic shift register 4, the data input multiplexer 8 selects the data and outputs it sequentially to each column branch under the data selection control. The eight cyclic submatrix calculation modules 9 in each column branch simultaneously perform multiple cyclic submatrix operations and store the results. After the cyclic submatrix calculation module 9 of the last column branch completes the XOR operation, it sends the operation result of each column branch to the parity bit generator 10 of its respective column. Each parity bit generator 10 performs an XOR operation on the calculation results of the eight cyclic submatrixes in its column to obtain the parity bit. Each parity bit generator 10 sends the generated parity bit to the data selector 11, and the data selector outputs the parity results sequentially.

[0015] Furthermore, in the cyclic submatrix calculation module 9, Matlab is used to find the positions of all '1's in the cyclic submatrix, and Matlab is used to find the positions of all '1's in the generated matrix. The positions of '0's in the cyclic submatrix are ignored. The position information of '1's in the cyclic submatrix is ​​converted into the corresponding positions of the input information codeword, and an XOR operation is performed to obtain the check bit.

[0016] The present invention has the following advantages over the prior art:

[0017] 1. Traditional encoding methods involve multiplying and adding information codewords and a generator matrix. However, the computational complexity increases with the size of the matrix, and high-speed encoding is difficult to achieve in hardware. The encoding method of this invention does not rely on a generator matrix or matrix vector. It only requires the position information of matrix '1', the information codeword, and the generation of check bits. This leverages the advantages of FPGAs in handling logic operations, requiring only a small amount of logic resources to meet high-speed encoding requirements, thus possessing high application value.

[0018] 2. The encoding method recommended by the CCSDS standard is only suitable for medium- and low-speed communication applications. The device of this invention can be implemented on the existing Xilinx XC5VSX-95T chip, with a single-core encoding rate of over 800Mbps, and can process 4 channels of data simultaneously.

[0019] 3. This invention adopts a high-speed parallel design approach, does not rely on matrices or matrix vectors, has low hardware resource consumption, high hardware processing speed, and can achieve efficient and high-speed encoding.

[0020] In summary, this invention uses the CCSDS protocol as a standard, combines matrix theory from linear algebra with the characteristics of FPGA chips, and designs a new LDPC encoding method that is simple to implement, consumes few chip resources, and has a high processing speed. It adopts a pipelined, multi-parallel processing method, which has excellent performance and a high encoding rate. Attached Figure Description

[0021] Figure 1This is a schematic diagram of the LDPC high-speed encoding device of the CCSDS deep space communication standard in this embodiment of the invention.

[0022] Figure 2 yes Figure 1 A schematic diagram of the LDPC check bit generator. Detailed Implementation

[0023] The present invention will now be further described with reference to the accompanying drawings and specific embodiments.

[0024] like Figure 1 As shown, a high-speed LDPC encoding device for the CCSDS deep space communication standard includes a data buffer 1, an input data splitter 2, an LDPC information bit serial memory 3-1, an LDPC information bit parallel memory 3-2, a circular shift register 4, an LDPC parity bit generator 5, a parity bit storage and bit order adjuster 6, and an output selector 7.

[0025] Data buffer 1 receives externally input data C to be encoded. The data width is 4 bits, and the data area length is indicated by the data enable B. Data synchronization is controlled by the input clock A. Data buffer 1 mainly performs external data buffering and format processing, ensuring that the data format is input to data splitter 2 in a 4-channel serial frame manner. Data splitter 2 divides the 4-channel serial data into two identical channels, which are then sent to LDPC information bit serial memory 3-1 and LDPC information bit parallel memory 3-2, respectively. Under clock control, information bit serial memory 3-1 serially inputs 1-bit of the externally input information bit to be encoded into memory for storage. Simultaneously, under clock control, LDPC information bit parallel memory 3-2 divides the externally input information bit to be encoded into 4 data blocks and stores them in 4 RAMs. All information bits... After storage is complete, the data stored in the four parallel RAMs is output simultaneously, arranged in high-low bit order, with the high bit first and the low bit last, and stored in shift register 4. The length L of the register is the length of the circular submatrix. Under clock control, the shift register is triggered to shift once on the rising edge of the clock until L-1 shifts are completed, returning to the initial phase. The L bits of data in the shift register are sent to LDPC parity bit generator 5, where LDPC parity bits are generated. After the LDPC parity bits are generated, because it is a parallel operation, they need to be sent to parity bit storage and bit order adjuster 6 for LDPC parity bit storage and bit order adjustment. Finally, in the output selector 7, the information bits stored in the LDPC information bit serial memory 3-1 and the parity bit information stored in the parity bit storage and bit order adjuster 6 are output using a switching switch.

[0026] Unlike traditional LDPC parity generators that require multiplication and addition operations between the encoded codeword and the encoded matrix or cyclic vector, the LDPC encoding in this device does not depend on the parity matrix or cyclic submatrix vector. Traditional methods involve cyclic shifting the matrix and multiplying and adding the information codeword; this device only requires shifting the information codeword, inputting the information, and applying the corresponding operational rules to determine the parity codeword. Specifically, this device uses Matlab to extract the positions of the "1"s in the cyclic submatrix of the generator matrix. Because LDPC encoding involves multiplication and addition between the information codeword and the generator matrix, the positions of "0"s in the matrix are ignored, and the position information of the "1"s is converted into input information codewords for computation.

[0027] like Figure 2 As shown, the LDPC parity bit generator 5 operates as follows:

[0028] After receiving the data input from the cyclic shift register 4, the data multiplexer 8 selects the data and outputs it sequentially to the 1 to 4K matrix calculation modules under the data selection control. K is selected according to the CCSDS specification, with different values ​​for different code rates: K=2 when the code rate is 1 / 2, K=4 when the code rate is 2 / 3, and K=8 when the code rate is 4 / 5.

[0029] The data input to the circular shift register 4 is fed into the eight parallel circular submatrix calculation modules (9) to complete the calculation of circular submatrix 1-1, circular submatrix 1-2...circular submatrix 1-8. After completing the calculation of the first column of eight matrices, the calculation result is stored first, and then the calculation of the next column is performed until all matrix operations are completed. Finally, the result of the calculation of each column of circular submatrix is ​​sent to the parity bit generator 10 of its respective column. In the parity bit generator 10, the obtained circular submatrix result is XORed to obtain the parity bit. The parity bit generator 10 sends the generated parity bit information to the data selector 11, and the data selector 11 outputs the parity results in sequence.

[0030] According to the CCSDS specification, the parity check matrix consists of 4K*8 sub-matrices. The input data to the circular shift register is updated once every one cycle. During the interval between two updates, the shift register is shifted under clock control and the data is sent to the parity bit generator 5 for calculation. After 4K updates, all parity bits are generated. The operation relationships of each sub-matrix are pre-generated by MATLAB.

[0031] The characteristics of the encoding matrix involved in this device are as follows:

[0032] If the code length is n and the information bit length is k, then the LDPC code rate r = k / n. Table 1 lists the code lengths and corresponding code rates recommended by the CCSDS 131.1-o-2 standard.

[0033] Table 1. Correspondence between information bit length k and code length n

[0034]

[0035] The parity check matrix H is composed of several M×M submatrices. The relationship between the submatrix block size, code length, and code rate is shown in Table 2. M is also the length of the cyclic submatrix.

[0036] Table 2 Submatrix Size Comparison Table

[0037]

[0038] First, according to the matrix generation method of CCSDS, the generator matrix and the parity check matrix related to the parity bit are decomposed into MK×3M submatrices. Since this type of coding is a pruning code, the last group of M matrices is deleted, so the final parity check matrix is ​​MK×2M. K is related to the code rate. When the code rate is 1 / 2, K=2; when the code rate is 2 / 3, K=4; and when the code rate is 4 / 5, K=8.

[0039] Let W i,j Let represent the i-th row and j-th column of the supervision matrix. Then W is as shown in matrix (1):

[0040] (1)

[0041] This supervision matrix can be further decomposed into multiple cyclic submatrices, let the cyclic submatrices be Z. i,j Let Z represent the cyclic submatrix in the i-th row and j-th column. i,j The size of W is L*L=(M / 4)*(M / 4), so W can be further represented as matrix (2):

[0042] (2)

[0043] Where the cyclic submatrix Z i,j The representation is as follows, as shown in matrix (3):

[0044] (3)

[0045] The next column is the previous column shifted down, up to column L.

[0046] A traditional coding method 1: The traditional coding method involves multiplying the direct information bits and the parity-check matrix, letting s = {s0, s1, ... s}. 4096 Let the encoded verification data vector be u = {u0, u1, ..., u}. 4096The formula is u = s•W, but this method is only suitable for situations where the matrix is ​​small and the program throughput is low, because the W matrix needs to be stored in the FPGA's RAM, and RAM resources are limited. In resource-constrained chiplets, this limits module reuse, resulting in a low final processing speed.

[0047] A traditional encoding method 2: Traditional encoding methods may also include the following: The CCSDS technical documentation states that the W matrix is ​​composed of L*L (L=M / 4) cyclic submatrices, and any submatrix Z... i,j It can be represented by matrix (3). Taking advantage of the cyclic properties of the W matrix and the ability of FPGA to perform data parallel processing, a high-speed parallel design can be adopted.

[0048] High-speed parallel design has two main ideas: 1. Pipeline design. 2. Multi-module parallel processing.

[0049] The information to be encoded is fed into the FPGA encoder and stored in RAM, with each group consisting of L units, for a total of x groups. The information code group s can then be represented as s = {T0, T1, ..., T}. x The length of T0 is exactly a submatrix Z. i,j The column size. Because each submatrix of matrix W is a cyclic matrix, the first column of matrix W is stored. When T0 is fully stored in RAM, the data of T0 is output along with the first row of matrix block {Z} of matrix W. 1,1 Z 1,2 ,……Z 1,y After multiplying rows and columns, and completing one column operation, the W matrix is ​​cyclically shifted and multiplied sequentially with T0. This operation can be completed in L clock cycles. While the operation on the first row of the W matrix is ​​complete, information T1 is just stored, and the operation on the second row of the W matrix begins. This process continues until T0 is completed. x The operation on the last row of the W matrix results in 2M parity bits, which, together with the information bits s, form a transmission frame.

[0050] The advantages of this method are continuous data input, low input / output latency (approximately within two frames), and high processing speed. The disadvantages are the large amount of FPGA registers and logic resources (LUTs). In resource-constrained chiplets, it limits module reuse, resulting in a lower final processing speed.

[0051] After summarizing the above traditional algorithms, this device proposes a new encoding scheme based on the structural characteristics of FPGA, as follows:

[0052] Leveraging the FPGA's strength in handling logic operations, this device utilizes LUT resources to perform AND, OR, XOR, and other logical operations as much as possible. The W matrix is ​​a known fixed matrix. Although it is a dense matrix, the number of '1's is still small compared to the entire matrix. It also has cyclic characteristics. Combining these two characteristics, this device can obtain an encoding method with low resource consumption and high speed, provided that the positions of '1's in the W matrix are known.

[0053] Below, we will first give a brief introduction to the multiplication principle of determinants. Let S be a 1×4 row vector (4), and Z be a 4×4 cyclic matrix (5).

[0054] (4)

[0055] (5)

[0056] Then T = S•Z = [1 0 1 0]. The first two elements of the first column of matrix Z are '1', and the rest are '0'. When performing matrix multiplication, only the value of the '1' position needs to be determined based on matrix S; the value of the '0' position is already determined, and any value multiplied by it will be '0'. Therefore, multiplying S by the first column of matrix Z means multiplying the first two elements of S. The second characteristic is that matrix Z is a cyclic matrix. The vectors in the next column of matrix Z are shifted down one position and then multiplied by matrix S. Conversely, if we expand the 1×4 row vector S into a 4×4 cyclic matrix, shift the next row vector one position to the right, and take the first column of Z, and then perform row and column multiplication, the result is the same. Combining the above two points, knowing the position of the '1' in the first column of the cyclic matrix, and that the cycle of S can replace the cycle of Z, we can discard the Z matrix and only need to calculate the corresponding '1' position element after obtaining the information bit S. In this way, the FPGA only needs to use LUT resources to perform a finite number of XOR operations to obtain the parity bit.

[0057] This encoding method allows for the development of new devices that consume fewer resources and achieve higher encoding speeds. Taking LDPC 1 / 2 (8192,4096) encoding as an example, one IP core encodes four frames simultaneously. Compared with traditional methods 1 and 2, and the new encoding algorithm of this device, the compiler selected is Xilinx's ISE, and the chip is Xilinx's V5-95t. The resource consumption is shown in the table below. The FPGA resources of this device are significantly reduced, and the processing speed can reach up to 2Gbps.

[0058] Table 3. FPGA Resource Ratio of Traditional Algorithm and Algorithm of This Invention

[0059]

[0060] Specifically, the working process of this device can be divided into the following steps:

[0061] Step 1:

[0062] Extracting Z using MATLAB i,j The position information of '1' in the matrix is ​​A0, A1, A2...A x ;

[0063] Step 2:

[0064] like Figure 1 As shown, data is input into data buffer 1 under the control of data enable input and clock input. Framing processing is performed in the data buffer, and frames are assembled according to the LDPC codeword length.

[0065] Step 3:

[0066] like Figure 1 As shown, in data splitter 2, the information to be encoded is sent to LDPC information bit serial memory 3-1 and LDPC information bit parallel memory 3-2 respectively.

[0067] Step 4:

[0068] The LDPC information bit serial memory 3-1 receives the data sent by the data splitter 2, stores the data information, and outputs it as information bits when finally outputting the encoded data.

[0069] The LDPC information bit serial memory 3-2 receives data from the data splitter 2 and stores it in four RAMs. Each RAM has 1 bit input and 32 bits output. Specifically, bits 1-32 are stored in the first RAM, bits 33-64 are stored in the second RAM, bits 65-96 are stored in the third RAM, bits 97-128 are stored in the fourth RAM, bits 129-160 are stored in the first RAM, and so on, until all information bits are stored.

[0070] Step 5:

[0071] After all information bits are stored, data from four RAMs are read simultaneously. Each RAM outputs 32 bits, which are sent to a circular shift register 4. The size of the circular shift register is L, the RAM read cycle is L, and the next set of data is read after L clock cycles.

[0072] Step 6:

[0073] The data from the circular shift register 4 is fed into the LDPC parity bit generator 5, and d = {d0, d1, ... d2}. L} represents the input data, L represents the length of the input data, and d represents the length of the input data. iFor any 1-bit information symbol, using the position information from step 1, correspond to the corresponding position in the interface input data, and perform an XOR operation to complete Z. i,j The first column operation, as the circular shift register 4 continuously shifts and inputs into the LDPC parity bit generator 5, follows the same operation rules, completing matrix Z after L cycles. i,j All operations are performed according to the following rules:

[0074] Dout=d(A0) xor d(A1) xor d(A2)……xor d(A x (6)

[0075] During the project implementation, in order to achieve high-speed coding, Z i,j The first row of the matrix Z 1,1 Z 1,2 ...Z 1,8 Simultaneously, the calculation is performed in parallel. After the calculation of the first row is completed, the calculation result is stored until all rows of matrix operations are completed. Finally, the intermediate results of each column operation are XORed to obtain the final check bit, which is then sent to the check bit storage and bit order adjustment module in sequence.

[0076] Step 7:

[0077] The LDPC parity generator outputs 8 bits in parallel, and the bit order is: {d1 d...} L+1 d 2L+1 d 3L+1 d 4L+1 d 5L+1 d 6L+1 d 7L+1}、{d2 d L+2 d 2L+2 d 3L+2 d 4L+2 d 5L+2 d 6L+2 d 7L+2}……{d L d 2L d 3L d 4L d 5L d 6L d 7L d 8L The data is stored in the RAM of the parity bit storage and bit order adjuster 6, and then adjusted according to d1d2d3d4……d 8L-1 d 8L Output is sent to output selector 7.

[0078] Step 8:

[0079] In the output selector 7, the information bit data in the LDPC information bit serial memory 3-1 is selected first, and then the parity bit information in the parity bit storage and bit order adjuster 6 is selected. At this point, a complete LDPC encoding of the CCSDS standard is generated.

[0080] In summary, this invention utilizes matrix computation from linear algebra and LDPC encoding theory from communication principles as guidance. It employs an LDPC encoding algorithm different from traditional technologies, leveraging the cyclic characteristics of the LDPC encoding matrix in the CCSDS deep space communication standard. It also utilizes the theory in linear algebra that matrix cycles can be replaced by cyclic encoded data, combined with the characteristic of FPGAs being adept at handling logical operations but not arithmetic operations, to achieve high-speed, low-resource-consumption LDPC encoding. Traditional LDPC encoding requires ROM or DDR to store the encoding matrix information, and then performs binary multiplication and addition operations on the information bits and the encoding matrix. This invention can achieve efficient LDPC encoding without needing to store the parity check matrix, only requiring knowledge of the "1" and "0" positions in the parity check matrix. This saves FPGA resources and improves encoding efficiency.

Claims

1. A high-speed LDPC encoding device based on the CCSDS deep space communication standard, characterized in that, Includes a data buffer (1), a data splitter (2), an LDPC information bit serial memory (3-1), an LDPC information bit parallel memory (3-2), a circular shift register (4), an LDPC parity bit generator (5), a parity bit storage and bit order adjuster (6), and an output selector (7). The data buffer (1) receives external input data to be encoded (C). The length of the data area of ​​the data to be encoded is indicated by the data enable (B). Data synchronization is controlled by the input clock (A). The data buffer (1) completes the buffering and format processing of external data, so that the data format is input to the data splitter (2) in the form of serial frames. The data splitter (2) divides the input serial data into two identical paths, which are sent to the LDPC information bit serial memory (3-1) and the LDPC information bit parallel memory (3-2) respectively. The serial information bit memory (3-1) stores the externally input information bits to be encoded serially into the memory under clock control; The LDPC information bit parallel memory (3-2) divides the externally input information bits to be encoded into 4 data blocks under clock control, and stores them in 4 parallel RAMs respectively; After all the information bits are stored, the data stored in the four parallel RAMs are output simultaneously, arranged in high and low bit order, with the high bit first and the low bit last, and stored in the circular shift register (4). The length L of the register is the length of the circular submatrix. Under clock control, the cyclic shift register (4) is triggered to shift once on the rising edge of the clock until L-1 shifts are completed and it returns to the initial phase. The L bits of data in the cyclic shift register (4) are sent to the LDPC check bit generator (5) to generate the LDPC check bit. After the LDPC check bit is generated, it is sent to the check bit storage and bit order adjuster (6) for LDPC check bit storage and bit order adjustment. Finally, the information bits stored in the LDPC information bit serial memory (3-1) and the check bit information stored in the check bit storage and bit order adjuster (6) are output in the output selector (7) using a switching switch.

2. The LDPC high-speed encoding device based on the CCSDS deep space communication standard according to claim 1, characterized in that, The LDPC parity generator (5) includes a data input multiplexer (8), a data selector (11), and 4K column branches. Each column branch includes 8 cyclic submatrix calculation modules (9) and a parity generator (10). K is selected according to CCSDS, with different values ​​for different code rates. K=2 when the code rate is 1 / 2, K=4 when the code rate is 2 / 3, and K=8 when the code rate is 4 / 5. After receiving the data input from the cyclic shift register (4), the data input multiplexer (8) selects the data and outputs it to each column branch in sequence under the data selection control. The eight cyclic submatrix calculation modules (9) in each column branch simultaneously perform multiple cyclic submatrix operations and store the operation results. After the cyclic submatrix calculation module (9) of the last column branch completes the XOR operation, it sends the operation results of each column branch to the parity bit generator (10) of its respective column. Each parity bit generator (10) performs an XOR operation on the calculation results of the eight cyclic submatrixes in its column to obtain the parity bit. Each parity bit generator (10) sends the generated parity bit to the data selector (11), and the data selector outputs the parity results in sequence.

3. The LDPC high-speed encoding device based on the CCSDS deep space communication standard according to claim 2, characterized in that, In the cyclic submatrix calculation module (9), Matlab is used to find the positions of all '1' in the cyclic submatrix, and Matlab is used to find the positions of all '1' in the generated matrix. The positions of '0' in the cyclic submatrix are ignored. The position information of '1' in the cyclic submatrix is ​​converted into the corresponding position of the input information codeword, and an XOR operation is performed to obtain the check bit.

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