An optimization system for line driver slew rate boost

Abstract

This invention provides an optimized system for improving the slew rate of a Line Driver, comprising a differential input module, a bias current module, an amplification module, an active load module, and a mirror load module. The differential input module receives the input signal and converts the voltage signal into a current signal. The bias current module provides a stable bias current to the circuit. The amplification module receives the current signal from the differential input module and achieves voltage gain. The amplification module is electrically connected to the active load module. The active load module can improve the amplification gain of the amplification module, replicate the current, and stabilize the output node. The mirror load module can replicate the signal amplification path of the amplification module to achieve symmetrical output, thereby improving the signal amplification effect and anti-interference reliability of the circuit and solving the problem of limited slew rate in traditional optimized systems for Line Drivers.

Description

Technical Field

[0001] This invention belongs to the field of line driver technology, and more specifically, relates to an optimization system for improving the slew rate of a line driver. Background Technology

[0002] In recent years, BPLC has been gradually used as a carrier technology in the field of smart meter reading. In order to obtain high-speed and high-precision data transmission, high linearity and high bandwidth line driver are key components in this system. Linearity is the main indicator for measuring line driver, which is mainly determined by the gain-bandwidth product of the amplifier. Therefore, current feedback operational amplifier plus differential structure has become a common choice. However, the even harmonic performance of this differential architecture is limited by the mismatch between the two channels caused by process changes and packaging differences. Its magnitude is already comparable to that of odd harmonics. Moreover, as the output swing and signal frequency increase, even harmonics will further deteriorate. The slew rate of some optimized systems used for line driver is limited. In the standby state, the quiescent current should be reduced as much as possible. When outputting high-frequency large signals, in order to ensure the requirements of harmonic distortion, the slew rate performance should be as high as possible. These two states create a contradiction between reducing quiescent current and increasing dynamic current. Now there is an urgent need for an optimized system for line driver with improved slew rate. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides an optimization system for improving the slew rate of a Line Driver, thereby solving the technical problem of limited slew rate in traditional optimization systems for Line Drivers in the prior art.

[0004] This invention provides an optimization system for improving the slew rate of Line Drivers, achieved through the following specific technical means: An optimized system for improving the slew rate of a Line Driver includes: a differential input module, a bias current module, an amplification module, an active load module, and a mirror load module. The differential input module is electrically connected to the bias current module. The differential input module is used to receive input signals, convert voltage signals into current signals, suppress common-mode interference, and provide stable bias. The bias current module provides a stable bias current to the circuit, improves the power supply rejection ratio, and avoids signal distortion. The output terminal of the differential input module is electrically connected to the input terminal of the amplification module. The amplification module is used to receive the current signal from the differential input module, realize voltage gain, and provide driving capability for the output. The output terminal of the bias current module is electrically connected to the input terminal of the amplification module and the active load module, respectively. The amplification module is electrically connected to the active load module. The active load module can improve the amplification gain of the amplification module, replicate the current, and stabilize the output node. The output terminal of the active load module is electrically connected to the input terminal of the mirror load module. The mirror load module can replicate the signal amplification path of the amplification module to achieve symmetrical output, thereby improving the signal amplification effect and anti-interference reliability of the circuit.

[0005] According to a preferred embodiment, the differential input module includes an NMOS transistor M1 and a PMOS transistor M2. The gate of the NMOS transistor M1 is electrically connected to the input signal VIN, and the drain of the NMOS transistor M1 is connected to the ground terminal. The NMOS transistor M1 is used to process the high-level range of the input signal and convert the input voltage signal into a drain current signal.

[0006] According to a preferred embodiment, the gate of the PMOS transistor M2 is electrically connected to the input signal VIN, and the source of the PMOS transistor M2 is connected to a ground current source. The PMOS transistor M2 is used to process the low-level range of the input signal to achieve an ultra-wide input common-mode range.

[0007] According to a preferred embodiment, the bias current module includes an N-type current source IBN1, one end of which is connected to a ground terminal. The N-type current source IBN1 serves as a reference current source, providing a reference current to the ground.

[0008] According to a preferred embodiment, the amplification module includes an NMOS transistor M4 and a PMOS transistor M3. The source of the PMOS transistor M3 is electrically connected to the source of the NMOS transistor M4, and the gate of the PMOS transistor M3 is electrically connected to the source of the NMOS transistor M1. The PMOS transistor M3 is used to increase the output impedance, thereby increasing the voltage gain.

[0009] According to a preferred embodiment, the active load module includes a current mirror M5 and a current mirror M8. The source of the current mirror M5 is electrically connected to the power supply, and the source of the current mirror M8 is electrically connected to the ground terminal. The current mirror M5 is used to provide high output impedance to improve the gain of the amplification stage and ensure stable load current.

[0010] According to a preferred embodiment, the mirrored load module includes a current mirror tube M7 and a current mirror tube M10. The source of the current mirror tube M7 is electrically connected to the power supply, and the source of the current mirror tube M10 is electrically connected to the ground terminal. The current mirror tubes M7 and M10 form a load balance, thereby improving the circuit's anti-interference capability.

[0011] Compared with the prior art, the present invention has the following beneficial effects: First, by incorporating an amplification module and an active load module, the instantaneous current is increased, enabling the output stage to drive the load capacitor to charge and discharge faster, thereby improving slew rate performance. When meeting specific slew rate requirements, there is no need to maintain excessively high quiescent current, thus reducing standby power consumption and improving current efficiency. Simultaneously, the matching of the dual-channel current is improved, reducing even-order harmonics caused by mismatch between the two channels, solving the problem of limited slew rate in traditional optimized systems used for line drivers. Second, by incorporating a differential input module, the circuit can cover a wide range of input voltages from ground to power without additional level offset circuitry. The symmetrical structure of the input stage can suppress common-mode interference signals. When power supply noise or environmental interference is superimposed on the input signal in common-mode form, the common-mode responses cancel each other out, thereby reducing the impact of interference on the signal and improving the signal processing stability of the circuit in complex electromagnetic environments, solving the problem of low reception stability in traditional optimized systems used for line drivers. Attached Figure Description

[0012] Figure 1 This is a diagram of a conventional current feedback driver architecture provided by the present invention.

[0013] Figure 2 The present invention provides a conventional current mirror drive circuit diagram.

[0014] Figure 3 The current bridge circuit diagram provided for this invention. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0016] As attached Figure 1 To be continued Figure 3As shown: This invention provides an optimization system for improving the slew rate of a line driver. The marine radar performance monitoring system includes a differential input module, a bias current module, an amplification module, an active load module, and a mirror load module. The differential input module is electrically connected to the bias current module. The differential input module receives the input signal, converts the voltage signal into a current signal, suppresses common-mode interference, and provides a stable bias. The bias current module provides a stable bias current to the circuit, improves the power supply rejection ratio, and avoids signal distortion. The output terminal of the differential input module is electrically connected to the input terminal of the amplification module. The amplification module receives the current signal from the differential input module, realizes voltage gain, and provides driving capability for the output. The output terminal of the bias current module is electrically connected to the input terminals of the amplification module and the active load module, respectively. The amplification module is electrically connected to the active load module. The active load module can improve the amplification gain of the amplification module, replicate the current, and stabilize the output node. The output terminal of the active load module is electrically connected to the input terminal of the mirror load module. The mirror load module can replicate the signal amplification path of the amplification module to achieve symmetrical output, improving the signal amplification effect and anti-interference reliability of the circuit.

[0017] Specifically, the differential input module includes an NMOS transistor M1 and a PMOS transistor M2. The gate of the NMOS transistor M1 is electrically connected to the input signal VIN, and the drain of the NMOS transistor M1 is connected to ground. The NMOS transistor M1 is used to process the high-level range of the input signal, converting the input voltage signal into a drain current signal. The gate of the PMOS transistor M2 is electrically connected to the input signal VIN, and the source of the PMOS transistor M2 is connected to a ground current source. The PMOS transistor M2 is used to process the low-level range of the input signal, achieving an ultra-wide input common-mode range. By combining the NMOS transistors M1 and M2, a wider input voltage range is covered, converting the input voltage signal into complementary drain current signals. At the same time, the structural characteristics of the transistors suppress common-mode interference signals, and a matching bias current source is used to maintain a stable operating point.

[0018] Specifically, the bias current module includes an N-type current source IBN1. One end of the N-type current source IBN1 is connected to the ground terminal. The N-type current source IBN1 serves as a reference current source, providing a reference current for grounding. The bias current module can reduce the impact of temperature and power supply voltage fluctuations on the circuit's operating state and ensure the normal implementation of the current mirror's current replication function.

[0019] Specifically, the amplification module includes an NMOS transistor M4 and a PMOS transistor M3. The source of the PMOS transistor M3 is electrically connected to the source of the NMOS transistor M4, and the gate of the PMOS transistor M3 is electrically connected to the source of the NMOS transistor M1. This increases the output impedance of the amplification stage, enhances the voltage gain of the circuit, and suppresses the Miller effect to optimize the high-frequency response performance of the circuit. The gate of the PMOS transistor M3 is connected to the feedback node VFB to introduce negative feedback, stabilize the gain and DC operating point of the circuit, ensure the linearity of the signal amplification process, and avoid signal distortion.

[0020] Specifically, the active load module includes current mirror tubes M5 and M8. The source of current mirror tube M5 is electrically connected to the power supply, and the source of current mirror tube M8 is electrically connected to the ground terminal. The active load module forms a current mirror structure through gate interconnection, providing a high-impedance load for the amplification stage, improving the voltage gain of the amplification stage, and replicating the reference current to achieve current symmetry between channels, completing the conversion of differential signals to single-ended voltage signals, stabilizing the voltage and current of the output node Vo1, and reducing signal fluctuations.

[0021] Specifically, the mirrored load module includes a current mirror tube M7 and a current mirror tube M10. The source of the current mirror tube M7 is electrically connected to the power supply, and the source of the current mirror tube M10 is electrically connected to the ground terminal, forming a load path, improving the common-mode rejection ratio of the circuit, enhancing the circuit's ability to resist power supply noise and environmental interference, and ensuring the stability of signal processing under complex operating conditions.

[0022] Basic principle: In standby mode, the current consumed by the negative input stage (FB) and the Vo1 output stage are respectively... and When operating normally, M3 is driven by the voltage difference of the input signal, generating an instantaneous current of The output stage current is The output stage slew rate is limited by the square law of current in the MOSFET. Even with the addition of a current bridge architecture, under the same conditions, the instantaneous current of M3 remains the same. Because it operates differentially, when M3 in channel one is driven, M4 in channel two is driven simultaneously, resulting in a current of... The IBP1 obtained after mirroring through M10 will additionally pull out M4's drain from M3, equal to the amount of M4 from channel 2. For channel one, M5, the instantaneous current becomes Then the instantaneous current of M6 can reach This improves the slew rate performance of the output stage, reduces standby power consumption and improves current efficiency under specific slew rate requirements, and at the same time reduces even harmonics caused by mismatch between the two channels.

[0023] The embodiments of the present invention are given for illustrative and descriptive purposes only, and are not intended to be exhaustive or to limit the invention to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described in order to better illustrate the principles and practical application of the invention, and to enable those skilled in the art to understand the invention and to design various embodiments with various modifications suitable for a particular purpose.

Claims

1. An optimization system for improving the sway rate of Line Drivers, characterized in that, The optimized system for improving the slew rate of the Line Driver includes a differential input module, a bias current module, an amplification module, an active load module, and a mirror load module. The differential input module is electrically connected to the bias current module. The differential input module is used to receive input signals, convert voltage signals into current signals, suppress common-mode interference, and provide stable bias. The bias current module provides a stable bias current to the circuit, improves the power supply rejection ratio, and avoids signal distortion. The output terminal of the differential input module is electrically connected to the input terminal of the amplification module. The amplification module is used to receive the current signal from the differential input module, realize voltage gain, and provide driving capability for the output. The output terminal of the bias current module is electrically connected to the input terminal of the amplification module and the active load module, respectively. The amplification module is electrically connected to the active load module. The active load module can improve the amplification gain of the amplification module, replicate the current, and stabilize the output node. The output terminal of the active load module is electrically connected to the input terminal of the mirror load module. The mirror load module can replicate the signal amplification path of the amplification module to achieve symmetrical output, thereby improving the signal amplification effect and anti-interference reliability of the circuit.

2. The optimization system for improving the sway rate of a Line Driver according to claim 1, characterized in that, include: The differential input module includes an NMOS transistor M1 and a PMOS transistor M2. The gate of the NMOS transistor M1 is electrically connected to the input signal VIN, and the drain of the NMOS transistor M1 is connected to the ground terminal. The NMOS transistor M1 is used to process the high-level range of the input signal and convert the input voltage signal into a drain current signal.

3. The optimization system for improving the sway rate of a Line Driver according to claim 2, characterized in that, include: The gate of the PMOS transistor M2 is electrically connected to the input signal VIN, and the source of the PMOS transistor M2 is connected to the ground current source. The PMOS transistor M2 is used to process the low-level range of the input signal to achieve an ultra-wide input common-mode range.

4. The optimization system for improving the sway rate of a Line Driver according to claim 1, characterized in that, include: The bias current module includes an N-type current source IBN1, one end of which is connected to the ground terminal. The N-type current source IBN1 serves as a reference current source, providing a reference current for grounding.

5. An optimization system for improving the sway rate of a Line Driver according to claim 2, characterized in that, include: The amplification module includes an NMOS transistor M4 and a PMOS transistor M3. The source of the PMOS transistor M3 is electrically connected to the source of the NMOS transistor M4, and the gate of the PMOS transistor M3 is electrically connected to the source of the NMOS transistor M1. The PMOS transistor M3 is used to increase the output impedance, thereby increasing the voltage gain.

6. The optimization system for improving the sway rate of a Line Driver according to claim 1, characterized in that, include: The active load module includes a current mirror M5 and a current mirror M8. The source of the current mirror M5 is electrically connected to the power supply, and the source of the current mirror M8 is electrically connected to the ground terminal. The current mirror M5 is used to provide high output impedance to improve the gain of the amplification stage and ensure stable load current.

7. An optimization system for improving the sway rate of a Line Driver according to claim 1, characterized in that, include: The mirrored load module includes a current mirror tube M7 and a current mirror tube M10. The source of the current mirror tube M7 is electrically connected to the power supply, and the source of the current mirror tube M10 is electrically connected to the ground terminal. The current mirror tubes M7 and M10 form a load balance, which improves the anti-interference capability of the circuit.

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