Timestamp acquisition compensation method, apparatus, and clock synchronization system

Abstract

A timestamp acquisition compensation method, apparatus, and clock synchronization system are disclosed. The method includes: generating multiple (M) sampling clocks with the same frequency and uniform phase distribution; parallel sampling and synchronization of an asynchronous timestamp request signal; timing comparison of the multiple synchronized pulse signals to determine a target sampling clock; and finally, using the edge trigger of the target clock to latch the timestamp. This application subdivides the entire master clock cycle in which the asynchronous request signal may occur into M time intervals. By selecting the target sampling clock, it is possible to determine which sub-interval the asynchronous request signal actually falls into, thereby significantly reducing the acquisition error from ±1 master clock cycle in traditional methods to within ±1 master clock cycle. Without actually increasing the system master clock frequency, the timestamp acquisition accuracy is significantly improved, and the error range can be precisely controlled and predicted by selecting the value of M.

Description

Technical Field

[0001] This application relates to the field of clock synchronization technology, specifically to a timestamp acquisition and compensation method, device, and clock synchronization system. Background Technology

[0002] In systems such as 5G communication and high-speed data exchange, various functional modules often operate in different clock domains. For example, the serializer / deserializer (SerDes) typically operates in the clock domain recovered from the data it receives, while the system's time management module operates in a global master clock domain. These two clock domains are asynchronous. When an event (such as the start of a data block transmission) needs to be accurately timestamped in the system's master clock domain, this involves timestamp acquisition across asynchronous clock domains.

[0003] Traditional asynchronous timestamp acquisition methods typically employ simple cross-clock domain synchronization circuits, such as using two-stage flip-flops to synchronize the asynchronous request signal before directly acquiring the timestamp using the system master clock. This method has an inherent drawback: since the transition edge of the asynchronous request signal can occur anywhere within the system master clock cycle, direct synchronization and sampling introduce random errors of up to ±1 master clock cycle. For example, when the system master clock is 1 GHz (period 1 ns), the acquisition error can be as high as ±1 ns. This large and uncontrollable error becomes a bottleneck restricting the performance of high-precision time synchronization systems. Summary of the Invention

[0004] This application provides a timestamp acquisition compensation method, device, and clock synchronization system, which can solve the technical problems of low timestamp acquisition accuracy and large error in the prior art.

[0005] In a first aspect, embodiments of this application provide a timestamp acquisition method, the timestamp acquisition method comprising: Based on the reference clock signal in the first clock domain, M sampled clock signals are generated. The frequencies of the M sampled clock signals are the same as the frequency of the reference clock signal, and their phases are uniformly distributed within one period of the reference clock signal. M is an even number. The timestamp request signal originating from the second clock domain is synchronized to the clock domain of each of the M sampled clock signals to obtain M synchronized pulse signals, wherein the second clock domain is asynchronous with the first clock domain; The timing of the M synchronized pulse signals is compared to determine the target sampling clock signal; In response to the effective clock edge of the target sampling clock signal, the latest time count value output by the time reference module is latched, and the latest time count value is compensated based on the phase information corresponding to the target sampling clock signal to obtain the acquisition timestamp corresponding to the timestamp request signal. The time reference module operates in the first clock domain and is used to generate continuously increasing time count values.

[0006] In conjunction with the first aspect, in one implementation, generating M sampled clock signals based on a reference clock signal in the first clock domain includes: The reference clock signal in the first clock domain is phase interpolated or delayed by a phase-locked loop or a delay phase-locked loop to generate M sampled clock signals with the same frequency as the reference clock signal and whose phases are uniformly distributed within one period of the reference clock signal.

[0007] In conjunction with the first aspect, in one implementation, performing a timing comparison of the M synchronized pulse signals to determine the target sampling clock signal includes: Determine the target synchronized pulse signal that is the last of the M synchronized pulse signals to transition from an invalid state to an effective state. The sampling clock signal corresponding to the target synchronized pulse signal is taken as the target sampling clock signal.

[0008] In conjunction with the first aspect, in one embodiment, the second clock domain is the recovery clock domain of the serializer / deserializer, and the timestamp request signal is periodically generated by the serializer / deserializer according to a preset request interval period, wherein the request interval period is greater than the time required for a complete timestamp acquisition process.

[0009] Secondly, embodiments of this application provide a timestamp compensation method, the timestamp compensation method comprising: Obtain the acquisition timestamp corresponding to the timestamp request signal determined according to the asynchronous clock timestamp acquisition method described in the first aspect; The acquisition timestamp is compensated based on a preset compensation value to obtain a transmission timestamp, wherein the preset compensation value is used to compensate for the processing delay between the time corresponding to the acquisition timestamp and the time when the data block starts to be transmitted on the physical link.

[0010] In conjunction with the second aspect, in one implementation, the preset compensation value is determined based on the service rate, the timestamp accuracy of the service requirements, and the data bit width of the data block.

[0011] In conjunction with the second aspect, in one implementation, the preset compensation value is expressed in the form of a fixed-point number.

[0012] Thirdly, embodiments of this application provide a timestamp acquisition device, the timestamp acquisition device comprising: The generation module is used to generate M sampled clock signals based on the reference clock signal of the first clock domain. The frequency of the M sampled clock signals is the same as the frequency of the reference clock signal, and their phases are uniformly distributed within one period of the reference clock signal. M is an even number. The synchronization module is used to synchronize the timestamp request signal originating from the second clock domain to the respective clock domains of the M sampled clock signals to obtain M synchronized pulse signals, wherein the second clock domain is asynchronous with the first clock domain; The filtering module is used to perform timing comparison on the M synchronized pulse signals to determine the target sampling clock signal; The latch module is used to latch the latest time count value output by the time base module in response to the effective clock edge of the target sampling clock signal, and to compensate the latest time count value based on the phase information corresponding to the target sampling clock signal to obtain the acquisition timestamp corresponding to the timestamp request signal. The time base module operates in the first clock domain and is used to generate continuously increasing time count values.

[0013] Fourthly, embodiments of this application provide a timestamp compensation device, the timestamp compensation device comprising: The acquisition module is used to acquire the acquisition timestamp corresponding to the timestamp request signal determined according to the asynchronous clock timestamp acquisition method described in the first aspect; The compensation module is used to compensate the acquisition timestamp based on a preset compensation value to obtain the transmission timestamp, wherein the preset compensation value is used to compensate for the processing delay between the time corresponding to the acquisition timestamp and the time when the data block starts to be transmitted on the physical link.

[0014] Fifthly, embodiments of this application provide a clock time system, which includes a timestamp acquisition device as described in the third aspect and a timestamp compensation device as described in the fourth aspect.

[0015] The beneficial effects of the technical solutions provided in this application include: In this embodiment, multiple (M) sampling clocks with the same frequency and uniform phase distribution are generated to sample and synchronize the asynchronous timestamp request signal in parallel. Then, the timing of the multiple synchronized pulse signals is compared to determine a target sampling clock. Finally, the edge of this target clock is used to trigger the latching of the timestamp. This embodiment subdivides the entire master clock cycle in which the asynchronous request signal may occur into M time intervals. By selecting the target sampling clock, it is possible to determine which subdivision interval the asynchronous request signal actually falls into, thereby significantly reducing the acquisition error from ±1 master clock cycle in traditional methods to ± Within one master clock cycle. This method achieves an equivalent oversampling effect without actually increasing the system master clock frequency, significantly improving the timestamp acquisition accuracy, and the error range can be precisely controlled and predicted by selecting the M value. Attached Figure Description

[0016] Figure 1 A flowchart illustrating the overall process of the asynchronous timestamp acquisition and compensation method provided in this application embodiment; Figure 2 This is a flowchart illustrating one embodiment of the timestamp collection method of this application; Figure 3 This is a schematic diagram illustrating the asynchronous timestamp acquisition principle using a 4-frequency division (M=4) example according to an embodiment of this application; Figure 4 This is a schematic diagram illustrating the logic implementation of pairwise comparisons in the SampleMux module in one embodiment of this application; Figure 5 This is a flowchart illustrating one embodiment of the timestamp compensation method of this application; Figure 6 This is a schematic diagram illustrating the process of returning a timestamp request signal in one embodiment of this application; Figure 7 This is a schematic diagram of the functional modules of an embodiment of the timestamp acquisition device of this application; Figure 8 This is a schematic diagram of the functional modules of an embodiment of the timestamp compensation device of this application. Detailed Implementation

[0017] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0018] To overcome the shortcomings of existing technologies, this invention provides a method for achieving high-precision asynchronous timestamp acquisition and compensation through phase subdivision and comparison selection. The core idea is to use multiple sampling clocks with uniformly distributed phases to sample and synchronize asynchronous request signals in parallel. By comparing the timing of these synchronized signals, the relative position of the asynchronous event within the master clock cycle is accurately determined, thereby locking the occurrence time with a precision far exceeding that of the master clock cycle. Furthermore, the end-to-end time synchronization accuracy of the system can be further improved through high-resolution compensation values. The overall process includes: on the system side (first clock domain), generating a multi-phase sampling clock based on the master clock; on the SerDes side (second clock domain), generating a timestamp request signal at the start boundary of the data block; synchronizing this request signal to each phase clock domain to obtain multiple pulses; comparing the timing of these pulses to select a target sampling clock; using the edge of the target clock to latch the system timestamp, completing high-precision acquisition; subsequently, compensating the acquired timestamp using high-resolution compensation values ​​to generate a transmission timestamp and embedding it into the data block for transmission; the receiving end can parse the timestamp from the data block and perform tracking and regeneration. (Refer to...) Figure 1 , Figure 1 This is a flowchart illustrating the overall process of the asynchronous timestamp acquisition and compensation method provided in this embodiment of the invention. Figure 1 As shown, the details are as follows: The Serdes timestamp processing module operates in its own Clk_serdes clock domain, periodically generating a timestamp request signal Req (aligned data envelopment). Meanwhile, the TimeSync (i.e., the time base module) runs in the Clk_1g clock domain, outputting a real-time accumulated time count value Ts1 (incrementing by 1ns per clk), and performing 2n (n is a positive integer greater than or equal to 1) phase division processing on Clk_1g.

[0019] Req is processed by CDC (cross-clock domain synchronization) and transitioned to the Clk_1g clock domain with 2n equally divided phases, generating 2n synchronized pulse signals (Req1~Req2n) with different rising edge positions.

[0020] The SampleMux module receives Req1 to Req2n and filters out the last pulse at the rising edge position by comparing them in pairs, marking it as MuxReq.

[0021] The SampleTmp module latches the latest output Ts1 of TimeSync based on the clock phase N corresponding to MuxReq, and adds the corresponding deviation (1 / 2n). N), to obtain the accurate collection timestamp Sample Ts.

[0022] Sample Ts is transmitted to the Serdes timestamp processing module. After compensating Sample Ts, the Serdes timestamp processing module continuously regenerates high-precision timestamp Ts2 within the interval of the Req request.

[0023] The Serdes timestamp processing module transmits the regenerated high-precision timestamp Ts2 to the downstream Lane receiving timestamp module, providing a unified synchronization benchmark for multi-channel data and completing end-to-end time synchronization.

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0025] Firstly, embodiments of this application provide a timestamp collection method.

[0026] In one embodiment, reference is made to Figure 2 , Figure 2 This is a flowchart illustrating one embodiment of the timestamp collection method of this application. Figure 2 As shown, the timestamp collection methods include: Step S10: Based on the reference clock signal of the first clock domain, generate M sampling clock signals. The frequency of the M sampling clock signals is the same as the frequency of the reference clock signal, and their phases are uniformly distributed within one period of the reference clock signal. M is an even number. In a preferred embodiment, the first clock domain is the system master clock domain, whose reference clock signal CLK_SYS has a frequency of 1 GHz and a period of 1 nanosecond. The time reference module (TimeSync) is a counter operating in this clock domain, whose count value increments by 1 on each rising edge of CLK_SYS, thus each increment represents the elapsed time of 1 nanosecond. The second clock domain is the receive recovery clock domain of a SerDes module, whose clock CLK_SERDES is recovered from the received data stream and is asynchronous with CLK_SYS.

[0027] Taking M=4 as an example, a multi-phase clock generation circuit (e.g., a four-phase output DLL) is used to divide the 1GHz CLK_SYS into four equal phases, generating four sampling clock signals, each with a frequency of 1GHz but with phases differing by 90 degrees (i.e., 1 / 4 of a CLK_SYS cycle), denoted as CLK_P0, CLK_P1, CLK_P2, and CLK_P3. CLK_P0 has the same phase as CLK_SYS.

[0028] Furthermore, in one embodiment, generating M sampling clock signals based on the reference clock signal of the first clock domain includes: The reference clock signal in the first clock domain is phase interpolated or delayed by a phase-locked loop or a delay phase-locked loop to generate M sampled clock signals with the same frequency as the reference clock signal and whose phases are uniformly distributed within one period of the reference clock signal.

[0029] In this embodiment, M=4 is taken as an example. The specific circuit for generating four 1GHz sampling clock signals with uniform phase distribution can employ a delay phase-locked loop (DLL) based on a voltage-controlled delay line. This DLL uses CLK_SYS as the reference input and contains a series of delay units. Through feedback control, the total delay is made exactly equal to one reference clock cycle, and CLK_P0 to CLK_P3 are led out from four equally spaced tap points. As an alternative, a phase-locked loop (PLL) with four phase outputs can also be used, which directly generates the required multiphase clock through the multiphase output structure of its internal voltage-controlled oscillator.

[0030] Step S20: Synchronize the timestamp request signal originating from the second clock domain to the respective clock domains of the M sampled clock signals to obtain M synchronized pulse signals. The second clock domain is asynchronous with the first clock domain. In this embodiment, when the SerDes module detects the start boundary (such as the start of a frame symbol) of a data block to be sent, it generates a high-level pulse with a clock cycle width as a timestamp request signal req under its own recovery clock domain CLK_SERDES. Subsequently, four independent cross-clock domain synchronizers are set up, each consisting of two cascaded D flip-flops. The req signal is sent to the four synchronizers with clocks of CLK_P0, CLK_P1, CLK_P2, and CLK_P3, respectively. After synchronization processing, four synchronized pulse signals, denoted as req_SYNC0, req_SYNC1, req_SYNC2, and req_SYNC3, are obtained, each stabilized in its respective sampling clock domain. The rising edges of these synchronized pulse signals are staggered due to the different phases of their sampling clocks. In addition, considering the different clock frequencies on both sides of the asynchronous processing, the pulse needs to be widened during the transition to avoid the loss of edges that are not sampled during the CDC processing of req. Then, after transitioning to clk_p0~clk_p3, the rising edge is taken as the synchronized pulse signal, namely req_SYNC0~req_SYNC3 as described above.

[0031] Step S30: Perform timing comparison on the M synchronized pulse signals to determine the target sampling clock signal; In this embodiment, the input of a comparison logic module (SampleMux) is connected to req_SYNC0~req_SYNC3. This comparison logic module is configured to continuously compare the timing states of these four signals. Its core function is to identify which synchronized pulse signal is the last to transition from low to high. Identifying the last synchronized pulse signal to transition from low to high determines its corresponding sampling clock signal as the target sampling clock signal. For example, if the comparison logic determines that req_SYNC2 is the last to transition, then the target sampling clock signal is determined to be CLK_P2.

[0032] Step S40: In response to the effective clock edge of the target sampling clock signal, latch the latest time count value output by the time reference module, and compensate the latest time count value based on the phase information corresponding to the target sampling clock signal to obtain the acquisition timestamp corresponding to the timestamp request signal. The time reference module operates in the first clock domain and is used to generate continuously increasing time count values.

[0033] In this embodiment, when the effective rising edge (denoted as time t_edge) of the target sampling clock signal CLK_P2 arrives, a latch (e.g., within the SampleTmp module) immediately captures the latest time count value output by the TimeSync module counter CNT at this time. Since CNT updates at the edges of CLK_SYS, and CLK_P2 is a phase-shifted version of CLK_SYS, the value of CNT is deterministic and stable at time t_edge. Assume the latched CNT value is 100. This value CNT=100 represents a precise "integer nanosecond" moment (i.e., the boundary starting at 100 ns), but it does not yet contain information about the specific position of the timestamp request signal within the CLK_P2 period.

[0034] The system pre-sets a deviation Delta[N] corresponding to the phase number N of each sampled clock signal. For the case of a uniform 4-phase distribution (M=4), the deviation can be defined as: Delta[N] = N (T_sys / M) = N 0.25 ns. Therefore, Delta[0] = 0 ns, Delta[1] = 0.25 ns, Delta[2] = 0.5 ns, Delta[3] = 0.75 ns.

[0035] Since the target sampling clock signal is CLK_P2, and its corresponding phase number is N=2, the corresponding deviation Delta[2]=0.5ns.

[0036] Then the acquisition timestamp T_sample = latched CNT value + phase deviation Delta[N], which is T_sample = 100 + 0.5 = 100.5ns in the example above.

[0037] Reference Figure 3 , Figure 3 This is a schematic diagram illustrating the asynchronous timestamp acquisition principle using a 4-frequency division (M=4) example from one embodiment of this application. Figure 3 As shown, taking M=4 (4 equal phases) as an example: Clk_1g is divided into 4 phases (0°, 90°, 180°, 270°), corresponding to 4 equally divided clocks (clk_1g, clk_1g_90phase, clk_1g_180phase, clk_1g_270phase), subdividing the possible intervals of the timestamp request signal req into 4 intervals (each interval is 0.25ns).

[0038] After being processed by CDC, req generates four request pulses (req1-req4), corresponding to four typical distribution scenarios (covering four intervals: (-0.25, 0], (0, 0.25], (0.25, 0.5], and (0.5, 0.75]).

[0039] Under the Clk_1g clock, the error introduced by CDC is a constant 2ns by default, and the error range of each interval is controlled within [0, 0.25ns). By verifying by diff = acquisition timestamp - req actual timestamp, the final acquisition timestamp is taken from the starting value of the interval (e.g., when req is in (0.25, 0.5], the acquisition timestamp is 0.25), ensuring that the error is controllable.

[0040] In one embodiment, the clock domain in which the time base module operates should ideally ensure that the accumulated value for each clock cycle is divisible by M. This avoids introducing unnecessary errors due to the presence of an uneliminable decimal part in the compensation value when compensating for M sampling clocks, and further ensures the accuracy of the timestamp.

[0041] In this embodiment, multiple (M) sampling clocks with the same frequency and uniform phase distribution are generated to sample and synchronize the asynchronous timestamp request signal in parallel. Then, the timing of the multiple synchronized pulse signals is compared to determine a target sampling clock. Finally, the edge of this target clock is used to trigger the latching of the timestamp. This embodiment subdivides the entire master clock cycle in which the asynchronous request signal may occur into M time intervals. By selecting the target sampling clock, it is possible to determine which subdivision interval the asynchronous request signal actually falls into, thereby significantly reducing the acquisition error from ±1 master clock cycle in traditional methods to ± Within one master clock cycle. This method achieves an equivalent oversampling effect without actually increasing the system master clock frequency, significantly improving the timestamp acquisition accuracy, and the error range can be precisely controlled and predicted by selecting the M value.

[0042] Furthermore, in one embodiment, performing a timing comparison on the M synchronized pulse signals to determine the target sampling clock signal includes: Determine the target synchronized pulse signal that is the last of the M synchronized pulse signals to change from an invalid state to an effective state; use the sampling clock signal corresponding to the target synchronized pulse signal as the target sampling clock signal.

[0043] In this embodiment, refer to Figure 4 , Figure 4 This is a schematic diagram illustrating the pairwise comparison logic of the SampleMux module in one embodiment of this application. Figure 4 As shown, for ease of explanation, taking M=2 as an example, the timestamp request signal req is synchronized to the clock domain of the two sampling clock signals to obtain two synchronized pulse signals req1 and req2. After two-stage delay (req1_dff2, req2_dff2), they are synchronized under the Clk_1g and clk_1g_inv clocks respectively.

[0044] By comparing the pulse positions of the two synchronized pulse signals after the delay (the horizontal axis is time scale 0-6), it can be determined which synchronized pulse signal has a later rising edge.

[0045] It's easy to understand that for the case where M=4, an arbitration tree can be constructed using multi-level similar comparison logic. For example, first compare pairs (req1 and req2, req3 and req4), select the later one in the two groups, and then perform a final comparison between the two winners to determine the one that transitions latest among the four signals.

[0046] Furthermore, in one embodiment, the second clock domain is the recovery clock domain of the serializer / deserializer, and the timestamp request signal is periodically generated by the serializer / deserializer according to a preset request interval period, wherein the request interval period is greater than the time required for a complete timestamp acquisition process.

[0047] In this embodiment, the logic for generating the timestamp request signal is as follows: when the built-in counter reaches the requested interval period (this interval period can be set by the user, but it must be greater than the time required for a complete timestamp acquisition process), a timestamp request is generated for the first bit of the data block corresponding to the current clock cycle. The data block can be a FlexE client data block, an OTN frame, or an ETH frame. The recovered clock field CLK_SERDES is the clock recovered from the line by the serializer / deserializer receive channel and used for sampling the received data.

[0048] Secondly, embodiments of this application also provide a timestamp compensation method.

[0049] In one embodiment, reference is made to Figure 5 , Figure 5 This is a flowchart illustrating one embodiment of the timestamp compensation method of this application. Figure 5 As shown, the timestamp compensation methods include: Step S50: Obtain the acquisition timestamp corresponding to the timestamp request signal determined according to the asynchronous clock timestamp acquisition method as described in the first aspect; Step S60: Compensate the acquisition timestamp based on a preset compensation value to obtain a transmission timestamp, wherein the preset compensation value is used to compensate for the processing delay between the time corresponding to the acquisition timestamp and the time when the data block starts transmitting on the physical link.

[0050] In this embodiment, after high-precision acquisition is completed (the first timestamp compensation is performed), timestamp compensation is performed again. The system presets a compensation value register, which stores a fine quantization compensation value (i.e., the preset compensation value). This preset compensation value is used to compensate for the processing delay between the time corresponding to the acquisition timestamp and the time when the data block begins to be transmitted on the physical link.

[0051] Specifically, the "collection timestamp" (denoted as T_capture) obtained according to the method described in the first aspect is read, and the preset compensation value (denoted as Delta) is read. The transmission timestamp is obtained by addition: T_tx = T_capture + Delta.

[0052] Furthermore, in one embodiment, the preset compensation value is determined based on the service rate, the timestamp accuracy of the service requirements, and the data bit width of the data block.

[0053] In this embodiment, since there is a certain time between the issuance of the timestamp request signal and the return of the requested timestamp, the current timestamp cannot be obtained immediately from the moment the timestamp request signal is generated, and the returned timestamp does not correspond to the current timestamp. Therefore, further compensation is needed to obtain a more accurate timestamp. (Refer to...) Figure 6 , Figure 6 This is a schematic diagram illustrating the process of returning a timestamp request signal in one embodiment of this application. Figure 6 As shown, the acquisition timestamp can only be obtained in Serdes after 9 clock cycles after the timestamp request signal is sent, and the actual aligned position of the obtained timestamp should be the position of ts_req_cdc. Therefore, there are three sources of error that need to be supplemented for the returned timestamp: The timestamp request signal ts_req is processed by CDC, the number of pipeline stages consumed in acquiring timestamps at 1 GHz, and the CDC processing of the acquired timestamps transitioning back to Serdes.

[0054] Referring to the explanation in the first aspect, the error in the first part can be reduced to 1 / 2n (ns) as much as possible by dividing the clock into M (M=2n) equal parts.

[0055] Since the frequency relationship between the two clocks, clk_serdes and clk_1g, is uncertain, the error of the second CDC processing is difficult to define directly. Therefore, the second and third parts are considered together. Counting from the request ts_req to ts_valid, it can be seen that the number of pipeline stages consumed in the timestamp acquisition process in clk_serdes is n, meaning that a total of n CLK errors need to be compensated. For Serdes, each data packet contains 40 bits of data. Therefore, the error value of each 40-bit error is evenly distributed to each CLK according to the gap of the Serdes packet interval for different services, resulting in the error of each CLK, i.e., 40b_offset / gap. By quantizing the compensation value of the CLK, error compensation can be performed on the second and third parts.

[0056] The time configuration for each 40-bit data block under each valid data network is: 40b_offset = (40 2^fraction_ns) (1 / Lane_speed) When the service rate Lane_speed is specified, the accuracy range of error compensation can be improved simply by increasing the bit width of fraction_ns. For example, the accuracy of 40b_offset obtained with a bit width of 10 bits of fraction_ns is 0.0009765625ns < 1ps.

[0057] Using the 40b_offset error compensation value, the timestamp value that aligns with the data position can be continuously regenerated under Serdes_vld starting from each time the acquisition timestamp is returned, and refreshed in the next timestamp return, so as to reduce the accumulated error caused by the continuous accumulation of compensation value.

[0058] Furthermore, in one embodiment, the preset compensation value is expressed in the form of a fixed-point number.

[0059] In this embodiment, the preset compensation value Delta is stored and calculated in hardware in a fixed-point number format. For example, a 32-bit fixed-point number is used, where the high 16 bits represent the integer part (unit: nanoseconds) and the low 16 bits represent the fractional part. The weight of the least significant bit (LSB) of the fractional part is 1 / (2^16) ≈ 0.000015 nanoseconds, and this "smallest unit" is much smaller than the 1 nanosecond system clock cycle. Therefore, the system can configure the compensation value with an accuracy of approximately 15 picoseconds, thereby achieving extremely high-precision sub-nanosecond latency compensation. For example, if the measured processing latency is 5.125 nanoseconds, Delta can be precisely configured to the corresponding fixed-point value, thereby eliminating the impact of this latency in T_tx.

[0060] Thirdly, embodiments of this application also provide a timestamp acquisition device.

[0061] In one embodiment, reference is made to Figure 7 , Figure 7 This is a functional module diagram of an embodiment of the timestamp acquisition device of this application. Figure 7 The timestamp acquisition device includes: The generation module 10 is used to generate M sampled clock signals based on the reference clock signal of the first clock domain. The frequency of the M sampled clock signals is the same as the frequency of the reference clock signal, and their phases are uniformly distributed within one period of the reference clock signal. M is an even number. Synchronization module 20 is used to synchronize the timestamp request signal originating from the second clock domain to the respective clock domains of the M sampled clock signals to obtain M synchronized pulse signals, wherein the second clock domain is asynchronous with the first clock domain; The filtering module 30 is used to perform timing comparison on the M synchronized pulse signals to determine the target sampling clock signal; The latch module 40 is used to latch the latest time count value output by the time base module in response to the effective clock edge of the target sampling clock signal, and to compensate the latest time count value based on the phase information corresponding to the target sampling clock signal to obtain the acquisition timestamp corresponding to the timestamp request signal. The time base module operates in the first clock domain and is used to generate continuously increasing time count values.

[0062] Furthermore, in one embodiment, the generation module 10 is used for: The reference clock signal in the first clock domain is phase interpolated or delayed by a phase-locked loop or a delay phase-locked loop to generate M sampled clock signals with the same frequency as the reference clock signal and whose phases are uniformly distributed within one period of the reference clock signal.

[0063] Furthermore, in one embodiment, the screening module 30 is used for: Determine the target synchronized pulse signal that is the last of the M synchronized pulse signals to transition from an invalid state to an effective state. The sampling clock signal corresponding to the target synchronized pulse signal is taken as the target sampling clock signal.

[0064] Furthermore, in one embodiment, the second clock domain is the recovery clock domain of the serializer / deserializer, and the timestamp request signal is periodically generated by the serializer / deserializer according to a preset request interval period, wherein the request interval period is greater than the time required for a complete timestamp acquisition process.

[0065] For specific embodiments of the third aspect, please refer to the various embodiments of the first aspect, which will not be repeated here.

[0066] Fourthly, embodiments of this application also provide a timestamp compensation device.

[0067] In one embodiment, reference is made to Figure 8 , Figure 8 This is a functional module diagram of an embodiment of the timestamp compensation device of this application. Figure 8 As shown, the timestamp compensation device includes: The acquisition module 50 is used to acquire the acquisition timestamp corresponding to the timestamp request signal determined according to the asynchronous clock timestamp acquisition method as described in the first aspect. The compensation module 60 is used to compensate the acquisition timestamp based on a preset compensation value to obtain a transmission timestamp, wherein the preset compensation value is used to compensate for the processing delay between the time corresponding to the acquisition timestamp and the time when the data block starts to be transmitted on the physical link.

[0068] Furthermore, in one embodiment, the preset compensation value is determined based on the service rate, the timestamp accuracy of the service requirements, and the data bit width of the data block.

[0069] Furthermore, in one embodiment, the preset compensation value is expressed in the form of a fixed-point number.

[0070] For specific embodiments of the fourth aspect, please refer to the various embodiments of the second aspect, which will not be repeated here.

[0071] Fifthly, embodiments of this application also provide a clock timing system.

[0072] In one embodiment, the clock timing system includes a timestamp acquisition device as described in the third aspect and a timestamp compensation device as described in the fourth aspect.

[0073] For specific embodiments of the fifth aspect, please refer to the embodiments of the first and second aspects, which will not be repeated here.

[0074] It should be noted that the sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0075] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. The terms "first," "second," and "third," etc., are used to distinguish different objects, etc., and do not indicate a sequence, nor do they limit "first," "second," and "third" to different types.

[0076] In the description of the embodiments of this application, terms such as "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a concrete manner.

[0077] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0078] In some processes described in the embodiments of this application, multiple operations or steps are included in a specific order. However, it should be understood that these operations or steps may not be executed in the order they appear in the embodiments of this application, or they may be executed in parallel. The sequence number of the operation is only used to distinguish different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed sequentially or in parallel, and these operations or steps may be combined.

[0079] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device to execute the methods described in the various embodiments of this application.

[0080] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A timestamp acquisition method, characterized in that, The timestamp acquisition method includes: Based on the reference clock signal in the first clock domain, M sampled clock signals are generated. The frequencies of the M sampled clock signals are the same as the frequency of the reference clock signal, and their phases are uniformly distributed within one period of the reference clock signal. M is an even number. The timestamp request signal originating from the second clock domain is synchronized to the clock domain of each of the M sampled clock signals to obtain M synchronized pulse signals, wherein the second clock domain is asynchronous with the first clock domain; The timing of the M synchronized pulse signals is compared to determine the target sampling clock signal; In response to the effective clock edge of the target sampling clock signal, the latest time count value output by the time reference module is latched, and the latest time count value is compensated based on the phase information corresponding to the target sampling clock signal to obtain the acquisition timestamp corresponding to the timestamp request signal. The time reference module operates in the first clock domain and is used to generate continuously increasing time count values.

2. The timestamp acquisition method as described in claim 1, characterized in that, Based on the reference clock signal in the first clock domain, M sampled clock signals are generated, including: The reference clock signal in the first clock domain is phase interpolated or delayed by a phase-locked loop or a delay phase-locked loop to generate M sampled clock signals with the same frequency as the reference clock signal and whose phases are uniformly distributed within one period of the reference clock signal.

3. The timestamp acquisition method as described in claim 1, characterized in that, The timing comparison of the M synchronized pulse signals to determine the target sampling clock signal includes: Determine the target synchronized pulse signal that is the last of the M synchronized pulse signals to transition from an invalid state to an effective state. The sampling clock signal corresponding to the target synchronized pulse signal is taken as the target sampling clock signal.

4. The timestamp acquisition method as described in claim 1, characterized in that, The second clock domain is the recovery clock domain of the serializer / deserializer. The timestamp request signal is generated periodically by the serializer / deserializer according to a preset request interval period, wherein the request interval period is greater than the time required for a complete timestamp acquisition process.

5. A timestamp compensation method, characterized in that, The timestamp compensation method includes: Obtain the acquisition timestamp corresponding to the timestamp request signal determined according to the asynchronous clock timestamp acquisition method as described in any one of claims 1 to 4; The acquisition timestamp is compensated based on a preset compensation value to obtain a transmission timestamp, wherein the preset compensation value is used to compensate for the processing delay between the time corresponding to the acquisition timestamp and the time when the data block starts to be transmitted on the physical link.

6. The timestamp compensation method as described in claim 5, characterized in that, The preset compensation value is determined based on the service rate, the timestamp accuracy required by the service, and the data bit width of the data block.

7. The timestamp compensation method as described in claim 6, characterized in that, The preset compensation value is expressed in the form of a fixed-point number.

8. A timestamp acquisition device, characterized in that, The timestamp acquisition device includes: The generation module is used to generate M sampled clock signals based on the reference clock signal of the first clock domain. The frequency of the M sampled clock signals is the same as the frequency of the reference clock signal, and their phases are uniformly distributed within one period of the reference clock signal. M is an even number. The synchronization module is used to synchronize the timestamp request signal originating from the second clock domain to the respective clock domains of the M sampled clock signals to obtain M synchronized pulse signals, wherein the second clock domain is asynchronous with the first clock domain; The filtering module is used to perform timing comparison on the M synchronized pulse signals to determine the target sampling clock signal; A latch module is used to latch the latest time count value output by the time base module in response to the effective clock edge of the target sampling clock signal, and use it as the acquisition timestamp corresponding to the timestamp request signal. The time base module operates in the first clock domain and is used to generate continuously increasing time count values.

9. A timestamp compensation device, characterized in that, The timestamp compensation device includes: The acquisition module is used to acquire the acquisition timestamp corresponding to the timestamp request signal determined according to the asynchronous clock timestamp acquisition method as described in any one of claims 1 to 4; The compensation module is used to compensate the acquisition timestamp based on a preset compensation value to obtain the transmission timestamp, wherein the preset compensation value is used to compensate for the processing delay between the time corresponding to the acquisition timestamp and the time when the data block starts to be transmitted on the physical link.

10. A clock timing system, characterized in that, The clock time system includes the timestamp acquisition device as described in claim 8 and the timestamp compensation device as described in claim 9.

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