A high-speed parallel bit synchronization loop design method and system based on FPGA

Abstract

This invention belongs to the field of signal synchronization technology in digital communication systems. It discloses a high-speed parallel bit synchronization loop design method based on FPGA. This invention adopts a collaborative design of parallel Farrow filter banks and grouped Gardner error detectors to significantly improve the throughput of bit synchronization loop calculation and overcome the limitation of FPGA clock rate on data processing. Through mean aggregation and k-fold phase error amortization mechanism, the multiple errors generated by parallel calculation are converged to a unified control word, which not only retains the efficiency of parallel architecture but also ensures loop stability. A parallel shift memory space and address pointer linkage mechanism is adopted, and the initial read position pointer is dynamically adjusted through feedback from a numerically controlled oscillator to achieve symbol phase deviation compensation without large-scale data copying. A 3*k depth parallel memory space is implemented through a shift register chain. With the multiplier multiplexing strategy, it is more friendly to hardware resources and easier to deploy in mainstream FPGA hardware.

Description

Technical Field

[0001] This invention belongs to the field of signal synchronization technology in digital communication systems, and particularly relates to a high-speed parallel bit synchronization loop design method and system based on FPGA. Background Technology

[0002] In digital communication systems, bit synchronization is one of the core technologies for ensuring correct signal demodulation at the receiver. Its key function is to ensure that the receiver can accurately identify the start time of transmitted symbols, thereby eliminating the impact of clock skew on signal demodulation. If bit synchronization fails, inter-symbol interference (ISI) will be significantly aggravated, leading to a sharp increase in the bit error rate (BER), and even causing communication link interruption. By adaptively adjusting the sampling clock phase through bit synchronization, the dynamic deviation between the clock phase and the symbol phase during signal sampling can be compensated in real time.

[0003] Traditional bit synchronization loops employ a serial processing mode, with basic procedures including interpolation filtering, timing error detection, loop filtering, and voltage-controlled oscillator control. However, as communication speeds increase, the system clock rate of FPGA hardware has begun to lag behind the sampling rate of the ADC and even the symbol rate of the baseband signal. Serial processing bit synchronization loops are no longer suitable for use in communication environments approaching or exceeding Gbps.

[0004] The invention patent with patent number CN119484743A discloses an FPGA implementation method for a DVB high-speed demodulator. The parallel bit synchronization method is a frequency domain phase estimation method. Its implementation involves complex exponential multiplication and large window accumulation, which requires more resources to implement in the computation of numerically controlled oscillators.

[0005] The invention patent with patent number CN114422062A discloses a communication synchronization method for an inter-satellite laser communication system based on FPGA. It introduces a parallel bit synchronization method based on identifying a specific code rate. This method has bit synchronization capability on a specific codeword, but its versatility is not strong.

[0006] The invention patent with patent number CN106130507A discloses a high-speed parallel bit synchronization filter time-varying coefficient update loop. This algorithm mainly relies on pre-calculated parallel filter banks stored in RAM and uses the interpolation offset calculated by a numerically controlled oscillator to read the filter coefficients of the parallel filter, thereby reducing the use of multiplier resources and increasing the real-time performance of the calculation. However, this method will use more RAM resources and its accuracy will also be negatively affected.

[0007] Based on the above analysis, the problems and shortcomings of the existing technology are as follows: As communication speeds increase, the system clock rate of FPGA hardware has begun to be slower than the sampling rate of the ADC and even slower than the symbol rate of the baseband signal. The bit synchronization ring in serial processing mode is no longer suitable for use in communication environments that are close to or even exceed Gbps. Summary of the Invention

[0008] To address the problems existing in the prior art, this invention provides a high-speed parallel bit synchronization loop design method based on FPGA.

[0009] This invention is implemented as follows: A high-speed parallel bit synchronization loop design method based on FPGA includes: Step S1, write k parallel sampling points X(k) Parallel shift storage space of length; During a single write operation, k sample points are written to the corresponding register clock via shifting or address pointers; the rest... The length register stores the k sampling points written in the first two writes, and according to... Selecting values ​​backward The k most recently written sample points are used as input to the parallel Farrow filter (the k most recently written sample points correspond to the positions in the...). The total index of the parallel shift storage space is The number of parallel operations k is an even multiple of sps, and sps is the oversampling factor and equal to 4 (if it is greater than 4, it is recommended to connect a downsampling extraction module in series before this module to make the oversampling factor reach 4). Read the start pointer for the Farrow filter and initialize it with k; Step S2, divide the k+sps sampling points into groups based on the number of symbols, with a step size of half a symbol length and a range of one symbol length. Group; (e.g.) Group 1 (This is the second group, and so on), each group corresponds to sampling points. Calculate it using equations (1) to (4) to obtain The output of a parallel Farrow filter ; The fractional interval of the numerically controlled oscillator output. The value can be based on The result is obtained by looking up a table (which can be written as a LUT table or a ROM table, based on...). The range of values ​​allows for table lookup to obtain... The error has a relatively small impact on the result. , , 3 can be achieved through shifting. The calculation requires the use of two multipliers to calculate the output of the numerically controlled oscillator. and its square and , The product; (1) (2) (3) (4) Step S3, take the output of step S2 Group them into groups of three; And except and The end of each group is the beginning of another group (e.g.) Group 1 (This is the second group, and so on). Each group is input into the Gardner timing error detector. The timing error detection method is determined by the modulation method of the signal. For example, the timing error detection method of BPSK follows equation (6), and the timing error detection method of QPSK follows equation (7). The timing error detection methods corresponding to more complex modulation methods will not be described here. The timing error obtained in this step is... indivual; (5) (6) (7) Step S4, take the output of step S3 Find the average value Based on the baseband signal correlation parameters, loop filter coefficients C1 and C2 are designed, and a loop filter composed of C1 and C2 is used to... and The control word is obtained through calculation. Design and control word of loop filter coefficients C1 and C2 The calculation involves knowledge related to loop filters. Step S5 involves setting the control word... Input to the numerically controlled oscillator, the register of the numerically controlled oscillator corresponds to the control word Perform accumulation and modulo 1; And based on the register modulo overflow, the distance between the current sampling point and the optimal sampling point is determined. When accumulating the control word and taking the modulo with 1, the formula (8) is followed, that is, the control word When accumulating, the value should be multiplied by the number of parallel inputs k to ensure that the cumulative phase error generated by the k inputs is included in the register value of the numerically controlled oscillator. ; through register value The fractional interval can be obtained by following equation (9). ,because After stabilizing, it tends to 0.5, therefore, in calculating the fractional interval... Directly to Simply shift one position to the left. (8) (9) S6, in comparison and The value is used to determine whether a jump has occurred. If so, it means that the distance between the current sampling point and the optimal sampling point exceeds one sampling point. In this case, the value is used to determine whether a jump has occurred. Adjustments will be made, specifically. When overflow Add 1, When overflow Decrease by 1 to make the Farrow filter closer to the optimal sampling point at the start of the next readout; Step S7, after the loop stabilizes, output the first... Each value is output as a bit synchronization result.

[0010] Furthermore, the parallel shift storage space, parallel Farrow filter, parallel Gardner timing error detector, loop filter, and numerically controlled oscillator are characterized in that: within a single clock cycle, there are a total of k sampling points (denoted as ) input to the high-speed parallel bit synchronization loop; the parallel shift storage space stores a total of 3k sampling points X(t), X(tk), and X(t-2k) for three consecutive clock cycles; during a single calculation, k+sps sampling points (sps being the oversampling factor) are selected from the i-th sampling point onwards as the input of the parallel Farrow filter (initial value is k) and 2*k / sps+1 outputs are obtained; the 2*k / sps+1 values ​​output by the Farrow filter are input to the parallel Gardner timing error detector to obtain k / sps+1 outputs as timing errors; the average value of the k / sps+1 timing errors is calculated and input to the loop filter to obtain a control word; the control word is input to the numerically controlled oscillator to obtain a phase control value; adjustments are made based on the overflow of the phase control value and the input is entered into the next round of bit synchronization loop until the loop tends to stabilize; A loop is formed by a parallel Farrow filter, a parallel Gardner timing error detector, a loop filter, and a numerically controlled oscillator. The phase control value output by the numerically controlled oscillator controls the position of the parallel Farrow filter reading the parallel shift memory space, thus forming a feedback loop. The output of the parallel Farrow filter is used as the output of the parallel bit synchronization loop; A single shift input must have at least two symbols, and the number of symbols must be even. The oversampling factor (sps) for each symbol must be at least 4, meaning the number of sampling points (k) per shift input must be at least 8. Only by meeting these conditions can the calculations of the parallel Farrow filter and the parallel Gardner timing error detector proceed normally. Storage space can be provided by shift registers or a combination of registers and address pointers.

[0011] Furthermore, the parallel Farrow filter consists of multiple basic Farrow filters, with the number of basic Farrow filters being 2*k / sps+1. Each basic Farrow filter calculates the symbols corresponding to the k+sps sampling points of the input separately, and this calculation is a parallel calculation. Each input must have at least four sampling points and require the output of a numerically controlled oscillator. The calculation requires a lookup table and two multipliers.

[0012] Furthermore, the outputs of the 2*k / sps+1 parallel Farrow filters are grouped into groups of three, and the last value of each group is the first value of the next group, except for the first two results. The error detection method is selected according to the modulation scheme. For example, in BPSK, the difference between the middle value of each group and the two preceding and following values ​​is multiplied as the output result of the Gardner timing error detector, i.e., the phase error. At this time, the number of output values ​​of the parallel Gardner timing error detector is k / sps.

[0013] Furthermore, the mean value of k / sps+1 phase error values ​​of the Gardner timing error detector output is calculated, and the control word is obtained from the values ​​of proportional coefficient C1 and integral coefficient C2.

[0014] Furthermore, the loop filter output control word is accumulated using a register value µ with an initial value of µ_0, and µ is continuously updated by taking the modulus of the accumulated result with 1. The value of µ is incremented or decremented by 1 according to the overflow and underflow pairs of µ. The registered value µ is characterized in that the accumulated ω_n when updating µ is multiplied by k. This operation can distribute the control word calculated by k sampling points to the next loop calculation. The range of µ is [0,1).

[0015] Another objective of this invention is to provide a high-speed parallel bit synchronization loop design system based on FPGA, comprising: The sampling module is used for writing k parallel sampling points X(k). The length is a parallel shift memory space; during a single write, k sampling points are written to the corresponding register clock via shift or address pointer, and the rest... The length register stores the k sampling points written in the first two writes, and according to... Selecting values ​​backward The k most recently written sample points are used as input to the parallel Farrow filter (the k most recently written sample points correspond to the positions in the...). The total index of the parallel shift storage space is The number of parallel operations k is an even multiple of sps, and sps is the oversampling factor and equal to 4 (if it is greater than 4, it is recommended to connect a downsampling extraction module in series before this module to make the oversampling factor reach 4). Read the start pointer for the Farrow filter and initialize it with k; The calculation module is used to divide the k+sps sampling points into a range based on the number of symbols, with a step size of half a symbol length and a range of one symbol length. Group; (e.g.) Group 1 (This is the second group, and so on), each group corresponds to sampling points. Calculate it using equations (1) to (4) to obtain The output of a parallel Farrow filter ; The fractional interval of the numerically controlled oscillator output. The value can be based on The result is obtained by looking up a table (which can be written as a LUT table or a ROM table, based on...). The range of values ​​allows for table lookup to obtain... The error has a relatively small impact on the result. , , 3 can be achieved through shifting. The calculation requires the use of two multipliers to calculate the output of the numerically controlled oscillator. and its square and , The product; (1) (2) (3) (4) The grouping module is used to group the output of step S2. Group them into groups of three; and except and The end of each group is the beginning of another group (e.g.) Group 1 (This is the second group, and so on). Each group is input into the Gardner timing error detector. The timing error detection method is determined by the modulation method of the signal. For example, the timing error detection method of BPSK follows equation (6), and the timing error detection method of QPSK follows equation (7). The timing error detection methods corresponding to more complex modulation methods will not be described here. The timing error obtained in this step is... indivual; (5) (6) (7) The mean calculation module is used to calculate the output of step S3. Find the average value Based on the baseband signal correlation parameters, loop filter coefficients C1 and C2 are designed, and a loop filter composed of C1 and C2 is used to... and The control word is obtained through calculation. Design and control word of loop filter coefficients C1 and C2 The calculation involves knowledge related to loop filters, and the modulus module is used to convert the control word... Input to the numerically controlled oscillator, the register of the numerically controlled oscillator corresponds to the control word Perform accumulation and modulo 1; And based on the register modulo overflow, the distance between the current sampling point and the optimal sampling point is determined. When accumulating the control word and taking the modulo with 1, the formula (8) is followed, that is, the control word When accumulating, the value should be multiplied by the number of parallel inputs k to ensure that the cumulative phase error generated by the k inputs is included in the register value of the numerically controlled oscillator. ; through register value The fractional interval can be obtained by following equation (9). ,because After stabilizing, it tends to 0.5, therefore, in calculating the fractional interval... Directly to Simply shift one position to the left. (8) (9) The judgment module is used for comparison. and The value is used to determine whether a jump has occurred. If so, it means that the distance between the current sampling point and the optimal sampling point exceeds one sampling point. In this case, the value is used to determine whether a jump has occurred. Adjustments will be made, specifically. When overflow Add 1, When overflow Decrease by 1 to make the Farrow filter closer to the optimal sampling point at the start of the next readout; The output module is used to output the first value of the Farrow filter after the loop has stabilized. Each value is output as a bit synchronization result.

[0016] Another object of the present invention is to provide a computer device including a memory and a processor, the memory storing a computer program, which, when executed by the processor, causes the processor to perform the steps of the FPGA-based high-speed parallel bit synchronization loop design method.

[0017] Another object of the present invention is to provide a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the steps of the FPGA-based high-speed parallel bit synchronization loop design method.

[0018] Another objective of this invention is to provide an information data processing terminal for implementing the FPGA-based high-speed parallel bit synchronization loop design system.

[0019] Based on the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solution to be protected by this invention are as follows: First, the solution provided by this invention addresses the symbol synchronization problem in high-speed communication scenarios. Through parallel architecture design, the symbol synchronization algorithm adapts to the requirements of parallel processing of baseband data in high-speed communication, making it particularly suitable for situations where the symbol rate or sampling rate is several times higher than the hardware clock and serial methods cannot be used for symbol synchronization. This invention achieves parallel processing of multiple sampling points within a single clock cycle through the collaborative design of parallel shift storage space, parallel Farrow filters, and parallel Gardner timing error detectors, combined with an optimized loop control mechanism, significantly improving the throughput of the synchronization loop.

[0020] This invention proposes a method for implementing a high-speed parallel bit synchronization loop under FPGA, introducing the following key technical points: 1. By decoupling Farrow interpolation and Gardner error detection into parallel computing units, pipeline throughput is significantly optimized; 2. By incorporating the inputs of the loop filter and the numerically controlled oscillator into the mean value of the parallel computation, a precise match between parallelism and computational accuracy is achieved; 3. A parallel shift storage space is introduced at the loop input terminal, and the initial read value of the parallel shift storage space is adjusted by the output of the numerically controlled oscillator, so as to realize the shift reading of the optimal sampling point when the bit synchronization loop detects that the sampling point is ahead or behind.

[0021] This invention, through its innovative parallel architecture design and loop control mechanism, offers the following advantages in high-speed communication scenarios: The co-design of parallel Farrow filter banks and grouped Gardner error detectors significantly improves the throughput of bit synchronization loop computation, breaking through the limitation of FPGA clock rate on data processing. By using mean aggregation and k-fold phase error amortization mechanism, the multi-path errors generated by parallel computing are converged to a unified control word, which not only preserves the efficiency of the parallel architecture but also ensures loop stability. A parallel shift memory space and address pointer linkage mechanism is adopted, and the initial read position pointer is dynamically adjusted through feedback from a numerically controlled oscillator to achieve symbol phase deviation compensation while avoiding large-scale data copying; By implementing a 3*k depth parallel storage space through a shift register chain, and in conjunction with a multiplier multiplexing strategy, it becomes more hardware resource-friendly and easier to deploy in mainstream FPGA hardware.

[0022] Secondly, this invention provides a method for implementing bit synchronization loops within the FPGA when the sampling frequency or even symbol rate of the baseband signal acquired by the AD converter is much higher than the clock frequency of the FPGA chip, by changing the bit synchronization loop from a traditional serial structure to a parallel structure. This method addresses the problem of FPGA clock frequency limitations in high-speed communication scenarios. Its core lies in the collaborative design of parallel shift storage space, parallel Farrow filter banks, parallel Gardner error detectors, loop filters, and numerically controlled oscillators to extract parallel input sampling points acquired by the AD converter. It optimizes the Farrow filter and Gardner error detector of the bit synchronization loop for parallel processing and innovatively introduces parallel shift storage space to read the start pointer of the Farrow filter. The control simulation of the overflow of the traditional serial numerically controlled oscillator starts the bit synchronization ring calculation, so that the architecture of the bit synchronization ring can be adapted to the sampling points of parallel input.

[0023] In the bit synchronization loop calculation under this parallel structure, the timing error calculated by the parallel Farrow filter and the parallel Gardner error detector is the average timing error of all sampling points in the input parallel loop. This average value represents the offset of all sampling points in a single input loop from the optimal sampling point. This calculation result can be directly connected to the structure of the loop filter and numerically controlled oscillator in a traditional bit synchronization loop. Since the timing error result of a single calculation is based on multiple parallel sampling points, the calculation of the numerically controlled oscillator should calculate the overflow situation according to the number of parallel sampling points in the input loop. The Farrow filter reads the start pointer by adjusting the overflow or underflow of the numerically controlled oscillator to access the parallel shift storage space. This allows for the search for the optimal sampling point when the current sampling point is more than one sampling point away from the optimal sampling point; while when the current sampling point is less than one sampling point away from the optimal sampling point, the timing error obtained from the parallel sampling points of the input loop is passed through the loop filter, and the output is used to control the Farrow filter.

[0024] This invention innovatively adjusts the overflow mechanism of the numerically controlled oscillator (CNC) in the bit synchronization loop. By parallelizing the calculations of the Farrow filter and Gardner error detector, and using parallel shift storage space in conjunction with the CNC oscillator overflow mechanism, the bit synchronization loop can perform calculations on parallel input signals. The new method provided by this invention retains all the structural elements of the bit synchronization loop, only adjusting the overflow mechanism of the CNC oscillator and the calculations of the Farrow filter and Gardner error detector. Its implementation in FPGA has sufficient reference value, and functionally it is no different from traditional bit synchronization loops. Attached Figure Description

[0025] Figure 1 This is a flowchart of a high-speed parallel bit synchronization loop design method based on FPGA provided in an embodiment of the present invention.

[0026] Figure 2 This is a system structure block diagram of the high-speed parallel bit synchronization loop design method based on FPGA provided in the embodiments of the present invention.

[0027] Figure 3 This is a schematic diagram of the overall high-speed parallel bit synchronization loop provided in an embodiment of the present invention.

[0028] Figure 4 This is a schematic diagram of parallel Farrow filter calculation when k=16 provided in an embodiment of the present invention.

[0029] Figure 5 This is a schematic diagram of the parallel Gardner error detector calculation when k=16 provided in an embodiment of the present invention.

[0030] Figure 6 is a comparison of the simulation results of the parallel bit synchronization ring and the traditional bit synchronization ring provided in the embodiment of the present invention, where (1) is the result of the traditional bit synchronization ring and (2) is the result of the parallel bit synchronization ring of the present invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0032] like Figure 1As shown in the figure, the high-speed parallel bit synchronization loop design method based on FPGA provided by this embodiment of the invention includes the following steps: Step S1, write k parallel sampling points X(k) The length of the parallel shift storage space, k is the number of parallel inputs to the high-speed parallel bit synchronization loop data of the FPGA, and X(k) represents the set of sampling points of the input high-speed parallel bit synchronization loop. During a single write operation, k sample points are written to the corresponding registers via shifting or address pointers; the rest... The length register stores the k sample points written in the first two writes, and the start pointer is read according to the Farrow filter. Selecting values ​​backward The k most recently written sample points are used as input to the parallel Farrow filter (the k most recently written sample points correspond to the positions in the...). The total index of the parallel shift storage space is The number of parallel operations, k, is an even multiple of SPS, where SPS is the oversampling factor and equals 4 (if the oversampling factor of the input bit synchronization loop signal is greater than 4, it is recommended to connect a downsampling decimation module in series before this module to make the oversampling factor reach 4). The Farrow filter reads the start pointer. The initial value is k; Step S2, divide the k+sps sampling points into groups based on the number of symbols, with a step size of half a symbol length and a range of one symbol length. Group; (e.g.) Group 1 (This is the second group, and so on), each group corresponds to sampling points. Calculate it using equations (1) to (4) to obtain The output of a parallel Farrow filter ; The fractional interval of the numerically controlled oscillator output. The value can be based on The result is obtained by looking up a table (which can be written as a LUT table or a ROM table, based on...). The range of values ​​allows for table lookup to obtain... The error has a relatively small impact on the result. , , 3 can be achieved through shifting. The calculation requires the use of two multipliers to calculate the output of the numerically controlled oscillator. and its square and , The product; (1) (2) (3) (4) Step S3, take the output of step S2 Group them into groups of three; And except and The end of each group is the beginning of another group (e.g.) Group 1 (This is the second group, and so on). Each group is input into the Gardner timing error detector. The timing error detection method is determined by the modulation method of the signal. For example, the timing error detection method of BPSK follows equation (6), and the timing error detection method of QPSK follows equation (7). The timing error detection methods corresponding to more complex modulation methods will not be described here. The timing error obtained in this step... common indivual; (5) (6) (7) Step S4, take the output of step S3 The mean of the timing error at time t is obtained by calculating the mean. Based on the baseband signal correlation parameters, loop filter coefficients C1 and C2 are designed, and a loop filter composed of C1 and C2 is used to... and The control word is obtained through calculation. Design and control word of loop filter coefficients C1 and C2 The calculation involves knowledge related to loop filters. Step S5 involves setting the control word... Input to the numerically controlled oscillator, the register of the numerically controlled oscillator corresponds to the control word Perform accumulation and modulo 1; And based on the register modulo overflow, the distance between the current sampling point and the optimal sampling point is determined. When accumulating the control word and taking the modulo with 1, the formula (8) is followed, that is, the control word When accumulating, the value should be multiplied by the number of parallel inputs k to ensure that the cumulative phase error generated by the k inputs is included in the register value of the numerically controlled oscillator. ; through register value The fractional interval can be obtained by following equation (9). ,because After stabilizing, it tends to 0.5, therefore, in calculating the fractional interval... Directly to Simply shift one position to the left. (8) (9) S6, in comparison and The value is used to determine whether a jump has occurred. If so, it means that the distance between the current sampling point and the optimal sampling point exceeds one sampling point. In this case, the value is used to determine whether a jump has occurred. Adjustments will be made, specifically. When overflow Add 1, When overflow Decrease by 1 to make the Farrow filter closer to the optimal sampling point at the start of the next readout; Step S7, after the loop stabilizes, output the first... Each value is output as a bit synchronization result.

[0033] The parallel shift storage space, parallel Farrow filter, parallel Gardner timing error detector, loop filter, and numerically controlled oscillator provided in this embodiment of the invention are characterized in that: a total of k sampling points (denoted as ) are input to the high-speed parallel bit synchronization loop in a single clock cycle; the parallel shift storage space stores a total of 3k sampling points X(t), X(tk), and X(t-2k) for three consecutive clock cycles; during a single calculation, k+sps sampling points (sps being the oversampling factor) are selected from the i-th sampling point onwards as the input of the parallel Farrow filter (initial value is k) and 2*k / sps+1 outputs are obtained; the 2*k / sps+1 values ​​output by the Farrow filter are input to the parallel Gardner timing error detector to obtain k / sps+1 outputs as timing errors; the average value of the k / sps+1 timing errors is calculated and input to the loop filter to obtain a control word; the control word is input to the numerically controlled oscillator to obtain a phase control value; adjustments are made according to the overflow of the phase control value and the input is entered into the next round of bit synchronization loop until the loop tends to stabilize; A loop is formed by a parallel Farrow filter, a parallel Gardner timing error detector, a loop filter, and a numerically controlled oscillator. The phase control value output by the numerically controlled oscillator controls the position of the parallel Farrow filter reading the parallel shift memory space, thus forming a feedback loop. The output of the parallel Farrow filter is used as the output of the parallel bit synchronization loop; A single shift input must have at least two symbols, and the number of symbols must be even. The oversampling factor (sps) for each symbol must be at least 4, meaning the number of sampling points (k) per shift input must be at least 8. Only by meeting these conditions can the calculations of the parallel Farrow filter and the parallel Gardner timing error detector proceed normally. Storage space can be provided by shift registers or a combination of registers and address pointers.

[0034] The parallel Farrow filter provided in this embodiment of the invention consists of multiple basic Farrow filters. The number of basic Farrow filters is 2*k / sps+1. Each basic Farrow filter calculates the symbols corresponding to the k+sps sampling points of the input separately. This calculation is a parallel calculation. Each input must have at least four sampling points and require the output of a numerically controlled oscillator. The calculation requires a lookup table and two multipliers.

[0035] The present invention provides a method for grouping the outputs of 2*k / sps+1 parallel Farrow filters into groups of three, with the last value of each group being the first value of the next group, except for the first two results. An error detection method is selected according to the modulation scheme. For example, in BPSK, the difference between the middle value of each group and the two preceding and following values ​​is multiplied to obtain the output result of the Gardner timing error detector, i.e., the phase error. At this time, the number of output values ​​of the parallel Gardner timing error detector is k / sps.

[0036] The calculation input value provided in this embodiment of the invention is the average of k / sps+1 phase error values ​​of the Gardner timing error detector output, and the control word is calculated from the values ​​of the proportional coefficient C1 and the integral coefficient C2.

[0037] The embodiment of the present invention provides that the loop filter output control word is accumulated by a register value µ with an initial value of µ_0, and µ is continuously updated by taking the modulo of the accumulation result with 1. The value of µ is incremented or decremented by 1 according to the overflow and underflow pair of µ. The registered value µ is characterized in that the accumulated ω_n when updating µ is multiplied by k. This operation can distribute the control word calculated by k sampling points to the next loop calculation. The range of µ is [0,1).

[0038] like Figure 2 As shown in the figure, an embodiment of the present invention provides a high-speed parallel bit synchronization loop design system based on FPGA, comprising: The sampling module is used for writing k parallel sampling points X(k). The length is a parallel shift memory space; during a single write, k sampling points are written to the corresponding register clock via shift or address pointer, and the rest... The length register stores the k sampling points written in the first two writes, and according to... Selecting values ​​backward The k most recently written sample points are used as input to the parallel Farrow filter (the k most recently written sample points correspond to the positions in the...). The total index of the parallel shift storage space is The number of parallel operations k is an even multiple of sps, and sps is the oversampling factor and equal to 4 (if it is greater than 4, it is recommended to connect a downsampling extraction module in series before this module to make the oversampling factor reach 4). Read the start pointer for the Farrow filter and initialize it with k; The calculation module is used to divide the k+sps sampling points into a range based on the number of symbols, with a step size of half a symbol length and a range of one symbol length. Group; (e.g.) Group 1 (This is the second group, and so on), each group corresponds to sampling points. Calculate it using equations (1) to (4) to obtain The output of a parallel Farrow filter ; The fractional interval of the numerically controlled oscillator output. The value can be based on The result is obtained by looking up a table (which can be written as a LUT table or a ROM table, based on...). The range of values ​​allows for table lookup to obtain... The error has a relatively small impact on the result. , , 3 can be achieved through shifting. The calculation requires the use of two multipliers to calculate the output of the numerically controlled oscillator. and its square and , The product; (1) (2) (3) (4) The grouping module is used to group the output of step S2. Group them into groups of three; and except and The end of each group is the beginning of another group (e.g.) Group 1 (This is the second group, and so on). Each group is input into the Gardner timing error detector. The timing error detection method is determined by the modulation method of the signal. For example, the timing error detection method of BPSK follows equation (6), and the timing error detection method of QPSK follows equation (7). The timing error detection methods corresponding to more complex modulation methods will not be described here. The timing error obtained in this step is... indivual; (5) (6) (7) The mean calculation module is used to calculate the output of step S3. Find the average value Based on the baseband signal correlation parameters, loop filter coefficients C1 and C2 are designed, and a loop filter composed of C1 and C2 is used to... and The control word is obtained through calculation. Design and control word of loop filter coefficients C1 and C2 The calculation involves knowledge related to loop filters, and the modulus module is used to convert the control word... Input to the numerically controlled oscillator, the register of the numerically controlled oscillator corresponds to the control word Perform accumulation and modulo 1; And based on the register modulo overflow, the distance between the current sampling point and the optimal sampling point is determined. When accumulating the control word and taking the modulo with 1, the formula (8) is followed, that is, the control word When accumulating, the value should be multiplied by the number of parallel inputs k to ensure that the cumulative phase error generated by the k inputs is included in the register value of the numerically controlled oscillator. ; through register value The fractional interval can be obtained by following equation (9). ,because After stabilizing, it tends to 0.5, therefore, in calculating the fractional interval... Directly to Simply shift one position to the left. (8) (9) The judgment module is used for comparison. and The value is used to determine whether a jump has occurred. If so, it means that the distance between the current sampling point and the optimal sampling point exceeds one sampling point. In this case, the value is used to determine whether a jump has occurred. Adjustments will be made, specifically. When overflow Add 1, When overflow Decrease by 1 to make the Farrow filter closer to the optimal sampling point at the start of the next readout; The output module is used to output the first value of the Farrow filter after the loop has stabilized. Each value is output as a bit synchronization result.

[0039] In high-speed digital communication systems, bit synchronization accuracy directly affects the correctness of subsequent decisions. Existing bit synchronization systems based on Gardner loops are mostly implemented in a serial structure, which is difficult to meet the real-time and parallel processing requirements of high code rate scenarios. Furthermore, traditional serial bit synchronization methods suffer from low resource utilization and high computational redundancy when facing high oversampling rates (e.g., SPS=4 or higher). Additionally, if the Farrow interpolation structure is not expanded in parallel, the interpolation accuracy is limited, leading to unstable synchronization accuracy, narrow capture range, and slow adjustment response. To address these issues, this invention designs a high-speed parallel bit synchronization loop system based on FPGA, achieving efficient parallel execution and fine-tuning capabilities for bit synchronization through structural reconstruction and algorithm rearrangement.

[0040] To achieve high-parallelism data processing, the system employs a 3×k shift register array, supporting k parallel inputs and managing data history using a shift window approach. This ensures that each Farrow interpolation yields k+sps of consecutive sampling points. This structure guarantees a complete refresh of the interpolation window per cycle even at high code rates, and allows for flexible adjustment of the synchronization position by adjusting the k_0 pointer. This mechanism avoids redundant data transfer and improves resource utilization efficiency.

[0041] In the Farrow interpolation module, the system constructs multiple interpolation groups for sampling points extracted at each sps / 2 interval, and performs non-integer interpolation with µ precision using the Farrow formula (based on cubic spline structure). µ and its square µ 2 The results are obtained through a lookup table (LUT or ROM), avoiding high-latency floating-point operations on the FPGA. Output calculation is completed through a combination of shifters and multipliers. This structure can be expanded in parallel to form 2×k / sps+1 interpolation units, achieving pipelined output and ensuring that interpolation estimation for multiple sampling points can be completed per symbol period.

[0042] In the timing error detection section, the system uses a sliding window mechanism to perform three-point overlapping grouping of the interpolated output and inputs each group to the Gardner error detector. The system supports mainstream modulation formats such as BPSK and QPSK, switching different error extraction logics according to the modulation method. This stage outputs k / sps of error signals, which are then calculated by the averaging module to obtain the average timing error Ga_MEAN(t) at the current time, reflecting the degree of offset of the current sampling point relative to the symbol center, providing a basis for subsequent control word calculation.

[0043] The system inputs Ga_MEAN(t) into a second-order loop filter and calculates the control word ω_m(t) using loop coefficients C1 and C2. This control word drives the numerically controlled oscillator (NCO) accumulator to achieve high-resolution adjustment of the symbol clock. In hardware implementation, the system constructs η(t) by performing a modulo-1 operation on the product of the control word and the parallelism k. K_0 is fine-tuned by determining modulo overflow, dynamically updating the readout start position of the Farrow filter to accurately approximate the optimal sampling point.

[0044] After the synchronization loop stabilizes, the system outputs the first 2×k / sps interpolation results of the Farrow filter as a synchronization data stream for subsequent demodulation or decision modules. This design utilizes the parallel computing and on-chip storage resources of the FPGA, employing a fully parallel structure, interpolation lookup table optimization, sliding window grouping, and dynamic symbol alignment mechanisms to achieve high-speed, high-precision, and low-latency bit synchronization. The system is particularly suitable for synchronization tasks in high bit-rate, short training sequences, or non-ideal channel environments, exhibiting good robustness and engineering feasibility.

[0045] Reference Figure 3 The bit synchronization loop consists of five main structures: a parallel shift storage space, a parallel Farrow filter, a parallel Gardner timing error detector, a loop filter, and a numerically controlled oscillator. The input of the bit synchronization loop enters the parallel shift storage space, and after the loop stabilizes, the bit synchronization loop selects the first value from the calculation result of the parallel Farrow filter as the output of the bit synchronization loop.

[0046] The timing error obtained by averaging the data after passing through a parallel Farrow filter and a parallel Gardner timing error detector can characterize the difference between the current sampling position and the fractional interval of the loop feedback and the optimal sampling point. The numerically controlled oscillator register value and fractional interval obtained by the loop filter and numerically controlled oscillator are continuously adjusted until they tend to stabilize. At this point, the loop is considered stable and the bit synchronization loop has found the optimal sampling point.

[0047] Reference Figure 4 Taking k=16 as an example, the input of the parallel Farrow filter contains a total of k+sps, which is 20 sampling points. These 20 sampling points are divided into 9 groups and input into 9 basic Farrow filters respectively. The output values ​​of the 9 Farrow filters are obtained by calculation using equations (1) to (4). After the loop stabilizes, the first 8 output values ​​will be used as the output of the bit synchronization loop.

[0048] Reference Figure 5Taking k=16 as an example, the nine inputs of the parallel Gardner error detector are divided into four groups during calculation. Each group selects its error calculation method according to its modulation mode when inputting a single Gardner error detector. Equations (6) and (7) are the error calculation methods under BPSK and QPSK modulation, respectively. After the calculation, four values ​​will be obtained. These four values ​​are the timing errors obtained after calculating the errors of the 20 sampling points input to the Farrow filter.

[0049] Figure 3 The loop filter shown is structurally no different from a traditional bit synchronization loop, so it will not be elaborated here. However, when calculating the timing error of the numerically controlled oscillator, it should be considered that the result is the result of 20 sampling points input. When these 20 sampling points are fully aligned, the two sampling points before and after each of the two input points correspond to half of the two symbols before and after. At this time, it is more conducive to error detection on the complete four symbols of the input, i.e., 16 sampling points. Therefore, in the calculation of the numerically controlled oscillator, the control word should be multiplied by AND, rather than ANDed.

[0050] The numerically controlled oscillator register value adjusts the starting pointer of the Farrow filter to facilitate finding the optimal sampling point. When overflow occurs, i.e., the difference between the value and the value exceeds a certain range (e.g., approaching 0 but approaching 1, or vice versa), it indicates that the distance between the current sampling point and the optimal sampling point exceeds one sampling point, and adjusting the fractional interval is no longer sufficient to find the optimal sampling point. When the value approaches 0 but approaches 1, it indicates underflow, meaning the pointer is lagging and should be decremented by 1; conversely, the pointer should be incremented by 1.

[0051] Compared with the traditional bit synchronization ring, the output of each module of the parallel input bit synchronization ring of the present invention is shown in Figure 6. Figure 6(1) shows the output of each module of the traditional serial bit synchronization ring structure in the simulation, and Figure 6(2) shows the output of each module of the corresponding parallel bit synchronization ring structure of the present invention in the simulation. According to the comparison, after the loop stabilizes, the control word output by the loop filter is and the timing error output of the Gardner error detector It fluctuates only slightly within a stable range of results, while the score intervals... The overflow situation differs significantly from that of CNC oscillators. The main reason is that the overflow mechanism of CNC oscillators is different. In each parallel calculation, the CNC oscillator can be considered to have overflowed k / 2 times (the number of points calculated in each loop is k).

[0052] Simulation results show that the parallel bit synchronization loop designed in this invention has the function of searching for the optimal sampling point of the signal. After the loop stabilizes, the optimal sampling point can be obtained through the output of the Farrow filter.

[0053] It should be noted that embodiments of the present invention can be implemented in hardware, software, or a combination of both. The hardware portion can be implemented using dedicated logic; the software portion can be stored in memory and executed by a suitable instruction execution system, such as a microprocessor or dedicated-design hardware. Those skilled in the art will understand that the above-described devices and methods can be implemented using computer-executable instructions and / or included in processor control code, for example, such code provided on a carrier medium such as a disk, CD, or DVD-ROM, a programmable memory such as read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. The devices and modules of the present invention can be implemented by hardware circuitry such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field-programmable gate arrays, programmable logic devices, etc., or by software executed by various types of processors, or by a combination of the above-described hardware circuitry and software, such as firmware.

[0054] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for designing a high-speed parallel bit- synchronous loop based on FPGA, characterized in that, Includes the following steps: A high-speed parallel bit synchronization loop design method based on FPGA includes the following steps: 1) Write the k parallel sampling points into a parallel shift storage space of length 3k; 2) Based on the starting position of the Farrow filter, read k+sps sampling points from the above storage space, and use 2×k / sps+1 basic Farrow filters for parallel interpolation to obtain 2×k / sps+1 outputs; 3) Group the above outputs into groups of 3 and input them into a parallel Gardner timing error detector to calculate the phase error, outputting k / sps timing errors; 4) The timing error is averaged to obtain the timing average error. This average error is then input into a loop filter consisting of proportional and integral coefficients to calculate the control word. 5) Input the control word into the accumulator register of the numerically controlled oscillator, calculate the updated register value and take the modulus with 1 to obtain the fractional interval; 6) Determine whether the range of the optimal sampling point is exceeded based on the change in the register value. If so, adjust the Farrow filter to read the starting position. 7) Output the first 2×k / sps values ​​of the Farrow filter as the bit synchronization result.

2. The method of claim 1, wherein the method further comprises: The parallel shift storage space, parallel Farrow filter, parallel Gardner timing error detector, loop filter, and numerically controlled oscillator are characterized by: k sampling points (denoted as k) input to the high-speed parallel bit synchronization loop in a single clock cycle; the parallel shift storage space stores 3k sampling points X(t), X(tk), and X(t-2k) for three consecutive clock cycles; during a single calculation, k+sps sampling points (sps being the oversampling factor) are selected from the i-th sampling point onwards as the input of the parallel Farrow filter (initial value k) and 2*k / sps+1 outputs are obtained; the 2*k / sps+1 values ​​output by the Farrow filter are input to the parallel Gardner timing error detector to obtain k / sps+1 outputs as timing errors; the average of the k / sps+1 timing errors is calculated and input to the loop filter to obtain a control word; the control word is input to the numerically controlled oscillator to obtain a phase control value; adjustments are made based on the overflow of the phase control value and the input is entered into the next round of bit synchronization loop until the loop tends to stabilize; A loop is formed by a parallel Farrow filter, a parallel Gardner timing error detector, a loop filter, and a numerically controlled oscillator. The phase control value output by the numerically controlled oscillator controls the position of the parallel Farrow filter reading the parallel shift memory space, thus forming a feedback loop. The output of the parallel Farrow filter is used as the output of the parallel bit synchronization loop; A single shift input must have at least two symbols, and the number of symbols must be even. The oversampling factor (sps) for each symbol must be at least 4, meaning the number of sampling points (k) per shift input must be at least 8. Only by meeting these conditions can the calculations of the parallel Farrow filter and the parallel Gardner timing error detector proceed normally. Storage space can be provided by shift registers or a combination of registers and address pointers.

3. The method of claim 1, wherein the method further comprises: determining a number of the plurality of FPGAs; and determining a number of the plurality of PLLs based on the number of the plurality of FPGAs. The parallel Farrow filter consists of multiple basic Farrow filters, with the number of basic Farrow filters being 2*k / sps+1. Each basic Farrow filter calculates the symbols corresponding to the k+sps sampling points of the input separately, and this calculation is parallel. Each input must have at least four sampling points and require the output of a numerically controlled oscillator. The calculation requires a lookup table and two multipliers.

4. The FPGA-based high-speed parallel bit synchronization loop design method as described in claim 1, characterized in that, The outputs of 2*k / sps+1 parallel Farrow filters are grouped into groups of three, and the last value of each group is the first value of the next group, except for the first two results. The error detection method is selected according to the modulation scheme. For example, in BPSK, the difference between the middle value of each group and the two preceding and following values ​​is multiplied as the output result of the Gardner timing error detector, i.e., the phase error. At this time, the number of output values ​​of the parallel Gardner timing error detector is k / sps.

5. The FPGA-based high-speed parallel bit synchronization loop design method as described in claim 1, characterized in that, The average of k / sps+1 phase error values ​​of the Gardner timing error detector is calculated as the input value, and the control word is obtained from the values ​​of the proportional coefficient C1 and the integral coefficient C2.

6. The FPGA-based high-speed parallel bit synchronization loop design method as described in claim 1, characterized in that, The loop filter output control word is accumulated by a register value µ with an initial value of µ_0, and µ is continuously updated by taking the modulo of the accumulated result with 1. The value of µ is incremented or decremented by 1 according to the overflow and underflow values ​​of µ. The registered value µ is characterized in that the accumulated ω_n when updating µ is multiplied by k. This operation can distribute the control word calculated by k sampling points to the next loop calculation. The range of µ is [0,1).

7. A high-speed parallel bit synchronization loop design system based on FPGA, implementing the high-speed parallel bit synchronization loop design method based on FPGA as described in any one of claims 1-6, characterized in that, The FPGA-based high-speed parallel bit synchronization loop design system includes: The sampling module is used for writing k parallel sampling points X(k). The length is a parallel shift memory space; during a single write operation, k sample points are written to the corresponding register clock via shifting or address pointers, and the rest... The length register stores the k sampling points written in the first two writes, and according to... Selecting values ​​backward The k most recently written sample points are used as input to the parallel Farrow filter (the k most recently written sample points correspond to the positions in the...). The total index of the parallel shift storage space is The number of parallel operations k is an even multiple of sps, and sps is the oversampling factor and equal to 4 (if it is greater than 4, it is recommended to connect a downsampling extraction module in series before this module to make the oversampling factor reach 4). Read the start pointer for the Farrow filter and initialize it with k; The calculation module is used to divide the k+sps sampling points into a range based on the number of symbols, with a step size of half a symbol length and a range of one symbol length. Group; (e.g.) Group 1 This is the second group, and so on. Each group corresponds to a sampling point. Calculate it using equations (1) to (4) to obtain The output of a parallel Farrow filter ; The fractional interval of the numerically controlled oscillator output. The value can be based on The result is obtained by looking up a table (which can be written as a LUT table or a ROM table, based on...). The range of values ​​allows for table lookup to obtain... The error has a relatively small impact on the result. , , 3 can be achieved through shifting. The calculation requires the use of two multipliers to calculate the output of the numerically controlled oscillator. and its square and , The product; (1) (2) (3) (4) The grouping module is used to group the output of step S2. Group them into groups of three; and except and The end of each group is the beginning of another group (e.g.) Group 1 (This is the second group, and so on). Each group is input into the Gardner timing error detector. The timing error detection method is determined by the modulation method of the signal. For example, the timing error detection method of BPSK follows equation (6), and the timing error detection method of QPSK follows equation (7). The timing error detection methods corresponding to more complex modulation methods will not be described here. The timing error obtained in this step is... indivual; (5) (6) (7) The mean calculation module is used to calculate the output of step S3. Find the average value Based on the baseband signal correlation parameters, loop filter coefficients C1 and C2 are designed, and a loop filter composed of C1 and C2 is used to... and The control word is obtained through calculation. Design and control word of loop filter coefficients C1 and C2 The calculations pertain to the knowledge related to loop filters. The modulus module is used to convert control words... Input to the numerically controlled oscillator, the register of the numerically controlled oscillator corresponds to the control word Accumulate and modulo 1; And based on the register modulo overflow, the distance between the current sampling point and the optimal sampling point is determined. When accumulating the control word and taking the modulo with 1, the formula (8) is followed, that is, the control word When accumulating, the value should be multiplied by the number of parallel inputs k to ensure that the cumulative phase error generated by the k inputs is included in the register value of the numerically controlled oscillator. ; through register value The fractional interval can be obtained by following equation (9). ,because After stabilizing, it tends to 0.5, therefore, in calculating the fractional interval... Directly to Simply shift one position to the left. (8) (9) The judgment module is used for comparison. and The value is used to determine whether a jump has occurred. If so, it means that the distance between the current sampling point and the optimal sampling point exceeds one sampling point. In this case, the value is used to determine whether a jump has occurred. Adjustments will be made, specifically. When overflow Add 1, When overflow Decrease by 1 to make the Farrow filter closer to the optimal sampling point at the start of the next readout; The output module is used to output the first value of the Farrow filter after the loop has stabilized. Each value is output as a bit synchronization result.

8. A computer device, characterized in that, The computer device includes a memory and a processor. The memory stores a computer program, which, when executed by the processor, causes the processor to perform the steps of the FPGA-based high-speed parallel bit synchronization loop design method as described in any one of claims 1-6.

9. A computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the steps of the FPGA-based high-speed parallel bit synchronization loop design method as described in any one of claims 1-6.

10. An information data processing terminal, characterized in that, The information data processing terminal is used to implement the FPGA-based high-speed parallel bit synchronization loop design system as described in claim 7.

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