Circuit board and design method

Abstract

The application provides a circuit board and a design method. The circuit board comprises a conductive layer and an insulating layer. The conductive layer and the insulating layer are arranged in an alternating stacked manner. At least two layers of the conductive layer are signal layers, and at least one layer is a ground layer. Signal transmission is achieved through non-through vias between the signal layers. The opposite ends of the non-through vias are both provided with pads, and the pads are electrically connected to the signal layers. The ground layer is an adjacent layer of the end pads of the non-through vias. A ground avoidance area is arranged on the ground layer in a region opposite to the pads along the stacking direction of the circuit board, so as to increase the spacing between the pads and the ground layer and reduce the capacitive coupling between the pads and the ground layer. In this way, by arranging the ground avoidance area on the ground layer adjacent to the pads, the impedance continuity required for high-speed signal transmission is achieved through a simple and low-cost structural design, and the design requirements of a high-density circuit board can be met.

Description

Technical Field

[0001] This application relates to the field of circuit board technology, and more particularly to a circuit board and its design method. Background Technology

[0002] As electronic devices evolve towards higher speeds and densities, non-through-hole vias (such as blind vias and buried vias) have become the core interconnect structure for multilayer circuit boards due to their ability to increase wiring density and save space, widely adapting to the needs of high-speed signal transmission. Impedance continuity is crucial for high-speed signal transmission; impedance fluctuations can cause signal reflection and distortion, affecting the normal operation of equipment. However, in non-through-hole via designs, the distance between the terminal pad and the adjacent ground plane is extremely small, easily leading to significant parasitic capacitive coupling. This causes the impedance at the via to deviate from the target value, resulting in impedance discontinuity and severely impacting the integrity of high-speed signals. Summary of the Invention

[0003] This application provides a circuit board and a design method to at least solve the above-mentioned problems in the related art.

[0004] To achieve the above objectives, this application provides the following technical solution: a circuit board, the circuit board including a conductive layer and an insulating layer, the conductive layer and the insulating layer are arranged in an alternating stacking direction, at least two of the conductive layers are signal layers and at least one is a ground layer, the signal layers are transmitted through non-penetrating vias, and each end of the non-penetrating via is provided with a pad, and the pad is electrically connected to the signal layer.

[0005] The ground plane is the adjacent layer to the end pad of the non-through via. A ground avoidance area is provided on the ground plane in the area directly opposite the pad along the stacking direction of the circuit board to increase the distance between the pad and the ground plane and reduce the capacitive coupling between the pad and the ground plane.

[0006] In some alternative implementations, the outline shape of the ground clearance area is adapted to the outline shape of the pad, and the size of the ground clearance area is not smaller than the size of the pad.

[0007] In some alternative implementations, the grounding avoidance zone can be any one of a circle, an ellipse, or a rectangle.

[0008] In some optional embodiments, there are multiple non-through vias, each with a pad at its end. An integrated ground clearance area is provided on the ground layer, and the projection of each pad along the stacking direction of the circuit board falls into the integrated ground clearance area. The integrated ground clearance area is formed by integrally connecting the projection areas of each pad.

[0009] In some alternative implementations, there are two non-through vias, and the pads of each non-through via are integrally connected along the projection area of ​​the circuit board stacking direction to form an elliptical integrated grounding avoidance area.

[0010] In some alternative implementations, the conductive layer through which the non-penetrating via passes is hollowed out to form a clearance area, and a gap is formed between the non-penetrating via and the conductive layer through which it passes.

[0011] In some alternative implementations, the non-through via is either a blind via or a buried via.

[0012] In some optional embodiments, this application also provides a circuit board design method applied to the aforementioned circuit board, the method comprising: Signal transmission between different signal layers is achieved through non-penetrating vias, with the ends of the non-penetrating vias forming pads on the signal layers, and the adjacent layer of the pads being the ground layer. On the ground plane, a ground avoidance area is set in the area directly opposite the pad along the stacking direction of the circuit board. The ground avoidance area increases the distance between the pad and the ground plane, reduces the capacitive coupling between the pad and the ground plane, and ensures the impedance continuity of high-speed signals at non-through vias.

[0013] In some optional implementations, there are multiple non-through vias, each with a pad at its end. An integrated ground avoidance area is provided on the ground layer, so that the projection of each pad along the stacking direction of the circuit board falls into the integrated ground avoidance area, and the integrated ground avoidance area is formed by integrally connecting the projection areas of each pad.

[0014] In some alternative implementations, the non-through via is either a laser via or a mechanical via.

[0015] In the aforementioned circuit board, on the one hand, by setting a ground avoidance area, the physical distance between the pads and the ground layer is increased. According to the basic principles of electromagnetism, the parasitic capacitive coupling strength between conductors is inversely proportional to the distance. Increasing the distance directly weakens the coupling effect between the two, effectively eliminating impedance abrupt changes and ensuring that the actual impedance at non-through vias matches the target impedance, thereby achieving the impedance continuity required for high-speed signal transmission. On the other hand, setting an avoidance area only for a single ground layer adjacent to the pads does not change the original stack-up structure of the circuit board. It does not require additional ground layers, vias, or other auxiliary structures, does not occupy additional wiring space, and does not damage the overall integrity of the ground layer. It adapts to the application requirements of multilayer circuit board wiring density and space saving. Moreover, the structure is simple, requires no additional investment, is easy to mass-produce, and has significant industrialization advantages. It can be quickly implemented in various multilayer circuit board products to meet practical application needs. Thus, by setting a ground avoidance area on the ground layer adjacent to the pads, a simple and low-cost structural design achieves both the impedance continuity required for high-speed signal transmission and adapts to the design requirements of high-density circuit boards.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0017] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, in which: In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0018] Figure 1 A schematic diagram of the circuit board structure in an embodiment of this application is shown; Figure 2 It shows Figure 1 Enlarged view of section II in the middle; Figure 3 It shows Figure 1 A schematic diagram of the cross-section of the circuit board along line III-III; Figure 4 It shows Figure 3 Enlarged view of part IV in the middle; Figure 5 The simulation diagram of the circuit board in Example 1, output by a simulation tool, is shown. Figure 6 The simulation diagram of the circuit board in Example 2, output by a simulation tool, is shown. Figure 7The eye diagram of the circuit board in Example 2, output using a simulation tool, is shown.

[0019] The following are the labels in the diagram: 10, Circuit board; 11, Conductive layer; 12, Non-through via; 121, Pad; 13, Grounding clearance area; 14, Clear area. Detailed Implementation

[0020] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

[0022] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0023] With the development of technology, electronic devices are acquiring information at an increasingly faster speed. The signal rate on the circuit board in hardware design is getting faster and faster. It is very important whether the high-speed signal can be transmitted completely from the generating end to the receiving end. However, in reality, the density on the circuit board is getting higher and higher, and laser drilling interconnection in the signal transmission path is unavoidable. Most existing laser drilling is through-hole, which does not have the problem of capacitive coupling with the adjacent ground layer.

[0024] In related technologies, as electronic devices develop towards higher speeds and higher densities, non-through vias (such as blind vias and buried vias) have become the core interconnect structure of multilayer circuit boards because they can increase the wiring density and save space, and are widely adapted to the needs of high-speed signal transmission. Impedance continuity is the key to high-speed signal transmission. Impedance fluctuations can cause signal reflection and distortion, affecting the normal operation of the equipment.

[0025] However, in actual design, the distance between the end pad of a non-through via on a circuit board and the adjacent ground plane is extremely small, which easily leads to significant parasitic capacitive coupling. This causes the impedance at the via to deviate from the target value, resulting in impedance discontinuity and seriously affecting the integrity of high-speed signals.

[0026] To address the aforementioned issues, researchers discovered that by setting ground avoidance zones on ground layers adjacent to the pads, the distance between the pads and adjacent ground layers is increased, which can effectively eliminate impedance abrupt changes. This allows the actual impedance at non-through vias to match the target impedance, achieving the impedance continuity required for high-speed signal transmission. Consequently, the circuit board can achieve the impedance continuity required for high-speed signal transmission with a simple and low-cost structural design, while also adapting to the design requirements of high-density circuit boards, thus solving the aforementioned problems.

[0027] Formula for pad-plane electrostatic capacitance (approx. for parallel plates): , in, The vacuum permittivity, Let A be the relative permittivity, d be the effective area of ​​the pad, and d be the distance between the disk and the adjacent plane. From these parameters, we can see that when the permittivity and pad area are constant, to remove or reduce capacitive coupling, we can increase the value of d, which means increasing the distance between the disk and the adjacent plane. In theoretical design scenarios, blind vias optimize the Z-space direction of the via disk, increasing the distance between the disk and the adjacent plane, reducing capacitive coupling between the via and the copper surface, and thus ensuring uniform characteristic impedance when signals are transmitted to the via.

[0028] The embodiments of this application will be described below with reference to the accompanying drawings.

[0029] Combination Figure 1 and 2 ; Figure 1 This is a schematic diagram of the circuit board structure; Figure 2 for Figure 1Enlarged view of part II in the middle; In some embodiments, this application provides a circuit board 10, the circuit board 10 including a conductive layer 11 and an insulating layer, the conductive layer 11 and the insulating layer are arranged in an alternating stacked manner, at least two of the conductive layers 11 are signal layers, the signal layers are used to transmit high-speed signals, and at least one layer is a ground layer, the ground layer is used for grounding, the signal layers are transmitted to each other through non-penetrating vias 12, each end of the non-penetrating via 12 is provided with a pad 121, and the pad 121 is electrically connected to the signal layer; the ground layer is the layer adjacent to the end pad 121 of the non-penetrating via 12, and a ground avoidance area 13 is provided on the ground layer in the area directly opposite the pad 121 along the stacking direction of the circuit board 10, so as to increase the distance between the pad 121 and the ground layer and reduce the capacitive coupling between the pad 121 and the ground layer.

[0030] In the aforementioned circuit board 10, on the one hand, by setting a ground avoidance area 13, the physical distance between the pad 121 and the ground layer is increased. According to the basic principles of electromagnetics, the parasitic capacitive coupling strength between conductors is inversely proportional to the distance. Increasing the distance can directly weaken the coupling effect between the two, effectively eliminating impedance abrupt change points, and enabling the actual impedance at the non-through via 12 to match the target impedance, thereby achieving the impedance continuity required for high-speed signal transmission. On the other hand, setting an avoidance area only for a single ground layer adjacent to the pad 121 does not change the original stack-up structure of the circuit board 10. It does not require additional ground layers, ground vias, or other auxiliary structures, does not occupy additional wiring space, and does not damage the overall integrity of the ground layer. It is suitable for the application requirements of wiring density and space saving in multilayer circuit boards 10. Moreover, the structure is simple, requires no additional investment, is easy to mass-produce, and has significant industrialization advantages. It can be quickly implemented in various multilayer circuit board 10 products to meet practical application needs. Thus, by setting a ground avoidance area 13 on the ground layer adjacent to the pad 121, the impedance continuity required for high-speed signal transmission is achieved with a simple and low-cost structural design, while also being able to adapt to the design requirements of the high-density circuit board 10.

[0031] In some embodiments, the outline shape of the ground clearance area 13 is adapted to the outline shape of the pad 121, and the size of the ground clearance area 13 is not smaller than the size of the pad 121. Thus, by adapting the outline shape of the ground clearance area 13 to the outline shape of the pad 121, and ensuring that its size is not smaller than the size of the pad 121, it ensures precise full coverage of the pad 121 by the ground clearance area 13, avoiding insufficient local spacing due to outline mismatch, completely eliminating coupling residues, further reducing the impedance fluctuation range at non-through vias 12, and making impedance continuity more stable. Furthermore, the adaptability design does not require additional expansion of the clearance area's redundant area, maximizing the preservation of the conductive area integrity of the grounding layer, balancing impedance optimization and grounding performance, and improving the practicality of the solution in different pad 121 design scenarios.

[0032] Combination Figure 2 In some embodiments, the grounding avoidance area 13 is shaped as a circle, an ellipse, or a rectangle. By limiting the shape of the grounding avoidance area 13 to any one of these shapes, it is possible to adapt to different pad 121 layout requirements through standardized shapes (circular shapes adapt to single-point pads 121, rectangular shapes adapt to array pads 121, and elliptical shapes adapt to elongated pad layouts 121), thus avoiding wasted circuit board space or processing difficulties caused by special shapes.

[0033] In some embodiments, there are multiple non-through vias 12, and each non-through via 12 is provided with a pad 121 at its end. An integrated ground avoidance area 13 is provided on the ground layer. The projection of each pad 121 along the stacking direction of the circuit board 10 falls into the integrated ground avoidance area 13, and the integrated ground avoidance area 13 is formed by integrally connecting the projection areas of each pad 121.

[0034] Thus, for application scenarios with multiple non-through vias 12, by setting an integrated grounding avoidance area 13, on the one hand, it can ensure that all pads 121 have sufficient coupling suppression space, achieve impedance consistency of the multi-via array, and avoid impedance differences caused by a single independent avoidance area; on the other hand, the integrated grounding avoidance area 13 design can maintain the overall continuity of the grounding layer, prevent the grounding layer from being divided into multiple discontinuous areas, ensure the integrity of the signal return path, effectively suppress electromagnetic interference, solve the core contradiction between impedance continuity and grounding layer network integrity in multi-via scenarios, thereby improving the stability and reliability of high-speed signal bus transmission.

[0035] Combination Figure 3 and 4 , Figure 3 for Figure 1 A schematic diagram of the cross-section of the circuit board along line III-III. Figure 4 for Figure 3 A magnified view of part IV is shown. In some embodiments, the number of non-through vias 12 is two, and the pads 121 of each non-through via 12 are integrally connected along the projection area of ​​the stacking direction of the circuit board 10 to form an elliptical integrated ground clearance area 13. The ellipse is the minimum enclosing shape of the projection of the two pads 121, which can minimize the clearance area, reduce the damage to the conductivity of the ground layer, and balance impedance optimization and ground layer utilization.

[0036] It should be noted that when there is one non-through via 12 in the circuit board 10, it can adapt to high-speed signal protocols such as High-Definition Multimedia Interface (HDMI) 2.1 single-channel signal and Peripheral Component Interconnect Express (PCIe) 4.0 / 5.0 single-channel signal; when there are two non-through vias 12 in the circuit board 10, it can adapt to high-speed signal protocols such as Peripheral Component Interconnect Express (PCIe) 4.0 / 6.0 differential signal pairs and High-Definition Multimedia Interface (HDMI) 2.1 differential signal pairs; when there are three or more non-through vias 12 in the circuit board 10, it can adapt to high-speed signal protocols such as High-End Field-Programmable Gate Array (FPGA) and Peripheral Component Interconnect Express (PCIe) 6.0. For multi-channel (x4 / x8 / x16) and other high-speed signal protocols, the target impedance for a single channel is 85-100Ω.

[0037] Combination Figure 2 In some embodiments, the conductive layer 11 through which the non-penetrating via 12 passes is hollowed out to form a clear area 14, and the non-penetrating via 12 forms a gap with the conductive layer 11 through which it passes via the clear area 14.

[0038] Thus, by hollowing out the conductive layer 11 through which the non-penetrating via 12 passes to form a clear area 14, on the one hand, the physical distance between the sidewall of the non-penetrating via 12 and the conductive layer 11 can be increased, suppressing the parasitic coupling between the sidewall and the intermediate conductive layer 11, and achieving full-link coupling suppression between the pad 121 and the ground layer, and between the hole wall of the non-penetrating via 12 and the conductive layer 11 through which it passes; on the other hand, it is not necessary to completely hollow out all conductive layers 11, but only to process the area through which the via passes, which avoids the destruction of the ground network integrity and further reduces the overall parasitic capacitance, thereby making the impedance error control at the non-penetrating via 12 more precise.

[0039] In some embodiments, the non-through via 12 is either a blind via or a buried via, in order to increase the wiring density of the multilayer circuit board 10 and save space.

[0040] This application also provides a circuit board design method, which is applied to the circuit board 10 described above, the method comprising: Step S1: Open non-penetrating vias 12 between multiple signal layers to enable signal transmission between different signal layers. The end of the non-penetrating via 12 forms a pad 121 on the signal layer, and the adjacent layer of the pad 121 is a ground layer. Step S2: On the ground layer, a ground avoidance area 13 is provided in the area directly opposite the pad 121 along the stacking direction of the circuit board 10. The ground avoidance area 13 increases the distance between the pad 121 and the ground layer, reduces the capacitive coupling between the pad 121 and the ground layer, and ensures the impedance continuity of high-speed signals at the non-through via 12.

[0041] Thus, this method employs a collaborative design where the end pad 121 of the non-through via 12 is adjacent to the ground plane, and a grounding avoidance area 13 is provided in the corresponding area of ​​the ground plane. On the one hand, the adjacent placement of the pad 121 and the ground plane shortens the signal return path, reduces the loop area, and lowers electromagnetic radiation; simultaneously, impedance continuity reduces the source of electromagnetic interference during signal transmission, and the design of the grounding avoidance area 13 further avoids crosstalk caused by capacitive coupling, improving the overall electromagnetic compatibility level of the circuit board 10 without requiring additional complex shielding structures; on the other hand, the grounding avoidance area 13 increases the... The spacing between pad 121 and the ground plane is specifically designed to reduce capacitive coupling between them, so that the equivalent impedance of the via area matches the impedance of the signal transmission line. This avoids impedance breakage caused by sudden changes in parasitic parameters (inductance, capacitance), and enables continuous impedance transmission of high-speed signals at non-through vias 12. On the other hand, this method only requires the inter-layer layout design of the circuit board 10. The ground plane avoidance area setting and the non-through vias 12 can be achieved using conventional processing technology. No special materials, equipment or additional processing steps are required. It is fully compatible with the existing manufacturing process of the circuit board 10, thereby reducing implementation costs.

[0042] In some embodiments, in step S1, there are multiple non-through vias 12, and each non-through via 12 has a pad 121 formed at its end. An integrated ground avoidance area 13 is provided on the ground layer, such that the projection of each pad 121 along the stacking direction of the circuit board 10 falls into the integrated ground avoidance area 13, and the integrated ground avoidance area 13 is formed by integrally connecting the projection areas of each pad 121.

[0043] Thus, for manufacturing scenarios with multiple non-through vias 12, by setting an integrated grounding clearance area 13, it is possible to ensure that the projected areas of all pads 121 are accurately covered during mass production, avoiding process errors such as positional offset and gap residue caused by multiple independent clearance areas. On the other hand, the manufacturing process of the integrated clearance area is simpler, eliminating the need to design a clearance area for each via separately, thus improving production efficiency. At the same time, it ensures the impedance consistency and ground network integrity of multi-via products, reducing the defect rate of high-speed signal transmission equipment.

[0044] In some embodiments, in step S1, the non-through via 12 is either a laser via or a mechanical via. Both via technologies are mature technologies in the industry, highly compatible with the setup process of the grounding avoidance zone 13, and can be quickly industrialized.

[0045] In some embodiments, the method further includes step S3, hollowing out a clearance area 14 in the conductive layer 11 through which the non-penetrating via 12 passes, wherein the non-penetrating via 12 forms a gap with the conductive layer 11 through the clearance area 14.

[0046] Thus, if the conductive layer 11 through which the non-penetrating via 12 passes (such as non-target signal layer, power layer, etc.) is not cleared, it is easy to form additional capacitive coupling or inductive interference with the via, resulting in multiple node abrupt changes in impedance on the via path. This step creates a clear area 14 by hollowing out the via, so that the non-penetrating via 12 and the conductive layer 11 it passes through maintain a preset distance, reducing the irregular superposition of parasitic parameters (parasitic capacitance, mutual inductance) throughout the entire path. This complements the design of the grounding avoidance area 13 adjacent to the grounding layer, ensuring the consistency between the equivalent impedance of the via area and the transmission line impedance in all aspects, and further improving the stability and accuracy of impedance continuity.

[0047] Example 1 This embodiment provides a circuit board 10, the specific structure of which is as follows: The circuit board employs an 8-layer, 10-layer stack design, with multiple alternating conductive layers 11 and insulating layers. The conductive layers 11 include signal layer L1, signal layer L2, signal layer L3, ground layer L4, and reference ground layer L5. The remaining layers are auxiliary conductive layers 11, and each conductive layer 11 is isolated from the others by insulating layers. Signal transmission between signal layer L1 and signal layer L3 is achieved through two non-through vias 12. Both non-through vias 12 are blind vias (penetrating only layers L1-L3), and their ends form circular pads 121 on signal layers L1 and L3 respectively. The pads 121 have a diameter of 16 mil and a center-to-center distance of 35 mil. Ground layer L4 is adjacent to the pads 121 at the ends of the non-through vias 12. Simultaneously, reference ground layer L5 serves as the signal return reference plane, further optimizing impedance matching. The high-speed signal transmitted between signal layers L1 and L3 is an HDMI 2.1 differential signal pair with a target impedance of 90Ω, compatible with a 12Gbps transmission rate.

[0048] Please combine Figure 5 , Figure 5 The simulation diagram of circuit board 10 in Example 1 is output by a simulation tool. Simulation test results: Using Ansys HFSS2023R2 simulation tool (the industry standard tool for electromagnetic simulation of circuit board 10), the simulation data shows that the maximum characteristic impedance of the two non-through vias in this scenario is 90.0425Ω, the minimum characteristic impedance is 88.2831Ω, the impedance fluctuation range is 1.76Ω, and the maximum error from the target impedance of 90Ω is -1.72Ω, which exceeds the allowable error range of ±0.5Ω and does not meet the impedance matching requirements of the differential signal pair.

[0049] Example 2 The difference between the circuit board 10 structure in this embodiment and that in embodiment 1 is that, in this embodiment, an integrated grounding avoidance area 13 is provided on the ground layer L4 in the area directly opposite the pad 121 along the stacking direction of the circuit board 10. The outline of the integrated grounding avoidance area 13 is as follows: concentric circles with the same diameter as the pad 121 are drawn with the center of each of the two pads 121 as the center, and then the two concentric circles are smoothly connected along the edge to form an elliptical integrated grounding avoidance area 13. This ensures that the projection of the two pads 121 along the stacking direction of the circuit board 10 falls completely within the avoidance area, and the avoidance area does not exceed the minimum enclosure range of the two pads 121, thus preserving the conductivity integrity of the ground layer L4 to the greatest extent.

[0050] Please combine Figure 6 , Figure 6 The simulation diagram of circuit board 10 in Example 2 is output by a simulation tool. Simulation test results: Using Ansys HFSS2023R2 simulation tool, the simulation data shows that the maximum characteristic impedance of the two non-through vias in this scenario is 90.4317Ω, the minimum characteristic impedance is 90.0117Ω, the impedance fluctuation range is 0.42Ω, and the maximum error from the target impedance of 90Ω is +0.43Ω, which does not exceed the allowable error range of ±0.5Ω, thus meeting the impedance matching requirements of the differential signal pair.

[0051] Please combine Figure 7 , Figure 7 The eye diagram of circuit board 10 in Example 2 is output by a simulation tool. Signal eye diagram test results: When circuit board 10 transmits HDMI 2.1 differential signal pairs, its eye diagram test results show that the eye width reaches 58ps, the eye height reaches 300mV, and the jitter value is controlled within 20ps. The blue diamond in the middle of the eye diagram is the reference eye diagram mask. This reference eye diagram mask is the core standard for judging whether the signal integrity meets the standard. Compared with the blue standard eye diagram mask in the middle, the eye diagram of this embodiment is more fully opened in the horizontal direction (eye width), has a larger amplitude in the vertical direction (eye height), and the jitter amplitude of the signal transition edge is significantly reduced. The eye diagram outline is more complete, the edges are neater, and there is no obvious signal distortion and crosstalk. The eye diagram quality is significantly improved.

[0052] As can be seen from the above two sets of embodiments, by setting the ground avoidance area 13 on the ground layer L4 as a core design, on the one hand, the impedance fluctuation range is reduced to 0.42Ω, and the maximum error with the target impedance is only ±0.43Ω, which is completely controlled within the allowable error range of ±0.5Ω. This completely eliminates the impedance mutation point and achieves impedance continuity at the non-through via 12. The eye diagram quality of the HDMI 12Gbps signal meets the standard, and the eye width and eye height meet the protocol requirements. The jitter is greatly reduced, proving that this solution can effectively avoid the reflection and distortion of high-speed signals and solve the core problem of impedance imbalance and substandard eye diagram quality in the dual-via differential signal transmission in the prior art. On the other hand, this application only sets the ground avoidance area 13 on the adjacent ground layer, without changing the original stack-up structure of the circuit board 10. It does not require additional ground layers, ground vias or auxiliary structures, and does not occupy additional wiring space. It perfectly adapts to the high-density design requirements of the multilayer circuit board 10, and does not require additional special processing technology, which has significant industrialization advantages.

[0053] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A circuit board, characterized in that, The circuit board includes a conductive layer and an insulating layer, which are stacked alternately. At least two of the conductive layers are signal layers and at least one is a ground layer. Signal transmission between the signal layers is achieved through non-through vias. Each non-through via has pads at both ends and is electrically connected to the signal layer through the pads. The ground layer is the adjacent layer to the pad of the non-through via. A ground avoidance area is provided on the ground layer in the area directly opposite the pad along the stacking direction of the circuit board to increase the distance between the pad and the ground layer and reduce the capacitive coupling between the pad and the ground layer.

2. The circuit board according to claim 1, characterized in that, The outline shape of the grounding avoidance area is adapted to the outline shape of the pad, and the size of the grounding avoidance area is not smaller than the size of the pad.

3. The circuit board according to claim 2, characterized in that, The grounding avoidance zone can be any one of a circle, an ellipse, or a rectangle.

4. The circuit board according to claim 1, characterized in that, The number of non-penetrating vias is multiple, and each non-penetrating via has a pad at its end. An integrated ground avoidance area is provided on the ground layer. The projection of each pad along the stacking direction of the circuit board falls into the integrated ground avoidance area, and the integrated ground avoidance area is formed by integrally connecting the projection areas of each pad.

5. The circuit board according to claim 4, characterized in that, The number of non-penetrating vias is two, and the pads of each non-penetrating via are integrally connected along the projection area of ​​the stacking direction of the circuit board to form an elliptical integrated grounding avoidance area.

6. The circuit board according to claim 1, characterized in that, The conductive layer through which the non-penetrating via passes is hollowed out to form a clear area, and the non-penetrating via forms a gap with the conductive layer through the clear area.

7. The circuit board according to claim 1, characterized in that, The non-penetrating via is either a blind hole or a buried hole.

8. A circuit board design method, characterized in that, The method is applied to the circuit board as described in any one of claims 1-7, and the method includes: Signal transmission between different signal layers is achieved through non-penetrating vias, with the ends of the non-penetrating vias forming pads on the signal layers, and the adjacent layer of the pads being the ground layer. On the grounding layer, a grounding avoidance area is provided in the area directly opposite the pad along the stacking direction of the circuit board. The grounding avoidance area increases the distance between the pad and the grounding layer, reduces the capacitive coupling between the pad and the grounding layer, and ensures the impedance continuity of high-speed signals at the non-through via.

9. The circuit board design method according to claim 8, characterized in that, The number of non-penetrating vias is multiple, and each non-penetrating via has a pad formed at its end. An integrated ground avoidance area is provided on the ground layer so that the projection of each pad along the stacking direction of the circuit board falls into the integrated ground avoidance area, and the integrated ground avoidance area is formed by integrally connecting the projection areas of each pad.

10. The circuit board design method according to claim 8, characterized in that, The non-penetrating via is either a laser via or a mechanical via.

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