A standard power cell structure fabrication method for embedded packaging

Abstract

The application relates to the field of advanced packaging technology of integrated circuits, and particularly relates to a manufacturing method of a standard power unit structure for embedded packaging. The method comprises the following steps: obtaining design parameters of all standard power units, performing patterned electroplating at one end of a copper plate to form a chip accommodating cavity and a positioning mark target, opening a blind groove in the copper plate to form an insulating area and a cutting area, dividing the copper plate into multiple copper base tables, retaining a layered structure of the copper plate as a connecting layer, mounting a chip to the chip accommodating cavity, performing whole-plate plastic packaging, windowing, laser drilling and metallization, forming interconnection vias and top external vias, manufacturing a rewiring layer, forming a half-bridge circuit, a full-bridge circuit, a cascade circuit, a multi-core series circuit, a multi-core parallel circuit or a single-core circuit, and removing the connecting layer to cut to obtain a standard power unit product. The application can batch-manufacture standard power units with high-efficiency heat dissipation function and different circuit structures including a multi-core series structure.

Description

Technical Field

[0001] This invention relates to the field of advanced integrated circuit packaging technology, and more specifically to a method for manufacturing a standard power cell structure for embedded packaging. Background Technology

[0002] Embedded packaging technology has attracted much attention due to its ability to effectively shorten interconnect lengths and improve system integration and electrical performance. Board-level embedded packaging directly embeds chips or passive components such as capacitors, resistors, and inductors within the packaging carrier structure, achieving system integration and functional modularization to form a complete microsystem. It features shorter interconnect paths, smaller package size, better electrothermal performance, and higher integration, thereby increasing the freedom of subsequent overall product design and shortening the development cycle.

[0003] Conventional embedded packaging technologies, such as Figure 1 As shown, direct interconnection between the chip and the PCB is achieved by directly embedding the bare chip die into the PCB substrate. With the development of wide bandgap semiconductors, power semiconductor devices are evolving towards higher power density, higher chip temperature, and higher reliability, which correspondingly places higher demands on the applicability of power semiconductor module packaging.

[0004] For MOS chips with a heat dissipation power exceeding 2W, the packaging method of directly embedding the chip into the PCB is not typically used. Instead, the chip is first integrated onto a precision-machined copper frame using high-performance interconnect technology. This copper frame often includes a 1-3mm thick copper block, forming a standard power unit with efficient heat dissipation capabilities. Figure 2 As shown.

[0005] This standard power unit is used as an embedded component instead of a bare chip and packaged into a PCB.

[0006] Currently, the following fabrication process is often used for such standard power units: a single copper block with a groove cavity is first prepared by precision machining, and then chips are mounted one by one on the individual copper blocks to form a standard power unit.

[0007] The above-described fabrication process has the following problems, which limit the further application of standard power units: 1. The process of mounting chips onto copper blocks one by one is cumbersome and has low production efficiency; 2. Unable to form a power module with a multi-core series structure: After the chip is mounted on the copper frame, it is difficult to process the lines between the chip pads. When multiple chips are mounted on the same copper block, the back electrodes of the vertical structure chips are all connected to the copper frame to form a parallel structure. The planar structure chips can only form an independent multi-core structure. 3. Interconnections between chip pads and between multiple chips need to be achieved by embedding them in the PCB and routing them on the same layer as the external circuitry, which increases the difficulty of routing and the risk of wire routing, and occupies valuable PCB routing space; 4. The power unit chip pads are exposed, posing a high risk of damage; 5. Drilling and alignment are difficult when embedding power units into PCB: There are mounting errors in the chip in the copper cavity, and there are also mounting errors when embedding power units into PCB. That is, drilling and routing need to overcome the aforementioned double errors, and the alignment accuracy requirement is extremely high, making alignment difficult. 6. When power units are embedded in PCBs, prepreg FR-4 semi-cured sheets are usually used as the insulating medium. During the lamination process, its thermal expansion coefficient, moisture absorption and moisture permeability are high, which can easily lead to thermal mismatch and chip failure. In addition, the hard glass fibers in the prepreg are in direct contact with the chip, which can easily cause physical damage to the chip edge when the lamination force is applied, leading to adverse conditions such as induced electrical breakdown in actual use.

[0008] 7. Standard power cells based on ceramic substrates have prominent ceramic layer edges, which are prone to breakage and create voids in the plastic encapsulation when embedded in a PCB. Summary of the Invention

[0009] To address the shortcomings of existing technologies, this invention provides a method for manufacturing a standard power cell structure for embedded packaging, which can simultaneously manufacture multiple standard power cells with different circuit structures on a single board. The specific technical solution is as follows: A method for manufacturing a standard power cell structure for embedded packaging includes the following steps: S10 obtains the design parameters of all standard power units. The standard power units are one or more of the following: half-bridge unit, cascade unit, full-bridge unit, multi-core series unit, multi-core parallel unit, and single-core unit. The design parameters include the size and mounting position of all chips, the size and position of chip pads, the interconnection lines between chips and the lines that export chip signals, the size parameters of the chip housing cavity, the size and position of the insulating area and the cutting area, and the shape, position and size of the alignment target.

[0010] A half-bridge unit is a standard power unit with the following structure: it contains two chips that form a half-bridge circuit, and the source, gate, and drain signals that need to be connected to the outside are brought out through interconnect vias.

[0011] A cascaded unit refers to a standard power unit with the following structure: it contains two chips that form a cascaded circuit, and the source, gate, and drain signals that need to be connected to the outside are brought out through interconnect vias.

[0012] A full-bridge cell refers to a standard power cell with the following structure: it is packaged with four chips, which form a full-bridge circuit. The source, gate, and drain signals that need to be connected to the outside are brought out through interconnect vias.

[0013] A multi-chip series unit refers to a standard power unit with the following structure: it is packaged with at least two chips, which form a series circuit between the at least two chips, and the source, gate and drain signals that need to be connected to the outside are respectively led out through interconnecting vias.

[0014] A multi-chip parallel unit refers to a standard power unit with the following structure: it is packaged with at least two chips, which form a parallel circuit between the at least two chips, and the source, gate and drain signals that need to be connected to the outside are respectively led out through interconnecting vias.

[0015] A single-chip cell refers to a standard power cell with the following structure: it contains a chip, and the source, gate, and drain signals of the chip are brought out through interconnect vias.

[0016] Here, "chip" refers to a power chip. It can be a vertically structured chip, meaning that the chip has electrodes on both the front and back sides, or a horizontally structured chip, meaning that the chip only has electrodes on the front side.

[0017] S20 According to the design parameters, patterned electroplating is performed on one end of the copper plate to form a chip receiving cavity and an alignment mark target; The patterned electroplating process involves using a substrate or PCB manufacturing process. After the pattern transfer is completed by exposure and development of a photosensitive dry film, a copper dam of a certain height is formed by electroplating. The copper dam serves as a sidewall, and the copper plate surface serves as a bottom wall, together forming a chip housing cavity. During electroplating, the height of the copper dam is controlled to be no less than the sum of the chip thickness and the solder layer thickness to ensure that the upper surface of the chip is not higher than the upper surface of the chip housing cavity after mounting, thus preventing the chip body from being subjected to excessive force during molding and pressing, which could lead to breakage.

[0018] This invention utilizes the surface of a copper plate as the bottom wall of the chip housing cavity, which has excellent flatness. It avoids unevenness caused by mechanical processing in traditional processes, such as tilting of the bottom wall or arc-shaped bottom caused by chemical etching, which can lead to uneven support during chip mounting and chip breakage.

[0019] The method of making alignment targets is to etch or laser ablate target graphics in the shape of crosses, concentric circles, rectangles, etc. on the surface of a copper plate by graphic transfer.

[0020] Alignment targets include whole-board alignment targets and unit alignment targets. Whole-board alignment targets are located in the edge area of ​​the copper plate and are used for accurate alignment in pattern transfer exposure, laser drilling and cutting processes. Unit alignment targets are located in the edge area of ​​the copper substrate and are used in the chip mounting process to achieve precise alignment.

[0021] S30 According to the design parameters, a blind slot is cut into the copper plate to form an insulation area and a cutting area. The insulation area divides the copper plate into multiple copper bases containing chip cavities. The layered structure of the copper plate below the blind slot serves as a connecting layer to maintain the integrity of the copper plate for easy whole-board processing. Insulation zone 12 is set to ensure a safe creepage insulation distance between two adjacent copper bases, based on the chip specifications and operating parameters. Cutting area 13 is used to cut individual products after the circuit fabrication is completed. Cutting thick copper plates will generate strong mechanical vibration and thermal effects, which will have an adverse effect on the chip and circuit. Pre-processing the cutting area before chip mounting can avoid the above-mentioned adverse effects during the final cutting.

[0022] S40 The chip is mounted into the chip receiving cavity according to the design parameters and the alignment target; S50 encapsulates and embeds the chip and chip receiving cavity on the entire board, so that the molding compound fills the insulating area and the cutting area to form the first molding layer; The molding compound used in this invention is a resin-based molding compound or ABF film (Ajinomoto encapsulation film). These materials significantly outperform the FR-4 prepreg used in PCB molding in terms of electrical properties, processing performance, and reliability. They have a lower dielectric constant, superior filling performance, lower water absorption, and stronger adhesion to metals. Their coefficient of thermal expansion can be precisely controlled to achieve optimal compatibility with the circuitry and chip. This step effectively encapsulates the chip and internal circuitry, protecting the fragile chip body and the interconnecting lines between chips, allowing the chip and power unit to maintain superior performance during use.

[0023] S60 opens a window in the first molding layer to expose the alignment mark target, and laser drills and metallizes the first molding layer according to the design parameters and the alignment mark target to form the required interconnecting vias and top external vias. The alignment target 9 used in the laser drilling of this invention is the same as the alignment target used during chip mounting. Within the chip mounting tolerance range, it will not cause misalignment accumulation that leads to drilling defects. Traditionally, individual power units are embedded in the PCB before the interconnecting lines are manufactured, resulting in chip mounting misalignment, power unit embedding misalignment, and drilling misalignment. Furthermore, since chip mounting and power unit embedding cannot use the same set of alignment marks, there is also misalignment of the alignment marks themselves. This quadruple misalignment risk greatly increases the processing difficulty. As described below, this invention pre-processes and encapsulates the chip pad interconnect vias and interconnecting lines, which have higher precision requirements, using molding compound. When embedding them into the PCB to connect to external circuits, only interconnect vias for the redistribution layer need to be formed, significantly reducing the precision requirements and making processing easier.

[0024] S70 According to the design parameters, manufacture the redistribution layer to form the half-bridge circuit, full-bridge circuit, cascaded circuit, multi-core series circuit, multi-core parallel circuit or single-core external circuit required for the standard power unit. Redundancy layer manufacturing processes enable the flexible and efficient rapid construction of different circuit topologies on the same process platform based on design parameters. Whether it's different power circuit structures such as half-bridge, full-bridge, or cascaded configurations, or different connection methods such as multi-core series, multi-core parallel, or single-core external connections, the circuit can be formed in one go through graphical customization of the redundancy layer, without changing the underlying process or performing complex subsequent rewiring. This significantly improves the adaptability and development efficiency of power modules, reduces manufacturing costs and cycles in multi-variety, small-batch customization scenarios, and provides highly integrated and flexible interconnect solutions for power semiconductor packaging.

[0025] The S80 removes the connecting layer and cuts along the cutting area to obtain a standard power unit product.

[0026] After removing the bonding layer, the cutting area of ​​this method only contains molding compound. The molding compound cutting process can avoid severe vibration and thermal effects, thus avoiding damage to the chip or circuit.

[0027] Furthermore, based on the aforementioned design parameters, the redistribution layer structure is manufactured to form the half-bridge structure required for each standard power unit as follows: The chip includes a first chip and a second chip. The first chip has a first gate pad, a first source pad and a first drain pad arranged on its front side. The second chip has a second gate pad, a second source pad and a second drain pad arranged on its front side. The copper substrate includes two chip receiving cavities, with the first chip mounted in one of the chip receiving cavities and the second chip mounted in the other chip receiving cavity; The rerouting layer includes a first rerouting layer and a second rerouting layer isolated by a dielectric layer; S701 manufactures the first wiring layer, one end of which is connected to the first drain pad via an interconnect via, and the other end is connected to the second source pad via an interconnect via. S702 encapsulates the first overlay layer to form the second encapsulation layer; S703 opens a window in the second molding layer to expose the alignment mark target, and laser drills and metallizes the second molding layer according to the alignment mark target to form the required interconnecting vias and top external vias; The second routing layer is manufactured, which includes a first source lead-out line and a second drain lead-out line. The first source lead-out line is connected to a first source pad through an interconnect via, and the second drain lead-out line is connected to a second drain pad through an interconnect via. The first gate pad forms a first external gate pad through a top external via, and the second gate pad forms a second external gate pad through a top external via. A half-bridge circuit is formed, in which the current directions of the first and second rewiring layers are opposite. Through the interleaved loops of the upper and lower layers in the spatial dimension, the stray inductance is greatly reduced, and the reliability of the power unit is further improved.

[0028] Furthermore, the redistribution layer is manufactured to form the full-bridge circuit required for each standard power unit: The copper substrate includes four chip receiving cavities, and two first chips and two second chips are respectively mounted in the four chip receiving cavities; Create two first-level wiring layers; Manufacture a full-bridge connection line, one end of which is connected to one of the two first-level wiring layers, and the other end is connected to the other first-level wiring layer; Simultaneously, the two first-level wiring layers and the full-bridge connection lines are encapsulated to form a second encapsulation layer; After opening a window in the second encapsulation layer and exposing the alignment target, the second encapsulation layer is laser-drilled and metallized according to the alignment target to form the required interconnecting vias and top external vias. Create two second wiring layers; The full-bridge circuit is thus formed.

[0029] Furthermore, based on the aforementioned design parameters, the redistribution layer structure is manufactured to form the cascaded circuits required for each standard power unit, as follows: The chip includes a third chip and a fourth chip. The third chip has a third gate pad, a third source pad and a third drain pad arranged on its front side. The fourth chip has a fourth gate pad, a fourth source pad arranged on its front side and a fourth drain pad arranged on its back side. The copper substrate includes two chip receiving cavities. The third chip is mounted in one of the chip receiving cavities, and the fourth chip is mounted in the other chip receiving cavity. The fourth drain pad is bonded to the bottom wall of the chip receiving cavity, so that the signal of the fourth drain pad is led out through the copper substrate. The rewiring layer includes a third rewiring layer and a fourth rewiring layer isolated by a dielectric layer; The third wiring layer is manufactured, which includes a third drain output line and a fourth source output line. The third drain output line forms a third drain external pad through a top external via. One end of the fourth source output line is connected to the third gate pad through an interconnect via, and the other end is connected to the fourth source pad through an interconnect via. The third wiring layer is encapsulated to form a second encapsulation layer; A window is made in the second encapsulation layer to expose the alignment mark target. The second encapsulation layer is then laser-drilled and metallized according to the alignment mark target to form the required interconnecting vias and top external vias. The fourth wiring layer is manufactured, and the fourth wiring layer includes a third source lead-out line. One end of the third source lead-out line is connected to the third source pad through an interconnect via, and the other end is connected to the fourth drain pad through an interconnect via and a copper base in sequence. The fourth gate pad is formed through a top external through-hole; The cascaded circuit is thus formed.

[0030] Furthermore, based on the aforementioned design parameters, a redistribution layer structure is manufactured to form the half-bridge circuit required for each standard power unit: The chip includes a fifth chip and a sixth chip. The fifth chip has a fifth gate pad and a fifth source pad arranged on its front side and a fifth drain pad arranged on its back side. The sixth chip has a sixth gate pad and a sixth source pad arranged on its front side and a sixth drain pad arranged on its back side. Two copper substrates, each containing a chip receiving cavity, are provided. The fifth chip is mounted in the chip receiving cavity of one of the copper substrates, and the fifth drain pad is bonded to the bottom wall of the chip receiving cavity, so that the signal of the fifth drain pad is led out through one of the copper substrates. The sixth chip is mounted in the chip receiving cavity of the other copper substrate, and the sixth drain pad is bonded to the bottom wall of the chip receiving cavity, so that the signal of the sixth drain pad is led out through the other copper substrate. The redistribution layer includes a fifth source lead-out line and a drain-source connection line. One end of the fifth source lead-out line is connected to the fifth source pad through an interconnect via. One end of the drain-source connection line is connected to the sixth source pad through an interconnect via, and the other end is connected to the fifth drain pad through an interconnect via and a copper base in sequence. The fifth gate pad is formed as a fifth external gate pad through a top external via, and the sixth gate pad is formed as a sixth external gate pad through a top external via; the sixth drain pad is formed as a sixth external drain pad through a copper base and a top external via. The half-bridge circuit is thus formed.

[0031] Furthermore, the manufacturing of the redistribution layer also includes forming connection circuits between half-bridge circuits, full-bridge circuits, cascaded circuits, multi-core series circuits, multi-core parallel circuits, or single-core circuits, and obtaining standard power unit expansion modules after cutting.

[0032] In this invention, different redistribution layer manufacturing steps can be achieved by designing redistribution layer patterns to form multiple different circuit layouts on a single board. In practical applications, when multiple power units need to work together, the connection lines of multiple standard power units can be designed together in the redistribution layer pattern. During processing, the functional circuits (i.e., half-bridge circuits, full-bridge circuits, cascaded circuits, multi-core series circuits, multi-core parallel circuits, or single-core circuits) and connection lines of the standard power units are formed simultaneously, and then packaged together using a molding process. After cutting, a standard power unit expansion module formed by interconnecting multiple standard power units is formed.

[0033] When this standard power unit expansion module is directly embedded into the PCB, it can further reduce the risk of PCB wiring and reduce PCB size.

[0034] Furthermore, the copper plate is made of pure copper, with a total thickness of 1mm-3mm, and the connecting layer thickness is 5-15% of the total thickness of the copper plate.

[0035] The copper plate needs to provide sufficient thickness for the copper substrate to meet the requirements of efficient heat dissipation of the power chip. Therefore, the thickness of the copper plate in this invention is set to 1mm-3mm; the thickness of the connecting layer is set to 5-15% of the total thickness of the copper plate, which can both maintain the shape of the whole plate and facilitate rapid removal during subsequent etching.

[0036] Furthermore, the copper plate is replaced by an AMB ceramic substrate (active metal brazing ceramic copper-clad substrate), which is formed by sequentially laminating an upper copper layer, a ceramic core layer and a lower copper layer, and the connecting layer is a ceramic core layer. Cancel the step of removing the connection layer; The formation of the cutting area includes, according to the design parameters, opening a blind slot from the upper copper layer to the ceramic core layer to form an upper cutting area; opening a blind slot from the lower copper layer to the ceramic core layer to form a lower cutting area; the geometric center line of the upper cutting area and the geometric center line of the lower cutting area are aligned with each other in the horizontal direction.

[0037] Under the same chip and power conditions, the thermal resistance of the AMB ceramic substrate is lower than that of a copper frame of the same size. This means that using a sandwich structure formed by an AMB ceramic substrate instead of a copper base formed by a thick copper block as the heat dissipation component of a standard power unit can achieve better heat dissipation performance. The reasons are as follows: The ceramic core layer has excellent insulation properties, eliminating the need for additional insulating pads when bonding it to the heat sink, thus eliminating the high thermal resistance introduced by insulating pads. In addition, the ceramic core layer itself has better thermal conductivity. After eliminating the need for additional insulating pads, the lower copper layer can be directly soldered to the heat sink, and the ceramic core layer bonds well with the upper and lower copper layers, further reducing the thermal resistance at each interface. Therefore, a standard power unit manufactured using an AMB ceramic substrate instead of a copper plate can have superior heat dissipation performance.

[0038] Furthermore, the cutting path is located on the geometric center line; The upper cutting area and the insulating area divide the upper copper layer into multiple copper base platforms containing chip cavities; The lower cutting area separates the lower copper layer into multiple lower copper bases; A first distance d1 is formed between the edge of the copper base and the nearest cutting path, and a second distance d2 is formed between the edge of the lower copper base and the nearest cutting path. The sum of the first distance d1, the second distance d2, and the thickness h of the ceramic core layer is the safe creepage distance between the copper base and the lower copper base. The relationship between the first distance d1 and the second distance d2 satisfies d1 / d2≥3.

[0039] The aforementioned creepage distance setting can prevent surface flashover between the copper base and the lower copper base. In addition, the first distance d1 is set to be more than three times the second distance d2. The purpose of this asymmetrical design is: firstly, to make the edge of the lower copper base 61 as close as possible to the cutting path, so that the lower copper base has a larger area to form a stable support for the ceramic core layer above, making the product structure of the power unit more reliable; secondly, to make the edge of the copper base further away from the cutting path, so as to provide a more sufficient creepage distance for the copper base on the high-voltage side, thereby balancing high-voltage insulation and mechanical support strength within a limited overall space, and preventing surface flashover.

[0040] The present invention also provides a standard power unit product manufactured using the manufacturing method described above.

[0041] In summary, this invention discloses a method for manufacturing a standard power cell structure for embedded packaging and a standard power cell product, the advantages of which are: 1. Standard power units with efficient heat dissipation functions can be mass-produced on a whole board; 2. One or more of the following can be manufactured in the same batch as needed: half-bridge unit, cascade unit, full-bridge unit, multi-core series unit, multi-core parallel unit, or single-core unit; 3. Standard power unit expansion modules, which are formed by interconnecting multiple standard power units, can be manufactured in the same batch as needed; this further improves the integration and security of the product. Users can directly customize the required functions. The standard power unit expansion modules are fully encapsulated and protected by plastic. When embedded in the PCB, standard packaging processes can be used uniformly, which greatly reduces the manufacturing cost and technical threshold of standard power unit embedded packaging and expands the applicable fields. 4. The chips and pads in the manufactured standard power units are encapsulated and protected by resin-based molding compound or ABF-type adhesive film to prevent electrical breakdown and other failures caused by physical damage when embedded in the PCB; 5. The present invention uses the same alignment target for chip mounting and subsequent drilling processes, which can avoid the superposition of mounting misalignment error and drilling misalignment error leading to drilling defects; 6. The present invention is based on a standard power unit manufactured on a ceramic substrate, which has a built-in ceramic core layer as an insulating layer. When embedded in the PCB and connected to the heat sink, no additional insulating layer is required, which can reduce thermal resistance and achieve better heat dissipation performance. 7. The present invention is based on a standard power unit manufactured on a ceramic substrate. Compared with the standard power unit of the ceramic substrate in the traditional solution, it does not have a protruding ceramic edge, thus avoiding the risk of breakage caused by the lamination process when embedding into the PCB. The edge of the copper base platform and the edge of the lower copper base maintain a certain safe distance from the edge of the ceramic core layer (i.e., the cutting line), and this safe distance is designed asymmetrically. While forming a safe creepage distance, it also provides mechanical support for the ceramic core layer, making the structure more reliable.

[0042] 8. The present invention forms a chip receiving cavity based on a copper plate or a ceramic substrate. The bottom wall of the chip receiving cavity is the surface of the copper plate or the ceramic substrate, which has a good flatness. The side walls of the chip receiving cavity are formed by patterned electroplating, and the height can be precisely controlled to ensure that the chip does not exceed the side walls of the chip receiving cavity, thus avoiding breakage caused by plastic encapsulation.

[0043] To further understand the features and technical content of this invention, please refer to the following detailed description and accompanying drawings. However, these descriptions and drawings are only for illustrating the invention and are not intended to limit the scope of protection of the invention in any way. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of existing technology for embedding chips into a PCB; Figure 2 This is a schematic diagram of a power unit based on existing technical standards; Figure 3-10 This is a schematic diagram of the manufacturing process of a half-bridge unit and a single-core unit in a standard power unit according to Embodiment 1 of the present invention; Figure 11-17 This is a schematic diagram of the process flow of a standard power cell manufacturing method based on a ceramic substrate according to Embodiment 2 of the present invention; Figure 18-26 This is a schematic diagram of the manufacturing process of a half-bridge unit in a standard power unit according to Embodiment 3 of the present invention; Figure 27-32 This is a schematic diagram of the manufacturing process of a half-bridge unit in a standard power unit according to Embodiment 4 of the present invention; Figure 33-35 This is a schematic diagram of the manufacturing process of a full-bridge unit in a standard power unit according to Embodiment 5 of the present invention; Figures 36-39This is a schematic diagram of the manufacturing process of a cascaded unit in a standard power unit according to Embodiment 6 of the present invention; Figure 40 This is a schematic diagram of a standard power unit embedded in a PCB according to the present invention.

[0045] In the picture: 1-Copper plate; 10-AMB ceramic substrate; 101-Upper copper layer; 102-Ceramic core layer; 103-Lower copper layer; 12-Insulating area; 13-Cut area; 131-Upper cut area; 132-Lower cut area; 133-Cut path; 14-Connection layer; 21-Half-bridge unit; 22-Cascaded unit; 23-Full-bridge unit; 26-Single-core unit; 3-Chip; 31-First chip; 311-First gate pad; 312-First source pad; 313-First drain pad; 32-Second chip; 321- Second gate pad; 322 - Second source pad; 323 - Second drain pad; 33 - Third chip; 331 - Third gate pad; 332 - Third source pad; 333 - Third drain pad; 34 - Fourth chip; 341 - Fourth gate pad; 342 - Fourth source pad; 343 - Fourth drain pad; 35 - Fifth chip; 351 - Fifth gate pad; 352 - Fifth source pad; 353 - Fifth drain pad; 36 - Sixth chip; 361 - Sixth gate pad; 362 - Sixth source pad; 363 - Sixth drain pad; 37 - Seventh chip; 371 - Seventh gate pad; 372 - Seventh source pad; 373 - Seventh drain pad; 4 - Redistribution layer; 400 - Full-bridge connection; 402 - First source lead-out line; 403 - Second drain lead-out line; 404 - Source-drain connection line; 405 - First external gate pad; 406 - Second external gate pad; 41 - First redistribution layer; 42 - Second redistribution layer; 43 - Third redistribution layer; 431 - Third drain lead-out line; 432 - Gate-source connection line; 441-Third drain external pad; 442-Cascaded source-drain connection line; 443-Fourth gate external pad; 451-Fifth gate external pad; 452-Fifth source lead-out line; 461-Sixth gate external pad; 462-Drain-source connection line; 463-Sixth drain external pad; 5-Chip housing cavity; 6-Copper base; 61-Lower copper base; 71-First molding layer; 72-Second molding layer; 8-PCB; 81-Peripheral circuit layer; 82-Heat conductive layer; 9-Alignment mark target. Detailed Implementation

[0046] The following is in conjunction with the appendix Figure 3-40 The present invention provides a further description of the manufacturing method of the standard power cell structure for embedded packaging.

[0047] Example 1 Figure 3-10The first embodiment of the present invention illustrates a standard power unit manufacturing method for embedded packaging, comprising the following steps: S10 Obtain the design parameters of all standard power units, namely half-bridge unit 21 and single-core unit 26; S20 According to the design parameters, patterned electroplating is performed on one end of the copper plate 1 to form a chip receiving cavity 5 and an alignment mark target 9; S30 According to the design parameters, a blind slot is opened on the copper plate 1 to form an insulating area 12 and a cutting area 13. The insulating area 12 divides the copper plate 1 into multiple copper bases 6 containing chip accommodating cavities 5. The layered structure of the copper plate 1 located below the blind slot serves as a connecting layer 14 to maintain the integrity of the copper plate 1 for easy whole-board processing. The copper plate itself is used as the connecting layer 14. Considering both structural strength and the convenience of subsequent processing, the thickness of the connecting layer accounts for 5%-15% of the total thickness of the copper plate.

[0048] S40 According to the design parameters and the alignment target 9, the chip 3 is mounted into the chip receiving cavity 5; Chip 3 includes chip 35 (fifth chip), chip 36 (sixth chip), and chip 37 (seventh chip): The insulating area 12 and the cutting area 13 divide the corresponding areas of the copper plate 1 to form three copper bases 6. Each copper base 6 includes a chip receiving cavity 5. The fifth chip 35 and the sixth chip 36 are respectively mounted in the chip receiving cavities 5 of two adjacent copper bases 6. The two adjacent copper bases 6 are separated and insulated by the insulating area 12. The seventh chip 37 is mounted in the copper base 6 surrounded by the cutting area 13.

[0049] S50 The chip 3 and chip receiving cavity 5 are encapsulated and embedded in the entire board, so that the molding compound fills the insulating area 12 and the cutting area 13 to form the first molding layer 71; S60 opens a window in the first molding layer 71 to expose the alignment mark target 9, and laser drills and metallizes the first molding layer 71 according to the design parameters and the alignment mark target 9 to form the required interconnecting vias and top external vias. S70 According to the design parameters, manufacture the redistribution layer 4 to form the half-bridge circuit and single-core circuit required for the standard power unit; like Figure 9 As shown, the fifth chip 35 has a fifth gate pad 351 and a fifth source pad 352 arranged on its front side and a fifth drain pad 353 arranged on its back side. The sixth chip 36 has a sixth gate pad 361 and a sixth source pad 362 arranged on its front side and a sixth drain pad 363 arranged on its back side. The seventh chip has a seventh gate pad 371 and a seventh source pad 372 arranged on its front side and a seventh drain pad 373 arranged on its back side.

[0050] The fifth chip 35 and the sixth chip 36 are connected to form a half-bridge circuit, specifically... The fifth drain pad 353 is bonded to the bottom wall of the chip receiving cavity 5, so that the signal of the fifth drain pad 353 is led out through one of the copper bases 6; the sixth drain pad 363 is bonded to the bottom wall of the chip receiving cavity 5, so that the signal of the sixth drain pad 363 is led out through another copper base 6. The redistribution layer 4 includes a fifth source lead-out line 452 and a drain-source connection line 462. One end of the fifth source lead-out line 452 is connected to the fifth source pad 352 through an interconnect via. One end of the drain-source connection line 462 is connected to the sixth source pad 362 through an interconnect via. The other end is connected to the fifth drain pad 353 through an interconnect via and a copper base 6 in sequence. The redistribution layer 4 also includes a fifth gate pad 351 formed by a top external via, a sixth gate pad 361 formed by a top external via, and a sixth drain pad 363 formed by a copper base 6 and a top external via. Based on the above circuit, the fifth chip 35 and the sixth chip 36 form a half-bridge circuit.

[0051] The redistribution layer 4 also forms the seventh gate external pad, the seventh source lead-out line and the seventh drain external pad of the seventh chip 37, and based on the above lines, a single-core circuit of the seventh chip 37 is formed.

[0052] After the S80 etching removes the interconnect layer 14, the molding compound cutting process can be used to cut along the cutting area 13 to obtain the half-bridge unit 21 and the single-core unit 26.

[0053] Example 2 Figure 11-17 The figure shows a manufacturing method for a standard power unit structure for embedded packaging according to the second embodiment of the present invention. The difference from the first embodiment is that an AMB ceramic substrate 10 is used to replace the copper plate 1 to manufacture the half-bridge unit. The AMB ceramic substrate 10 is formed by sequentially pressing an upper copper layer 101, a ceramic core layer 102 and a lower copper layer 103. In this embodiment, the alignment target 9 is manufactured by removing copper from a portion of the upper copper layer to expose the ceramic core layer, and then using laser ablation to etch target patterns such as crosses, concentric circles, and rectangles into the ceramic core layer. A blind slot is cut from the upper copper layer 101 to the ceramic core layer 102 to form an insulating region 12 and an upper cutting region 131. The insulating region 12 and the upper cutting region 131 divide the corresponding area of ​​the upper copper layer 101 to form three copper base platforms 6. A blind slot is cut from the lower copper layer 103 to the ceramic core layer 102 to form a lower cutting region 132. The lower cutting region 132 separates the lower copper layer 103 into the lower copper base 61 of each power unit. The upper cutting region 131 and the lower cutting region 132 together constitute the cutting region 13.

[0054] The geometric center lines of the upper cutting area 131 and the lower cutting area 132 are aligned with each other in the horizontal direction, and the cutting path 133 is located on the geometric center line.

[0055] To avoid surface flashover between the copper base 6 and the lower copper base 61, during the processing of the cutting area 13, the edges of the copper base 6 and the lower copper base 61 are kept apart from the cutting path 133, thereby forming a safe creepage distance between the copper base 6 and the lower copper base 61. like Figure 13 As shown, the distance between the edge 6a of the copper base 6 and the cutting path 133 is d1, and the distance between the edge 61a of the lower copper base 61 and the cutting path 133 is d2. The distance d1 is set to be greater than the distance d2.

[0056] Preferably, the distance d2 is set to the minimum dimension achievable by the current manufacturing process, while the distance d1 is set to be greater than d2. Specifically, the ratio of d1 to d2 is designed to be no less than 3. For example, when the ceramic core layer thickness h is 0.5 mm and the minimum creepage distance (h + d1 + d2) is 5.5 mm, d1 is set to be no greater than 1.25 mm and d2 is set to be no less than 3.75 mm.

[0057] Example 3 Figure 18-26 The figure shows a method for manufacturing a half-bridge unit in a standard power unit for embedded packaging according to a third embodiment of the present invention, comprising the following steps: S10 Obtain the design parameters of all standard power units, including half-bridge unit 21; S20 According to the design parameters, patterned electroplating is performed on one end of the copper plate 1 to form a chip receiving cavity 5 and an alignment mark target 9 (not shown). S30 According to the design parameters, a blind slot is opened in the copper plate 1 to form an insulating area 12 (not shown) and a cutting area 13. The insulating area 12 divides the copper plate 1 into multiple copper bases 6 (one of which is shown in this embodiment). The copper base 6 shown in this embodiment includes two chip receiving cavities 5. The layered structure of the copper plate 1 located below the blind groove serves as a connecting layer 14 to maintain the integrity of the copper plate 1 for easy processing of the whole plate; S40 According to the design parameters and the alignment target 9, the chip 3 is mounted into the chip receiving cavity 5; As shown in the figure, chip 3 includes a first chip 31 and a second chip 32. The first chip 31 has a first gate pad 311, a first source pad 312 and a first drain pad 313 arranged on its front side. The second chip 32 has a second gate pad 321, a second source pad 322 and a second drain pad 323 arranged on its front side; The first source pad 312 and the first drain pad are alternately arranged; the second source pad 322 and the second drain pad are alternately arranged. The first chip 31 is mounted in one chip receiving cavity 5, and the second chip is mounted in another chip receiving cavity 5; S50 The chip 3 and chip receiving cavity 5 are encapsulated in a whole board, so that the molding compound fills the insulating area 12 (not shown) and the cutting area 13 to form the first molding layer 71; S60 Opens a window in the first molding layer 71 to expose the alignment target 9 (not shown), and laser drills and metallizes the first molding layer 71 according to the design parameters and the alignment target 9 to form the required interconnecting vias and top external vias; S70 According to the design parameters, manufacture the redistribution layer 4 to form the half-bridge circuit required for the standard power unit; The redistribution layer 4 includes a first source lead-out line 402, a second drain lead-out line 403, a source-drain connection line 404, a first gate external pad 405, and a second gate external pad 406. The first source lead-out line 402 is connected to the first source pad 312 through an interconnect via, and the second drain lead-out line 403 is connected to the second drain pad 323 through an interconnect via; one end of the source-drain connection line 404 is connected to the first drain pad 313 through an interconnect via, and the other end is connected to the second source pad 322 through an interconnect via; the first gate pad 311 forms the first gate external pad 405 through a top external via, and the second gate pad 321 forms the second gate external pad 406 through a top external via.

[0058] S80 Remove the connecting layer 14 and cut along the cutting area 13 to obtain the half-bridge unit 21.

[0059] Example 4 Figure 27-32The figure shows a method for manufacturing a half-bridge unit in a standard power unit for embedded packaging according to the fourth embodiment of the present invention. The difference from the third embodiment is that the structure and manufacturing method of the redistribution layer 4 in this embodiment are as follows: The redistribution layer 4 includes a first redistribution layer 41 and a second redistribution layer 42 isolated by a dielectric layer. The manufacturing method includes the following steps: S701 manufactures the first redistribution layer 41, such as Figure 27 As shown in Figure 28, it includes a source-drain connection line 404. One end of the source-drain connection line 404 is connected to the first drain pad 313 through an interconnection via, and the other end is connected to the second source pad 322 through an interconnection via. S702 encapsulates the first redistribution layer 41 to form the second encapsulation layer 72; S703 opens a window in the second molding layer 72 to expose the alignment mark target 9 (not shown), and laser drills and metallizes the second molding layer 72 according to the alignment mark target 9 to form the required interconnecting vias and top external vias; Fabricating the second redistribution layer 42, such as Figure 30 As shown in Figure 32, the second redistribution layer 42 includes a first source outgoing line 402 and a second drain outgoing line 403. The first source outgoing line 402 is connected to the first source pad 312 through interconnect vias, and the second drain outgoing line 403 is connected to the second drain pad 323 through interconnect vias. The first gate pad 311 forms a first gate external pad 405 through a top external via, and the second gate pad 321 forms a second gate external pad 406 through a top external via. The half-bridge circuit is formed, and after cutting, half-bridge unit 21 is obtained, as shown below. Figure 31 As shown.

[0060] The first wiring layer 41 and the second wiring layer 42 have a parallel and vertically aligned structure. When in operation, the first wiring layer 41 and the second wiring layer 42 carry currents in opposite directions, and the magnetic fields generated cancel each other out, achieving extremely low stray inductance.

[0061] Example 5 Figure 33-35 The figure shows a method for manufacturing a full-bridge unit 23 in a standard power unit for embedded packaging according to the fifth embodiment of the present invention, including the following steps: The copper base 6 includes four chip receiving cavities 5, and two first chips 31 and two second chips 32 are respectively mounted in the four chip receiving cavities 5. Two first redistribution layers 41 are manufactured according to the method in Example 4, such as... Figure 34 As shown: Manufacture a full-bridge connection line 400, one end of which is connected to one of the two first rewiring layers 41, and the other end is connected to the other first rewiring layer 41; Simultaneously, two first rewiring layers 41 and full-bridge connection lines 400 are encapsulated to form a second encapsulation layer 72; After opening a window in the second molding layer 72 and exposing the alignment target 9 (not shown), the second molding layer 72 is laser-drilled and metallized according to the alignment target 9 to form the required interconnecting vias and top external vias; Fabricate two second wiring layers 42, such as Figure 35 As shown; The full-bridge circuit is formed, and after cutting, the full-bridge unit 23 is obtained.

[0062] In this embodiment, the full-bridge unit 23 can also be regarded as a standard power unit expansion module connected by two half-bridge units 21.

[0063] Example 6 Figures 36-39 The figure shown is a method for manufacturing a cascaded unit in a standard power unit for embedded packaging according to the sixth embodiment of the present invention, which differs from embodiment 4 in that: The chip 3 includes a third chip 33 and a fourth chip 34. The third chip 33 has a third gate pad 331, a third source pad 332 and a third drain pad 333 arranged on its front side. The fourth chip 34 has a fourth gate pad 341 and a fourth source pad 342 arranged on its front side and a fourth drain pad 343 arranged on its back side. The copper base 6 includes two chip receiving cavities 5. The third chip 33 is mounted in one of the chip receiving cavities 5, and the fourth chip 34 is mounted in the other chip receiving cavity 5. The fourth drain pad 343 is bonded to the bottom wall of the chip receiving cavity 5. The redistribution layer 4 includes a third redistribution layer 43 and a fourth redistribution layer 44 isolated by a dielectric layer; The third wiring layer 43 is manufactured, which includes a third drain lead-out line 431 and a gate-source connection line 432. The third drain lead-out line 431 is connected to the third drain pad 333 through an interconnect via. One end of the gate-source connection line 432 is connected to the third gate pad 331 through an interconnect via, and the other end is connected to the fourth source pad 342 through an interconnect via. The third wiring layer 43 is encapsulated to form a second encapsulation layer 72; A window is made in the second molding layer 72 to expose the alignment mark target 9 (not shown) manufactured in step S2. The second molding layer 72 is then laser-drilled and metallized according to the alignment mark target 9 to form the required interconnecting vias and top external vias. The fourth wiring layer 44 is manufactured. The fourth wiring layer includes a cascaded source-drain connection line 442. One end of the cascaded source-drain connection line 442 is connected to the third source pad 332 through an interconnect via, and the other end is connected to the fourth drain pad 343 in sequence through an interconnect via and a copper base 6. The third drain lead-out line 431 forms a third drain external pad 441 through a top external through-hole; the fourth gate pad 341 forms a fourth gate external pad 443 through a top external through-hole; thus forming the cascaded circuit; the remaining steps are the same as in Embodiment 4, and the cascaded unit 22 is obtained after cutting.

[0064] Figure 40 A schematic diagram of a half-bridge structure embedded in a PCB 8 according to the present invention is shown. It can be seen that the complete function can be achieved by simply connecting the pads or lines in the redistribution layer 4 to the peripheral circuit layer 81 through interconnect vias. There is no need for multiple layers of wiring to interconnect different power units, which reduces the risk of wiring loops. Only one thermal conductive layer 82 is needed on the back side, which serves as a heat conduction layer and a stacking balance layer for the peripheral circuit layer 81. Adding a corresponding wiring layer on the back side can significantly reduce the size of the finished PCB.

[0065] The standard power units and standard power unit expansion modules obtained in the various embodiments of the present invention have all implemented the interconnection lines between internal chips. Therefore, when embedded in a PCB, the above-mentioned standard process can be used to achieve complete functionality.

Claims

1. A method for manufacturing a standard power cell structure for embedded packaging, characterized in that, Includes the following steps: S10 Obtain the design parameters of all standard power units, wherein the standard power units are one or more of the following: half-bridge unit (21), cascaded unit (22), full-bridge unit (23), multi-core series unit, multi-core parallel unit, and single-core unit (26); S20 According to the design parameters, patterned electroplating is performed on one end of the copper plate (1) to form a chip receiving cavity (5) and a positioning mark target (9). S30 According to the design parameters, a blind slot is opened on the copper plate (1) to form an insulating area (12) and a cutting area (13). The insulating area (12) divides the copper plate (1) into multiple copper bases (6) containing chip cavities (5). The layered structure of the copper plate (1) located below the blind slot serves as a connecting layer (14) to maintain the integrity of the copper plate (1) so as to facilitate the whole board processing. S40 The chip (3) is mounted into the chip receiving cavity (5) according to the design parameters and the alignment target (9); S50 The chip (3) and chip receiving cavity (5) are encapsulated in a whole board, so that the molding compound fills the insulating area (12) and the cutting area (13) to form the first molding layer (71). S60 opens a window in the first molding layer (71) to expose the alignment mark target (9), and laser drills and metallizes the first molding layer (71) according to the design parameters and the alignment mark target (9) to form the required interconnecting vias and top external vias; S70 According to the design parameters, manufacture the redistribution layer (4) to form the half-bridge circuit, full-bridge circuit, cascade circuit, multi-core series circuit, multi-core parallel circuit or single-core circuit required for the standard power unit; S80 Remove the connecting layer (14) and cut along the cutting area (13) to obtain a standard power unit product.

2. The manufacturing method according to claim 1, characterized in that, The step of manufacturing the rewiring layer structure according to the design parameters to form the half-bridge circuit required for each standard power unit is as follows: The chip (3) includes a first chip (31) and a second chip (32). The first chip (31) has a first gate pad (311), a first source pad (312) and a first drain pad (313) arranged on its front side. The second chip (32) has a second gate pad (321), a second source pad (322) and a second drain pad (323) arranged on its front side. The copper substrate (6) includes two chip receiving cavities (5), the first chip (31) is mounted in one chip receiving cavity (5), and the second chip is mounted in the other chip receiving cavity (5); The redistribution layer (4) includes a first redistribution layer (41) and a second redistribution layer (42) isolated by a dielectric layer. S701 manufactures the first redistribution layer (41), which includes a source-drain connection line (404). One end of the source-drain connection line (404) is connected to the first drain pad (313) through an interconnect via, and the other end is connected to the second source pad (322) through an interconnect via. S702 encapsulates the first redistribution layer (41) to form the second encapsulation layer (72); S703 opens a window in the second molding layer (72) to expose the alignment mark target (9), and laser drills and metallizes the second molding layer (72) according to the alignment mark target (9) to form the required interconnecting vias and top external vias; The second redistribution layer (42) is manufactured, which includes a first source lead-out line (402) and a second drain lead-out line (403). The first source lead-out line (402) is connected to the first source pad (312) through an interconnect via, and the second drain lead-out line (403) is connected to the second drain pad (323) through an interconnect via. The first gate pad (311) forms a first gate external pad (405) through a top external via, and the second gate pad (321) forms a second gate external pad (406) through a top external via. The half-bridge circuit and half-bridge unit (21) are formed, and when in operation, the first redistribution layer (41) and the second redistribution layer (42) have opposite current directions.

3. The manufacturing method according to claim 2, characterized in that, The manufacturing redistribution layer (4) forms the full-bridge circuit required for each standard power unit as follows: The copper base (6) includes four chip receiving cavities (5), and two first chips (31) and two second chips (32) are respectively mounted in the four chip receiving cavities (5); Two first super-wiring layers (41) are fabricated. Manufacture a full-bridge connection line (400), one end of which is connected to one of the two first rewiring layers (41), and the other end is connected to the other first rewiring layer (41); Simultaneously, the two first rewiring layers (41) and the full-bridge connection line (400) are encapsulated to form the second encapsulation layer (72). After opening a window in the second molding layer (72) and exposing the alignment target (9), the second molding layer (72) is laser-drilled and metallized according to the alignment target (9) to form the required interconnecting vias and top external vias; Fabricate two second wiring layers (42); The full-bridge circuit and full-bridge unit (23) are formed.

4. The manufacturing method according to claim 1, characterized in that, The process of manufacturing the redistribution layer structure according to the design parameters to form the cascaded circuit required for each standard power unit is as follows: The chip (3) includes a third chip (33) and a fourth chip (34). The third chip (33) has a third gate pad (331), a third source pad (332) and a third drain pad (333) arranged on its front side. The fourth chip (34) has a fourth gate pad (341) and a fourth source pad (342) arranged on its front side and a fourth drain pad (343) arranged on its back side. The copper base (6) includes two chip receiving cavities (5), the third chip (33) is mounted in one of the chip receiving cavities (5), the fourth chip (34) is mounted in the other chip receiving cavity (5), and the fourth drain pad (343) is bonded to the bottom wall of the chip receiving cavity (5), so that the signal of the fourth drain pad (343) is led out through the copper base (6); The redistribution layer (4) includes a third redistribution layer (43) and a fourth redistribution layer (44) isolated by a dielectric layer. The third wiring layer (43) is fabricated, which includes a third drain lead-out line (431) and a gate-source connection line (432). The third drain lead-out line (431) is connected to the third drain pad (333) through an interconnect via. One end of the gate-source connection line (432) is connected to the third gate pad (331) through an interconnect via, and the other end is connected to the fourth source pad (342) through an interconnect via. The third wiring layer (43) is encapsulated to form a second encapsulation layer (72); A window is opened in the second molding layer (72) to expose the alignment mark target (9) manufactured in step S2. The second molding layer (72) is laser drilled and metallized according to the alignment mark target (9) to form the required interconnecting vias and top external vias. The fourth wiring layer (44) is manufactured, which includes a cascaded source-drain connection line (442). One end of the cascaded source-drain connection line (442) is connected to the third source pad (332) through an interconnect via, and the other end is connected to the fourth drain pad (343) through an interconnect via and a copper base (6) in sequence. The third drain lead-out line (431) forms a third drain external pad (441) through a top external through-hole; the fourth gate pad (341) forms a fourth gate external pad (443) through a top external through-hole; thus forming a cascaded circuit and the cascaded unit (22).

5. The manufacturing method according to claim 1, characterized in that, The step of manufacturing the rewiring layer structure according to the design parameters to form the half-bridge circuit required for each standard power unit is as follows: The chip (3) includes a fifth chip (35) and a sixth chip (36). The fifth chip (35) has a fifth gate pad (351) and a fifth source pad (352) arranged on its front side and a fifth drain pad (353) arranged on its back side. The sixth chip (36) has a sixth gate pad (361) and a sixth source pad (362) arranged on its front side and a sixth drain pad (363) arranged on its back side. Two copper substrates (6) each contain a chip receiving cavity (5). A fifth chip (35) is mounted in the chip receiving cavity (5) of one of the copper substrates (6). The fifth drain pad (353) is bonded to the bottom wall of the chip receiving cavity (5), so that the signal of the fifth drain pad (353) is led out through one of the copper substrates (6). A sixth chip (36) is mounted in the chip receiving cavity (5) of the other copper substrate (6). The sixth drain pad (363) is bonded to the bottom wall of the chip receiving cavity (5), so that the signal of the sixth drain pad (363) is led out through the other copper substrate (6). The redistribution layer (4) includes a fifth source lead-out line (452) and a drain-source connection line (462). One end of the fifth source lead-out line (452) is connected to the fifth source pad (352) through an interconnect via. One end of the drain-source connection line (462) is connected to the sixth source pad (362) through an interconnect via. The other end is connected to the fifth drain pad (353) through an interconnect via and a copper base (6) in sequence. The redistribution layer (4) also includes a fifth gate pad (351) formed by a top external via to form a fifth gate external pad (451), and a sixth gate pad (361) formed by a top external via to form a sixth gate external pad (461); the sixth drain pad (363) is formed by a copper base (6) and a top external via to form a sixth drain external pad (463). The half-bridge circuit and half-bridge unit (21) are formed.

6. The manufacturing method according to claim 1, characterized in that, The manufacturing redistribution layer (4) also includes forming a connection circuit between the half-bridge circuit, full-bridge circuit, cascaded circuit, multi-core series circuit, multi-core parallel circuit or single-core circuit, and obtaining a standard power unit expansion module after cutting.

7. The manufacturing method according to claim 1, characterized in that, The copper plate (1) is pure copper with a total thickness of 1mm-3mm, and the thickness of the connecting layer (14) is 5-15% of the total thickness of the copper plate (1).

8. The manufacturing method according to claim 1, characterized in that, The copper plate (1) is replaced by a double-sided copper AMB ceramic substrate (10), which is formed by sequentially pressing an upper copper layer (101), a ceramic core layer (102) and a lower copper layer (103), and the connecting layer (14) is the ceramic core layer (102). Cancel the step of removing the connection layer (14); The formation of the cutting area (13) includes, according to the design parameters, opening a blind slot from the upper copper layer (101) to the ceramic core layer (102) to form an upper cutting area (131); and opening a blind slot from the lower copper layer (103) to the ceramic core layer (102) to form a lower cutting area (132). The geometric center line of the upper cutting area (131) and the geometric center line of the lower cutting area (132) are aligned with each other in the horizontal direction.

9. The manufacturing method according to claim 8, characterized in that, The cutting path (133) is located on the geometric center line; The upper cutting area (131) and the insulating area (12) divide the upper copper layer (101) into multiple copper bases (6) containing chip accommodating cavities (5). The lower cutting area (132) separates the lower copper layer (103) into multiple lower copper bases (61). A first distance d1 is formed between the edge of the copper base (6) and the nearest cutting path (133), and a second distance d2 is formed between the edge of the lower copper base (61) and the nearest cutting path (133). The sum of the first distance d1, the second distance d2 and the thickness h of the ceramic core layer is the safe creepage distance between the copper base (6) and the lower copper base (61); wherein the relationship between the first distance d1 and the second distance d2 satisfies d1 / d2≥3; After the redistribution layer (4) is manufactured, it is cut along the cutting path (133) to obtain a standard power unit product.

10. A standard power unit product, characterized in that, Manufactured using the manufacturing method as described in any one of claims 1-8.

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